1 2 #include <drm/drmP.h> 3 #include <drm/drm_dp_mst_helper.h> 4 #include <drm/drm_fb_helper.h> 5 6 #include "radeon.h" 7 #include "atom.h" 8 #include "ni_reg.h" 9 10 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector); 11 12 static int radeon_atom_set_enc_offset(int id) 13 { 14 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, 15 EVERGREEN_CRTC1_REGISTER_OFFSET, 16 EVERGREEN_CRTC2_REGISTER_OFFSET, 17 EVERGREEN_CRTC3_REGISTER_OFFSET, 18 EVERGREEN_CRTC4_REGISTER_OFFSET, 19 EVERGREEN_CRTC5_REGISTER_OFFSET, 20 0x13830 - 0x7030 }; 21 22 return offsets[id]; 23 } 24 25 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary, 26 struct radeon_encoder_mst *mst_enc, 27 enum radeon_hpd_id hpd, bool enable) 28 { 29 struct drm_device *dev = primary->base.dev; 30 struct radeon_device *rdev = dev->dev_private; 31 uint32_t reg; 32 int retries = 0; 33 uint32_t temp; 34 35 reg = RREG32(NI_DIG_BE_CNTL + primary->offset); 36 37 /* set MST mode */ 38 reg &= ~NI_DIG_FE_DIG_MODE(7); 39 reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST); 40 41 if (enable) 42 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); 43 else 44 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); 45 46 reg |= NI_DIG_HPD_SELECT(hpd); 47 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); 48 WREG32(NI_DIG_BE_CNTL + primary->offset, reg); 49 50 if (enable) { 51 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); 52 53 do { 54 temp = RREG32(NI_DIG_FE_CNTL + offset); 55 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000); 56 if (retries == 10000) 57 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe); 58 } 59 return 0; 60 } 61 62 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary, 63 int stream_number, 64 int fe, 65 int slots) 66 { 67 struct drm_device *dev = primary->base.dev; 68 struct radeon_device *rdev = dev->dev_private; 69 u32 temp, val; 70 int retries = 0; 71 int satreg, satidx; 72 73 satreg = stream_number >> 1; 74 satidx = stream_number & 1; 75 76 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset); 77 78 val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe); 79 80 val <<= (16 * satidx); 81 82 temp &= ~(0xffff << (16 * satidx)); 83 84 temp |= val; 85 86 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp); 87 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); 88 89 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); 90 91 do { 92 unsigned value1, value2; 93 udelay(10); 94 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); 95 96 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK; 97 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT; 98 99 if (!value1 && !value2) 100 break; 101 } while (retries++ < 50); 102 103 if (retries == 10000) 104 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset); 105 106 /* MTP 16 ? */ 107 return 0; 108 } 109 110 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn, 111 struct radeon_encoder *primary) 112 { 113 struct drm_device *dev = mst_conn->base.dev; 114 struct stream_attribs new_attribs[6]; 115 int i; 116 int idx = 0; 117 struct radeon_connector *radeon_connector; 118 struct drm_connector *connector; 119 120 memset(new_attribs, 0, sizeof(new_attribs)); 121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 122 struct radeon_encoder *subenc; 123 struct radeon_encoder_mst *mst_enc; 124 125 radeon_connector = to_radeon_connector(connector); 126 if (!radeon_connector->is_mst_connector) 127 continue; 128 129 if (radeon_connector->mst_port != mst_conn) 130 continue; 131 132 subenc = radeon_connector->mst_encoder; 133 mst_enc = subenc->enc_priv; 134 135 if (!mst_enc->enc_active) 136 continue; 137 138 new_attribs[idx].fe = mst_enc->fe; 139 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port); 140 idx++; 141 } 142 143 for (i = 0; i < idx; i++) { 144 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe || 145 new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) { 146 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots); 147 mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe; 148 mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots; 149 } 150 } 151 152 for (i = idx; i < mst_conn->enabled_attribs; i++) { 153 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0); 154 mst_conn->cur_stream_attribs[i].fe = 0; 155 mst_conn->cur_stream_attribs[i].slots = 0; 156 } 157 mst_conn->enabled_attribs = idx; 158 return 0; 159 } 160 161 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp) 162 { 163 struct drm_device *dev = mst->base.dev; 164 struct radeon_device *rdev = dev->dev_private; 165 struct radeon_encoder_mst *mst_enc = mst->enc_priv; 166 uint32_t val, temp; 167 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); 168 int retries = 0; 169 uint32_t x = drm_fixp2int(avg_time_slots_per_mtp); 170 uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26); 171 172 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y); 173 174 WREG32(NI_DP_MSE_RATE_CNTL + offset, val); 175 176 do { 177 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); 178 udelay(10); 179 } while ((temp & 0x1) && (retries++ < 10000)); 180 181 if (retries >= 10000) 182 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe); 183 return 0; 184 } 185 186 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector) 187 { 188 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 189 struct radeon_connector *master = radeon_connector->mst_port; 190 struct edid *edid; 191 int ret = 0; 192 193 edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port); 194 radeon_connector->edid = edid; 195 DRM_DEBUG_KMS("edid retrieved %p\n", edid); 196 if (radeon_connector->edid) { 197 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 198 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 199 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid); 200 return ret; 201 } 202 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 203 204 return ret; 205 } 206 207 static int radeon_dp_mst_get_modes(struct drm_connector *connector) 208 { 209 return radeon_dp_mst_get_ddc_modes(connector); 210 } 211 212 static enum drm_mode_status 213 radeon_dp_mst_mode_valid(struct drm_connector *connector, 214 struct drm_display_mode *mode) 215 { 216 /* TODO - validate mode against available PBN for link */ 217 if (mode->clock < 10000) 218 return MODE_CLOCK_LOW; 219 220 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 221 return MODE_H_ILLEGAL; 222 223 return MODE_OK; 224 } 225 226 static struct drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector) 227 { 228 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 229 230 return &radeon_connector->mst_encoder->base; 231 } 232 233 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = { 234 .get_modes = radeon_dp_mst_get_modes, 235 .mode_valid = radeon_dp_mst_mode_valid, 236 .best_encoder = radeon_mst_best_encoder, 237 }; 238 239 static enum drm_connector_status 240 radeon_dp_mst_detect(struct drm_connector *connector, bool force) 241 { 242 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 243 struct radeon_connector *master = radeon_connector->mst_port; 244 245 return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port); 246 } 247 248 static void 249 radeon_dp_mst_connector_destroy(struct drm_connector *connector) 250 { 251 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 252 struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder; 253 254 drm_encoder_cleanup(&radeon_encoder->base); 255 kfree(radeon_encoder); 256 drm_connector_cleanup(connector); 257 kfree(radeon_connector); 258 } 259 260 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = { 261 .dpms = drm_helper_connector_dpms, 262 .detect = radeon_dp_mst_detect, 263 .fill_modes = drm_helper_probe_single_connector_modes, 264 .destroy = radeon_dp_mst_connector_destroy, 265 }; 266 267 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 268 struct drm_dp_mst_port *port, 269 const char *pathprop) 270 { 271 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); 272 struct drm_device *dev = master->base.dev; 273 struct radeon_connector *radeon_connector; 274 struct drm_connector *connector; 275 276 radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL); 277 if (!radeon_connector) 278 return NULL; 279 280 radeon_connector->is_mst_connector = true; 281 connector = &radeon_connector->base; 282 radeon_connector->port = port; 283 radeon_connector->mst_port = master; 284 DRM_DEBUG_KMS("\n"); 285 286 drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); 287 drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs); 288 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master); 289 290 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); 291 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); 292 drm_mode_connector_set_path_property(connector, pathprop); 293 294 return connector; 295 } 296 297 static void radeon_dp_register_mst_connector(struct drm_connector *connector) 298 { 299 struct drm_device *dev = connector->dev; 300 struct radeon_device *rdev = dev->dev_private; 301 302 radeon_fb_add_connector(rdev, connector); 303 304 drm_connector_register(connector); 305 } 306 307 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 308 struct drm_connector *connector) 309 { 310 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); 311 struct drm_device *dev = master->base.dev; 312 struct radeon_device *rdev = dev->dev_private; 313 314 drm_connector_unregister(connector); 315 radeon_fb_remove_connector(rdev, connector); 316 drm_connector_cleanup(connector); 317 318 kfree(connector); 319 DRM_DEBUG_KMS("\n"); 320 } 321 322 static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) 323 { 324 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); 325 struct drm_device *dev = master->base.dev; 326 327 drm_kms_helper_hotplug_event(dev); 328 } 329 330 const struct drm_dp_mst_topology_cbs mst_cbs = { 331 .add_connector = radeon_dp_add_mst_connector, 332 .register_connector = radeon_dp_register_mst_connector, 333 .destroy_connector = radeon_dp_destroy_mst_connector, 334 .hotplug = radeon_dp_mst_hotplug, 335 }; 336 337 static struct radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder) 338 { 339 struct drm_device *dev = encoder->dev; 340 struct drm_connector *connector; 341 342 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 343 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 344 if (!connector->encoder) 345 continue; 346 if (!radeon_connector->is_mst_connector) 347 continue; 348 349 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder); 350 if (connector->encoder == encoder) 351 return radeon_connector; 352 } 353 return NULL; 354 } 355 356 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 357 { 358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 359 struct drm_device *dev = crtc->dev; 360 struct radeon_device *rdev = dev->dev_private; 361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); 362 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; 363 struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base); 364 int dp_clock; 365 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; 366 367 if (radeon_connector) { 368 radeon_connector->pixelclock_for_modeset = mode->clock; 369 if (radeon_connector->base.display_info.bpc) 370 radeon_crtc->bpc = radeon_connector->base.display_info.bpc; 371 else 372 radeon_crtc->bpc = 8; 373 } 374 375 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock); 376 dp_clock = dig_connector->dp_clock; 377 radeon_crtc->ss_enabled = 378 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 379 ASIC_INTERNAL_SS_ON_DP, 380 dp_clock); 381 } 382 383 static void 384 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) 385 { 386 struct drm_device *dev = encoder->dev; 387 struct radeon_device *rdev = dev->dev_private; 388 struct radeon_encoder *radeon_encoder, *primary; 389 struct radeon_encoder_mst *mst_enc; 390 struct radeon_encoder_atom_dig *dig_enc; 391 struct radeon_connector *radeon_connector; 392 struct drm_crtc *crtc; 393 struct radeon_crtc *radeon_crtc; 394 int ret, slots; 395 s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp; 396 if (!ASIC_IS_DCE5(rdev)) { 397 DRM_ERROR("got mst dpms on non-DCE5\n"); 398 return; 399 } 400 401 radeon_connector = radeon_mst_find_connector(encoder); 402 if (!radeon_connector) 403 return; 404 405 radeon_encoder = to_radeon_encoder(encoder); 406 407 mst_enc = radeon_encoder->enc_priv; 408 409 primary = mst_enc->primary; 410 411 dig_enc = primary->enc_priv; 412 413 crtc = encoder->crtc; 414 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links); 415 416 switch (mode) { 417 case DRM_MODE_DPMS_ON: 418 dig_enc->active_mst_links++; 419 420 radeon_crtc = to_radeon_crtc(crtc); 421 422 if (dig_enc->active_mst_links == 1) { 423 mst_enc->fe = dig_enc->dig_encoder; 424 mst_enc->fe_from_be = true; 425 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); 426 427 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0); 428 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, 429 0, 0, dig_enc->dig_encoder); 430 431 if (radeon_dp_needs_link_train(mst_enc->connector) || 432 dig_enc->active_mst_links == 1) { 433 radeon_dp_link_train(&primary->base, &mst_enc->connector->base); 434 } 435 436 } else { 437 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); 438 if (mst_enc->fe == -1) 439 DRM_ERROR("failed to get frontend for dig encoder\n"); 440 mst_enc->fe_from_be = false; 441 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); 442 } 443 444 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder, 445 dig_enc->linkb, radeon_crtc->crtc_id); 446 447 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr, 448 mst_enc->pbn); 449 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr, 450 radeon_connector->port, 451 mst_enc->pbn, slots); 452 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); 453 454 radeon_dp_mst_set_be_cntl(primary, mst_enc, 455 radeon_connector->mst_port->hpd.hpd, true); 456 457 mst_enc->enc_active = true; 458 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); 459 460 fixed_pbn = drm_int2fixp(mst_enc->pbn); 461 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div); 462 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot); 463 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp); 464 465 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, 466 mst_enc->fe); 467 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); 468 469 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); 470 471 break; 472 case DRM_MODE_DPMS_STANDBY: 473 case DRM_MODE_DPMS_SUSPEND: 474 case DRM_MODE_DPMS_OFF: 475 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links); 476 477 if (!mst_enc->enc_active) 478 return; 479 480 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port); 481 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); 482 483 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); 484 /* and this can also fail */ 485 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); 486 487 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port); 488 489 mst_enc->enc_active = false; 490 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); 491 492 radeon_dp_mst_set_be_cntl(primary, mst_enc, 493 radeon_connector->mst_port->hpd.hpd, false); 494 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, 495 mst_enc->fe); 496 497 if (!mst_enc->fe_from_be) 498 radeon_atom_release_dig_encoder(rdev, mst_enc->fe); 499 500 mst_enc->fe_from_be = false; 501 dig_enc->active_mst_links--; 502 if (dig_enc->active_mst_links == 0) { 503 /* drop link */ 504 } 505 506 break; 507 } 508 509 } 510 511 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder, 512 const struct drm_display_mode *mode, 513 struct drm_display_mode *adjusted_mode) 514 { 515 struct radeon_encoder_mst *mst_enc; 516 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 517 struct radeon_connector_atom_dig *dig_connector; 518 int bpp = 24; 519 520 mst_enc = radeon_encoder->enc_priv; 521 522 mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp); 523 524 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices; 525 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", 526 mst_enc->primary->active_device, mst_enc->primary->devices, 527 mst_enc->connector->devices, mst_enc->primary->base.encoder_type); 528 529 530 drm_mode_set_crtcinfo(adjusted_mode, 0); 531 dig_connector = mst_enc->connector->con_priv; 532 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); 533 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); 534 DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, 535 dig_connector->dp_lane_count, dig_connector->dp_clock); 536 return true; 537 } 538 539 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder) 540 { 541 struct radeon_connector *radeon_connector; 542 struct radeon_encoder *radeon_encoder, *primary; 543 struct radeon_encoder_mst *mst_enc; 544 struct radeon_encoder_atom_dig *dig_enc; 545 546 radeon_connector = radeon_mst_find_connector(encoder); 547 if (!radeon_connector) { 548 DRM_DEBUG_KMS("failed to find connector %p\n", encoder); 549 return; 550 } 551 radeon_encoder = to_radeon_encoder(encoder); 552 553 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 554 555 mst_enc = radeon_encoder->enc_priv; 556 557 primary = mst_enc->primary; 558 559 dig_enc = primary->enc_priv; 560 561 mst_enc->port = radeon_connector->port; 562 563 if (dig_enc->dig_encoder == -1) { 564 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); 565 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder); 566 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder); 567 568 569 } 570 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset); 571 } 572 573 static void 574 radeon_mst_encoder_mode_set(struct drm_encoder *encoder, 575 struct drm_display_mode *mode, 576 struct drm_display_mode *adjusted_mode) 577 { 578 DRM_DEBUG_KMS("\n"); 579 } 580 581 static void radeon_mst_encoder_commit(struct drm_encoder *encoder) 582 { 583 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 584 DRM_DEBUG_KMS("\n"); 585 } 586 587 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = { 588 .dpms = radeon_mst_encoder_dpms, 589 .mode_fixup = radeon_mst_mode_fixup, 590 .prepare = radeon_mst_encoder_prepare, 591 .mode_set = radeon_mst_encoder_mode_set, 592 .commit = radeon_mst_encoder_commit, 593 }; 594 595 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder) 596 { 597 drm_encoder_cleanup(encoder); 598 kfree(encoder); 599 } 600 601 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = { 602 .destroy = radeon_dp_mst_encoder_destroy, 603 }; 604 605 static struct radeon_encoder * 606 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector) 607 { 608 struct drm_device *dev = connector->base.dev; 609 struct radeon_device *rdev = dev->dev_private; 610 struct radeon_encoder *radeon_encoder; 611 struct radeon_encoder_mst *mst_enc; 612 struct drm_encoder *encoder; 613 const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private; 614 struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base); 615 616 DRM_DEBUG_KMS("enc master is %p\n", enc_master); 617 radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL); 618 if (!radeon_encoder) 619 return NULL; 620 621 radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL); 622 if (!radeon_encoder->enc_priv) { 623 kfree(radeon_encoder); 624 return NULL; 625 } 626 encoder = &radeon_encoder->base; 627 switch (rdev->num_crtc) { 628 case 1: 629 encoder->possible_crtcs = 0x1; 630 break; 631 case 2: 632 default: 633 encoder->possible_crtcs = 0x3; 634 break; 635 case 4: 636 encoder->possible_crtcs = 0xf; 637 break; 638 case 6: 639 encoder->possible_crtcs = 0x3f; 640 break; 641 } 642 643 drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs, 644 DRM_MODE_ENCODER_DPMST, NULL); 645 drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs); 646 647 mst_enc = radeon_encoder->enc_priv; 648 mst_enc->connector = connector; 649 mst_enc->primary = to_radeon_encoder(enc_master); 650 radeon_encoder->is_mst_encoder = true; 651 return radeon_encoder; 652 } 653 654 int 655 radeon_dp_mst_init(struct radeon_connector *radeon_connector) 656 { 657 struct drm_device *dev = radeon_connector->base.dev; 658 659 if (!radeon_connector->ddc_bus->has_aux) 660 return 0; 661 662 radeon_connector->mst_mgr.cbs = &mst_cbs; 663 return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, 664 &radeon_connector->ddc_bus->aux, 16, 6, 665 radeon_connector->base.base.id); 666 } 667 668 int 669 radeon_dp_mst_probe(struct radeon_connector *radeon_connector) 670 { 671 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 672 struct drm_device *dev = radeon_connector->base.dev; 673 struct radeon_device *rdev = dev->dev_private; 674 int ret; 675 u8 msg[1]; 676 677 if (!radeon_mst) 678 return 0; 679 680 if (!ASIC_IS_DCE5(rdev)) 681 return 0; 682 683 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) 684 return 0; 685 686 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg, 687 1); 688 if (ret) { 689 if (msg[0] & DP_MST_CAP) { 690 DRM_DEBUG_KMS("Sink is MST capable\n"); 691 dig_connector->is_mst = true; 692 } else { 693 DRM_DEBUG_KMS("Sink is not MST capable\n"); 694 dig_connector->is_mst = false; 695 } 696 697 } 698 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, 699 dig_connector->is_mst); 700 return dig_connector->is_mst; 701 } 702 703 int 704 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector) 705 { 706 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 707 int retry; 708 709 if (dig_connector->is_mst) { 710 u8 esi[16] = { 0 }; 711 int dret; 712 int ret = 0; 713 bool handled; 714 715 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, 716 DP_SINK_COUNT_ESI, esi, 8); 717 go_again: 718 if (dret == 8) { 719 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); 720 ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled); 721 722 if (handled) { 723 for (retry = 0; retry < 3; retry++) { 724 int wret; 725 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, 726 DP_SINK_COUNT_ESI + 1, &esi[1], 3); 727 if (wret == 3) 728 break; 729 } 730 731 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, 732 DP_SINK_COUNT_ESI, esi, 8); 733 if (dret == 8) { 734 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); 735 goto go_again; 736 } 737 } else 738 ret = 0; 739 740 return ret; 741 } else { 742 DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret); 743 dig_connector->is_mst = false; 744 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, 745 dig_connector->is_mst); 746 /* send a hotplug event */ 747 } 748 } 749 return -EINVAL; 750 } 751 752 #if defined(CONFIG_DEBUG_FS) 753 754 static int radeon_debugfs_mst_info(struct seq_file *m, void *data) 755 { 756 struct drm_info_node *node = (struct drm_info_node *)m->private; 757 struct drm_device *dev = node->minor->dev; 758 struct drm_connector *connector; 759 struct radeon_connector *radeon_connector; 760 struct radeon_connector_atom_dig *dig_connector; 761 int i; 762 763 drm_modeset_lock_all(dev); 764 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 765 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 766 continue; 767 768 radeon_connector = to_radeon_connector(connector); 769 dig_connector = radeon_connector->con_priv; 770 if (radeon_connector->is_mst_connector) 771 continue; 772 if (!dig_connector->is_mst) 773 continue; 774 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr); 775 776 for (i = 0; i < radeon_connector->enabled_attribs; i++) 777 seq_printf(m, "attrib %d: %d %d\n", i, 778 radeon_connector->cur_stream_attribs[i].fe, 779 radeon_connector->cur_stream_attribs[i].slots); 780 } 781 drm_modeset_unlock_all(dev); 782 return 0; 783 } 784 785 static struct drm_info_list radeon_debugfs_mst_list[] = { 786 {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL}, 787 }; 788 #endif 789 790 int radeon_mst_debugfs_init(struct radeon_device *rdev) 791 { 792 #if defined(CONFIG_DEBUG_FS) 793 return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1); 794 #endif 795 return 0; 796 } 797