1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/vga_switcheroo.h> 41 #include <drm/drm_gem.h> 42 #include <drm/drm_fb_helper.h> 43 44 #include "drm_crtc_helper.h" 45 #include "radeon_kfd.h" 46 47 /* 48 * KMS wrapper. 49 * - 2.0.0 - initial interface 50 * - 2.1.0 - add square tiling interface 51 * - 2.2.0 - add r6xx/r7xx const buffer support 52 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 53 * - 2.4.0 - add crtc id query 54 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 55 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 56 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 57 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 58 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 59 * 2.10.0 - fusion 2D tiling 60 * 2.11.0 - backend map, initial compute support for the CS checker 61 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 62 * 2.13.0 - virtual memory support, streamout 63 * 2.14.0 - add evergreen tiling informations 64 * 2.15.0 - add max_pipes query 65 * 2.16.0 - fix evergreen 2D tiled surface calculation 66 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 67 * 2.18.0 - r600-eg: allow "invalid" DB formats 68 * 2.19.0 - r600-eg: MSAA textures 69 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 70 * 2.21.0 - r600-r700: FMASK and CMASK 71 * 2.22.0 - r600 only: RESOLVE_BOX allowed 72 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 73 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 74 * 2.25.0 - eg+: new info request for num SE and num SH 75 * 2.26.0 - r600-eg: fix htile size computation 76 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 77 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 78 * 2.29.0 - R500 FP16 color clear registers 79 * 2.30.0 - fix for FMASK texturing 80 * 2.31.0 - Add fastfb support for rs690 81 * 2.32.0 - new info request for rings working 82 * 2.33.0 - Add SI tiling mode array query 83 * 2.34.0 - Add CIK tiling mode array query 84 * 2.35.0 - Add CIK macrotile mode array query 85 * 2.36.0 - Fix CIK DCE tiling setup 86 * 2.37.0 - allow GS ring setup on r6xx/r7xx 87 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 88 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 89 * 2.39.0 - Add INFO query for number of active CUs 90 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 91 * CS to GPU on >= r600 92 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 93 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 94 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 95 * 2.44.0 - SET_APPEND_CNT packet3 support 96 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 97 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 98 * 2.47.0 - Add UVD_NO_OP register support 99 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 100 */ 101 #define KMS_DRIVER_MAJOR 2 102 #define KMS_DRIVER_MINOR 48 103 #define KMS_DRIVER_PATCHLEVEL 0 104 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 105 int radeon_driver_unload_kms(struct drm_device *dev); 106 void radeon_driver_lastclose_kms(struct drm_device *dev); 107 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 108 void radeon_driver_postclose_kms(struct drm_device *dev, 109 struct drm_file *file_priv); 110 void radeon_driver_preclose_kms(struct drm_device *dev, 111 struct drm_file *file_priv); 112 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 113 bool fbcon, bool freeze); 114 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 115 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 116 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 117 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 118 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 119 int *max_error, 120 struct timeval *vblank_time, 121 unsigned flags); 122 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 123 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 124 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 125 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 126 void radeon_gem_object_free(struct drm_gem_object *obj); 127 int radeon_gem_object_open(struct drm_gem_object *obj, 128 struct drm_file *file_priv); 129 void radeon_gem_object_close(struct drm_gem_object *obj, 130 struct drm_file *file_priv); 131 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, 132 struct drm_gem_object *gobj, 133 int flags); 134 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 135 unsigned int flags, int *vpos, int *hpos, 136 ktime_t *stime, ktime_t *etime, 137 const struct drm_display_mode *mode); 138 extern bool radeon_is_px(struct drm_device *dev); 139 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 140 extern int radeon_max_kms_ioctl; 141 #ifdef DUMBBELL_WIP 142 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 143 #endif /* DUMBBELL_WIP */ 144 int radeon_mode_dumb_mmap(struct drm_file *filp, 145 struct drm_device *dev, 146 uint32_t handle, uint64_t *offset_p); 147 int radeon_mode_dumb_create(struct drm_file *file_priv, 148 struct drm_device *dev, 149 struct drm_mode_create_dumb *args); 150 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 151 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 152 struct dma_buf_attachment *, 153 struct sg_table *sg); 154 int radeon_gem_prime_pin(struct drm_gem_object *obj); 155 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 156 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 157 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 158 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 159 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 160 unsigned long arg); 161 162 /* atpx handler */ 163 #if defined(CONFIG_VGA_SWITCHEROO) 164 void radeon_register_atpx_handler(void); 165 void radeon_unregister_atpx_handler(void); 166 #else 167 static inline void radeon_register_atpx_handler(void) {} 168 static inline void radeon_unregister_atpx_handler(void) {} 169 #endif 170 171 int radeon_no_wb; 172 int radeon_modeset = -1; 173 int radeon_dynclks = -1; 174 int radeon_r4xx_atom = 0; 175 int radeon_agpmode = 0; 176 int radeon_vram_limit = 0; 177 int radeon_gart_size = -1; /* auto */ 178 int radeon_benchmarking = 0; 179 int radeon_testing = 0; 180 int radeon_connector_table = 0; 181 int radeon_tv = 1; 182 int radeon_audio = -1; 183 int radeon_disp_priority = 0; 184 #ifdef __DragonFly__ 185 int radeon_hw_i2c = 1; 186 #else 187 int radeon_hw_i2c = 0; 188 #endif 189 int radeon_pcie_gen2 = -1; 190 int radeon_msi = -1; 191 int radeon_lockup_timeout = 10000; 192 int radeon_fastfb = 0; 193 int radeon_dpm = -1; 194 int radeon_aspm = -1; 195 int radeon_runtime_pm = -1; 196 int radeon_hard_reset = 0; 197 int radeon_vm_size = 8; 198 int radeon_vm_block_size = -1; 199 int radeon_deep_color = 0; 200 int radeon_use_pflipirq = 2; 201 int radeon_bapm = -1; 202 int radeon_backlight = -1; 203 int radeon_auxch = -1; 204 int radeon_mst = 0; 205 int radeon_uvd = 1; 206 int radeon_vce = 1; 207 208 TUNABLE_INT("drm.radeon.no_wb", &radeon_no_wb); 209 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 210 module_param_named(no_wb, radeon_no_wb, int, 0444); 211 212 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 213 module_param_named(modeset, radeon_modeset, int, 0400); 214 215 TUNABLE_INT("drm.radeon.dynclks", &radeon_dynclks); 216 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 217 module_param_named(dynclks, radeon_dynclks, int, 0444); 218 219 TUNABLE_INT("drm.radeon.r4xx_atom", &radeon_r4xx_atom); 220 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 221 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 222 223 TUNABLE_INT("drm.radeon.vram_limit", &radeon_vram_limit); 224 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 225 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 226 227 TUNABLE_INT("drm.radeon.agpmode", &radeon_agpmode); 228 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 229 module_param_named(agpmode, radeon_agpmode, int, 0444); 230 231 TUNABLE_INT("drm.radeon.gart_size", &radeon_gart_size); 232 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 233 module_param_named(gartsize, radeon_gart_size, int, 0600); 234 235 TUNABLE_INT("drm.radeon.benchmarking", &radeon_benchmarking); 236 MODULE_PARM_DESC(benchmark, "Run benchmark"); 237 module_param_named(benchmark, radeon_benchmarking, int, 0444); 238 239 TUNABLE_INT("drm.radeon.testing", &radeon_testing); 240 MODULE_PARM_DESC(test, "Run tests"); 241 module_param_named(test, radeon_testing, int, 0444); 242 243 TUNABLE_INT("drm.radeon.connector_table", &radeon_connector_table); 244 MODULE_PARM_DESC(connector_table, "Force connector table"); 245 module_param_named(connector_table, radeon_connector_table, int, 0444); 246 247 TUNABLE_INT("drm.radeon.tv", &radeon_tv); 248 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 249 module_param_named(tv, radeon_tv, int, 0444); 250 251 TUNABLE_INT("drm.radeon.audio", &radeon_audio); 252 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 253 module_param_named(audio, radeon_audio, int, 0444); 254 255 TUNABLE_INT("drm.radeon.disp_priority", &radeon_disp_priority); 256 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 257 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 258 259 TUNABLE_INT("drm.radeon.hw_i2c", &radeon_hw_i2c); 260 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 261 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 262 263 TUNABLE_INT("drm.radeon.pcie_gen2", &radeon_pcie_gen2); 264 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 265 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 266 267 TUNABLE_INT("drm.radeon.msi", &radeon_msi); 268 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 269 module_param_named(msi, radeon_msi, int, 0444); 270 271 TUNABLE_INT("drm.radeon.lockup_timeout", &radeon_lockup_timeout); 272 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 273 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 274 275 TUNABLE_INT("drm.radeon.fastfb", &radeon_fastfb); 276 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 277 module_param_named(fastfb, radeon_fastfb, int, 0444); 278 279 TUNABLE_INT("drm.radeon.dpm", &radeon_dpm); 280 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 281 module_param_named(dpm, radeon_dpm, int, 0444); 282 283 TUNABLE_INT("drm.radeon.aspm", &radeon_aspm); 284 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 285 module_param_named(aspm, radeon_aspm, int, 0444); 286 287 TUNABLE_INT("drm.radeon.runtime_pm", &radeon_runtime_pm); /* careful with this */ 288 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 289 module_param_named(runpm, radeon_runtime_pm, int, 0444); 290 291 TUNABLE_INT("drm.radeon.hard_reset", &radeon_hard_reset); /* very careful with this */ 292 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 293 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 294 295 TUNABLE_INT("drm.radeon.vm_size", &radeon_vm_size); 296 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 297 module_param_named(vm_size, radeon_vm_size, int, 0444); 298 299 TUNABLE_INT("drm.radeon.vm_block_size", &radeon_vm_block_size); 300 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 301 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 302 303 TUNABLE_INT("drm.radeon.deep_color", &radeon_deep_color); 304 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 305 module_param_named(deep_color, radeon_deep_color, int, 0444); 306 307 TUNABLE_INT("drm.radeon.use_pflipirq", &radeon_use_pflipirq); 308 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 309 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 310 311 TUNABLE_INT("drm.radeon.bapm", &radeon_bapm); 312 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 313 module_param_named(bapm, radeon_bapm, int, 0444); 314 315 TUNABLE_INT("drm.radeon.backlight", &radeon_backlight); 316 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 317 module_param_named(backlight, radeon_backlight, int, 0444); 318 319 TUNABLE_INT("drm.radeon.auxch", &radeon_auxch); 320 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 321 module_param_named(auxch, radeon_auxch, int, 0444); 322 323 TUNABLE_INT("drm.radeon.mst", &radeon_mst); 324 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 325 module_param_named(mst, radeon_mst, int, 0444); 326 327 TUNABLE_INT("drm.radeon.uvd", &radeon_uvd); 328 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 329 module_param_named(uvd, radeon_uvd, int, 0444); 330 331 TUNABLE_INT("drm.radeon.vce", &radeon_vce); 332 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 333 module_param_named(vce, radeon_vce, int, 0444); 334 335 static struct pci_device_id pciidlist[] = { 336 radeon_PCI_IDS 337 }; 338 339 MODULE_DEVICE_TABLE(pci, pciidlist); 340 341 static struct drm_driver kms_driver; 342 343 bool radeon_device_is_virtual(void); 344 345 #ifdef DUMBBELL_WIP 346 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 347 { 348 struct apertures_struct *ap; 349 bool primary = false; 350 351 ap = alloc_apertures(1); 352 if (!ap) 353 return -ENOMEM; 354 355 ap->ranges[0].base = pci_resource_start(pdev, 0); 356 ap->ranges[0].size = pci_resource_len(pdev, 0); 357 358 #ifdef CONFIG_X86 359 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 360 #endif 361 drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 362 kfree(ap); 363 364 return 0; 365 } 366 #endif /* DUMBBELL_WIP */ 367 368 static int radeon_pci_probe(struct pci_dev *pdev, 369 const struct pci_device_id *ent) 370 { 371 #if 0 372 int ret; 373 374 /* 375 * Initialize amdkfd before starting radeon. If it was not loaded yet, 376 * defer radeon probing 377 */ 378 ret = radeon_kfd_init(); 379 if (ret == -EPROBE_DEFER) 380 return ret; 381 382 if (vga_switcheroo_client_probe_defer(pdev)) 383 return -EPROBE_DEFER; 384 385 /* Get rid of things like offb */ 386 ret = radeon_kick_out_firmware_fb(pdev); 387 if (ret) 388 return ret; 389 #endif 390 391 return drm_get_pci_dev(pdev, ent, &kms_driver); 392 } 393 394 #ifdef DUMBBELL_WIP 395 static void 396 radeon_pci_remove(struct pci_dev *pdev) 397 { 398 struct drm_device *dev = pci_get_drvdata(pdev); 399 400 drm_put_dev(dev); 401 } 402 403 static void 404 radeon_pci_shutdown(struct pci_dev *pdev) 405 { 406 /* if we are running in a VM, make sure the device 407 * torn down properly on reboot/shutdown. 408 * unfortunately we can't detect certain 409 * hypervisors so just do this all the time. 410 */ 411 radeon_pci_remove(pdev); 412 } 413 414 static int radeon_pmops_suspend(struct device *dev) 415 { 416 struct pci_dev *pdev = to_pci_dev(dev); 417 struct drm_device *drm_dev = pci_get_drvdata(pdev); 418 return radeon_suspend_kms(drm_dev, true, true, false); 419 } 420 421 static int radeon_pmops_resume(struct device *dev) 422 { 423 struct pci_dev *pdev = to_pci_dev(dev); 424 struct drm_device *drm_dev = pci_get_drvdata(pdev); 425 426 /* GPU comes up enabled by the bios on resume */ 427 if (radeon_is_px(drm_dev)) { 428 pm_runtime_disable(dev); 429 pm_runtime_set_active(dev); 430 pm_runtime_enable(dev); 431 } 432 433 return radeon_resume_kms(drm_dev, true, true); 434 } 435 436 static int radeon_pmops_freeze(struct device *dev) 437 { 438 struct pci_dev *pdev = to_pci_dev(dev); 439 struct drm_device *drm_dev = pci_get_drvdata(pdev); 440 return radeon_suspend_kms(drm_dev, false, true, true); 441 } 442 443 static int radeon_pmops_thaw(struct device *dev) 444 { 445 struct pci_dev *pdev = to_pci_dev(dev); 446 struct drm_device *drm_dev = pci_get_drvdata(pdev); 447 return radeon_resume_kms(drm_dev, false, true); 448 } 449 450 static int radeon_pmops_runtime_suspend(struct device *dev) 451 { 452 struct pci_dev *pdev = to_pci_dev(dev); 453 struct drm_device *drm_dev = pci_get_drvdata(pdev); 454 int ret; 455 456 if (!radeon_is_px(drm_dev)) { 457 pm_runtime_forbid(dev); 458 return -EBUSY; 459 } 460 461 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 462 drm_kms_helper_poll_disable(drm_dev); 463 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 464 465 ret = radeon_suspend_kms(drm_dev, false, false, false); 466 pci_save_state(pdev); 467 pci_disable_device(pdev); 468 pci_ignore_hotplug(pdev); 469 if (radeon_is_atpx_hybrid()) 470 pci_set_power_state(pdev, PCI_D3cold); 471 else if (!radeon_has_atpx_dgpu_power_cntl()) 472 pci_set_power_state(pdev, PCI_D3hot); 473 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 474 475 return 0; 476 } 477 478 static int radeon_pmops_runtime_resume(struct device *dev) 479 { 480 struct pci_dev *pdev = to_pci_dev(dev); 481 struct drm_device *drm_dev = pci_get_drvdata(pdev); 482 int ret; 483 484 if (!radeon_is_px(drm_dev)) 485 return -EINVAL; 486 487 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 488 489 if (radeon_is_atpx_hybrid() || 490 !radeon_has_atpx_dgpu_power_cntl()) 491 pci_set_power_state(pdev, PCI_D0); 492 pci_restore_state(pdev); 493 ret = pci_enable_device(pdev); 494 if (ret) 495 return ret; 496 pci_set_master(pdev); 497 498 ret = radeon_resume_kms(drm_dev, false, false); 499 drm_kms_helper_poll_enable(drm_dev); 500 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 501 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 502 return 0; 503 } 504 505 static int radeon_pmops_runtime_idle(struct device *dev) 506 { 507 struct pci_dev *pdev = to_pci_dev(dev); 508 struct drm_device *drm_dev = pci_get_drvdata(pdev); 509 struct drm_crtc *crtc; 510 511 if (!radeon_is_px(drm_dev)) { 512 pm_runtime_forbid(dev); 513 return -EBUSY; 514 } 515 516 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 517 if (crtc->enabled) { 518 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 519 return -EBUSY; 520 } 521 } 522 523 pm_runtime_mark_last_busy(dev); 524 pm_runtime_autosuspend(dev); 525 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 526 return 1; 527 } 528 529 long radeon_drm_ioctl(struct file *filp, 530 unsigned int cmd, unsigned long arg) 531 { 532 struct drm_file *file_priv = filp->private_data; 533 struct drm_device *dev; 534 long ret; 535 dev = file_priv->minor->dev; 536 ret = pm_runtime_get_sync(dev->dev); 537 if (ret < 0) 538 return ret; 539 540 ret = drm_ioctl(filp, cmd, arg); 541 542 pm_runtime_mark_last_busy(dev->dev); 543 pm_runtime_put_autosuspend(dev->dev); 544 return ret; 545 } 546 547 static const struct dev_pm_ops radeon_pm_ops = { 548 .suspend = radeon_pmops_suspend, 549 .resume = radeon_pmops_resume, 550 .freeze = radeon_pmops_freeze, 551 .thaw = radeon_pmops_thaw, 552 .poweroff = radeon_pmops_freeze, 553 .restore = radeon_pmops_resume, 554 .runtime_suspend = radeon_pmops_runtime_suspend, 555 .runtime_resume = radeon_pmops_runtime_resume, 556 .runtime_idle = radeon_pmops_runtime_idle, 557 }; 558 #endif /* DUMBBELL_WIP */ 559 560 static const struct file_operations radeon_driver_kms_fops = { 561 .owner = THIS_MODULE, 562 #if 0 563 .open = drm_open, 564 .release = drm_release, 565 .unlocked_ioctl = radeon_drm_ioctl, 566 .mmap = radeon_mmap, 567 .poll = drm_poll, 568 .read = drm_read, 569 #endif 570 #ifdef CONFIG_COMPAT 571 .compat_ioctl = radeon_kms_compat_ioctl, 572 #endif 573 }; 574 575 static int radeon_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 576 struct sysctl_oid *top) 577 { 578 return drm_add_busid_modesetting(dev, ctx, top); 579 } 580 581 static struct drm_driver kms_driver = { 582 .driver_features = 583 DRIVER_USE_AGP | 584 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 585 DRIVER_PRIME | DRIVER_RENDER, 586 .load = radeon_driver_load_kms, 587 .open = radeon_driver_open_kms, 588 .preclose = radeon_driver_preclose_kms, 589 .postclose = radeon_driver_postclose_kms, 590 .lastclose = radeon_driver_lastclose_kms, 591 .set_busid = drm_pci_set_busid, 592 .unload = radeon_driver_unload_kms, 593 .get_vblank_counter = radeon_get_vblank_counter_kms, 594 .enable_vblank = radeon_enable_vblank_kms, 595 .disable_vblank = radeon_disable_vblank_kms, 596 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 597 .get_scanout_position = radeon_get_crtc_scanoutpos, 598 .irq_preinstall = radeon_driver_irq_preinstall_kms, 599 .irq_postinstall = radeon_driver_irq_postinstall_kms, 600 .irq_uninstall = radeon_driver_irq_uninstall_kms, 601 .irq_handler = radeon_driver_irq_handler_kms, 602 .sysctl_init = radeon_sysctl_init, 603 .ioctls = radeon_ioctls_kms, 604 .gem_free_object_unlocked = radeon_gem_object_free, 605 .gem_open_object = radeon_gem_object_open, 606 .gem_close_object = radeon_gem_object_close, 607 .dumb_create = radeon_mode_dumb_create, 608 .dumb_map_offset = radeon_mode_dumb_mmap, 609 .dumb_destroy = drm_gem_dumb_destroy, 610 .fops = &radeon_driver_kms_fops, 611 612 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 613 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 614 .gem_prime_export = radeon_gem_prime_export, 615 .gem_prime_import = drm_gem_prime_import, 616 .gem_prime_pin = radeon_gem_prime_pin, 617 .gem_prime_unpin = radeon_gem_prime_unpin, 618 .gem_prime_res_obj = radeon_gem_prime_res_obj, 619 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 620 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 621 .gem_prime_vmap = radeon_gem_prime_vmap, 622 .gem_prime_vunmap = radeon_gem_prime_vunmap, 623 624 .name = DRIVER_NAME, 625 .desc = DRIVER_DESC, 626 .date = DRIVER_DATE, 627 .major = KMS_DRIVER_MAJOR, 628 .minor = KMS_DRIVER_MINOR, 629 .patchlevel = KMS_DRIVER_PATCHLEVEL, 630 }; 631 632 static struct drm_driver *driver; 633 static struct pci_driver *pdriver; 634 635 #ifdef CONFIG_DRM_RADEON_UMS 636 static struct pci_driver radeon_pci_driver = { 637 .name = DRIVER_NAME, 638 .id_table = pciidlist, 639 }; 640 #endif 641 642 static struct pci_driver radeon_kms_pci_driver = { 643 #if 0 644 .name = DRIVER_NAME, 645 .id_table = pciidlist, 646 .probe = radeon_pci_probe, 647 .remove = radeon_pci_remove, 648 .shutdown = radeon_pci_shutdown, 649 .driver.pm = &radeon_pm_ops, 650 #endif 651 }; 652 653 static int __init radeon_init(void) 654 { 655 if (vgacon_text_force() && radeon_modeset == -1) { 656 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 657 radeon_modeset = 0; 658 } 659 /* set to modesetting by default if not nomodeset */ 660 if (radeon_modeset == -1) 661 radeon_modeset = 1; 662 663 if (radeon_modeset == 1) { 664 DRM_INFO("radeon kernel modesetting enabled.\n"); 665 driver = &kms_driver; 666 pdriver = &radeon_kms_pci_driver; 667 driver->driver_features |= DRIVER_MODESET; 668 driver->num_ioctls = radeon_max_kms_ioctl; 669 radeon_register_atpx_handler(); 670 671 } else { 672 DRM_ERROR("No UMS support in radeon module!\n"); 673 return -EINVAL; 674 } 675 676 /* let modprobe override vga console setting */ 677 return drm_pci_init(driver, pdriver); 678 } 679 680 static void __exit radeon_exit(void) 681 { 682 radeon_kfd_fini(); 683 #if 0 684 drm_pci_exit(driver, pdriver); 685 #endif 686 radeon_unregister_atpx_handler(); 687 } 688 689 /* =================================================================== */ 690 691 static int 692 radeon_pci_probe_dfly(device_t kdev) 693 { 694 int device, i = 0; 695 const struct pci_device_id *ent; 696 static struct pci_dev *pdev = NULL; 697 static device_t bsddev; 698 699 if (pci_get_class(kdev) != PCIC_DISPLAY) 700 return ENXIO; 701 702 if (pci_get_vendor(kdev) != PCI_VENDOR_ID_ATI) 703 return ENXIO; 704 705 device = pci_get_device(kdev); 706 707 for (i = 0; pciidlist[i].device != 0; i++) { 708 if (pciidlist[i].device == device) { 709 ent = &pciidlist[i]; 710 goto found; 711 } 712 } 713 714 return ENXIO; 715 found: 716 if (!strcmp(device_get_name(kdev), "drmsub")) 717 bsddev = device_get_parent(kdev); 718 else 719 bsddev = kdev; 720 721 drm_init_pdev(bsddev, &pdev); 722 723 /* Print the contents of pdev struct. */ 724 drm_print_pdev(pdev); 725 726 return radeon_pci_probe(pdev, ent); 727 } 728 729 static int radeon_driver_attach(device_t kdev) 730 { 731 return 0; 732 } 733 734 static int 735 radeon_suspend(device_t kdev) 736 { 737 struct drm_softc *softc = device_get_softc(kdev); 738 struct drm_device *dev = softc->drm_driver_data; 739 740 return -radeon_suspend_kms(dev, true, true, false); 741 } 742 743 static int 744 radeon_resume(device_t kdev) 745 { 746 struct drm_softc *softc = device_get_softc(kdev); 747 struct drm_device *dev = softc->drm_driver_data; 748 749 return -radeon_resume_kms(dev, true, true); 750 } 751 752 static device_method_t radeon_methods[] = { 753 /* Device interface */ 754 DEVMETHOD(device_probe, radeon_pci_probe_dfly), 755 DEVMETHOD(device_attach, radeon_driver_attach), 756 DEVMETHOD(device_suspend, radeon_suspend), 757 DEVMETHOD(device_resume, radeon_resume), 758 DEVMETHOD(device_detach, drm_device_detach), 759 DEVMETHOD_END 760 }; 761 762 static driver_t radeon_driver = { 763 "drm", 764 radeon_methods, 765 sizeof(struct drm_softc) 766 }; 767 768 module_init(radeon_init); 769 module_exit(radeon_exit); 770 771 extern devclass_t drm_devclass; 772 DRIVER_MODULE_ORDERED(radeon, vgapci, radeon_driver, drm_devclass, 773 NULL, NULL, SI_ORDER_ANY); 774 MODULE_DEPEND(radeon, drm, 1, 1, 1); 775 #ifdef CONFIG_ACPI 776 MODULE_DEPEND(radeon, acpi, 1, 1, 1); 777 #endif 778