1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 * 31 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_drv.c 254885 2013-08-25 19:37:15Z dumbbell $ 32 */ 33 34 #include <drm/drmP.h> 35 #include <uapi_drm/radeon_drm.h> 36 #include "radeon_drv.h" 37 #include "radeon_gem.h" 38 #include "radeon_kms.h" 39 #include "radeon_irq_kms.h" 40 41 #include <drm/drm_pciids.h> 42 #include <linux/module.h> 43 #ifdef PM_TODO 44 #include <linux/pm_runtime.h> 45 #include <linux/vga_switcheroo.h> 46 #endif 47 48 #include <drm/drm_gem.h> 49 50 #include "drm/drm_crtc_helper.h" 51 /* 52 * KMS wrapper. 53 * - 2.0.0 - initial interface 54 * - 2.1.0 - add square tiling interface 55 * - 2.2.0 - add r6xx/r7xx const buffer support 56 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 57 * - 2.4.0 - add crtc id query 58 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 59 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 60 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 61 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 62 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 63 * 2.10.0 - fusion 2D tiling 64 * 2.11.0 - backend map, initial compute support for the CS checker 65 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 66 * 2.13.0 - virtual memory support, streamout 67 * 2.14.0 - add evergreen tiling informations 68 * 2.15.0 - add max_pipes query 69 * 2.16.0 - fix evergreen 2D tiled surface calculation 70 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 71 * 2.18.0 - r600-eg: allow "invalid" DB formats 72 * 2.19.0 - r600-eg: MSAA textures 73 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 74 * 2.21.0 - r600-r700: FMASK and CMASK 75 * 2.22.0 - r600 only: RESOLVE_BOX allowed 76 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 77 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 78 * 2.25.0 - eg+: new info request for num SE and num SH 79 * 2.26.0 - r600-eg: fix htile size computation 80 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 81 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 82 * 2.29.0 - R500 FP16 color clear registers 83 * 2.30.0 - fix for FMASK texturing 84 * 2.31.0 - Add fastfb support for rs690 85 * 2.32.0 - new info request for rings working 86 * 2.33.0 - Add SI tiling mode array query 87 * 2.34.0 - Add CIK tiling mode array query 88 * 2.35.0 - Add CIK macrotile mode array query 89 * 2.36.0 - Fix CIK DCE tiling setup 90 * 2.37.0 - allow GS ring setup on r6xx/r7xx 91 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 92 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 93 * 2.39.0 - Add INFO query for number of active CUs 94 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 95 * CS to GPU on >= r600 96 */ 97 #define KMS_DRIVER_MAJOR 2 98 #define KMS_DRIVER_MINOR 40 99 #define KMS_DRIVER_PATCHLEVEL 0 100 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 101 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 102 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 103 unsigned int flags, 104 int *vpos, int *hpos, ktime_t *stime, 105 ktime_t *etime); 106 extern bool radeon_is_px(struct drm_device *dev); 107 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 108 extern int radeon_max_kms_ioctl; 109 #ifdef DUMBBELL_WIP 110 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 111 #endif /* DUMBBELL_WIP */ 112 int radeon_mode_dumb_mmap(struct drm_file *filp, 113 struct drm_device *dev, 114 uint32_t handle, uint64_t *offset_p); 115 int radeon_mode_dumb_create(struct drm_file *file_priv, 116 struct drm_device *dev, 117 struct drm_mode_create_dumb *args); 118 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 119 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 120 size_t size, 121 struct sg_table *sg); 122 int radeon_gem_prime_pin(struct drm_gem_object *obj); 123 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 124 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 125 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 126 127 #if defined(CONFIG_DEBUG_FS) 128 int radeon_debugfs_init(struct drm_minor *minor); 129 void radeon_debugfs_cleanup(struct drm_minor *minor); 130 #endif 131 132 /* atpx handler */ 133 #if defined(CONFIG_VGA_SWITCHEROO) 134 void radeon_register_atpx_handler(void); 135 void radeon_unregister_atpx_handler(void); 136 #else 137 static inline void radeon_register_atpx_handler(void) {} 138 static inline void radeon_unregister_atpx_handler(void) {} 139 #endif 140 141 int radeon_no_wb; 142 int radeon_modeset = 1; 143 int radeon_dynclks = -1; 144 int radeon_r4xx_atom = 0; 145 int radeon_agpmode = 0; 146 int radeon_vram_limit = 0; 147 int radeon_gart_size = -1; /* auto */ 148 int radeon_benchmarking = 0; 149 int radeon_testing = 0; 150 int radeon_connector_table = 0; 151 int radeon_tv = 1; 152 int radeon_audio = -1; 153 int radeon_disp_priority = 0; 154 int radeon_hw_i2c = 0; 155 int radeon_pcie_gen2 = -1; 156 int radeon_msi = -1; 157 int radeon_lockup_timeout = 10000; 158 int radeon_fastfb = 0; 159 int radeon_dpm = -1; 160 int radeon_aspm = -1; 161 int radeon_runtime_pm = -1; 162 int radeon_hard_reset = 0; 163 int radeon_vm_size = 8; 164 int radeon_vm_block_size = -1; 165 int radeon_deep_color = 0; 166 int radeon_use_pflipirq = 2; 167 int radeon_bapm = -1; 168 int radeon_backlight = -1; 169 170 TUNABLE_INT("drm.radeon.no_wb", &radeon_no_wb); 171 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 172 module_param_named(no_wb, radeon_no_wb, int, 0444); 173 174 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 175 module_param_named(modeset, radeon_modeset, int, 0400); 176 177 TUNABLE_INT("drm.radeon.dynclks", &radeon_dynclks); 178 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 179 module_param_named(dynclks, radeon_dynclks, int, 0444); 180 181 TUNABLE_INT("drm.radeon.r4xx_atom", &radeon_r4xx_atom); 182 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 183 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 184 185 TUNABLE_INT("drm.radeon.vram_limit", &radeon_vram_limit); 186 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 187 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 188 189 TUNABLE_INT("drm.radeon.agpmode", &radeon_agpmode); 190 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 191 module_param_named(agpmode, radeon_agpmode, int, 0444); 192 193 TUNABLE_INT("drm.radeon.gart_size", &radeon_gart_size); 194 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 195 module_param_named(gartsize, radeon_gart_size, int, 0600); 196 197 TUNABLE_INT("drm.radeon.benchmarking", &radeon_benchmarking); 198 MODULE_PARM_DESC(benchmark, "Run benchmark"); 199 module_param_named(benchmark, radeon_benchmarking, int, 0444); 200 201 TUNABLE_INT("drm.radeon.testing", &radeon_testing); 202 MODULE_PARM_DESC(test, "Run tests"); 203 module_param_named(test, radeon_testing, int, 0444); 204 205 TUNABLE_INT("drm.radeon.connector_table", &radeon_connector_table); 206 MODULE_PARM_DESC(connector_table, "Force connector table"); 207 module_param_named(connector_table, radeon_connector_table, int, 0444); 208 209 TUNABLE_INT("drm.radeon.tv", &radeon_tv); 210 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 211 module_param_named(tv, radeon_tv, int, 0444); 212 213 TUNABLE_INT("drm.radeon.audio", &radeon_audio); 214 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 215 module_param_named(audio, radeon_audio, int, 0444); 216 217 TUNABLE_INT("drm.radeon.disp_priority", &radeon_disp_priority); 218 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 219 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 220 221 TUNABLE_INT("drm.radeon.hw_i2c", &radeon_hw_i2c); 222 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 223 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 224 225 TUNABLE_INT("drm.radeon.pcie_gen2", &radeon_pcie_gen2); 226 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 227 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 228 229 TUNABLE_INT("drm.radeon.msi", &radeon_msi); 230 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 231 module_param_named(msi, radeon_msi, int, 0444); 232 233 TUNABLE_INT("drm.radeon.lockup_timeout", &radeon_lockup_timeout); 234 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 235 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 236 237 TUNABLE_INT("drm.radeon.fastfb", &radeon_fastfb); 238 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 239 module_param_named(fastfb, radeon_fastfb, int, 0444); 240 241 TUNABLE_INT("drm.radeon.dpm", &radeon_dpm); 242 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 243 module_param_named(dpm, radeon_dpm, int, 0444); 244 245 TUNABLE_INT("drm.radeon.aspm", &radeon_aspm); 246 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 247 module_param_named(aspm, radeon_aspm, int, 0444); 248 249 TUNABLE_INT("drm.radeon.runtime_pm", &radeon_runtime_pm); /* careful with this */ 250 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 251 module_param_named(runpm, radeon_runtime_pm, int, 0444); 252 253 TUNABLE_INT("drm.radeon.hard_reset", &radeon_hard_reset); /* very careful with this */ 254 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 255 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 256 257 TUNABLE_INT("drm.radeon.vm_size", &radeon_vm_size); 258 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 259 module_param_named(vm_size, radeon_vm_size, int, 0444); 260 261 TUNABLE_INT("drm.radeon.vm_block_size", &radeon_vm_block_size); 262 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 263 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 264 265 TUNABLE_INT("drm.radeon.deep_color", &radeon_deep_color); 266 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 267 module_param_named(deep_color, radeon_deep_color, int, 0444); 268 269 TUNABLE_INT("drm.radeon.use_pflipirq", &radeon_use_pflipirq); 270 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 271 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 272 273 TUNABLE_INT("drm.radeon.bapm", &radeon_bapm); 274 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 275 module_param_named(bapm, radeon_bapm, int, 0444); 276 277 TUNABLE_INT("drm.radeon.backlight", &radeon_backlight); 278 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 279 module_param_named(backlight, radeon_backlight, int, 0444); 280 281 static drm_pci_id_list_t pciidlist[] = { 282 radeon_PCI_IDS 283 }; 284 285 #ifdef CONFIG_DRM_RADEON_UMS 286 287 #ifdef DUMBBELL_WIP 288 289 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 290 { 291 drm_radeon_private_t *dev_priv = dev->dev_private; 292 293 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 294 return 0; 295 296 /* Disable *all* interrupts */ 297 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 298 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 299 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 300 return 0; 301 } 302 303 static int radeon_resume(struct drm_device *dev) 304 { 305 drm_radeon_private_t *dev_priv = dev->dev_private; 306 307 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 308 return 0; 309 310 /* Restore interrupt registers */ 311 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 312 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 313 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 314 return 0; 315 } 316 #endif /* DUMBBELL_WIP */ 317 318 #ifdef DUMBBELL_WIP 319 static const struct file_operations radeon_driver_old_fops = { 320 .owner = THIS_MODULE, 321 .open = drm_open, 322 .release = drm_release, 323 .unlocked_ioctl = drm_ioctl, 324 .mmap = drm_mmap, 325 .poll = drm_poll, 326 .read = drm_read, 327 #ifdef CONFIG_COMPAT 328 .compat_ioctl = radeon_compat_ioctl, 329 #endif 330 .llseek = noop_llseek, 331 }; 332 333 static struct drm_driver driver_old = { 334 .driver_features = 335 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | 336 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 337 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 338 .load = radeon_driver_load, 339 .firstopen = radeon_driver_firstopen, 340 .open = radeon_driver_open, 341 .preclose = radeon_driver_preclose, 342 .postclose = radeon_driver_postclose, 343 .lastclose = radeon_driver_lastclose, 344 .unload = radeon_driver_unload, 345 #ifdef DUMBBELL_WIP 346 .suspend = radeon_suspend, 347 .resume = radeon_resume, 348 #endif /* DUMBBELL_WIP */ 349 .get_vblank_counter = radeon_get_vblank_counter, 350 .enable_vblank = radeon_enable_vblank, 351 .disable_vblank = radeon_disable_vblank, 352 .master_create = radeon_master_create, 353 .master_destroy = radeon_master_destroy, 354 .irq_preinstall = radeon_driver_irq_preinstall, 355 .irq_postinstall = radeon_driver_irq_postinstall, 356 .irq_uninstall = radeon_driver_irq_uninstall, 357 .irq_handler = radeon_driver_irq_handler, 358 .ioctls = radeon_ioctls, 359 .dma_ioctl = radeon_cp_buffers, 360 .fops = &radeon_driver_old_fops, 361 .name = DRIVER_NAME, 362 .desc = DRIVER_DESC, 363 .date = DRIVER_DATE, 364 .major = DRIVER_MAJOR, 365 .minor = DRIVER_MINOR, 366 .patchlevel = DRIVER_PATCHLEVEL, 367 }; 368 #endif /* DUMBBELL_WIP */ 369 370 #endif 371 372 static struct drm_driver kms_driver; 373 374 #ifdef DUMBBELL_WIP 375 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 376 { 377 struct apertures_struct *ap; 378 bool primary = false; 379 380 ap = alloc_apertures(1); 381 if (!ap) 382 return -ENOMEM; 383 384 ap->ranges[0].base = pci_resource_start(pdev, 0); 385 ap->ranges[0].size = pci_resource_len(pdev, 0); 386 387 #ifdef CONFIG_X86 388 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 389 #endif 390 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 391 kfree(ap); 392 393 return 0; 394 } 395 396 static int radeon_pci_probe(struct pci_dev *pdev, 397 const struct pci_device_id *ent) 398 { 399 int ret; 400 401 /* Get rid of things like offb */ 402 ret = radeon_kick_out_firmware_fb(pdev); 403 if (ret) 404 return ret; 405 406 return drm_get_pci_dev(pdev, ent, &kms_driver); 407 } 408 409 static void 410 radeon_pci_remove(struct pci_dev *pdev) 411 { 412 struct drm_device *dev = pci_get_drvdata(pdev); 413 414 drm_put_dev(dev); 415 } 416 417 static int radeon_pmops_suspend(struct device *dev) 418 { 419 struct pci_dev *pdev = to_pci_dev(dev); 420 struct drm_device *drm_dev = pci_get_drvdata(pdev); 421 return radeon_suspend_kms(drm_dev, true, true); 422 } 423 424 static int radeon_pmops_resume(struct device *dev) 425 { 426 struct pci_dev *pdev = to_pci_dev(dev); 427 struct drm_device *drm_dev = pci_get_drvdata(pdev); 428 return radeon_resume_kms(drm_dev, true, true); 429 } 430 431 static int radeon_pmops_freeze(struct device *dev) 432 { 433 struct pci_dev *pdev = to_pci_dev(dev); 434 struct drm_device *drm_dev = pci_get_drvdata(pdev); 435 return radeon_suspend_kms(drm_dev, false, true); 436 } 437 438 static int radeon_pmops_thaw(struct device *dev) 439 { 440 struct pci_dev *pdev = to_pci_dev(dev); 441 struct drm_device *drm_dev = pci_get_drvdata(pdev); 442 return radeon_resume_kms(drm_dev, false, true); 443 } 444 445 static int radeon_pmops_runtime_suspend(struct device *dev) 446 { 447 struct pci_dev *pdev = to_pci_dev(dev); 448 struct drm_device *drm_dev = pci_get_drvdata(pdev); 449 int ret; 450 451 if (!radeon_is_px(drm_dev)) { 452 #ifdef PM_TODO 453 pm_runtime_forbid(dev); 454 #endif 455 return -EBUSY; 456 } 457 458 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 459 drm_kms_helper_poll_disable(drm_dev); 460 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 461 462 ret = radeon_suspend_kms(drm_dev, false, false); 463 pci_save_state(pdev); 464 pci_disable_device(pdev); 465 pci_set_power_state(pdev, PCI_D3cold); 466 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 467 468 return 0; 469 } 470 471 static int radeon_pmops_runtime_resume(struct device *dev) 472 { 473 struct pci_dev *pdev = to_pci_dev(dev); 474 struct drm_device *drm_dev = pci_get_drvdata(pdev); 475 int ret; 476 477 if (!radeon_is_px(drm_dev)) 478 return -EINVAL; 479 480 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 481 482 pci_set_power_state(pdev, PCI_D0); 483 pci_restore_state(pdev); 484 ret = pci_enable_device(pdev); 485 if (ret) 486 return ret; 487 pci_set_master(pdev); 488 489 ret = radeon_resume_kms(drm_dev, false, false); 490 drm_kms_helper_poll_enable(drm_dev); 491 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 492 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 493 return 0; 494 } 495 496 static int radeon_pmops_runtime_idle(struct device *dev) 497 { 498 struct pci_dev *pdev = to_pci_dev(dev); 499 struct drm_device *drm_dev = pci_get_drvdata(pdev); 500 struct drm_crtc *crtc; 501 502 if (!radeon_is_px(drm_dev)) { 503 #ifdef PM_TODO 504 pm_runtime_forbid(dev); 505 #endif 506 return -EBUSY; 507 } 508 509 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 510 if (crtc->enabled) { 511 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 512 return -EBUSY; 513 } 514 } 515 516 pm_runtime_mark_last_busy(dev); 517 pm_runtime_autosuspend(dev); 518 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 519 return 1; 520 } 521 522 long radeon_drm_ioctl(struct file *filp, 523 unsigned int cmd, unsigned long arg) 524 { 525 struct drm_file *file_priv = filp->private_data; 526 struct drm_device *dev; 527 long ret; 528 dev = file_priv->minor->dev; 529 ret = pm_runtime_get_sync(dev->dev); 530 if (ret < 0) 531 return ret; 532 533 ret = drm_ioctl(filp, cmd, arg); 534 535 pm_runtime_mark_last_busy(dev->dev); 536 pm_runtime_put_autosuspend(dev->dev); 537 return ret; 538 } 539 540 static const struct dev_pm_ops radeon_pm_ops = { 541 .suspend = radeon_pmops_suspend, 542 .resume = radeon_pmops_resume, 543 .freeze = radeon_pmops_freeze, 544 .thaw = radeon_pmops_thaw, 545 .poweroff = radeon_pmops_freeze, 546 .restore = radeon_pmops_resume, 547 .runtime_suspend = radeon_pmops_runtime_suspend, 548 .runtime_resume = radeon_pmops_runtime_resume, 549 .runtime_idle = radeon_pmops_runtime_idle, 550 }; 551 552 static const struct file_operations radeon_driver_kms_fops = { 553 .owner = THIS_MODULE, 554 .open = drm_open, 555 .release = drm_release, 556 .unlocked_ioctl = radeon_drm_ioctl, 557 .mmap = radeon_mmap, 558 .poll = drm_poll, 559 .read = drm_read, 560 #ifdef CONFIG_COMPAT 561 .compat_ioctl = radeon_kms_compat_ioctl, 562 #endif 563 }; 564 #endif /* DUMBBELL_WIP */ 565 566 static int radeon_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 567 struct sysctl_oid *top) 568 { 569 return drm_add_busid_modesetting(dev, ctx, top); 570 } 571 572 static struct drm_driver kms_driver = { 573 .driver_features = 574 DRIVER_USE_AGP | 575 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 576 DRIVER_PRIME | DRIVER_RENDER, 577 .load = radeon_driver_load_kms, 578 .use_msi = radeon_msi_ok, 579 .open = radeon_driver_open_kms, 580 .preclose = radeon_driver_preclose_kms, 581 .postclose = radeon_driver_postclose_kms, 582 .lastclose = radeon_driver_lastclose_kms, 583 .unload = radeon_driver_unload_kms, 584 .get_vblank_counter = radeon_get_vblank_counter_kms, 585 .enable_vblank = radeon_enable_vblank_kms, 586 .disable_vblank = radeon_disable_vblank_kms, 587 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 588 .get_scanout_position = radeon_get_crtc_scanoutpos, 589 .irq_preinstall = radeon_driver_irq_preinstall_kms, 590 .irq_postinstall = radeon_driver_irq_postinstall_kms, 591 .irq_uninstall = radeon_driver_irq_uninstall_kms, 592 .irq_handler = radeon_driver_irq_handler_kms, 593 .sysctl_init = radeon_sysctl_init, 594 .ioctls = radeon_ioctls_kms, 595 .gem_free_object = radeon_gem_object_free, 596 .gem_open_object = radeon_gem_object_open, 597 .gem_close_object = radeon_gem_object_close, 598 .dumb_create = radeon_mode_dumb_create, 599 .dumb_map_offset = radeon_mode_dumb_mmap, 600 .dumb_destroy = drm_gem_dumb_destroy, 601 #ifdef DUMBBELL_WIP 602 .fops = &radeon_driver_kms_fops, 603 #endif /* DUMBBELL_WIP */ 604 605 #ifdef DUMBBELL_WIP 606 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 607 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 608 .gem_prime_export = drm_gem_prime_export, 609 .gem_prime_import = drm_gem_prime_import, 610 .gem_prime_pin = radeon_gem_prime_pin, 611 .gem_prime_unpin = radeon_gem_prime_unpin, 612 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 613 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 614 .gem_prime_vmap = radeon_gem_prime_vmap, 615 .gem_prime_vunmap = radeon_gem_prime_vunmap, 616 #endif /* DUMBBELL_WIP */ 617 618 .name = DRIVER_NAME, 619 .desc = DRIVER_DESC, 620 .date = DRIVER_DATE, 621 .major = KMS_DRIVER_MAJOR, 622 .minor = KMS_DRIVER_MINOR, 623 .patchlevel = KMS_DRIVER_PATCHLEVEL, 624 }; 625 626 #ifdef DUMBBELL_WIP 627 static struct drm_driver *driver; 628 static struct pci_driver *pdriver; 629 630 #ifdef CONFIG_DRM_RADEON_UMS 631 static struct pci_driver radeon_pci_driver = { 632 .name = DRIVER_NAME, 633 .id_table = pciidlist, 634 }; 635 #endif 636 637 static struct pci_driver radeon_kms_pci_driver = { 638 .name = DRIVER_NAME, 639 .id_table = pciidlist, 640 .probe = radeon_pci_probe, 641 .remove = radeon_pci_remove, 642 .driver.pm = &radeon_pm_ops, 643 }; 644 645 static int __init radeon_init(void) 646 { 647 if (radeon_modeset == 1) { 648 DRM_INFO("radeon kernel modesetting enabled.\n"); 649 driver = &kms_driver; 650 pdriver = &radeon_kms_pci_driver; 651 driver->driver_features |= DRIVER_MODESET; 652 driver->num_ioctls = radeon_max_kms_ioctl; 653 radeon_register_atpx_handler(); 654 655 } else { 656 #ifdef CONFIG_DRM_RADEON_UMS 657 DRM_INFO("radeon userspace modesetting enabled.\n"); 658 driver = &driver_old; 659 pdriver = &radeon_pci_driver; 660 driver->driver_features &= ~DRIVER_MODESET; 661 driver->num_ioctls = radeon_max_ioctl; 662 #else 663 DRM_ERROR("No UMS support in radeon module!\n"); 664 return -EINVAL; 665 #endif 666 } 667 668 /* let modprobe override vga console setting */ 669 return drm_pci_init(driver, pdriver); 670 } 671 672 static void __exit radeon_exit(void) 673 { 674 drm_pci_exit(driver, pdriver); 675 radeon_unregister_atpx_handler(); 676 } 677 #endif /* DUMBBELL_WIP */ 678 679 /* =================================================================== */ 680 681 static int 682 radeon_probe(device_t kdev) 683 { 684 685 return drm_probe(kdev, pciidlist); 686 } 687 688 static int 689 radeon_attach(device_t kdev) 690 { 691 struct drm_device *dev; 692 693 dev = device_get_softc(kdev); 694 if (radeon_modeset == 1) { 695 kms_driver.driver_features |= DRIVER_MODESET; 696 kms_driver.num_ioctls = radeon_max_kms_ioctl; 697 radeon_register_atpx_handler(); 698 } 699 dev->driver = &kms_driver; 700 return (drm_attach(kdev, pciidlist)); 701 } 702 703 static int 704 radeon_suspend(device_t kdev) 705 { 706 struct drm_device *dev; 707 int ret; 708 709 dev = device_get_softc(kdev); 710 ret = radeon_suspend_kms(dev, true, true); 711 712 return (-ret); 713 } 714 715 static int 716 radeon_resume(device_t kdev) 717 { 718 struct drm_device *dev; 719 int ret; 720 721 dev = device_get_softc(kdev); 722 ret = radeon_resume_kms(dev, true, true); 723 724 return (-ret); 725 } 726 727 static device_method_t radeon_methods[] = { 728 /* Device interface */ 729 DEVMETHOD(device_probe, radeon_probe), 730 DEVMETHOD(device_attach, radeon_attach), 731 DEVMETHOD(device_suspend, radeon_suspend), 732 DEVMETHOD(device_resume, radeon_resume), 733 DEVMETHOD(device_detach, drm_release), 734 DEVMETHOD_END 735 }; 736 737 static driver_t radeon_driver = { 738 "drm", 739 radeon_methods, 740 sizeof(struct drm_device) 741 }; 742 743 extern devclass_t drm_devclass; 744 DRIVER_MODULE_ORDERED(radeonkms, vgapci, radeon_driver, drm_devclass, 745 NULL, NULL, SI_ORDER_ANY); 746 MODULE_DEPEND(radeonkms, drm, 1, 1, 1); 747 MODULE_DEPEND(radeonkms, agp, 1, 1, 1); 748 MODULE_DEPEND(radeonkms, iicbus, 1, 1, 1); 749 MODULE_DEPEND(radeonkms, iic, 1, 1, 1); 750 MODULE_DEPEND(radeonkms, iicbb, 1, 1, 1); 751