1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 * 31 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_drv.c 254885 2013-08-25 19:37:15Z dumbbell $ 32 */ 33 34 #include <drm/drmP.h> 35 #include <uapi_drm/radeon_drm.h> 36 #include "radeon_drv.h" 37 #include "radeon_gem.h" 38 #include "radeon_kms.h" 39 #include "radeon_irq_kms.h" 40 41 #include <drm/drm_pciids.h> 42 #include <linux/module.h> 43 #ifdef PM_TODO 44 #include <linux/pm_runtime.h> 45 #include <linux/vga_switcheroo.h> 46 #endif 47 #include "drm/drm_crtc_helper.h" 48 /* 49 * KMS wrapper. 50 * - 2.0.0 - initial interface 51 * - 2.1.0 - add square tiling interface 52 * - 2.2.0 - add r6xx/r7xx const buffer support 53 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 54 * - 2.4.0 - add crtc id query 55 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 56 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 57 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 58 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 59 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 60 * 2.10.0 - fusion 2D tiling 61 * 2.11.0 - backend map, initial compute support for the CS checker 62 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 63 * 2.13.0 - virtual memory support, streamout 64 * 2.14.0 - add evergreen tiling informations 65 * 2.15.0 - add max_pipes query 66 * 2.16.0 - fix evergreen 2D tiled surface calculation 67 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 68 * 2.18.0 - r600-eg: allow "invalid" DB formats 69 * 2.19.0 - r600-eg: MSAA textures 70 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 71 * 2.21.0 - r600-r700: FMASK and CMASK 72 * 2.22.0 - r600 only: RESOLVE_BOX allowed 73 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 74 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 75 * 2.25.0 - eg+: new info request for num SE and num SH 76 * 2.26.0 - r600-eg: fix htile size computation 77 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 78 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 79 * 2.29.0 - R500 FP16 color clear registers 80 * 2.30.0 - fix for FMASK texturing 81 * 2.31.0 - Add fastfb support for rs690 82 * 2.32.0 - new info request for rings working 83 * 2.33.0 - Add SI tiling mode array query 84 * 2.34.0 - Add CIK tiling mode array query 85 * 2.35.0 - Add CIK macrotile mode array query 86 * 2.36.0 - Fix CIK DCE tiling setup 87 * 2.37.0 - allow GS ring setup on r6xx/r7xx 88 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 89 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 90 * 2.39.0 - Add INFO query for number of active CUs 91 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 92 * CS to GPU on >= r600 93 */ 94 #define KMS_DRIVER_MAJOR 2 95 #define KMS_DRIVER_MINOR 40 96 #define KMS_DRIVER_PATCHLEVEL 0 97 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 98 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 99 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 100 unsigned int flags, 101 int *vpos, int *hpos, ktime_t *stime, 102 ktime_t *etime); 103 extern bool radeon_is_px(struct drm_device *dev); 104 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 105 extern int radeon_max_kms_ioctl; 106 #ifdef DUMBBELL_WIP 107 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 108 #endif /* DUMBBELL_WIP */ 109 int radeon_mode_dumb_mmap(struct drm_file *filp, 110 struct drm_device *dev, 111 uint32_t handle, uint64_t *offset_p); 112 int radeon_mode_dumb_create(struct drm_file *file_priv, 113 struct drm_device *dev, 114 struct drm_mode_create_dumb *args); 115 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 116 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 117 size_t size, 118 struct sg_table *sg); 119 int radeon_gem_prime_pin(struct drm_gem_object *obj); 120 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 121 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 122 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 123 124 #if defined(CONFIG_DEBUG_FS) 125 int radeon_debugfs_init(struct drm_minor *minor); 126 void radeon_debugfs_cleanup(struct drm_minor *minor); 127 #endif 128 129 /* atpx handler */ 130 #if defined(CONFIG_VGA_SWITCHEROO) 131 void radeon_register_atpx_handler(void); 132 void radeon_unregister_atpx_handler(void); 133 #else 134 static inline void radeon_register_atpx_handler(void) {} 135 static inline void radeon_unregister_atpx_handler(void) {} 136 #endif 137 138 int radeon_no_wb; 139 int radeon_modeset = 1; 140 int radeon_dynclks = -1; 141 int radeon_r4xx_atom = 0; 142 int radeon_agpmode = 0; 143 int radeon_vram_limit = 0; 144 int radeon_gart_size = -1; /* auto */ 145 int radeon_benchmarking = 0; 146 int radeon_testing = 0; 147 int radeon_connector_table = 0; 148 int radeon_tv = 1; 149 int radeon_audio = -1; 150 int radeon_disp_priority = 0; 151 int radeon_hw_i2c = 0; 152 int radeon_pcie_gen2 = -1; 153 int radeon_msi = -1; 154 int radeon_lockup_timeout = 10000; 155 int radeon_fastfb = 0; 156 int radeon_dpm = -1; 157 int radeon_aspm = -1; 158 int radeon_runtime_pm = -1; 159 int radeon_hard_reset = 0; 160 int radeon_vm_size = 8; 161 int radeon_vm_block_size = -1; 162 int radeon_deep_color = 0; 163 int radeon_use_pflipirq = 2; 164 int radeon_bapm = -1; 165 int radeon_backlight = -1; 166 167 TUNABLE_INT("drm.radeon.no_wb", &radeon_no_wb); 168 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 169 module_param_named(no_wb, radeon_no_wb, int, 0444); 170 171 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 172 module_param_named(modeset, radeon_modeset, int, 0400); 173 174 TUNABLE_INT("drm.radeon.dynclks", &radeon_dynclks); 175 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 176 module_param_named(dynclks, radeon_dynclks, int, 0444); 177 178 TUNABLE_INT("drm.radeon.r4xx_atom", &radeon_r4xx_atom); 179 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 180 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 181 182 TUNABLE_INT("drm.radeon.vram_limit", &radeon_vram_limit); 183 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 184 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 185 186 TUNABLE_INT("drm.radeon.agpmode", &radeon_agpmode); 187 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 188 module_param_named(agpmode, radeon_agpmode, int, 0444); 189 190 TUNABLE_INT("drm.radeon.gart_size", &radeon_gart_size); 191 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 192 module_param_named(gartsize, radeon_gart_size, int, 0600); 193 194 TUNABLE_INT("drm.radeon.benchmarking", &radeon_benchmarking); 195 MODULE_PARM_DESC(benchmark, "Run benchmark"); 196 module_param_named(benchmark, radeon_benchmarking, int, 0444); 197 198 TUNABLE_INT("drm.radeon.testing", &radeon_testing); 199 MODULE_PARM_DESC(test, "Run tests"); 200 module_param_named(test, radeon_testing, int, 0444); 201 202 TUNABLE_INT("drm.radeon.connector_table", &radeon_connector_table); 203 MODULE_PARM_DESC(connector_table, "Force connector table"); 204 module_param_named(connector_table, radeon_connector_table, int, 0444); 205 206 TUNABLE_INT("drm.radeon.tv", &radeon_tv); 207 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 208 module_param_named(tv, radeon_tv, int, 0444); 209 210 TUNABLE_INT("drm.radeon.audio", &radeon_audio); 211 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 212 module_param_named(audio, radeon_audio, int, 0444); 213 214 TUNABLE_INT("drm.radeon.disp_priority", &radeon_disp_priority); 215 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 216 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 217 218 TUNABLE_INT("drm.radeon.hw_i2c", &radeon_hw_i2c); 219 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 220 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 221 222 TUNABLE_INT("drm.radeon.pcie_gen2", &radeon_pcie_gen2); 223 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 224 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 225 226 TUNABLE_INT("drm.radeon.msi", &radeon_msi); 227 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 228 module_param_named(msi, radeon_msi, int, 0444); 229 230 TUNABLE_INT("drm.radeon.lockup_timeout", &radeon_lockup_timeout); 231 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 232 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 233 234 TUNABLE_INT("drm.radeon.fastfb", &radeon_fastfb); 235 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 236 module_param_named(fastfb, radeon_fastfb, int, 0444); 237 238 TUNABLE_INT("drm.radeon.dpm", &radeon_dpm); 239 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 240 module_param_named(dpm, radeon_dpm, int, 0444); 241 242 TUNABLE_INT("drm.radeon.aspm", &radeon_aspm); 243 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 244 module_param_named(aspm, radeon_aspm, int, 0444); 245 246 TUNABLE_INT("drm.radeon.runtime_pm", &radeon_runtime_pm); /* careful with this */ 247 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 248 module_param_named(runpm, radeon_runtime_pm, int, 0444); 249 250 TUNABLE_INT("drm.radeon.hard_reset", &radeon_hard_reset); /* very careful with this */ 251 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 252 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 253 254 TUNABLE_INT("drm.radeon.vm_size", &radeon_vm_size); 255 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 256 module_param_named(vm_size, radeon_vm_size, int, 0444); 257 258 TUNABLE_INT("drm.radeon.vm_block_size", &radeon_vm_block_size); 259 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 260 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 261 262 TUNABLE_INT("drm.radeon.deep_color", &radeon_deep_color); 263 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 264 module_param_named(deep_color, radeon_deep_color, int, 0444); 265 266 TUNABLE_INT("drm.radeon.use_pflipirq", &radeon_use_pflipirq); 267 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 268 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 269 270 TUNABLE_INT("drm.radeon.bapm", &radeon_bapm); 271 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 272 module_param_named(bapm, radeon_bapm, int, 0444); 273 274 TUNABLE_INT("drm.radeon.backlight", &radeon_backlight); 275 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 276 module_param_named(backlight, radeon_backlight, int, 0444); 277 278 static drm_pci_id_list_t pciidlist[] = { 279 radeon_PCI_IDS 280 }; 281 282 #ifdef CONFIG_DRM_RADEON_UMS 283 284 #ifdef DUMBBELL_WIP 285 286 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 287 { 288 drm_radeon_private_t *dev_priv = dev->dev_private; 289 290 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 291 return 0; 292 293 /* Disable *all* interrupts */ 294 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 295 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 296 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 297 return 0; 298 } 299 300 static int radeon_resume(struct drm_device *dev) 301 { 302 drm_radeon_private_t *dev_priv = dev->dev_private; 303 304 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 305 return 0; 306 307 /* Restore interrupt registers */ 308 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 309 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 310 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 311 return 0; 312 } 313 #endif /* DUMBBELL_WIP */ 314 315 #ifdef DUMBBELL_WIP 316 static const struct file_operations radeon_driver_old_fops = { 317 .owner = THIS_MODULE, 318 .open = drm_open, 319 .release = drm_release, 320 .unlocked_ioctl = drm_ioctl, 321 .mmap = drm_mmap, 322 .poll = drm_poll, 323 .read = drm_read, 324 #ifdef CONFIG_COMPAT 325 .compat_ioctl = radeon_compat_ioctl, 326 #endif 327 .llseek = noop_llseek, 328 }; 329 330 static struct drm_driver driver_old = { 331 .driver_features = 332 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | 333 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 334 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 335 .load = radeon_driver_load, 336 .firstopen = radeon_driver_firstopen, 337 .open = radeon_driver_open, 338 .preclose = radeon_driver_preclose, 339 .postclose = radeon_driver_postclose, 340 .lastclose = radeon_driver_lastclose, 341 .unload = radeon_driver_unload, 342 #ifdef DUMBBELL_WIP 343 .suspend = radeon_suspend, 344 .resume = radeon_resume, 345 #endif /* DUMBBELL_WIP */ 346 .get_vblank_counter = radeon_get_vblank_counter, 347 .enable_vblank = radeon_enable_vblank, 348 .disable_vblank = radeon_disable_vblank, 349 .master_create = radeon_master_create, 350 .master_destroy = radeon_master_destroy, 351 .irq_preinstall = radeon_driver_irq_preinstall, 352 .irq_postinstall = radeon_driver_irq_postinstall, 353 .irq_uninstall = radeon_driver_irq_uninstall, 354 .irq_handler = radeon_driver_irq_handler, 355 .ioctls = radeon_ioctls, 356 .dma_ioctl = radeon_cp_buffers, 357 .fops = &radeon_driver_old_fops, 358 .name = DRIVER_NAME, 359 .desc = DRIVER_DESC, 360 .date = DRIVER_DATE, 361 .major = DRIVER_MAJOR, 362 .minor = DRIVER_MINOR, 363 .patchlevel = DRIVER_PATCHLEVEL, 364 }; 365 #endif /* DUMBBELL_WIP */ 366 367 #endif 368 369 static struct drm_driver kms_driver; 370 371 #ifdef DUMBBELL_WIP 372 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 373 { 374 struct apertures_struct *ap; 375 bool primary = false; 376 377 ap = alloc_apertures(1); 378 if (!ap) 379 return -ENOMEM; 380 381 ap->ranges[0].base = pci_resource_start(pdev, 0); 382 ap->ranges[0].size = pci_resource_len(pdev, 0); 383 384 #ifdef CONFIG_X86 385 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 386 #endif 387 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 388 kfree(ap); 389 390 return 0; 391 } 392 393 static int radeon_pci_probe(struct pci_dev *pdev, 394 const struct pci_device_id *ent) 395 { 396 int ret; 397 398 /* Get rid of things like offb */ 399 ret = radeon_kick_out_firmware_fb(pdev); 400 if (ret) 401 return ret; 402 403 return drm_get_pci_dev(pdev, ent, &kms_driver); 404 } 405 406 static void 407 radeon_pci_remove(struct pci_dev *pdev) 408 { 409 struct drm_device *dev = pci_get_drvdata(pdev); 410 411 drm_put_dev(dev); 412 } 413 414 static int radeon_pmops_suspend(struct device *dev) 415 { 416 struct pci_dev *pdev = to_pci_dev(dev); 417 struct drm_device *drm_dev = pci_get_drvdata(pdev); 418 return radeon_suspend_kms(drm_dev, true, true); 419 } 420 421 static int radeon_pmops_resume(struct device *dev) 422 { 423 struct pci_dev *pdev = to_pci_dev(dev); 424 struct drm_device *drm_dev = pci_get_drvdata(pdev); 425 return radeon_resume_kms(drm_dev, true, true); 426 } 427 428 static int radeon_pmops_freeze(struct device *dev) 429 { 430 struct pci_dev *pdev = to_pci_dev(dev); 431 struct drm_device *drm_dev = pci_get_drvdata(pdev); 432 return radeon_suspend_kms(drm_dev, false, true); 433 } 434 435 static int radeon_pmops_thaw(struct device *dev) 436 { 437 struct pci_dev *pdev = to_pci_dev(dev); 438 struct drm_device *drm_dev = pci_get_drvdata(pdev); 439 return radeon_resume_kms(drm_dev, false, true); 440 } 441 442 static int radeon_pmops_runtime_suspend(struct device *dev) 443 { 444 struct pci_dev *pdev = to_pci_dev(dev); 445 struct drm_device *drm_dev = pci_get_drvdata(pdev); 446 int ret; 447 448 if (!radeon_is_px(drm_dev)) { 449 #ifdef PM_TODO 450 pm_runtime_forbid(dev); 451 #endif 452 return -EBUSY; 453 } 454 455 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 456 drm_kms_helper_poll_disable(drm_dev); 457 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 458 459 ret = radeon_suspend_kms(drm_dev, false, false); 460 pci_save_state(pdev); 461 pci_disable_device(pdev); 462 pci_set_power_state(pdev, PCI_D3cold); 463 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 464 465 return 0; 466 } 467 468 static int radeon_pmops_runtime_resume(struct device *dev) 469 { 470 struct pci_dev *pdev = to_pci_dev(dev); 471 struct drm_device *drm_dev = pci_get_drvdata(pdev); 472 int ret; 473 474 if (!radeon_is_px(drm_dev)) 475 return -EINVAL; 476 477 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 478 479 pci_set_power_state(pdev, PCI_D0); 480 pci_restore_state(pdev); 481 ret = pci_enable_device(pdev); 482 if (ret) 483 return ret; 484 pci_set_master(pdev); 485 486 ret = radeon_resume_kms(drm_dev, false, false); 487 drm_kms_helper_poll_enable(drm_dev); 488 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 489 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 490 return 0; 491 } 492 493 static int radeon_pmops_runtime_idle(struct device *dev) 494 { 495 struct pci_dev *pdev = to_pci_dev(dev); 496 struct drm_device *drm_dev = pci_get_drvdata(pdev); 497 struct drm_crtc *crtc; 498 499 if (!radeon_is_px(drm_dev)) { 500 #ifdef PM_TODO 501 pm_runtime_forbid(dev); 502 #endif 503 return -EBUSY; 504 } 505 506 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 507 if (crtc->enabled) { 508 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 509 return -EBUSY; 510 } 511 } 512 513 pm_runtime_mark_last_busy(dev); 514 pm_runtime_autosuspend(dev); 515 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 516 return 1; 517 } 518 519 long radeon_drm_ioctl(struct file *filp, 520 unsigned int cmd, unsigned long arg) 521 { 522 struct drm_file *file_priv = filp->private_data; 523 struct drm_device *dev; 524 long ret; 525 dev = file_priv->minor->dev; 526 ret = pm_runtime_get_sync(dev->dev); 527 if (ret < 0) 528 return ret; 529 530 ret = drm_ioctl(filp, cmd, arg); 531 532 pm_runtime_mark_last_busy(dev->dev); 533 pm_runtime_put_autosuspend(dev->dev); 534 return ret; 535 } 536 537 static const struct dev_pm_ops radeon_pm_ops = { 538 .suspend = radeon_pmops_suspend, 539 .resume = radeon_pmops_resume, 540 .freeze = radeon_pmops_freeze, 541 .thaw = radeon_pmops_thaw, 542 .poweroff = radeon_pmops_freeze, 543 .restore = radeon_pmops_resume, 544 .runtime_suspend = radeon_pmops_runtime_suspend, 545 .runtime_resume = radeon_pmops_runtime_resume, 546 .runtime_idle = radeon_pmops_runtime_idle, 547 }; 548 549 static const struct file_operations radeon_driver_kms_fops = { 550 .owner = THIS_MODULE, 551 .open = drm_open, 552 .release = drm_release, 553 .unlocked_ioctl = radeon_drm_ioctl, 554 .mmap = radeon_mmap, 555 .poll = drm_poll, 556 .read = drm_read, 557 #ifdef CONFIG_COMPAT 558 .compat_ioctl = radeon_kms_compat_ioctl, 559 #endif 560 }; 561 #endif /* DUMBBELL_WIP */ 562 563 static struct drm_driver kms_driver = { 564 .driver_features = 565 DRIVER_USE_AGP | 566 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 567 DRIVER_PRIME | DRIVER_RENDER, 568 .load = radeon_driver_load_kms, 569 .use_msi = radeon_msi_ok, 570 .open = radeon_driver_open_kms, 571 .preclose = radeon_driver_preclose_kms, 572 .postclose = radeon_driver_postclose_kms, 573 .lastclose = radeon_driver_lastclose_kms, 574 .unload = radeon_driver_unload_kms, 575 .get_vblank_counter = radeon_get_vblank_counter_kms, 576 .enable_vblank = radeon_enable_vblank_kms, 577 .disable_vblank = radeon_disable_vblank_kms, 578 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 579 .get_scanout_position = radeon_get_crtc_scanoutpos, 580 .irq_preinstall = radeon_driver_irq_preinstall_kms, 581 .irq_postinstall = radeon_driver_irq_postinstall_kms, 582 .irq_uninstall = radeon_driver_irq_uninstall_kms, 583 .irq_handler = radeon_driver_irq_handler_kms, 584 .ioctls = radeon_ioctls_kms, 585 .gem_free_object = radeon_gem_object_free, 586 .gem_open_object = radeon_gem_object_open, 587 .gem_close_object = radeon_gem_object_close, 588 .dumb_create = radeon_mode_dumb_create, 589 .dumb_map_offset = radeon_mode_dumb_mmap, 590 .dumb_destroy = drm_gem_dumb_destroy, 591 #ifdef DUMBBELL_WIP 592 .fops = &radeon_driver_kms_fops, 593 #endif /* DUMBBELL_WIP */ 594 595 #ifdef DUMBBELL_WIP 596 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 597 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 598 .gem_prime_export = drm_gem_prime_export, 599 .gem_prime_import = drm_gem_prime_import, 600 .gem_prime_pin = radeon_gem_prime_pin, 601 .gem_prime_unpin = radeon_gem_prime_unpin, 602 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 603 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 604 .gem_prime_vmap = radeon_gem_prime_vmap, 605 .gem_prime_vunmap = radeon_gem_prime_vunmap, 606 #endif /* DUMBBELL_WIP */ 607 608 .name = DRIVER_NAME, 609 .desc = DRIVER_DESC, 610 .date = DRIVER_DATE, 611 .major = KMS_DRIVER_MAJOR, 612 .minor = KMS_DRIVER_MINOR, 613 .patchlevel = KMS_DRIVER_PATCHLEVEL, 614 }; 615 616 #ifdef DUMBBELL_WIP 617 static struct drm_driver *driver; 618 static struct pci_driver *pdriver; 619 620 #ifdef CONFIG_DRM_RADEON_UMS 621 static struct pci_driver radeon_pci_driver = { 622 .name = DRIVER_NAME, 623 .id_table = pciidlist, 624 }; 625 #endif 626 627 static struct pci_driver radeon_kms_pci_driver = { 628 .name = DRIVER_NAME, 629 .id_table = pciidlist, 630 .probe = radeon_pci_probe, 631 .remove = radeon_pci_remove, 632 .driver.pm = &radeon_pm_ops, 633 }; 634 635 static int __init radeon_init(void) 636 { 637 if (radeon_modeset == 1) { 638 DRM_INFO("radeon kernel modesetting enabled.\n"); 639 driver = &kms_driver; 640 pdriver = &radeon_kms_pci_driver; 641 driver->driver_features |= DRIVER_MODESET; 642 driver->num_ioctls = radeon_max_kms_ioctl; 643 radeon_register_atpx_handler(); 644 645 } else { 646 #ifdef CONFIG_DRM_RADEON_UMS 647 DRM_INFO("radeon userspace modesetting enabled.\n"); 648 driver = &driver_old; 649 pdriver = &radeon_pci_driver; 650 driver->driver_features &= ~DRIVER_MODESET; 651 driver->num_ioctls = radeon_max_ioctl; 652 #else 653 DRM_ERROR("No UMS support in radeon module!\n"); 654 return -EINVAL; 655 #endif 656 } 657 658 /* let modprobe override vga console setting */ 659 return drm_pci_init(driver, pdriver); 660 } 661 662 static void __exit radeon_exit(void) 663 { 664 drm_pci_exit(driver, pdriver); 665 radeon_unregister_atpx_handler(); 666 } 667 #endif /* DUMBBELL_WIP */ 668 669 /* =================================================================== */ 670 671 static int 672 radeon_probe(device_t kdev) 673 { 674 675 return drm_probe(kdev, pciidlist); 676 } 677 678 static int 679 radeon_attach(device_t kdev) 680 { 681 struct drm_device *dev; 682 683 dev = device_get_softc(kdev); 684 if (radeon_modeset == 1) { 685 kms_driver.driver_features |= DRIVER_MODESET; 686 kms_driver.num_ioctls = radeon_max_kms_ioctl; 687 radeon_register_atpx_handler(); 688 } 689 dev->driver = &kms_driver; 690 return (drm_attach(kdev, pciidlist)); 691 } 692 693 static int 694 radeon_suspend(device_t kdev) 695 { 696 struct drm_device *dev; 697 int ret; 698 699 dev = device_get_softc(kdev); 700 ret = radeon_suspend_kms(dev, true, true); 701 702 return (-ret); 703 } 704 705 static int 706 radeon_resume(device_t kdev) 707 { 708 struct drm_device *dev; 709 int ret; 710 711 dev = device_get_softc(kdev); 712 ret = radeon_resume_kms(dev, true, true); 713 714 return (-ret); 715 } 716 717 static device_method_t radeon_methods[] = { 718 /* Device interface */ 719 DEVMETHOD(device_probe, radeon_probe), 720 DEVMETHOD(device_attach, radeon_attach), 721 DEVMETHOD(device_suspend, radeon_suspend), 722 DEVMETHOD(device_resume, radeon_resume), 723 DEVMETHOD(device_detach, drm_release), 724 DEVMETHOD_END 725 }; 726 727 static driver_t radeon_driver = { 728 "drm", 729 radeon_methods, 730 sizeof(struct drm_device) 731 }; 732 733 extern devclass_t drm_devclass; 734 DRIVER_MODULE_ORDERED(radeonkms, vgapci, radeon_driver, drm_devclass, 735 NULL, NULL, SI_ORDER_ANY); 736 MODULE_DEPEND(radeonkms, drm, 1, 1, 1); 737 MODULE_DEPEND(radeonkms, agp, 1, 1, 1); 738 MODULE_DEPEND(radeonkms, iicbus, 1, 1, 1); 739 MODULE_DEPEND(radeonkms, iic, 1, 1, 1); 740 MODULE_DEPEND(radeonkms, iicbb, 1, 1, 1); 741