1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/compat.h> 42 #include <drm/drm_gem.h> 43 #include <drm/drm_fb_helper.h> 44 45 #include <drm/drm_crtc_helper.h> 46 47 /* 48 * KMS wrapper. 49 * - 2.0.0 - initial interface 50 * - 2.1.0 - add square tiling interface 51 * - 2.2.0 - add r6xx/r7xx const buffer support 52 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 53 * - 2.4.0 - add crtc id query 54 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 55 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 56 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 57 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 58 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 59 * 2.10.0 - fusion 2D tiling 60 * 2.11.0 - backend map, initial compute support for the CS checker 61 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 62 * 2.13.0 - virtual memory support, streamout 63 * 2.14.0 - add evergreen tiling informations 64 * 2.15.0 - add max_pipes query 65 * 2.16.0 - fix evergreen 2D tiled surface calculation 66 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 67 * 2.18.0 - r600-eg: allow "invalid" DB formats 68 * 2.19.0 - r600-eg: MSAA textures 69 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 70 * 2.21.0 - r600-r700: FMASK and CMASK 71 * 2.22.0 - r600 only: RESOLVE_BOX allowed 72 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 73 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 74 * 2.25.0 - eg+: new info request for num SE and num SH 75 * 2.26.0 - r600-eg: fix htile size computation 76 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 77 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 78 * 2.29.0 - R500 FP16 color clear registers 79 * 2.30.0 - fix for FMASK texturing 80 * 2.31.0 - Add fastfb support for rs690 81 * 2.32.0 - new info request for rings working 82 * 2.33.0 - Add SI tiling mode array query 83 * 2.34.0 - Add CIK tiling mode array query 84 * 2.35.0 - Add CIK macrotile mode array query 85 * 2.36.0 - Fix CIK DCE tiling setup 86 * 2.37.0 - allow GS ring setup on r6xx/r7xx 87 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 88 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 89 * 2.39.0 - Add INFO query for number of active CUs 90 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 91 * CS to GPU on >= r600 92 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 93 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 94 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 95 * 2.44.0 - SET_APPEND_CNT packet3 support 96 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 97 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 98 * 2.47.0 - Add UVD_NO_OP register support 99 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 100 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 101 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 102 */ 103 #define KMS_DRIVER_MAJOR 2 104 #define KMS_DRIVER_MINOR 50 105 #define KMS_DRIVER_PATCHLEVEL 0 106 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 107 void radeon_driver_unload_kms(struct drm_device *dev); 108 void radeon_driver_lastclose_kms(struct drm_device *dev); 109 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 110 void radeon_driver_postclose_kms(struct drm_device *dev, 111 struct drm_file *file_priv); 112 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 113 bool fbcon, bool freeze); 114 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 115 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 116 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 117 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 118 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 119 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 120 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 121 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 122 void radeon_gem_object_free(struct drm_gem_object *obj); 123 int radeon_gem_object_open(struct drm_gem_object *obj, 124 struct drm_file *file_priv); 125 void radeon_gem_object_close(struct drm_gem_object *obj, 126 struct drm_file *file_priv); 127 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, 128 struct drm_gem_object *gobj, 129 int flags); 130 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 131 unsigned int flags, int *vpos, int *hpos, 132 ktime_t *stime, ktime_t *etime, 133 const struct drm_display_mode *mode); 134 extern bool radeon_is_px(struct drm_device *dev); 135 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 136 extern int radeon_max_kms_ioctl; 137 #ifdef DUMBBELL_WIP 138 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 139 #endif /* DUMBBELL_WIP */ 140 int radeon_mode_dumb_mmap(struct drm_file *filp, 141 struct drm_device *dev, 142 uint32_t handle, uint64_t *offset_p); 143 int radeon_mode_dumb_create(struct drm_file *file_priv, 144 struct drm_device *dev, 145 struct drm_mode_create_dumb *args); 146 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 147 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 148 struct dma_buf_attachment *, 149 struct sg_table *sg); 150 int radeon_gem_prime_pin(struct drm_gem_object *obj); 151 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 152 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 153 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 154 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 155 156 /* atpx handler */ 157 #if defined(CONFIG_VGA_SWITCHEROO) 158 void radeon_register_atpx_handler(void); 159 void radeon_unregister_atpx_handler(void); 160 #else 161 static inline void radeon_register_atpx_handler(void) {} 162 static inline void radeon_unregister_atpx_handler(void) {} 163 #endif 164 165 int radeon_no_wb; 166 int radeon_modeset = -1; 167 int radeon_dynclks = -1; 168 int radeon_r4xx_atom = 0; 169 int radeon_agpmode = 0; 170 int radeon_vram_limit = 0; 171 int radeon_gart_size = -1; /* auto */ 172 int radeon_benchmarking = 0; 173 int radeon_testing = 0; 174 int radeon_connector_table = 0; 175 int radeon_tv = 1; 176 int radeon_audio = -1; 177 int radeon_disp_priority = 0; 178 #ifdef __DragonFly__ 179 int radeon_hw_i2c = 1; 180 #else 181 int radeon_hw_i2c = 0; 182 #endif 183 int radeon_pcie_gen2 = -1; 184 int radeon_msi = -1; 185 int radeon_lockup_timeout = 10000; 186 int radeon_fastfb = 0; 187 int radeon_dpm = -1; 188 int radeon_aspm = -1; 189 int radeon_runtime_pm = -1; 190 int radeon_hard_reset = 0; 191 int radeon_vm_size = 8; 192 int radeon_vm_block_size = -1; 193 int radeon_deep_color = 0; 194 int radeon_use_pflipirq = 2; 195 int radeon_bapm = -1; 196 int radeon_backlight = -1; 197 int radeon_auxch = -1; 198 int radeon_mst = 0; 199 int radeon_uvd = 1; 200 int radeon_vce = 1; 201 202 TUNABLE_INT("drm.radeon.no_wb", &radeon_no_wb); 203 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 204 module_param_named(no_wb, radeon_no_wb, int, 0444); 205 206 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 207 module_param_named(modeset, radeon_modeset, int, 0400); 208 209 TUNABLE_INT("drm.radeon.dynclks", &radeon_dynclks); 210 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 211 module_param_named(dynclks, radeon_dynclks, int, 0444); 212 213 TUNABLE_INT("drm.radeon.r4xx_atom", &radeon_r4xx_atom); 214 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 215 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 216 217 TUNABLE_INT("drm.radeon.vram_limit", &radeon_vram_limit); 218 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 219 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 220 221 TUNABLE_INT("drm.radeon.agpmode", &radeon_agpmode); 222 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 223 module_param_named(agpmode, radeon_agpmode, int, 0444); 224 225 TUNABLE_INT("drm.radeon.gart_size", &radeon_gart_size); 226 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 227 module_param_named(gartsize, radeon_gart_size, int, 0600); 228 229 TUNABLE_INT("drm.radeon.benchmarking", &radeon_benchmarking); 230 MODULE_PARM_DESC(benchmark, "Run benchmark"); 231 module_param_named(benchmark, radeon_benchmarking, int, 0444); 232 233 TUNABLE_INT("drm.radeon.testing", &radeon_testing); 234 MODULE_PARM_DESC(test, "Run tests"); 235 module_param_named(test, radeon_testing, int, 0444); 236 237 TUNABLE_INT("drm.radeon.connector_table", &radeon_connector_table); 238 MODULE_PARM_DESC(connector_table, "Force connector table"); 239 module_param_named(connector_table, radeon_connector_table, int, 0444); 240 241 TUNABLE_INT("drm.radeon.tv", &radeon_tv); 242 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 243 module_param_named(tv, radeon_tv, int, 0444); 244 245 TUNABLE_INT("drm.radeon.audio", &radeon_audio); 246 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 247 module_param_named(audio, radeon_audio, int, 0444); 248 249 TUNABLE_INT("drm.radeon.disp_priority", &radeon_disp_priority); 250 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 251 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 252 253 TUNABLE_INT("drm.radeon.hw_i2c", &radeon_hw_i2c); 254 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 255 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 256 257 TUNABLE_INT("drm.radeon.pcie_gen2", &radeon_pcie_gen2); 258 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 259 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 260 261 TUNABLE_INT("drm.radeon.msi", &radeon_msi); 262 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 263 module_param_named(msi, radeon_msi, int, 0444); 264 265 TUNABLE_INT("drm.radeon.lockup_timeout", &radeon_lockup_timeout); 266 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 267 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 268 269 TUNABLE_INT("drm.radeon.fastfb", &radeon_fastfb); 270 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 271 module_param_named(fastfb, radeon_fastfb, int, 0444); 272 273 TUNABLE_INT("drm.radeon.dpm", &radeon_dpm); 274 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 275 module_param_named(dpm, radeon_dpm, int, 0444); 276 277 TUNABLE_INT("drm.radeon.aspm", &radeon_aspm); 278 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 279 module_param_named(aspm, radeon_aspm, int, 0444); 280 281 TUNABLE_INT("drm.radeon.runtime_pm", &radeon_runtime_pm); /* careful with this */ 282 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 283 module_param_named(runpm, radeon_runtime_pm, int, 0444); 284 285 TUNABLE_INT("drm.radeon.hard_reset", &radeon_hard_reset); /* very careful with this */ 286 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 287 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 288 289 TUNABLE_INT("drm.radeon.vm_size", &radeon_vm_size); 290 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 291 module_param_named(vm_size, radeon_vm_size, int, 0444); 292 293 TUNABLE_INT("drm.radeon.vm_block_size", &radeon_vm_block_size); 294 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 295 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 296 297 TUNABLE_INT("drm.radeon.deep_color", &radeon_deep_color); 298 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 299 module_param_named(deep_color, radeon_deep_color, int, 0444); 300 301 TUNABLE_INT("drm.radeon.use_pflipirq", &radeon_use_pflipirq); 302 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 303 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 304 305 TUNABLE_INT("drm.radeon.bapm", &radeon_bapm); 306 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 307 module_param_named(bapm, radeon_bapm, int, 0444); 308 309 TUNABLE_INT("drm.radeon.backlight", &radeon_backlight); 310 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 311 module_param_named(backlight, radeon_backlight, int, 0444); 312 313 TUNABLE_INT("drm.radeon.auxch", &radeon_auxch); 314 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 315 module_param_named(auxch, radeon_auxch, int, 0444); 316 317 TUNABLE_INT("drm.radeon.mst", &radeon_mst); 318 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 319 module_param_named(mst, radeon_mst, int, 0444); 320 321 TUNABLE_INT("drm.radeon.uvd", &radeon_uvd); 322 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 323 module_param_named(uvd, radeon_uvd, int, 0444); 324 325 TUNABLE_INT("drm.radeon.vce", &radeon_vce); 326 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 327 module_param_named(vce, radeon_vce, int, 0444); 328 329 int radeon_si_support = 1; 330 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 331 module_param_named(si_support, radeon_si_support, int, 0444); 332 333 int radeon_cik_support = 1; 334 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 335 module_param_named(cik_support, radeon_cik_support, int, 0444); 336 337 #ifdef CONFIG_DRM_AMDGPU_CIK 338 int radeon_cik_support = 0; 339 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 340 module_param_named(cik_support, radeon_cik_support, int, 0444); 341 #endif 342 343 static struct pci_device_id pciidlist[] = { 344 radeon_PCI_IDS 345 }; 346 347 MODULE_DEVICE_TABLE(pci, pciidlist); 348 349 static struct drm_driver kms_driver; 350 351 bool radeon_device_is_virtual(void); 352 353 #ifdef DUMBBELL_WIP 354 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 355 { 356 struct apertures_struct *ap; 357 bool primary = false; 358 359 ap = alloc_apertures(1); 360 if (!ap) 361 return -ENOMEM; 362 363 ap->ranges[0].base = pci_resource_start(pdev, 0); 364 ap->ranges[0].size = pci_resource_len(pdev, 0); 365 366 #ifdef CONFIG_X86 367 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 368 #endif 369 drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 370 kfree(ap); 371 372 return 0; 373 } 374 #endif /* DUMBBELL_WIP */ 375 376 static int radeon_pci_probe(struct pci_dev *pdev, 377 const struct pci_device_id *ent) 378 { 379 #if 0 380 int ret; 381 382 if (vga_switcheroo_client_probe_defer(pdev)) 383 return -EPROBE_DEFER; 384 385 /* Get rid of things like offb */ 386 ret = radeon_kick_out_firmware_fb(pdev); 387 if (ret) 388 return ret; 389 #endif 390 391 return drm_get_pci_dev(pdev, ent, &kms_driver); 392 } 393 394 #ifdef DUMBBELL_WIP 395 static void 396 radeon_pci_remove(struct pci_dev *pdev) 397 { 398 struct drm_device *dev = pci_get_drvdata(pdev); 399 400 drm_put_dev(dev); 401 } 402 403 static void 404 radeon_pci_shutdown(struct pci_dev *pdev) 405 { 406 /* if we are running in a VM, make sure the device 407 * torn down properly on reboot/shutdown 408 */ 409 if (radeon_device_is_virtual()) 410 radeon_pci_remove(pdev); 411 } 412 413 static int radeon_pmops_suspend(struct device *dev) 414 { 415 struct pci_dev *pdev = to_pci_dev(dev); 416 struct drm_device *drm_dev = pci_get_drvdata(pdev); 417 return radeon_suspend_kms(drm_dev, true, true, false); 418 } 419 420 static int radeon_pmops_resume(struct device *dev) 421 { 422 struct pci_dev *pdev = to_pci_dev(dev); 423 struct drm_device *drm_dev = pci_get_drvdata(pdev); 424 425 /* GPU comes up enabled by the bios on resume */ 426 if (radeon_is_px(drm_dev)) { 427 pm_runtime_disable(dev); 428 pm_runtime_set_active(dev); 429 pm_runtime_enable(dev); 430 } 431 432 return radeon_resume_kms(drm_dev, true, true); 433 } 434 435 static int radeon_pmops_freeze(struct device *dev) 436 { 437 struct pci_dev *pdev = to_pci_dev(dev); 438 struct drm_device *drm_dev = pci_get_drvdata(pdev); 439 return radeon_suspend_kms(drm_dev, false, true, true); 440 } 441 442 static int radeon_pmops_thaw(struct device *dev) 443 { 444 struct pci_dev *pdev = to_pci_dev(dev); 445 struct drm_device *drm_dev = pci_get_drvdata(pdev); 446 return radeon_resume_kms(drm_dev, false, true); 447 } 448 449 static int radeon_pmops_runtime_suspend(struct device *dev) 450 { 451 struct pci_dev *pdev = to_pci_dev(dev); 452 struct drm_device *drm_dev = pci_get_drvdata(pdev); 453 int ret; 454 455 if (!radeon_is_px(drm_dev)) { 456 pm_runtime_forbid(dev); 457 return -EBUSY; 458 } 459 460 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 461 drm_kms_helper_poll_disable(drm_dev); 462 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 463 464 ret = radeon_suspend_kms(drm_dev, false, false, false); 465 pci_save_state(pdev); 466 pci_disable_device(pdev); 467 pci_ignore_hotplug(pdev); 468 if (radeon_is_atpx_hybrid()) 469 pci_set_power_state(pdev, PCI_D3cold); 470 else if (!radeon_has_atpx_dgpu_power_cntl()) 471 pci_set_power_state(pdev, PCI_D3hot); 472 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 473 474 return 0; 475 } 476 477 static int radeon_pmops_runtime_resume(struct device *dev) 478 { 479 struct pci_dev *pdev = to_pci_dev(dev); 480 struct drm_device *drm_dev = pci_get_drvdata(pdev); 481 int ret; 482 483 if (!radeon_is_px(drm_dev)) 484 return -EINVAL; 485 486 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 487 488 if (radeon_is_atpx_hybrid() || 489 !radeon_has_atpx_dgpu_power_cntl()) 490 pci_set_power_state(pdev, PCI_D0); 491 pci_restore_state(pdev); 492 ret = pci_enable_device(pdev); 493 if (ret) 494 return ret; 495 pci_set_master(pdev); 496 497 ret = radeon_resume_kms(drm_dev, false, false); 498 drm_kms_helper_poll_enable(drm_dev); 499 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 500 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 501 return 0; 502 } 503 504 static int radeon_pmops_runtime_idle(struct device *dev) 505 { 506 struct pci_dev *pdev = to_pci_dev(dev); 507 struct drm_device *drm_dev = pci_get_drvdata(pdev); 508 struct drm_crtc *crtc; 509 510 if (!radeon_is_px(drm_dev)) { 511 pm_runtime_forbid(dev); 512 return -EBUSY; 513 } 514 515 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 516 if (crtc->enabled) { 517 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 518 return -EBUSY; 519 } 520 } 521 522 pm_runtime_mark_last_busy(dev); 523 pm_runtime_autosuspend(dev); 524 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 525 return 1; 526 } 527 528 long radeon_drm_ioctl(struct file *filp, 529 unsigned int cmd, unsigned long arg) 530 { 531 struct drm_file *file_priv = filp->private_data; 532 struct drm_device *dev; 533 long ret; 534 dev = file_priv->minor->dev; 535 ret = pm_runtime_get_sync(dev->dev); 536 if (ret < 0) 537 return ret; 538 539 ret = drm_ioctl(filp, cmd, arg); 540 541 pm_runtime_mark_last_busy(dev->dev); 542 pm_runtime_put_autosuspend(dev->dev); 543 return ret; 544 } 545 546 #ifdef CONFIG_COMPAT 547 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 548 { 549 unsigned int nr = DRM_IOCTL_NR(cmd); 550 int ret; 551 552 if (nr < DRM_COMMAND_BASE) 553 return drm_compat_ioctl(filp, cmd, arg); 554 555 ret = radeon_drm_ioctl(filp, cmd, arg); 556 557 return ret; 558 } 559 #endif 560 561 static const struct dev_pm_ops radeon_pm_ops = { 562 .suspend = radeon_pmops_suspend, 563 .resume = radeon_pmops_resume, 564 .freeze = radeon_pmops_freeze, 565 .thaw = radeon_pmops_thaw, 566 .poweroff = radeon_pmops_freeze, 567 .restore = radeon_pmops_resume, 568 .runtime_suspend = radeon_pmops_runtime_suspend, 569 .runtime_resume = radeon_pmops_runtime_resume, 570 .runtime_idle = radeon_pmops_runtime_idle, 571 }; 572 #endif /* DUMBBELL_WIP */ 573 574 static const struct file_operations radeon_driver_kms_fops = { 575 .owner = THIS_MODULE, 576 #if 0 577 .open = drm_open, 578 .release = drm_release, 579 .unlocked_ioctl = radeon_drm_ioctl, 580 .mmap = radeon_mmap, 581 .poll = drm_poll, 582 .read = drm_read, 583 #endif 584 #ifdef CONFIG_COMPAT 585 .compat_ioctl = radeon_kms_compat_ioctl, 586 #endif 587 }; 588 589 static int radeon_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 590 struct sysctl_oid *top) 591 { 592 return drm_add_busid_modesetting(dev, ctx, top); 593 } 594 595 static bool 596 radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 597 bool in_vblank_irq, int *vpos, int *hpos, 598 ktime_t *stime, ktime_t *etime, 599 const struct drm_display_mode *mode) 600 { 601 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 602 stime, etime, mode); 603 } 604 605 static struct drm_driver kms_driver = { 606 .driver_features = 607 DRIVER_USE_AGP | 608 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 609 DRIVER_PRIME | DRIVER_RENDER, 610 .load = radeon_driver_load_kms, 611 .open = radeon_driver_open_kms, 612 .postclose = radeon_driver_postclose_kms, 613 .lastclose = radeon_driver_lastclose_kms, 614 .unload = radeon_driver_unload_kms, 615 .get_vblank_counter = radeon_get_vblank_counter_kms, 616 .enable_vblank = radeon_enable_vblank_kms, 617 .disable_vblank = radeon_disable_vblank_kms, 618 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 619 .get_scanout_position = radeon_get_crtc_scanout_position, 620 .irq_preinstall = radeon_driver_irq_preinstall_kms, 621 .irq_postinstall = radeon_driver_irq_postinstall_kms, 622 .irq_uninstall = radeon_driver_irq_uninstall_kms, 623 .irq_handler = radeon_driver_irq_handler_kms, 624 .sysctl_init = radeon_sysctl_init, 625 .ioctls = radeon_ioctls_kms, 626 .gem_free_object_unlocked = radeon_gem_object_free, 627 .gem_open_object = radeon_gem_object_open, 628 .gem_close_object = radeon_gem_object_close, 629 .dumb_create = radeon_mode_dumb_create, 630 .dumb_map_offset = radeon_mode_dumb_mmap, 631 .fops = &radeon_driver_kms_fops, 632 633 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 634 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 635 .gem_prime_export = radeon_gem_prime_export, 636 .gem_prime_import = drm_gem_prime_import, 637 .gem_prime_pin = radeon_gem_prime_pin, 638 .gem_prime_unpin = radeon_gem_prime_unpin, 639 .gem_prime_res_obj = radeon_gem_prime_res_obj, 640 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 641 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 642 .gem_prime_vmap = radeon_gem_prime_vmap, 643 .gem_prime_vunmap = radeon_gem_prime_vunmap, 644 645 .name = DRIVER_NAME, 646 .desc = DRIVER_DESC, 647 .date = DRIVER_DATE, 648 .major = KMS_DRIVER_MAJOR, 649 .minor = KMS_DRIVER_MINOR, 650 .patchlevel = KMS_DRIVER_PATCHLEVEL, 651 }; 652 653 static struct drm_driver *driver; 654 static struct pci_driver *pdriver; 655 656 #ifdef CONFIG_DRM_RADEON_UMS 657 static struct pci_driver radeon_pci_driver = { 658 .name = DRIVER_NAME, 659 .id_table = pciidlist, 660 }; 661 #endif 662 663 static struct pci_driver radeon_kms_pci_driver = { 664 #if 0 665 .name = DRIVER_NAME, 666 .id_table = pciidlist, 667 .probe = radeon_pci_probe, 668 .remove = radeon_pci_remove, 669 .shutdown = radeon_pci_shutdown, 670 .driver.pm = &radeon_pm_ops, 671 #endif 672 }; 673 674 static int __init radeon_init(void) 675 { 676 if (vgacon_text_force() && radeon_modeset == -1) { 677 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 678 radeon_modeset = 0; 679 } 680 /* set to modesetting by default if not nomodeset */ 681 if (radeon_modeset == -1) 682 radeon_modeset = 1; 683 684 if (radeon_modeset == 1) { 685 DRM_INFO("radeon kernel modesetting enabled.\n"); 686 driver = &kms_driver; 687 pdriver = &radeon_kms_pci_driver; 688 driver->driver_features |= DRIVER_MODESET; 689 driver->num_ioctls = radeon_max_kms_ioctl; 690 radeon_register_atpx_handler(); 691 692 } else { 693 DRM_ERROR("No UMS support in radeon module!\n"); 694 return -EINVAL; 695 } 696 697 return pci_register_driver(pdriver); 698 } 699 700 static void __exit radeon_exit(void) 701 { 702 #if 0 703 drm_pci_exit(driver, pdriver); 704 #endif 705 radeon_unregister_atpx_handler(); 706 } 707 708 /* =================================================================== */ 709 710 static int 711 radeon_pci_probe_dfly(device_t kdev) 712 { 713 int device, i = 0; 714 const struct pci_device_id *ent; 715 static struct pci_dev *pdev = NULL; 716 static device_t bsddev; 717 718 if (pci_get_class(kdev) != PCIC_DISPLAY) 719 return ENXIO; 720 721 if (pci_get_vendor(kdev) != PCI_VENDOR_ID_ATI) 722 return ENXIO; 723 724 device = pci_get_device(kdev); 725 726 for (i = 0; pciidlist[i].device != 0; i++) { 727 if (pciidlist[i].device == device) { 728 ent = &pciidlist[i]; 729 goto found; 730 } 731 } 732 733 return ENXIO; 734 found: 735 if (!strcmp(device_get_name(kdev), "drmsub")) 736 bsddev = device_get_parent(kdev); 737 else 738 bsddev = kdev; 739 740 drm_init_pdev(bsddev, &pdev); 741 742 /* Print the contents of pdev struct. */ 743 drm_print_pdev(pdev); 744 745 return radeon_pci_probe(pdev, ent); 746 } 747 748 static int radeon_driver_attach(device_t kdev) 749 { 750 return 0; 751 } 752 753 static int 754 radeon_suspend(device_t kdev) 755 { 756 struct drm_softc *softc = device_get_softc(kdev); 757 struct drm_device *dev = softc->drm_driver_data; 758 759 return -radeon_suspend_kms(dev, true, true, false); 760 } 761 762 static int 763 radeon_resume(device_t kdev) 764 { 765 struct drm_softc *softc = device_get_softc(kdev); 766 struct drm_device *dev = softc->drm_driver_data; 767 768 return -radeon_resume_kms(dev, true, true); 769 } 770 771 static device_method_t radeon_methods[] = { 772 /* Device interface */ 773 DEVMETHOD(device_probe, radeon_pci_probe_dfly), 774 DEVMETHOD(device_attach, radeon_driver_attach), 775 DEVMETHOD(device_suspend, radeon_suspend), 776 DEVMETHOD(device_resume, radeon_resume), 777 DEVMETHOD(device_detach, drm_device_detach), 778 DEVMETHOD_END 779 }; 780 781 static driver_t radeon_driver = { 782 "drm", 783 radeon_methods, 784 sizeof(struct drm_softc) 785 }; 786 787 module_init(radeon_init); 788 module_exit(radeon_exit); 789 790 extern devclass_t drm_devclass; 791 DRIVER_MODULE_ORDERED(radeon, vgapci, radeon_driver, &drm_devclass, 792 NULL, NULL, SI_ORDER_ANY); 793 MODULE_DEPEND(radeon, drm, 1, 1, 1); 794 #ifdef CONFIG_ACPI 795 MODULE_DEPEND(radeon, acpi, 1, 1, 1); 796 #endif 797