1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 * 31 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_drv.c 254885 2013-08-25 19:37:15Z dumbbell $ 32 */ 33 34 #include <drm/drmP.h> 35 #include <drm/radeon_drm.h> 36 #include "radeon_drv.h" 37 #include "radeon_gem.h" 38 #include "radeon_kms.h" 39 #include "radeon_irq_kms.h" 40 41 #include <drm/drm_pciids.h> 42 #include <linux/module.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/vga_switcheroo.h> 45 #include <drm/drm_gem.h> 46 47 #include "drm/drm_crtc_helper.h" 48 /* 49 * KMS wrapper. 50 * - 2.0.0 - initial interface 51 * - 2.1.0 - add square tiling interface 52 * - 2.2.0 - add r6xx/r7xx const buffer support 53 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 54 * - 2.4.0 - add crtc id query 55 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 56 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 57 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 58 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 59 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 60 * 2.10.0 - fusion 2D tiling 61 * 2.11.0 - backend map, initial compute support for the CS checker 62 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 63 * 2.13.0 - virtual memory support, streamout 64 * 2.14.0 - add evergreen tiling informations 65 * 2.15.0 - add max_pipes query 66 * 2.16.0 - fix evergreen 2D tiled surface calculation 67 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 68 * 2.18.0 - r600-eg: allow "invalid" DB formats 69 * 2.19.0 - r600-eg: MSAA textures 70 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 71 * 2.21.0 - r600-r700: FMASK and CMASK 72 * 2.22.0 - r600 only: RESOLVE_BOX allowed 73 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 74 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 75 * 2.25.0 - eg+: new info request for num SE and num SH 76 * 2.26.0 - r600-eg: fix htile size computation 77 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 78 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 79 * 2.29.0 - R500 FP16 color clear registers 80 * 2.30.0 - fix for FMASK texturing 81 * 2.31.0 - Add fastfb support for rs690 82 * 2.32.0 - new info request for rings working 83 * 2.33.0 - Add SI tiling mode array query 84 * 2.34.0 - Add CIK tiling mode array query 85 * 2.35.0 - Add CIK macrotile mode array query 86 * 2.36.0 - Fix CIK DCE tiling setup 87 * 2.37.0 - allow GS ring setup on r6xx/r7xx 88 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 89 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 90 * 2.39.0 - Add INFO query for number of active CUs 91 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 92 * CS to GPU on >= r600 93 */ 94 #define KMS_DRIVER_MAJOR 2 95 #define KMS_DRIVER_MINOR 40 96 #define KMS_DRIVER_PATCHLEVEL 0 97 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 98 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 99 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 100 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 101 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 102 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 103 int *max_error, 104 struct timeval *vblank_time, 105 unsigned flags); 106 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 107 unsigned int flags, int *vpos, int *hpos, 108 ktime_t *stime, ktime_t *etime, 109 const struct drm_display_mode *mode); 110 extern bool radeon_is_px(struct drm_device *dev); 111 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 112 extern int radeon_max_kms_ioctl; 113 #ifdef DUMBBELL_WIP 114 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 115 #endif /* DUMBBELL_WIP */ 116 int radeon_mode_dumb_mmap(struct drm_file *filp, 117 struct drm_device *dev, 118 uint32_t handle, uint64_t *offset_p); 119 int radeon_mode_dumb_create(struct drm_file *file_priv, 120 struct drm_device *dev, 121 struct drm_mode_create_dumb *args); 122 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 123 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 124 struct dma_buf_attachment *, 125 struct sg_table *sg); 126 int radeon_gem_prime_pin(struct drm_gem_object *obj); 127 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 128 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 129 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 130 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 131 132 #if defined(CONFIG_DEBUG_FS) 133 int radeon_debugfs_init(struct drm_minor *minor); 134 void radeon_debugfs_cleanup(struct drm_minor *minor); 135 #endif 136 137 /* atpx handler */ 138 #if defined(CONFIG_VGA_SWITCHEROO) 139 void radeon_register_atpx_handler(void); 140 void radeon_unregister_atpx_handler(void); 141 #else 142 static inline void radeon_register_atpx_handler(void) {} 143 static inline void radeon_unregister_atpx_handler(void) {} 144 #endif 145 146 int radeon_no_wb; 147 int radeon_modeset = 1; 148 int radeon_dynclks = -1; 149 int radeon_r4xx_atom = 0; 150 int radeon_agpmode = 0; 151 int radeon_vram_limit = 0; 152 int radeon_gart_size = -1; /* auto */ 153 int radeon_benchmarking = 0; 154 int radeon_testing = 0; 155 int radeon_connector_table = 0; 156 int radeon_tv = 1; 157 int radeon_audio = -1; 158 int radeon_disp_priority = 0; 159 int radeon_hw_i2c = 0; 160 int radeon_pcie_gen2 = -1; 161 int radeon_msi = -1; 162 int radeon_lockup_timeout = 10000; 163 int radeon_fastfb = 0; 164 int radeon_dpm = -1; 165 int radeon_aspm = -1; 166 int radeon_runtime_pm = -1; 167 int radeon_hard_reset = 0; 168 int radeon_vm_size = 8; 169 int radeon_vm_block_size = -1; 170 int radeon_deep_color = 0; 171 int radeon_use_pflipirq = 2; 172 int radeon_bapm = -1; 173 int radeon_backlight = -1; 174 175 TUNABLE_INT("drm.radeon.no_wb", &radeon_no_wb); 176 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 177 module_param_named(no_wb, radeon_no_wb, int, 0444); 178 179 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 180 module_param_named(modeset, radeon_modeset, int, 0400); 181 182 TUNABLE_INT("drm.radeon.dynclks", &radeon_dynclks); 183 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 184 module_param_named(dynclks, radeon_dynclks, int, 0444); 185 186 TUNABLE_INT("drm.radeon.r4xx_atom", &radeon_r4xx_atom); 187 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 188 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 189 190 TUNABLE_INT("drm.radeon.vram_limit", &radeon_vram_limit); 191 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 192 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 193 194 TUNABLE_INT("drm.radeon.agpmode", &radeon_agpmode); 195 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 196 module_param_named(agpmode, radeon_agpmode, int, 0444); 197 198 TUNABLE_INT("drm.radeon.gart_size", &radeon_gart_size); 199 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 200 module_param_named(gartsize, radeon_gart_size, int, 0600); 201 202 TUNABLE_INT("drm.radeon.benchmarking", &radeon_benchmarking); 203 MODULE_PARM_DESC(benchmark, "Run benchmark"); 204 module_param_named(benchmark, radeon_benchmarking, int, 0444); 205 206 TUNABLE_INT("drm.radeon.testing", &radeon_testing); 207 MODULE_PARM_DESC(test, "Run tests"); 208 module_param_named(test, radeon_testing, int, 0444); 209 210 TUNABLE_INT("drm.radeon.connector_table", &radeon_connector_table); 211 MODULE_PARM_DESC(connector_table, "Force connector table"); 212 module_param_named(connector_table, radeon_connector_table, int, 0444); 213 214 TUNABLE_INT("drm.radeon.tv", &radeon_tv); 215 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 216 module_param_named(tv, radeon_tv, int, 0444); 217 218 TUNABLE_INT("drm.radeon.audio", &radeon_audio); 219 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 220 module_param_named(audio, radeon_audio, int, 0444); 221 222 TUNABLE_INT("drm.radeon.disp_priority", &radeon_disp_priority); 223 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 224 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 225 226 TUNABLE_INT("drm.radeon.hw_i2c", &radeon_hw_i2c); 227 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 228 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 229 230 TUNABLE_INT("drm.radeon.pcie_gen2", &radeon_pcie_gen2); 231 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 232 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 233 234 TUNABLE_INT("drm.radeon.msi", &radeon_msi); 235 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 236 module_param_named(msi, radeon_msi, int, 0444); 237 238 TUNABLE_INT("drm.radeon.lockup_timeout", &radeon_lockup_timeout); 239 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 240 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 241 242 TUNABLE_INT("drm.radeon.fastfb", &radeon_fastfb); 243 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 244 module_param_named(fastfb, radeon_fastfb, int, 0444); 245 246 TUNABLE_INT("drm.radeon.dpm", &radeon_dpm); 247 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 248 module_param_named(dpm, radeon_dpm, int, 0444); 249 250 TUNABLE_INT("drm.radeon.aspm", &radeon_aspm); 251 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 252 module_param_named(aspm, radeon_aspm, int, 0444); 253 254 TUNABLE_INT("drm.radeon.runtime_pm", &radeon_runtime_pm); /* careful with this */ 255 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 256 module_param_named(runpm, radeon_runtime_pm, int, 0444); 257 258 TUNABLE_INT("drm.radeon.hard_reset", &radeon_hard_reset); /* very careful with this */ 259 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 260 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 261 262 TUNABLE_INT("drm.radeon.vm_size", &radeon_vm_size); 263 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 264 module_param_named(vm_size, radeon_vm_size, int, 0444); 265 266 TUNABLE_INT("drm.radeon.vm_block_size", &radeon_vm_block_size); 267 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 268 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 269 270 TUNABLE_INT("drm.radeon.deep_color", &radeon_deep_color); 271 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 272 module_param_named(deep_color, radeon_deep_color, int, 0444); 273 274 TUNABLE_INT("drm.radeon.use_pflipirq", &radeon_use_pflipirq); 275 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 276 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 277 278 TUNABLE_INT("drm.radeon.bapm", &radeon_bapm); 279 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 280 module_param_named(bapm, radeon_bapm, int, 0444); 281 282 TUNABLE_INT("drm.radeon.backlight", &radeon_backlight); 283 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 284 module_param_named(backlight, radeon_backlight, int, 0444); 285 286 static drm_pci_id_list_t pciidlist[] = { 287 radeon_PCI_IDS 288 }; 289 290 static struct drm_driver kms_driver; 291 292 #ifdef DUMBBELL_WIP 293 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 294 { 295 struct apertures_struct *ap; 296 bool primary = false; 297 298 ap = alloc_apertures(1); 299 if (!ap) 300 return -ENOMEM; 301 302 ap->ranges[0].base = pci_resource_start(pdev, 0); 303 ap->ranges[0].size = pci_resource_len(pdev, 0); 304 305 #ifdef CONFIG_X86 306 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 307 #endif 308 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 309 kfree(ap); 310 311 return 0; 312 } 313 314 static int radeon_pci_probe(struct pci_dev *pdev, 315 const struct pci_device_id *ent) 316 { 317 int ret; 318 319 /* Get rid of things like offb */ 320 ret = radeon_kick_out_firmware_fb(pdev); 321 if (ret) 322 return ret; 323 324 return drm_get_pci_dev(pdev, ent, &kms_driver); 325 } 326 327 static void 328 radeon_pci_remove(struct pci_dev *pdev) 329 { 330 struct drm_device *dev = pci_get_drvdata(pdev); 331 332 drm_put_dev(dev); 333 } 334 335 static int radeon_pmops_suspend(struct device *dev) 336 { 337 struct pci_dev *pdev = to_pci_dev(dev); 338 struct drm_device *drm_dev = pci_get_drvdata(pdev); 339 return radeon_suspend_kms(drm_dev, true, true); 340 } 341 342 static int radeon_pmops_resume(struct device *dev) 343 { 344 struct pci_dev *pdev = to_pci_dev(dev); 345 struct drm_device *drm_dev = pci_get_drvdata(pdev); 346 return radeon_resume_kms(drm_dev, true, true); 347 } 348 349 static int radeon_pmops_freeze(struct device *dev) 350 { 351 struct pci_dev *pdev = to_pci_dev(dev); 352 struct drm_device *drm_dev = pci_get_drvdata(pdev); 353 return radeon_suspend_kms(drm_dev, false, true); 354 } 355 356 static int radeon_pmops_thaw(struct device *dev) 357 { 358 struct pci_dev *pdev = to_pci_dev(dev); 359 struct drm_device *drm_dev = pci_get_drvdata(pdev); 360 return radeon_resume_kms(drm_dev, false, true); 361 } 362 363 static int radeon_pmops_runtime_suspend(struct device *dev) 364 { 365 struct pci_dev *pdev = to_pci_dev(dev); 366 struct drm_device *drm_dev = pci_get_drvdata(pdev); 367 int ret; 368 369 if (!radeon_is_px(drm_dev)) { 370 #ifdef PM_TODO 371 pm_runtime_forbid(dev); 372 #endif 373 return -EBUSY; 374 } 375 376 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 377 drm_kms_helper_poll_disable(drm_dev); 378 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 379 380 ret = radeon_suspend_kms(drm_dev, false, false); 381 pci_save_state(pdev); 382 pci_disable_device(pdev); 383 pci_set_power_state(pdev, PCI_D3cold); 384 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 385 386 return 0; 387 } 388 389 static int radeon_pmops_runtime_resume(struct device *dev) 390 { 391 struct pci_dev *pdev = to_pci_dev(dev); 392 struct drm_device *drm_dev = pci_get_drvdata(pdev); 393 int ret; 394 395 if (!radeon_is_px(drm_dev)) 396 return -EINVAL; 397 398 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 399 400 pci_set_power_state(pdev, PCI_D0); 401 pci_restore_state(pdev); 402 ret = pci_enable_device(pdev); 403 if (ret) 404 return ret; 405 pci_set_master(pdev); 406 407 ret = radeon_resume_kms(drm_dev, false, false); 408 drm_kms_helper_poll_enable(drm_dev); 409 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 410 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 411 return 0; 412 } 413 414 static int radeon_pmops_runtime_idle(struct device *dev) 415 { 416 struct pci_dev *pdev = to_pci_dev(dev); 417 struct drm_device *drm_dev = pci_get_drvdata(pdev); 418 struct drm_crtc *crtc; 419 420 if (!radeon_is_px(drm_dev)) { 421 #ifdef PM_TODO 422 pm_runtime_forbid(dev); 423 #endif 424 return -EBUSY; 425 } 426 427 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 428 if (crtc->enabled) { 429 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 430 return -EBUSY; 431 } 432 } 433 434 pm_runtime_mark_last_busy(dev); 435 pm_runtime_autosuspend(dev); 436 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 437 return 1; 438 } 439 440 long radeon_drm_ioctl(struct file *filp, 441 unsigned int cmd, unsigned long arg) 442 { 443 struct drm_file *file_priv = filp->private_data; 444 struct drm_device *dev; 445 long ret; 446 dev = file_priv->minor->dev; 447 ret = pm_runtime_get_sync(dev->dev); 448 if (ret < 0) 449 return ret; 450 451 ret = drm_ioctl(filp, cmd, arg); 452 453 pm_runtime_mark_last_busy(dev->dev); 454 pm_runtime_put_autosuspend(dev->dev); 455 return ret; 456 } 457 458 static const struct dev_pm_ops radeon_pm_ops = { 459 .suspend = radeon_pmops_suspend, 460 .resume = radeon_pmops_resume, 461 .freeze = radeon_pmops_freeze, 462 .thaw = radeon_pmops_thaw, 463 .poweroff = radeon_pmops_freeze, 464 .restore = radeon_pmops_resume, 465 .runtime_suspend = radeon_pmops_runtime_suspend, 466 .runtime_resume = radeon_pmops_runtime_resume, 467 .runtime_idle = radeon_pmops_runtime_idle, 468 }; 469 470 static const struct file_operations radeon_driver_kms_fops = { 471 .owner = THIS_MODULE, 472 .open = drm_open, 473 .release = drm_release, 474 .unlocked_ioctl = radeon_drm_ioctl, 475 .mmap = radeon_mmap, 476 .poll = drm_poll, 477 .read = drm_read, 478 #ifdef CONFIG_COMPAT 479 .compat_ioctl = radeon_kms_compat_ioctl, 480 #endif 481 }; 482 #endif /* DUMBBELL_WIP */ 483 484 static int radeon_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 485 struct sysctl_oid *top) 486 { 487 return drm_add_busid_modesetting(dev, ctx, top); 488 } 489 490 static struct drm_driver kms_driver = { 491 .driver_features = 492 DRIVER_USE_AGP | 493 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 494 DRIVER_PRIME | DRIVER_RENDER, 495 .load = radeon_driver_load_kms, 496 .open = radeon_driver_open_kms, 497 .preclose = radeon_driver_preclose_kms, 498 .postclose = radeon_driver_postclose_kms, 499 .lastclose = radeon_driver_lastclose_kms, 500 .unload = radeon_driver_unload_kms, 501 .get_vblank_counter = radeon_get_vblank_counter_kms, 502 .enable_vblank = radeon_enable_vblank_kms, 503 .disable_vblank = radeon_disable_vblank_kms, 504 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 505 .get_scanout_position = radeon_get_crtc_scanoutpos, 506 .irq_preinstall = radeon_driver_irq_preinstall_kms, 507 .irq_postinstall = radeon_driver_irq_postinstall_kms, 508 .irq_uninstall = radeon_driver_irq_uninstall_kms, 509 .irq_handler = radeon_driver_irq_handler_kms, 510 .sysctl_init = radeon_sysctl_init, 511 .ioctls = radeon_ioctls_kms, 512 .gem_free_object = radeon_gem_object_free, 513 .gem_open_object = radeon_gem_object_open, 514 .gem_close_object = radeon_gem_object_close, 515 .dumb_create = radeon_mode_dumb_create, 516 .dumb_map_offset = radeon_mode_dumb_mmap, 517 .dumb_destroy = drm_gem_dumb_destroy, 518 #ifdef DUMBBELL_WIP 519 .fops = &radeon_driver_kms_fops, 520 #endif /* DUMBBELL_WIP */ 521 522 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 523 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 524 #ifdef DUMBBELL_WIP 525 .gem_prime_export = drm_gem_prime_export, 526 .gem_prime_import = drm_gem_prime_import, 527 .gem_prime_pin = radeon_gem_prime_pin, 528 .gem_prime_unpin = radeon_gem_prime_unpin, 529 .gem_prime_res_obj = radeon_gem_prime_res_obj, 530 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 531 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 532 .gem_prime_vmap = radeon_gem_prime_vmap, 533 .gem_prime_vunmap = radeon_gem_prime_vunmap, 534 #endif /* DUMBBELL_WIP */ 535 536 .name = DRIVER_NAME, 537 .desc = DRIVER_DESC, 538 .date = DRIVER_DATE, 539 .major = KMS_DRIVER_MAJOR, 540 .minor = KMS_DRIVER_MINOR, 541 .patchlevel = KMS_DRIVER_PATCHLEVEL, 542 }; 543 544 #ifdef DUMBBELL_WIP 545 static struct drm_driver *driver; 546 static struct pci_driver *pdriver; 547 548 static struct pci_driver radeon_kms_pci_driver = { 549 .name = DRIVER_NAME, 550 .id_table = pciidlist, 551 .probe = radeon_pci_probe, 552 .remove = radeon_pci_remove, 553 .driver.pm = &radeon_pm_ops, 554 }; 555 556 static int __init radeon_init(void) 557 { 558 if (radeon_modeset == 1) { 559 DRM_INFO("radeon kernel modesetting enabled.\n"); 560 driver = &kms_driver; 561 pdriver = &radeon_kms_pci_driver; 562 driver->driver_features |= DRIVER_MODESET; 563 driver->num_ioctls = radeon_max_kms_ioctl; 564 radeon_register_atpx_handler(); 565 566 } else { 567 DRM_ERROR("No UMS support in radeon module!\n"); 568 return -EINVAL; 569 } 570 571 /* let modprobe override vga console setting */ 572 return drm_pci_init(driver, pdriver); 573 } 574 575 static void __exit radeon_exit(void) 576 { 577 drm_pci_exit(driver, pdriver); 578 radeon_unregister_atpx_handler(); 579 } 580 #endif /* DUMBBELL_WIP */ 581 582 /* =================================================================== */ 583 584 static int 585 radeon_probe(device_t kdev) 586 { 587 588 return drm_probe(kdev, pciidlist); 589 } 590 591 static int 592 radeon_attach(device_t kdev) 593 { 594 struct drm_device *dev; 595 596 dev = device_get_softc(kdev); 597 if (radeon_modeset == 1) { 598 kms_driver.driver_features |= DRIVER_MODESET; 599 kms_driver.num_ioctls = radeon_max_kms_ioctl; 600 radeon_register_atpx_handler(); 601 } 602 dev->driver = &kms_driver; 603 return (drm_attach(kdev, pciidlist)); 604 } 605 606 static int 607 radeon_suspend(device_t kdev) 608 { 609 struct drm_device *dev; 610 int ret; 611 612 dev = device_get_softc(kdev); 613 ret = radeon_suspend_kms(dev, true, true); 614 615 return (-ret); 616 } 617 618 static int 619 radeon_resume(device_t kdev) 620 { 621 struct drm_device *dev; 622 int ret; 623 624 dev = device_get_softc(kdev); 625 ret = radeon_resume_kms(dev, true, true); 626 627 return (-ret); 628 } 629 630 static device_method_t radeon_methods[] = { 631 /* Device interface */ 632 DEVMETHOD(device_probe, radeon_probe), 633 DEVMETHOD(device_attach, radeon_attach), 634 DEVMETHOD(device_suspend, radeon_suspend), 635 DEVMETHOD(device_resume, radeon_resume), 636 DEVMETHOD(device_detach, drm_release), 637 DEVMETHOD_END 638 }; 639 640 static driver_t radeon_driver = { 641 "drm", 642 radeon_methods, 643 sizeof(struct drm_device) 644 }; 645 646 extern devclass_t drm_devclass; 647 DRIVER_MODULE_ORDERED(radeonkms, vgapci, radeon_driver, drm_devclass, 648 NULL, NULL, SI_ORDER_ANY); 649 MODULE_DEPEND(radeonkms, drm, 1, 1, 1); 650 MODULE_DEPEND(radeonkms, agp, 1, 1, 1); 651 MODULE_DEPEND(radeonkms, iicbus, 1, 1, 1); 652 MODULE_DEPEND(radeonkms, iic, 1, 1, 1); 653 MODULE_DEPEND(radeonkms, iicbb, 1, 1, 1); 654 #ifdef CONFIG_ACPI 655 MODULE_DEPEND(radeonkms, acpi, 1, 1, 1); 656 #endif 657