1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 * 31 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_drv.c 254885 2013-08-25 19:37:15Z dumbbell $ 32 */ 33 34 #include <drm/drmP.h> 35 #include <drm/radeon_drm.h> 36 #include "radeon_drv.h" 37 #include "radeon_gem.h" 38 #include "radeon_kms.h" 39 #include "radeon_irq_kms.h" 40 41 #include <drm/drm_pciids.h> 42 #include <linux/module.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/vga_switcheroo.h> 45 #include <drm/drm_gem.h> 46 47 #include "drm/drm_crtc_helper.h" 48 #include "radeon_kfd.h" 49 50 /* 51 * KMS wrapper. 52 * - 2.0.0 - initial interface 53 * - 2.1.0 - add square tiling interface 54 * - 2.2.0 - add r6xx/r7xx const buffer support 55 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 56 * - 2.4.0 - add crtc id query 57 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 58 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 59 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 60 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 61 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 62 * 2.10.0 - fusion 2D tiling 63 * 2.11.0 - backend map, initial compute support for the CS checker 64 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 65 * 2.13.0 - virtual memory support, streamout 66 * 2.14.0 - add evergreen tiling informations 67 * 2.15.0 - add max_pipes query 68 * 2.16.0 - fix evergreen 2D tiled surface calculation 69 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 70 * 2.18.0 - r600-eg: allow "invalid" DB formats 71 * 2.19.0 - r600-eg: MSAA textures 72 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 73 * 2.21.0 - r600-r700: FMASK and CMASK 74 * 2.22.0 - r600 only: RESOLVE_BOX allowed 75 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 76 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 77 * 2.25.0 - eg+: new info request for num SE and num SH 78 * 2.26.0 - r600-eg: fix htile size computation 79 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 80 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 81 * 2.29.0 - R500 FP16 color clear registers 82 * 2.30.0 - fix for FMASK texturing 83 * 2.31.0 - Add fastfb support for rs690 84 * 2.32.0 - new info request for rings working 85 * 2.33.0 - Add SI tiling mode array query 86 * 2.34.0 - Add CIK tiling mode array query 87 * 2.35.0 - Add CIK macrotile mode array query 88 * 2.36.0 - Fix CIK DCE tiling setup 89 * 2.37.0 - allow GS ring setup on r6xx/r7xx 90 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 91 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 92 * 2.39.0 - Add INFO query for number of active CUs 93 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 94 * CS to GPU on >= r600 95 */ 96 #define KMS_DRIVER_MAJOR 2 97 #define KMS_DRIVER_MINOR 40 98 #define KMS_DRIVER_PATCHLEVEL 0 99 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 100 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 101 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 102 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 103 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 104 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 105 int *max_error, 106 struct timeval *vblank_time, 107 unsigned flags); 108 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 109 unsigned int flags, int *vpos, int *hpos, 110 ktime_t *stime, ktime_t *etime, 111 const struct drm_display_mode *mode); 112 extern bool radeon_is_px(struct drm_device *dev); 113 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 114 extern int radeon_max_kms_ioctl; 115 #ifdef DUMBBELL_WIP 116 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 117 #endif /* DUMBBELL_WIP */ 118 int radeon_mode_dumb_mmap(struct drm_file *filp, 119 struct drm_device *dev, 120 uint32_t handle, uint64_t *offset_p); 121 int radeon_mode_dumb_create(struct drm_file *file_priv, 122 struct drm_device *dev, 123 struct drm_mode_create_dumb *args); 124 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 125 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 126 struct dma_buf_attachment *, 127 struct sg_table *sg); 128 int radeon_gem_prime_pin(struct drm_gem_object *obj); 129 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 130 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 131 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 132 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 133 134 #if defined(CONFIG_DEBUG_FS) 135 int radeon_debugfs_init(struct drm_minor *minor); 136 void radeon_debugfs_cleanup(struct drm_minor *minor); 137 #endif 138 139 /* atpx handler */ 140 #if defined(CONFIG_VGA_SWITCHEROO) 141 void radeon_register_atpx_handler(void); 142 void radeon_unregister_atpx_handler(void); 143 #else 144 static inline void radeon_register_atpx_handler(void) {} 145 static inline void radeon_unregister_atpx_handler(void) {} 146 #endif 147 148 int radeon_no_wb; 149 int radeon_modeset = 1; 150 int radeon_dynclks = -1; 151 int radeon_r4xx_atom = 0; 152 int radeon_agpmode = 0; 153 int radeon_vram_limit = 0; 154 int radeon_gart_size = -1; /* auto */ 155 int radeon_benchmarking = 0; 156 int radeon_testing = 0; 157 int radeon_connector_table = 0; 158 int radeon_tv = 1; 159 int radeon_audio = -1; 160 int radeon_disp_priority = 0; 161 #ifdef __DragonFly__ 162 int radeon_hw_i2c = 1; 163 #else 164 int radeon_hw_i2c = 0; 165 #endif 166 int radeon_pcie_gen2 = -1; 167 int radeon_msi = -1; 168 int radeon_lockup_timeout = 10000; 169 int radeon_fastfb = 0; 170 int radeon_dpm = -1; 171 int radeon_aspm = -1; 172 int radeon_runtime_pm = -1; 173 int radeon_hard_reset = 0; 174 int radeon_vm_size = 8; 175 int radeon_vm_block_size = -1; 176 int radeon_deep_color = 0; 177 int radeon_use_pflipirq = 2; 178 int radeon_bapm = -1; 179 int radeon_backlight = -1; 180 181 TUNABLE_INT("drm.radeon.no_wb", &radeon_no_wb); 182 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 183 module_param_named(no_wb, radeon_no_wb, int, 0444); 184 185 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 186 module_param_named(modeset, radeon_modeset, int, 0400); 187 188 TUNABLE_INT("drm.radeon.dynclks", &radeon_dynclks); 189 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 190 module_param_named(dynclks, radeon_dynclks, int, 0444); 191 192 TUNABLE_INT("drm.radeon.r4xx_atom", &radeon_r4xx_atom); 193 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 194 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 195 196 TUNABLE_INT("drm.radeon.vram_limit", &radeon_vram_limit); 197 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 198 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 199 200 TUNABLE_INT("drm.radeon.agpmode", &radeon_agpmode); 201 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 202 module_param_named(agpmode, radeon_agpmode, int, 0444); 203 204 TUNABLE_INT("drm.radeon.gart_size", &radeon_gart_size); 205 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 206 module_param_named(gartsize, radeon_gart_size, int, 0600); 207 208 TUNABLE_INT("drm.radeon.benchmarking", &radeon_benchmarking); 209 MODULE_PARM_DESC(benchmark, "Run benchmark"); 210 module_param_named(benchmark, radeon_benchmarking, int, 0444); 211 212 TUNABLE_INT("drm.radeon.testing", &radeon_testing); 213 MODULE_PARM_DESC(test, "Run tests"); 214 module_param_named(test, radeon_testing, int, 0444); 215 216 TUNABLE_INT("drm.radeon.connector_table", &radeon_connector_table); 217 MODULE_PARM_DESC(connector_table, "Force connector table"); 218 module_param_named(connector_table, radeon_connector_table, int, 0444); 219 220 TUNABLE_INT("drm.radeon.tv", &radeon_tv); 221 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 222 module_param_named(tv, radeon_tv, int, 0444); 223 224 TUNABLE_INT("drm.radeon.audio", &radeon_audio); 225 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 226 module_param_named(audio, radeon_audio, int, 0444); 227 228 TUNABLE_INT("drm.radeon.disp_priority", &radeon_disp_priority); 229 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 230 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 231 232 TUNABLE_INT("drm.radeon.hw_i2c", &radeon_hw_i2c); 233 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 234 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 235 236 TUNABLE_INT("drm.radeon.pcie_gen2", &radeon_pcie_gen2); 237 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 238 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 239 240 TUNABLE_INT("drm.radeon.msi", &radeon_msi); 241 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 242 module_param_named(msi, radeon_msi, int, 0444); 243 244 TUNABLE_INT("drm.radeon.lockup_timeout", &radeon_lockup_timeout); 245 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 246 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 247 248 TUNABLE_INT("drm.radeon.fastfb", &radeon_fastfb); 249 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 250 module_param_named(fastfb, radeon_fastfb, int, 0444); 251 252 TUNABLE_INT("drm.radeon.dpm", &radeon_dpm); 253 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 254 module_param_named(dpm, radeon_dpm, int, 0444); 255 256 TUNABLE_INT("drm.radeon.aspm", &radeon_aspm); 257 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 258 module_param_named(aspm, radeon_aspm, int, 0444); 259 260 TUNABLE_INT("drm.radeon.runtime_pm", &radeon_runtime_pm); /* careful with this */ 261 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 262 module_param_named(runpm, radeon_runtime_pm, int, 0444); 263 264 TUNABLE_INT("drm.radeon.hard_reset", &radeon_hard_reset); /* very careful with this */ 265 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 266 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 267 268 TUNABLE_INT("drm.radeon.vm_size", &radeon_vm_size); 269 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 270 module_param_named(vm_size, radeon_vm_size, int, 0444); 271 272 TUNABLE_INT("drm.radeon.vm_block_size", &radeon_vm_block_size); 273 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 274 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 275 276 TUNABLE_INT("drm.radeon.deep_color", &radeon_deep_color); 277 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 278 module_param_named(deep_color, radeon_deep_color, int, 0444); 279 280 TUNABLE_INT("drm.radeon.use_pflipirq", &radeon_use_pflipirq); 281 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 282 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 283 284 TUNABLE_INT("drm.radeon.bapm", &radeon_bapm); 285 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 286 module_param_named(bapm, radeon_bapm, int, 0444); 287 288 TUNABLE_INT("drm.radeon.backlight", &radeon_backlight); 289 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 290 module_param_named(backlight, radeon_backlight, int, 0444); 291 292 static drm_pci_id_list_t pciidlist[] = { 293 radeon_PCI_IDS 294 }; 295 296 static struct drm_driver kms_driver; 297 298 #ifdef DUMBBELL_WIP 299 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 300 { 301 struct apertures_struct *ap; 302 bool primary = false; 303 304 ap = alloc_apertures(1); 305 if (!ap) 306 return -ENOMEM; 307 308 ap->ranges[0].base = pci_resource_start(pdev, 0); 309 ap->ranges[0].size = pci_resource_len(pdev, 0); 310 311 #ifdef CONFIG_X86 312 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 313 #endif 314 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 315 kfree(ap); 316 317 return 0; 318 } 319 320 static int radeon_pci_probe(struct pci_dev *pdev, 321 const struct pci_device_id *ent) 322 { 323 int ret; 324 325 /* Get rid of things like offb */ 326 ret = radeon_kick_out_firmware_fb(pdev); 327 if (ret) 328 return ret; 329 330 return drm_get_pci_dev(pdev, ent, &kms_driver); 331 } 332 333 static void 334 radeon_pci_remove(struct pci_dev *pdev) 335 { 336 struct drm_device *dev = pci_get_drvdata(pdev); 337 338 drm_put_dev(dev); 339 } 340 341 static int radeon_pmops_suspend(struct device *dev) 342 { 343 struct pci_dev *pdev = to_pci_dev(dev); 344 struct drm_device *drm_dev = pci_get_drvdata(pdev); 345 return radeon_suspend_kms(drm_dev, true, true); 346 } 347 348 static int radeon_pmops_resume(struct device *dev) 349 { 350 struct pci_dev *pdev = to_pci_dev(dev); 351 struct drm_device *drm_dev = pci_get_drvdata(pdev); 352 return radeon_resume_kms(drm_dev, true, true); 353 } 354 355 static int radeon_pmops_freeze(struct device *dev) 356 { 357 struct pci_dev *pdev = to_pci_dev(dev); 358 struct drm_device *drm_dev = pci_get_drvdata(pdev); 359 return radeon_suspend_kms(drm_dev, false, true); 360 } 361 362 static int radeon_pmops_thaw(struct device *dev) 363 { 364 struct pci_dev *pdev = to_pci_dev(dev); 365 struct drm_device *drm_dev = pci_get_drvdata(pdev); 366 return radeon_resume_kms(drm_dev, false, true); 367 } 368 369 static int radeon_pmops_runtime_suspend(struct device *dev) 370 { 371 struct pci_dev *pdev = to_pci_dev(dev); 372 struct drm_device *drm_dev = pci_get_drvdata(pdev); 373 int ret; 374 375 if (!radeon_is_px(drm_dev)) { 376 #ifdef PM_TODO 377 pm_runtime_forbid(dev); 378 #endif 379 return -EBUSY; 380 } 381 382 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 383 drm_kms_helper_poll_disable(drm_dev); 384 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 385 386 ret = radeon_suspend_kms(drm_dev, false, false); 387 pci_save_state(pdev); 388 pci_disable_device(pdev); 389 pci_set_power_state(pdev, PCI_D3cold); 390 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 391 392 return 0; 393 } 394 395 static int radeon_pmops_runtime_resume(struct device *dev) 396 { 397 struct pci_dev *pdev = to_pci_dev(dev); 398 struct drm_device *drm_dev = pci_get_drvdata(pdev); 399 int ret; 400 401 if (!radeon_is_px(drm_dev)) 402 return -EINVAL; 403 404 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 405 406 pci_set_power_state(pdev, PCI_D0); 407 pci_restore_state(pdev); 408 ret = pci_enable_device(pdev); 409 if (ret) 410 return ret; 411 pci_set_master(pdev); 412 413 ret = radeon_resume_kms(drm_dev, false, false); 414 drm_kms_helper_poll_enable(drm_dev); 415 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 416 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 417 return 0; 418 } 419 420 static int radeon_pmops_runtime_idle(struct device *dev) 421 { 422 struct pci_dev *pdev = to_pci_dev(dev); 423 struct drm_device *drm_dev = pci_get_drvdata(pdev); 424 struct drm_crtc *crtc; 425 426 if (!radeon_is_px(drm_dev)) { 427 #ifdef PM_TODO 428 pm_runtime_forbid(dev); 429 #endif 430 return -EBUSY; 431 } 432 433 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 434 if (crtc->enabled) { 435 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 436 return -EBUSY; 437 } 438 } 439 440 pm_runtime_mark_last_busy(dev); 441 pm_runtime_autosuspend(dev); 442 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 443 return 1; 444 } 445 446 long radeon_drm_ioctl(struct file *filp, 447 unsigned int cmd, unsigned long arg) 448 { 449 struct drm_file *file_priv = filp->private_data; 450 struct drm_device *dev; 451 long ret; 452 dev = file_priv->minor->dev; 453 ret = pm_runtime_get_sync(dev->dev); 454 if (ret < 0) 455 return ret; 456 457 ret = drm_ioctl(filp, cmd, arg); 458 459 pm_runtime_mark_last_busy(dev->dev); 460 pm_runtime_put_autosuspend(dev->dev); 461 return ret; 462 } 463 464 static const struct dev_pm_ops radeon_pm_ops = { 465 .suspend = radeon_pmops_suspend, 466 .resume = radeon_pmops_resume, 467 .freeze = radeon_pmops_freeze, 468 .thaw = radeon_pmops_thaw, 469 .poweroff = radeon_pmops_freeze, 470 .restore = radeon_pmops_resume, 471 .runtime_suspend = radeon_pmops_runtime_suspend, 472 .runtime_resume = radeon_pmops_runtime_resume, 473 .runtime_idle = radeon_pmops_runtime_idle, 474 }; 475 476 static const struct file_operations radeon_driver_kms_fops = { 477 .owner = THIS_MODULE, 478 .open = drm_open, 479 .release = drm_release, 480 .unlocked_ioctl = radeon_drm_ioctl, 481 .mmap = radeon_mmap, 482 .poll = drm_poll, 483 .read = drm_read, 484 #ifdef CONFIG_COMPAT 485 .compat_ioctl = radeon_kms_compat_ioctl, 486 #endif 487 }; 488 #endif /* DUMBBELL_WIP */ 489 490 static int radeon_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 491 struct sysctl_oid *top) 492 { 493 return drm_add_busid_modesetting(dev, ctx, top); 494 } 495 496 static struct drm_driver kms_driver = { 497 .driver_features = 498 DRIVER_USE_AGP | 499 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 500 DRIVER_PRIME | DRIVER_RENDER, 501 .load = radeon_driver_load_kms, 502 .open = radeon_driver_open_kms, 503 .preclose = radeon_driver_preclose_kms, 504 .postclose = radeon_driver_postclose_kms, 505 .lastclose = radeon_driver_lastclose_kms, 506 .unload = radeon_driver_unload_kms, 507 .get_vblank_counter = radeon_get_vblank_counter_kms, 508 .enable_vblank = radeon_enable_vblank_kms, 509 .disable_vblank = radeon_disable_vblank_kms, 510 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 511 .get_scanout_position = radeon_get_crtc_scanoutpos, 512 .irq_preinstall = radeon_driver_irq_preinstall_kms, 513 .irq_postinstall = radeon_driver_irq_postinstall_kms, 514 .irq_uninstall = radeon_driver_irq_uninstall_kms, 515 .irq_handler = radeon_driver_irq_handler_kms, 516 .sysctl_init = radeon_sysctl_init, 517 .ioctls = radeon_ioctls_kms, 518 .gem_free_object = radeon_gem_object_free, 519 .gem_open_object = radeon_gem_object_open, 520 .gem_close_object = radeon_gem_object_close, 521 .dumb_create = radeon_mode_dumb_create, 522 .dumb_map_offset = radeon_mode_dumb_mmap, 523 .dumb_destroy = drm_gem_dumb_destroy, 524 #ifdef DUMBBELL_WIP 525 .fops = &radeon_driver_kms_fops, 526 #endif /* DUMBBELL_WIP */ 527 528 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 529 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 530 #ifdef DUMBBELL_WIP 531 .gem_prime_export = drm_gem_prime_export, 532 .gem_prime_import = drm_gem_prime_import, 533 .gem_prime_pin = radeon_gem_prime_pin, 534 .gem_prime_unpin = radeon_gem_prime_unpin, 535 .gem_prime_res_obj = radeon_gem_prime_res_obj, 536 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 537 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 538 .gem_prime_vmap = radeon_gem_prime_vmap, 539 .gem_prime_vunmap = radeon_gem_prime_vunmap, 540 #endif /* DUMBBELL_WIP */ 541 542 .name = DRIVER_NAME, 543 .desc = DRIVER_DESC, 544 .date = DRIVER_DATE, 545 .major = KMS_DRIVER_MAJOR, 546 .minor = KMS_DRIVER_MINOR, 547 .patchlevel = KMS_DRIVER_PATCHLEVEL, 548 }; 549 550 #ifdef DUMBBELL_WIP 551 static struct drm_driver *driver; 552 static struct pci_driver *pdriver; 553 554 static struct pci_driver radeon_kms_pci_driver = { 555 .name = DRIVER_NAME, 556 .id_table = pciidlist, 557 .probe = radeon_pci_probe, 558 .remove = radeon_pci_remove, 559 .driver.pm = &radeon_pm_ops, 560 }; 561 562 static int __init radeon_init(void) 563 { 564 if (radeon_modeset == 1) { 565 DRM_INFO("radeon kernel modesetting enabled.\n"); 566 driver = &kms_driver; 567 pdriver = &radeon_kms_pci_driver; 568 driver->driver_features |= DRIVER_MODESET; 569 driver->num_ioctls = radeon_max_kms_ioctl; 570 radeon_register_atpx_handler(); 571 572 } else { 573 DRM_ERROR("No UMS support in radeon module!\n"); 574 return -EINVAL; 575 } 576 577 radeon_kfd_init(); 578 579 /* let modprobe override vga console setting */ 580 return drm_pci_init(driver, pdriver); 581 } 582 583 static void __exit radeon_exit(void) 584 { 585 radeon_kfd_fini(); 586 drm_pci_exit(driver, pdriver); 587 radeon_unregister_atpx_handler(); 588 } 589 #endif /* DUMBBELL_WIP */ 590 591 /* =================================================================== */ 592 593 static int 594 radeon_probe(device_t kdev) 595 { 596 597 return drm_probe(kdev, pciidlist); 598 } 599 600 static int 601 radeon_attach(device_t kdev) 602 { 603 struct drm_device *dev; 604 605 dev = device_get_softc(kdev); 606 if (radeon_modeset == 1) { 607 kms_driver.driver_features |= DRIVER_MODESET; 608 kms_driver.num_ioctls = radeon_max_kms_ioctl; 609 radeon_register_atpx_handler(); 610 } 611 dev->driver = &kms_driver; 612 return (drm_attach(kdev, pciidlist)); 613 } 614 615 static int 616 radeon_suspend(device_t kdev) 617 { 618 struct drm_device *dev; 619 int ret; 620 621 dev = device_get_softc(kdev); 622 ret = radeon_suspend_kms(dev, true, true); 623 624 return (-ret); 625 } 626 627 static int 628 radeon_resume(device_t kdev) 629 { 630 struct drm_device *dev; 631 int ret; 632 633 dev = device_get_softc(kdev); 634 ret = radeon_resume_kms(dev, true, true); 635 636 return (-ret); 637 } 638 639 static device_method_t radeon_methods[] = { 640 /* Device interface */ 641 DEVMETHOD(device_probe, radeon_probe), 642 DEVMETHOD(device_attach, radeon_attach), 643 DEVMETHOD(device_suspend, radeon_suspend), 644 DEVMETHOD(device_resume, radeon_resume), 645 DEVMETHOD(device_detach, drm_release), 646 DEVMETHOD_END 647 }; 648 649 static driver_t radeon_driver = { 650 "drm", 651 radeon_methods, 652 sizeof(struct drm_device) 653 }; 654 655 extern devclass_t drm_devclass; 656 DRIVER_MODULE_ORDERED(radeonkms, vgapci, radeon_driver, drm_devclass, 657 NULL, NULL, SI_ORDER_ANY); 658 MODULE_DEPEND(radeonkms, drm, 1, 1, 1); 659 MODULE_DEPEND(radeonkms, agp, 1, 1, 1); 660 MODULE_DEPEND(radeonkms, iicbus, 1, 1, 1); 661 MODULE_DEPEND(radeonkms, iic, 1, 1, 1); 662 MODULE_DEPEND(radeonkms, iicbb, 1, 1, 1); 663 #ifdef CONFIG_ACPI 664 MODULE_DEPEND(radeonkms, acpi, 1, 1, 1); 665 #endif 666