1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31 #ifndef __RADEON_DRV_H__ 32 #define __RADEON_DRV_H__ 33 34 #include <linux/firmware.h> 35 #include <drm/drm_legacy.h> 36 37 #include <drm/ati_pcigart.h> 38 #include "radeon_family.h" 39 40 /* General customization: 41 */ 42 43 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 44 45 #define DRIVER_NAME "radeon" 46 #define DRIVER_DESC "ATI Radeon" 47 #define DRIVER_DATE "20080528" 48 49 /* Interface history: 50 * 51 * 1.1 - ?? 52 * 1.2 - Add vertex2 ioctl (keith) 53 * - Add stencil capability to clear ioctl (gareth, keith) 54 * - Increase MAX_TEXTURE_LEVELS (brian) 55 * 1.3 - Add cmdbuf ioctl (keith) 56 * - Add support for new radeon packets (keith) 57 * - Add getparam ioctl (keith) 58 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 59 * 1.4 - Add scratch registers to get_param ioctl. 60 * 1.5 - Add r200 packets to cmdbuf ioctl 61 * - Add r200 function to init ioctl 62 * - Add 'scalar2' instruction to cmdbuf 63 * 1.6 - Add static GART memory manager 64 * Add irq handler (won't be turned on unless X server knows to) 65 * Add irq ioctls and irq_active getparam. 66 * Add wait command for cmdbuf ioctl 67 * Add GART offset query for getparam 68 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 69 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 70 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 71 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 72 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 73 * Add 'GET' queries for starting additional clients on different VT's. 74 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 75 * Add texture rectangle support for r100. 76 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 77 * clients use to tell the DRM where they think the framebuffer is 78 * located in the card's address space 79 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 80 * and GL_EXT_blend_[func|equation]_separate on r200 81 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 82 * (No 3D support yet - just microcode loading). 83 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 84 * - Add hyperz support, add hyperz flags to clear ioctl. 85 * 1.14- Add support for color tiling 86 * - Add R100/R200 surface allocation/free support 87 * 1.15- Add support for texture micro tiling 88 * - Add support for r100 cube maps 89 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 90 * texture filtering on r200 91 * 1.17- Add initial support for R300 (3D). 92 * 1.18- Add support for GL_ATI_fragment_shader, new packets 93 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 94 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 95 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 96 * 1.19- Add support for gart table in FB memory and PCIE r300 97 * 1.20- Add support for r300 texrect 98 * 1.21- Add support for card type getparam 99 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 100 * 1.23- Add new radeon memory map work from benh 101 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 102 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 103 * new packet type) 104 * 1.26- Add support for variable size PCI(E) gart aperture 105 * 1.27- Add support for IGP GART 106 * 1.28- Add support for VBL on CRTC2 107 * 1.29- R500 3D cmd buffer support 108 * 1.30- Add support for occlusion queries 109 * 1.31- Add support for num Z pipes from GET_PARAM 110 * 1.32- fixes for rv740 setup 111 * 1.33- Add r6xx/r7xx const buffer support 112 * 1.34- fix evergreen/cayman GS register 113 */ 114 #define DRIVER_MAJOR 1 115 #define DRIVER_MINOR 34 116 #define DRIVER_PATCHLEVEL 0 117 118 #ifdef PM_TODO 119 long radeon_drm_ioctl(struct file *filp, 120 unsigned int cmd, unsigned long arg); 121 #endif 122 123 /* The rest of the file is DEPRECATED! */ 124 #ifdef CONFIG_DRM_RADEON_UMS 125 126 enum radeon_cp_microcode_version { 127 UCODE_R100, 128 UCODE_R200, 129 UCODE_R300, 130 }; 131 132 typedef struct drm_radeon_freelist { 133 unsigned int age; 134 struct drm_buf *buf; 135 struct drm_radeon_freelist *next; 136 struct drm_radeon_freelist *prev; 137 } drm_radeon_freelist_t; 138 139 typedef struct drm_radeon_ring_buffer { 140 u32 *start; 141 u32 *end; 142 int size; 143 int size_l2qw; 144 145 int rptr_update; /* Double Words */ 146 int rptr_update_l2qw; /* log2 Quad Words */ 147 148 int fetch_size; /* Double Words */ 149 int fetch_size_l2ow; /* log2 Oct Words */ 150 151 u32 tail; 152 u32 tail_mask; 153 int space; 154 155 int high_mark; 156 } drm_radeon_ring_buffer_t; 157 158 typedef struct drm_radeon_depth_clear_t { 159 u32 rb3d_cntl; 160 u32 rb3d_zstencilcntl; 161 u32 se_cntl; 162 } drm_radeon_depth_clear_t; 163 164 struct drm_radeon_driver_file_fields { 165 int64_t radeon_fb_delta; 166 }; 167 168 struct mem_block { 169 struct mem_block *next; 170 struct mem_block *prev; 171 int start; 172 int size; 173 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 174 }; 175 176 struct radeon_surface { 177 int refcount; 178 u32 lower; 179 u32 upper; 180 u32 flags; 181 }; 182 183 struct radeon_virt_surface { 184 int surface_index; 185 u32 lower; 186 u32 upper; 187 u32 flags; 188 struct drm_file *file_priv; 189 #define PCIGART_FILE_PRIV ((void *) -1L) 190 }; 191 192 #define RADEON_FLUSH_EMITED (1 << 0) 193 #define RADEON_PURGE_EMITED (1 << 1) 194 195 struct drm_radeon_master_private { 196 drm_local_map_t *sarea; 197 drm_radeon_sarea_t *sarea_priv; 198 }; 199 200 typedef struct drm_radeon_private { 201 drm_radeon_ring_buffer_t ring; 202 203 u32 fb_location; 204 u32 fb_size; 205 int new_memmap; 206 207 int gart_size; 208 u32 gart_vm_start; 209 unsigned long gart_buffers_offset; 210 211 int cp_mode; 212 int cp_running; 213 214 drm_radeon_freelist_t *head; 215 drm_radeon_freelist_t *tail; 216 int last_buf; 217 int writeback_works; 218 219 int usec_timeout; 220 221 int microcode_version; 222 223 struct { 224 u32 boxes; 225 int freelist_timeouts; 226 int freelist_loops; 227 int requested_bufs; 228 int last_frame_reads; 229 int last_clear_reads; 230 int clears; 231 int texture_uploads; 232 } stats; 233 234 int do_boxes; 235 int page_flipping; 236 237 u32 color_fmt; 238 unsigned int front_offset; 239 unsigned int front_pitch; 240 unsigned int back_offset; 241 unsigned int back_pitch; 242 243 u32 depth_fmt; 244 unsigned int depth_offset; 245 unsigned int depth_pitch; 246 247 u32 front_pitch_offset; 248 u32 back_pitch_offset; 249 u32 depth_pitch_offset; 250 251 drm_radeon_depth_clear_t depth_clear; 252 253 unsigned long ring_offset; 254 unsigned long ring_rptr_offset; 255 unsigned long buffers_offset; 256 unsigned long gart_textures_offset; 257 258 drm_local_map_t *sarea; 259 drm_local_map_t *cp_ring; 260 drm_local_map_t *ring_rptr; 261 drm_local_map_t *gart_textures; 262 263 struct mem_block *gart_heap; 264 struct mem_block *fb_heap; 265 266 /* SW interrupt */ 267 wait_queue_head_t swi_queue; 268 atomic_t swi_emitted; 269 int vblank_crtc; 270 uint32_t irq_enable_reg; 271 uint32_t r500_disp_irq_reg; 272 273 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 274 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 275 276 unsigned long pcigart_offset; 277 unsigned int pcigart_offset_set; 278 struct drm_ati_pcigart_info gart_info; 279 280 u32 scratch_ages[5]; 281 282 int have_z_offset; 283 284 /* starting from here on, data is preserved across an open */ 285 uint32_t flags; /* see radeon_chip_flags */ 286 resource_size_t fb_aper_offset; 287 288 int num_gb_pipes; 289 int num_z_pipes; 290 int track_flush; 291 drm_local_map_t *mmio; 292 293 /* r6xx/r7xx pipe/shader config */ 294 int r600_max_pipes; 295 int r600_max_tile_pipes; 296 int r600_max_simds; 297 int r600_max_backends; 298 int r600_max_gprs; 299 int r600_max_threads; 300 int r600_max_stack_entries; 301 int r600_max_hw_contexts; 302 int r600_max_gs_threads; 303 int r600_sx_max_export_size; 304 int r600_sx_max_export_pos_size; 305 int r600_sx_max_export_smx_size; 306 int r600_sq_num_cf_insts; 307 int r700_sx_num_of_sets; 308 int r700_sc_prim_fifo_size; 309 int r700_sc_hiz_tile_fifo_size; 310 int r700_sc_earlyz_tile_fifo_fize; 311 int r600_group_size; 312 int r600_npipes; 313 int r600_nbanks; 314 315 struct lock cs_mutex; 316 u32 cs_id_scnt; 317 u32 cs_id_wcnt; 318 /* r6xx/r7xx drm blit vertex buffer */ 319 struct drm_buf *blit_vb; 320 321 /* firmware */ 322 const struct firmware *me_fw, *pfp_fw; 323 } drm_radeon_private_t; 324 325 typedef struct drm_radeon_buf_priv { 326 u32 age; 327 } drm_radeon_buf_priv_t; 328 329 struct drm_buffer; 330 331 typedef struct drm_radeon_kcmd_buffer { 332 int bufsz; 333 struct drm_buffer *buffer; 334 int nbox; 335 struct drm_clip_rect __user *boxes; 336 } drm_radeon_kcmd_buffer_t; 337 338 extern int radeon_no_wb; 339 extern struct drm_ioctl_desc radeon_ioctls[]; 340 extern int radeon_max_ioctl; 341 342 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 343 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 344 345 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 346 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 347 348 /* Check whether the given hardware address is inside the framebuffer or the 349 * GART area. 350 */ 351 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 352 u64 off) 353 { 354 u32 fb_start = dev_priv->fb_location; 355 u32 fb_end = fb_start + dev_priv->fb_size - 1; 356 u32 gart_start = dev_priv->gart_vm_start; 357 u32 gart_end = gart_start + dev_priv->gart_size - 1; 358 359 return ((off >= fb_start && off <= fb_end) || 360 (off >= gart_start && off <= gart_end)); 361 } 362 363 /* radeon_state.c */ 364 extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); 365 366 /* radeon_cp.c */ 367 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 368 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 369 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 370 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 371 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 372 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 373 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 374 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 375 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 376 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 377 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 378 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 379 380 extern void radeon_freelist_reset(struct drm_device * dev); 381 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 382 383 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 384 385 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 386 387 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 388 extern int radeon_presetup(struct drm_device *dev); 389 extern int radeon_driver_postcleanup(struct drm_device *dev); 390 391 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 392 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 393 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 394 extern void radeon_mem_takedown(struct mem_block **heap); 395 extern void radeon_mem_release(struct drm_file *file_priv, 396 struct mem_block *heap); 397 398 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 399 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 400 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 401 402 /* radeon_irq.c */ 403 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 404 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 405 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 406 407 extern void radeon_do_release(struct drm_device * dev); 408 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 409 extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 410 extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 411 extern irqreturn_t radeon_driver_irq_handler(void *arg); 412 extern void radeon_driver_irq_preinstall(struct drm_device * dev); 413 extern int radeon_driver_irq_postinstall(struct drm_device *dev); 414 extern void radeon_driver_irq_uninstall(struct drm_device * dev); 415 extern void radeon_enable_interrupt(struct drm_device *dev); 416 extern int radeon_vblank_crtc_get(struct drm_device *dev); 417 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 418 419 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 420 extern int radeon_driver_unload(struct drm_device *dev); 421 extern int radeon_driver_firstopen(struct drm_device *dev); 422 extern void radeon_driver_preclose(struct drm_device *dev, 423 struct drm_file *file_priv); 424 extern void radeon_driver_postclose(struct drm_device *dev, 425 struct drm_file *file_priv); 426 extern void radeon_driver_lastclose(struct drm_device * dev); 427 extern int radeon_driver_open(struct drm_device *dev, 428 struct drm_file *file_priv); 429 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 430 unsigned long arg); 431 432 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); 433 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); 434 extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master); 435 /* r300_cmdbuf.c */ 436 extern void r300_init_reg_flags(struct drm_device *dev); 437 438 extern int r300_do_cp_cmdbuf(struct drm_device *dev, 439 struct drm_file *file_priv, 440 drm_radeon_kcmd_buffer_t *cmdbuf); 441 442 /* r600_cp.c */ 443 extern int r600_do_engine_reset(struct drm_device *dev); 444 extern int r600_do_cleanup_cp(struct drm_device *dev); 445 extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 446 struct drm_file *file_priv); 447 extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 448 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 449 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 450 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 451 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 452 extern int r600_cp_dispatch_indirect(struct drm_device *dev, 453 struct drm_buf *buf, int start, int end); 454 extern int r600_page_table_init(struct drm_device *dev); 455 extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 456 extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 457 extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); 458 extern int r600_cp_dispatch_texture(struct drm_device *dev, 459 struct drm_file *file_priv, 460 drm_radeon_texture_t *tex, 461 drm_radeon_tex_image_t *image); 462 /* r600_blit.c */ 463 extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); 464 extern void r600_done_blit_copy(struct drm_device *dev); 465 extern void r600_blit_copy(struct drm_device *dev, 466 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 467 int size_bytes); 468 extern void r600_blit_swap(struct drm_device *dev, 469 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 470 int sx, int sy, int dx, int dy, 471 int w, int h, int src_pitch, int dst_pitch, int cpp); 472 473 /* Flags for stats.boxes 474 */ 475 #define RADEON_BOX_DMA_IDLE 0x1 476 #define RADEON_BOX_RING_FULL 0x2 477 #define RADEON_BOX_FLIP 0x4 478 #define RADEON_BOX_WAIT_IDLE 0x8 479 #define RADEON_BOX_TEXTURE_LOAD 0x10 480 481 /* Register definitions, register access macros and drmAddMap constants 482 * for Radeon kernel driver. 483 */ 484 #define RADEON_MM_INDEX 0x0000 485 #define RADEON_MM_DATA 0x0004 486 487 #define RADEON_AGP_COMMAND 0x0f60 488 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 489 # define RADEON_AGP_ENABLE (1<<8) 490 #define RADEON_AUX_SCISSOR_CNTL 0x26f0 491 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 492 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 493 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 494 # define RADEON_SCISSOR_0_ENABLE (1 << 28) 495 # define RADEON_SCISSOR_1_ENABLE (1 << 29) 496 # define RADEON_SCISSOR_2_ENABLE (1 << 30) 497 498 /* 499 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 500 * don't have an explicit bus mastering disable bit. It's handled 501 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 502 * handling, not bus mastering itself. 503 */ 504 #define RADEON_BUS_CNTL 0x0030 505 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 506 # define RADEON_BUS_MASTER_DIS (1 << 6) 507 /* rs600/rs690/rs740 */ 508 # define RS600_BUS_MASTER_DIS (1 << 14) 509 # define RS600_MSI_REARM (1 << 20) 510 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 511 512 #define RADEON_BUS_CNTL1 0x0034 513 # define RADEON_PMI_BM_DIS (1 << 2) 514 # define RADEON_PMI_INT_DIS (1 << 3) 515 516 #define RV370_BUS_CNTL 0x004c 517 # define RV370_PMI_BM_DIS (1 << 5) 518 # define RV370_PMI_INT_DIS (1 << 6) 519 520 #define RADEON_MSI_REARM_EN 0x0160 521 /* rv370/rv380, rv410, r423/r430/r480, r5xx */ 522 # define RV370_MSI_REARM_EN (1 << 0) 523 524 #define RADEON_CLOCK_CNTL_DATA 0x000c 525 # define RADEON_PLL_WR_EN (1 << 7) 526 #define RADEON_CLOCK_CNTL_INDEX 0x0008 527 #define RADEON_CONFIG_APER_SIZE 0x0108 528 #define RADEON_CONFIG_MEMSIZE 0x00f8 529 #define RADEON_CRTC_OFFSET 0x0224 530 #define RADEON_CRTC_OFFSET_CNTL 0x0228 531 # define RADEON_CRTC_TILE_EN (1 << 15) 532 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 533 #define RADEON_CRTC2_OFFSET 0x0324 534 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 535 536 #define RADEON_PCIE_INDEX 0x0030 537 #define RADEON_PCIE_DATA 0x0034 538 #define RADEON_PCIE_TX_GART_CNTL 0x10 539 # define RADEON_PCIE_TX_GART_EN (1 << 0) 540 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 541 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 542 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 543 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 544 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 545 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 546 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 547 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 548 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 549 #define RADEON_PCIE_TX_GART_BASE 0x13 550 #define RADEON_PCIE_TX_GART_START_LO 0x14 551 #define RADEON_PCIE_TX_GART_START_HI 0x15 552 #define RADEON_PCIE_TX_GART_END_LO 0x16 553 #define RADEON_PCIE_TX_GART_END_HI 0x17 554 555 #define RS480_NB_MC_INDEX 0x168 556 # define RS480_NB_MC_IND_WR_EN (1 << 8) 557 #define RS480_NB_MC_DATA 0x16c 558 559 #define RS690_MC_INDEX 0x78 560 # define RS690_MC_INDEX_MASK 0x1ff 561 # define RS690_MC_INDEX_WR_EN (1 << 9) 562 # define RS690_MC_INDEX_WR_ACK 0x7f 563 #define RS690_MC_DATA 0x7c 564 565 /* MC indirect registers */ 566 #define RS480_MC_MISC_CNTL 0x18 567 # define RS480_DISABLE_GTW (1 << 1) 568 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 569 # define RS480_GART_INDEX_REG_EN (1 << 12) 570 # define RS690_BLOCK_GFX_D3_EN (1 << 14) 571 #define RS480_K8_FB_LOCATION 0x1e 572 #define RS480_GART_FEATURE_ID 0x2b 573 # define RS480_HANG_EN (1 << 11) 574 # define RS480_TLB_ENABLE (1 << 18) 575 # define RS480_P2P_ENABLE (1 << 19) 576 # define RS480_GTW_LAC_EN (1 << 25) 577 # define RS480_2LEVEL_GART (0 << 30) 578 # define RS480_1LEVEL_GART (1 << 30) 579 # define RS480_PDC_EN (1 << 31) 580 #define RS480_GART_BASE 0x2c 581 #define RS480_GART_CACHE_CNTRL 0x2e 582 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 583 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 584 # define RS480_GART_EN (1 << 0) 585 # define RS480_VA_SIZE_32MB (0 << 1) 586 # define RS480_VA_SIZE_64MB (1 << 1) 587 # define RS480_VA_SIZE_128MB (2 << 1) 588 # define RS480_VA_SIZE_256MB (3 << 1) 589 # define RS480_VA_SIZE_512MB (4 << 1) 590 # define RS480_VA_SIZE_1GB (5 << 1) 591 # define RS480_VA_SIZE_2GB (6 << 1) 592 #define RS480_AGP_MODE_CNTL 0x39 593 # define RS480_POST_GART_Q_SIZE (1 << 18) 594 # define RS480_NONGART_SNOOP (1 << 19) 595 # define RS480_AGP_RD_BUF_SIZE (1 << 20) 596 # define RS480_REQ_TYPE_SNOOP_SHIFT 22 597 # define RS480_REQ_TYPE_SNOOP_MASK 0x3 598 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 599 #define RS480_MC_MISC_UMA_CNTL 0x5f 600 #define RS480_MC_MCLK_CNTL 0x7a 601 #define RS480_MC_UMA_DUALCH_CNTL 0x86 602 603 #define RS690_MC_FB_LOCATION 0x100 604 #define RS690_MC_AGP_LOCATION 0x101 605 #define RS690_MC_AGP_BASE 0x102 606 #define RS690_MC_AGP_BASE_2 0x103 607 608 #define RS600_MC_INDEX 0x70 609 # define RS600_MC_ADDR_MASK 0xffff 610 # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 611 # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 612 # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 613 # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 614 # define RS600_MC_IND_AIC_RBS (1 << 20) 615 # define RS600_MC_IND_CITF_ARB0 (1 << 21) 616 # define RS600_MC_IND_CITF_ARB1 (1 << 22) 617 # define RS600_MC_IND_WR_EN (1 << 23) 618 #define RS600_MC_DATA 0x74 619 620 #define RS600_MC_STATUS 0x0 621 # define RS600_MC_IDLE (1 << 1) 622 #define RS600_MC_FB_LOCATION 0x4 623 #define RS600_MC_AGP_LOCATION 0x5 624 #define RS600_AGP_BASE 0x6 625 #define RS600_AGP_BASE_2 0x7 626 #define RS600_MC_CNTL1 0x9 627 # define RS600_ENABLE_PAGE_TABLES (1 << 26) 628 #define RS600_MC_PT0_CNTL 0x100 629 # define RS600_ENABLE_PT (1 << 0) 630 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 631 # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 632 # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 633 # define RS600_INVALIDATE_L2_CACHE (1 << 29) 634 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 635 # define RS600_ENABLE_PAGE_TABLE (1 << 0) 636 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 637 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 638 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 639 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 640 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 641 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 642 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 643 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c 644 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 645 # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 646 # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 647 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 648 # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 649 # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 650 # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 651 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 652 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 653 # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 654 # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 655 # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 656 # define RS600_INVALIDATE_L1_TLB (1 << 20) 657 658 #define R520_MC_IND_INDEX 0x70 659 #define R520_MC_IND_WR_EN (1 << 24) 660 #define R520_MC_IND_DATA 0x74 661 662 #define RV515_MC_FB_LOCATION 0x01 663 #define RV515_MC_AGP_LOCATION 0x02 664 #define RV515_MC_AGP_BASE 0x03 665 #define RV515_MC_AGP_BASE_2 0x04 666 667 #define R520_MC_FB_LOCATION 0x04 668 #define R520_MC_AGP_LOCATION 0x05 669 #define R520_MC_AGP_BASE 0x06 670 #define R520_MC_AGP_BASE_2 0x07 671 672 #define RADEON_MPP_TB_CONFIG 0x01c0 673 #define RADEON_MEM_CNTL 0x0140 674 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 675 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 676 #define RS480_AGP_BASE_2 0x0164 677 #define RADEON_AGP_BASE 0x0170 678 679 /* pipe config regs */ 680 #define R400_GB_PIPE_SELECT 0x402c 681 #define RV530_GB_PIPE_SELECT2 0x4124 682 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 683 #define R300_GB_TILE_CONFIG 0x4018 684 # define R300_ENABLE_TILING (1 << 0) 685 # define R300_PIPE_COUNT_RV350 (0 << 1) 686 # define R300_PIPE_COUNT_R300 (3 << 1) 687 # define R300_PIPE_COUNT_R420_3P (6 << 1) 688 # define R300_PIPE_COUNT_R420 (7 << 1) 689 # define R300_TILE_SIZE_8 (0 << 4) 690 # define R300_TILE_SIZE_16 (1 << 4) 691 # define R300_TILE_SIZE_32 (2 << 4) 692 # define R300_SUBPIXEL_1_12 (0 << 16) 693 # define R300_SUBPIXEL_1_16 (1 << 16) 694 #define R300_DST_PIPE_CONFIG 0x170c 695 # define R300_PIPE_AUTO_CONFIG (1 << 31) 696 #define R300_RB2D_DSTCACHE_MODE 0x3428 697 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 698 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 699 700 #define RADEON_RB3D_COLOROFFSET 0x1c40 701 #define RADEON_RB3D_COLORPITCH 0x1c48 702 703 #define RADEON_SRC_X_Y 0x1590 704 705 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 706 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 707 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 708 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 709 # define RADEON_GMC_BRUSH_NONE (15 << 4) 710 # define RADEON_GMC_DST_16BPP (4 << 8) 711 # define RADEON_GMC_DST_24BPP (5 << 8) 712 # define RADEON_GMC_DST_32BPP (6 << 8) 713 # define RADEON_GMC_DST_DATATYPE_SHIFT 8 714 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 715 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 716 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 717 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 718 # define RADEON_GMC_WR_MSK_DIS (1 << 30) 719 # define RADEON_ROP3_S 0x00cc0000 720 # define RADEON_ROP3_P 0x00f00000 721 #define RADEON_DP_WRITE_MASK 0x16cc 722 #define RADEON_SRC_PITCH_OFFSET 0x1428 723 #define RADEON_DST_PITCH_OFFSET 0x142c 724 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 725 # define RADEON_DST_TILE_LINEAR (0 << 30) 726 # define RADEON_DST_TILE_MACRO (1 << 30) 727 # define RADEON_DST_TILE_MICRO (2 << 30) 728 # define RADEON_DST_TILE_BOTH (3 << 30) 729 730 #define RADEON_SCRATCH_REG0 0x15e0 731 #define RADEON_SCRATCH_REG1 0x15e4 732 #define RADEON_SCRATCH_REG2 0x15e8 733 #define RADEON_SCRATCH_REG3 0x15ec 734 #define RADEON_SCRATCH_REG4 0x15f0 735 #define RADEON_SCRATCH_REG5 0x15f4 736 #define RADEON_SCRATCH_UMSK 0x0770 737 #define RADEON_SCRATCH_ADDR 0x0774 738 739 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 740 741 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 742 743 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 744 745 #define R600_SCRATCH_REG0 0x8500 746 #define R600_SCRATCH_REG1 0x8504 747 #define R600_SCRATCH_REG2 0x8508 748 #define R600_SCRATCH_REG3 0x850c 749 #define R600_SCRATCH_REG4 0x8510 750 #define R600_SCRATCH_REG5 0x8514 751 #define R600_SCRATCH_REG6 0x8518 752 #define R600_SCRATCH_REG7 0x851c 753 #define R600_SCRATCH_UMSK 0x8540 754 #define R600_SCRATCH_ADDR 0x8544 755 756 #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 757 758 #define RADEON_GEN_INT_CNTL 0x0040 759 # define RADEON_CRTC_VBLANK_MASK (1 << 0) 760 # define RADEON_CRTC2_VBLANK_MASK (1 << 9) 761 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 762 # define RADEON_SW_INT_ENABLE (1 << 25) 763 764 #define RADEON_GEN_INT_STATUS 0x0044 765 # define RADEON_CRTC_VBLANK_STAT (1 << 0) 766 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 767 # define RADEON_CRTC2_VBLANK_STAT (1 << 9) 768 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 769 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 770 # define RADEON_SW_INT_TEST (1 << 25) 771 # define RADEON_SW_INT_TEST_ACK (1 << 25) 772 # define RADEON_SW_INT_FIRE (1 << 26) 773 # define R500_DISPLAY_INT_STATUS (1 << 0) 774 775 #define RADEON_HOST_PATH_CNTL 0x0130 776 # define RADEON_HDP_SOFT_RESET (1 << 26) 777 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 778 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 779 780 #define RADEON_ISYNC_CNTL 0x1724 781 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 782 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 783 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 784 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 785 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 786 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 787 788 #define RADEON_RBBM_GUICNTL 0x172c 789 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 790 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 791 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 792 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 793 794 #define RADEON_MC_AGP_LOCATION 0x014c 795 #define RADEON_MC_FB_LOCATION 0x0148 796 #define RADEON_MCLK_CNTL 0x0012 797 # define RADEON_FORCEON_MCLKA (1 << 16) 798 # define RADEON_FORCEON_MCLKB (1 << 17) 799 # define RADEON_FORCEON_YCLKA (1 << 18) 800 # define RADEON_FORCEON_YCLKB (1 << 19) 801 # define RADEON_FORCEON_MC (1 << 20) 802 # define RADEON_FORCEON_AIC (1 << 21) 803 804 #define RADEON_PP_BORDER_COLOR_0 0x1d40 805 #define RADEON_PP_BORDER_COLOR_1 0x1d44 806 #define RADEON_PP_BORDER_COLOR_2 0x1d48 807 #define RADEON_PP_CNTL 0x1c38 808 # define RADEON_SCISSOR_ENABLE (1 << 1) 809 #define RADEON_PP_LUM_MATRIX 0x1d00 810 #define RADEON_PP_MISC 0x1c14 811 #define RADEON_PP_ROT_MATRIX_0 0x1d58 812 #define RADEON_PP_TXFILTER_0 0x1c54 813 #define RADEON_PP_TXOFFSET_0 0x1c5c 814 #define RADEON_PP_TXFILTER_1 0x1c6c 815 #define RADEON_PP_TXFILTER_2 0x1c84 816 817 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 818 #define R300_DSTCACHE_CTLSTAT 0x1714 819 # define R300_RB2D_DC_FLUSH (3 << 0) 820 # define R300_RB2D_DC_FREE (3 << 2) 821 # define R300_RB2D_DC_FLUSH_ALL 0xf 822 # define R300_RB2D_DC_BUSY (1 << 31) 823 #define RADEON_RB3D_CNTL 0x1c3c 824 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 825 # define RADEON_PLANE_MASK_ENABLE (1 << 1) 826 # define RADEON_DITHER_ENABLE (1 << 2) 827 # define RADEON_ROUND_ENABLE (1 << 3) 828 # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 829 # define RADEON_DITHER_INIT (1 << 5) 830 # define RADEON_ROP_ENABLE (1 << 6) 831 # define RADEON_STENCIL_ENABLE (1 << 7) 832 # define RADEON_Z_ENABLE (1 << 8) 833 # define RADEON_ZBLOCK16 (1 << 15) 834 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 835 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 836 #define RADEON_RB3D_DEPTHPITCH 0x1c28 837 #define RADEON_RB3D_PLANEMASK 0x1d84 838 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 839 #define RADEON_RB3D_ZCACHE_MODE 0x3250 840 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 841 # define RADEON_RB3D_ZC_FLUSH (1 << 0) 842 # define RADEON_RB3D_ZC_FREE (1 << 2) 843 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 844 # define RADEON_RB3D_ZC_BUSY (1 << 31) 845 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 846 # define R300_ZC_FLUSH (1 << 0) 847 # define R300_ZC_FREE (1 << 1) 848 # define R300_ZC_BUSY (1 << 31) 849 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 850 # define RADEON_RB3D_DC_FLUSH (3 << 0) 851 # define RADEON_RB3D_DC_FREE (3 << 2) 852 # define RADEON_RB3D_DC_FLUSH_ALL 0xf 853 # define RADEON_RB3D_DC_BUSY (1 << 31) 854 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 855 # define R300_RB3D_DC_FLUSH (2 << 0) 856 # define R300_RB3D_DC_FREE (2 << 2) 857 # define R300_RB3D_DC_FINISH (1 << 4) 858 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 859 # define RADEON_Z_TEST_MASK (7 << 4) 860 # define RADEON_Z_TEST_ALWAYS (7 << 4) 861 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 862 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 863 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 864 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 865 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 866 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 867 # define RADEON_FORCE_Z_DIRTY (1 << 29) 868 # define RADEON_Z_WRITE_ENABLE (1 << 30) 869 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 870 #define RADEON_RBBM_SOFT_RESET 0x00f0 871 # define RADEON_SOFT_RESET_CP (1 << 0) 872 # define RADEON_SOFT_RESET_HI (1 << 1) 873 # define RADEON_SOFT_RESET_SE (1 << 2) 874 # define RADEON_SOFT_RESET_RE (1 << 3) 875 # define RADEON_SOFT_RESET_PP (1 << 4) 876 # define RADEON_SOFT_RESET_E2 (1 << 5) 877 # define RADEON_SOFT_RESET_RB (1 << 6) 878 # define RADEON_SOFT_RESET_HDP (1 << 7) 879 /* 880 * 6:0 Available slots in the FIFO 881 * 8 Host Interface active 882 * 9 CP request active 883 * 10 FIFO request active 884 * 11 Host Interface retry active 885 * 12 CP retry active 886 * 13 FIFO retry active 887 * 14 FIFO pipeline busy 888 * 15 Event engine busy 889 * 16 CP command stream busy 890 * 17 2D engine busy 891 * 18 2D portion of render backend busy 892 * 20 3D setup engine busy 893 * 26 GA engine busy 894 * 27 CBA 2D engine busy 895 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 896 * command stream queue not empty or Ring Buffer not empty 897 */ 898 #define RADEON_RBBM_STATUS 0x0e40 899 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 900 /* #define RADEON_RBBM_STATUS 0x1740 */ 901 /* bits 6:0 are dword slots available in the cmd fifo */ 902 # define RADEON_RBBM_FIFOCNT_MASK 0x007f 903 # define RADEON_HIRQ_ON_RBB (1 << 8) 904 # define RADEON_CPRQ_ON_RBB (1 << 9) 905 # define RADEON_CFRQ_ON_RBB (1 << 10) 906 # define RADEON_HIRQ_IN_RTBUF (1 << 11) 907 # define RADEON_CPRQ_IN_RTBUF (1 << 12) 908 # define RADEON_CFRQ_IN_RTBUF (1 << 13) 909 # define RADEON_PIPE_BUSY (1 << 14) 910 # define RADEON_ENG_EV_BUSY (1 << 15) 911 # define RADEON_CP_CMDSTRM_BUSY (1 << 16) 912 # define RADEON_E2_BUSY (1 << 17) 913 # define RADEON_RB2D_BUSY (1 << 18) 914 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 915 # define RADEON_VAP_BUSY (1 << 20) 916 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 917 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 918 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 919 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 920 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 921 # define RADEON_GA_BUSY (1 << 26) 922 # define RADEON_CBA2D_BUSY (1 << 27) 923 # define RADEON_RBBM_ACTIVE (1 << 31) 924 #define RADEON_RE_LINE_PATTERN 0x1cd0 925 #define RADEON_RE_MISC 0x26c4 926 #define RADEON_RE_TOP_LEFT 0x26c0 927 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 928 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 929 #define RADEON_RE_STIPPLE_DATA 0x1ccc 930 931 #define RADEON_SCISSOR_TL_0 0x1cd8 932 #define RADEON_SCISSOR_BR_0 0x1cdc 933 #define RADEON_SCISSOR_TL_1 0x1ce0 934 #define RADEON_SCISSOR_BR_1 0x1ce4 935 #define RADEON_SCISSOR_TL_2 0x1ce8 936 #define RADEON_SCISSOR_BR_2 0x1cec 937 #define RADEON_SE_COORD_FMT 0x1c50 938 #define RADEON_SE_CNTL 0x1c4c 939 # define RADEON_FFACE_CULL_CW (0 << 0) 940 # define RADEON_BFACE_SOLID (3 << 1) 941 # define RADEON_FFACE_SOLID (3 << 3) 942 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 943 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 944 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 945 # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 946 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 947 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 948 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 949 # define RADEON_FOG_SHADE_FLAT (1 << 14) 950 # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 951 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 952 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 953 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 954 # define RADEON_ROUND_MODE_TRUNC (0 << 28) 955 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 956 #define RADEON_SE_CNTL_STATUS 0x2140 957 #define RADEON_SE_LINE_WIDTH 0x1db8 958 #define RADEON_SE_VPORT_XSCALE 0x1d98 959 #define RADEON_SE_ZBIAS_FACTOR 0x1db0 960 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 961 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 962 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 963 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 964 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 965 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 966 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 967 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 968 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 969 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 970 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc 971 #define RADEON_SURFACE_CNTL 0x0b00 972 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 973 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 974 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 975 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 976 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 977 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 978 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 979 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 980 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 981 #define RADEON_SURFACE0_INFO 0x0b0c 982 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 983 # define RADEON_SURF_TILE_MODE_MASK (3 << 16) 984 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 985 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 986 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 987 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 988 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 989 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 990 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 991 #define RADEON_SURFACE1_INFO 0x0b1c 992 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 993 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 994 #define RADEON_SURFACE2_INFO 0x0b2c 995 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 996 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 997 #define RADEON_SURFACE3_INFO 0x0b3c 998 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 999 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1000 #define RADEON_SURFACE4_INFO 0x0b4c 1001 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1002 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1003 #define RADEON_SURFACE5_INFO 0x0b5c 1004 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1005 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1006 #define RADEON_SURFACE6_INFO 0x0b6c 1007 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1008 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1009 #define RADEON_SURFACE7_INFO 0x0b7c 1010 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1011 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1012 #define RADEON_SW_SEMAPHORE 0x013c 1013 1014 #define RADEON_WAIT_UNTIL 0x1720 1015 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1016 # define RADEON_WAIT_2D_IDLE (1 << 14) 1017 # define RADEON_WAIT_3D_IDLE (1 << 15) 1018 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1019 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1020 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1021 1022 #define RADEON_RB3D_ZMASKOFFSET 0x3234 1023 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1024 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1025 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1026 1027 /* CP registers */ 1028 #define RADEON_CP_ME_RAM_ADDR 0x07d4 1029 #define RADEON_CP_ME_RAM_RADDR 0x07d8 1030 #define RADEON_CP_ME_RAM_DATAH 0x07dc 1031 #define RADEON_CP_ME_RAM_DATAL 0x07e0 1032 1033 #define RADEON_CP_RB_BASE 0x0700 1034 #define RADEON_CP_RB_CNTL 0x0704 1035 # define RADEON_BUF_SWAP_32BIT (2 << 16) 1036 # define RADEON_RB_NO_UPDATE (1 << 27) 1037 # define RADEON_RB_RPTR_WR_ENA (1 << 31) 1038 #define RADEON_CP_RB_RPTR_ADDR 0x070c 1039 #define RADEON_CP_RB_RPTR 0x0710 1040 #define RADEON_CP_RB_WPTR 0x0714 1041 1042 #define RADEON_CP_RB_WPTR_DELAY 0x0718 1043 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 1044 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1045 1046 #define RADEON_CP_IB_BASE 0x0738 1047 1048 #define RADEON_CP_CSQ_CNTL 0x0740 1049 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1050 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1051 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1052 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1053 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1054 # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1055 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1056 1057 #define R300_CP_RESYNC_ADDR 0x0778 1058 #define R300_CP_RESYNC_DATA 0x077c 1059 1060 #define RADEON_AIC_CNTL 0x01d0 1061 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1062 # define RS400_MSI_REARM (1 << 3) 1063 #define RADEON_AIC_STAT 0x01d4 1064 #define RADEON_AIC_PT_BASE 0x01d8 1065 #define RADEON_AIC_LO_ADDR 0x01dc 1066 #define RADEON_AIC_HI_ADDR 0x01e0 1067 #define RADEON_AIC_TLB_ADDR 0x01e4 1068 #define RADEON_AIC_TLB_DATA 0x01e8 1069 1070 /* CP command packets */ 1071 #define RADEON_CP_PACKET0 0x00000000 1072 # define RADEON_ONE_REG_WR (1 << 15) 1073 #define RADEON_CP_PACKET1 0x40000000 1074 #define RADEON_CP_PACKET2 0x80000000 1075 #define RADEON_CP_PACKET3 0xC0000000 1076 # define RADEON_CP_NOP 0x00001000 1077 # define RADEON_CP_NEXT_CHAR 0x00001900 1078 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1079 # define RADEON_CP_SET_SCISSORS 0x00001E00 1080 /* GEN_INDX_PRIM is unsupported starting with R300 */ 1081 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1082 # define RADEON_WAIT_FOR_IDLE 0x00002600 1083 # define RADEON_3D_DRAW_VBUF 0x00002800 1084 # define RADEON_3D_DRAW_IMMD 0x00002900 1085 # define RADEON_3D_DRAW_INDX 0x00002A00 1086 # define RADEON_CP_LOAD_PALETTE 0x00002C00 1087 # define RADEON_3D_LOAD_VBPNTR 0x00002F00 1088 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1089 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1090 # define RADEON_3D_CLEAR_ZMASK 0x00003200 1091 # define RADEON_CP_INDX_BUFFER 0x00003300 1092 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1093 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1094 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1095 # define RADEON_3D_CLEAR_HIZ 0x00003700 1096 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1097 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1098 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 1099 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1100 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1101 1102 # define R600_IT_INDIRECT_BUFFER_END 0x00001700 1103 # define R600_IT_SET_PREDICATION 0x00002000 1104 # define R600_IT_REG_RMW 0x00002100 1105 # define R600_IT_COND_EXEC 0x00002200 1106 # define R600_IT_PRED_EXEC 0x00002300 1107 # define R600_IT_START_3D_CMDBUF 0x00002400 1108 # define R600_IT_DRAW_INDEX_2 0x00002700 1109 # define R600_IT_CONTEXT_CONTROL 0x00002800 1110 # define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 1111 # define R600_IT_INDEX_TYPE 0x00002A00 1112 # define R600_IT_DRAW_INDEX 0x00002B00 1113 # define R600_IT_DRAW_INDEX_AUTO 0x00002D00 1114 # define R600_IT_DRAW_INDEX_IMMD 0x00002E00 1115 # define R600_IT_NUM_INSTANCES 0x00002F00 1116 # define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 1117 # define R600_IT_INDIRECT_BUFFER_MP 0x00003800 1118 # define R600_IT_MEM_SEMAPHORE 0x00003900 1119 # define R600_IT_MPEG_INDEX 0x00003A00 1120 # define R600_IT_WAIT_REG_MEM 0x00003C00 1121 # define R600_IT_MEM_WRITE 0x00003D00 1122 # define R600_IT_INDIRECT_BUFFER 0x00003200 1123 # define R600_IT_SURFACE_SYNC 0x00004300 1124 # define R600_CB0_DEST_BASE_ENA (1 << 6) 1125 # define R600_TC_ACTION_ENA (1 << 23) 1126 # define R600_VC_ACTION_ENA (1 << 24) 1127 # define R600_CB_ACTION_ENA (1 << 25) 1128 # define R600_DB_ACTION_ENA (1 << 26) 1129 # define R600_SH_ACTION_ENA (1 << 27) 1130 # define R600_SMX_ACTION_ENA (1 << 28) 1131 # define R600_IT_ME_INITIALIZE 0x00004400 1132 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1133 # define R600_IT_COND_WRITE 0x00004500 1134 # define R600_IT_EVENT_WRITE 0x00004600 1135 # define R600_IT_EVENT_WRITE_EOP 0x00004700 1136 # define R600_IT_ONE_REG_WRITE 0x00005700 1137 # define R600_IT_SET_CONFIG_REG 0x00006800 1138 # define R600_SET_CONFIG_REG_OFFSET 0x00008000 1139 # define R600_SET_CONFIG_REG_END 0x0000ac00 1140 # define R600_IT_SET_CONTEXT_REG 0x00006900 1141 # define R600_SET_CONTEXT_REG_OFFSET 0x00028000 1142 # define R600_SET_CONTEXT_REG_END 0x00029000 1143 # define R600_IT_SET_ALU_CONST 0x00006A00 1144 # define R600_SET_ALU_CONST_OFFSET 0x00030000 1145 # define R600_SET_ALU_CONST_END 0x00032000 1146 # define R600_IT_SET_BOOL_CONST 0x00006B00 1147 # define R600_SET_BOOL_CONST_OFFSET 0x0003e380 1148 # define R600_SET_BOOL_CONST_END 0x00040000 1149 # define R600_IT_SET_LOOP_CONST 0x00006C00 1150 # define R600_SET_LOOP_CONST_OFFSET 0x0003e200 1151 # define R600_SET_LOOP_CONST_END 0x0003e380 1152 # define R600_IT_SET_RESOURCE 0x00006D00 1153 # define R600_SET_RESOURCE_OFFSET 0x00038000 1154 # define R600_SET_RESOURCE_END 0x0003c000 1155 # define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 1156 # define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 1157 # define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 1158 # define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 1159 # define R600_IT_SET_SAMPLER 0x00006E00 1160 # define R600_SET_SAMPLER_OFFSET 0x0003c000 1161 # define R600_SET_SAMPLER_END 0x0003cff0 1162 # define R600_IT_SET_CTL_CONST 0x00006F00 1163 # define R600_SET_CTL_CONST_OFFSET 0x0003cff0 1164 # define R600_SET_CTL_CONST_END 0x0003e200 1165 # define R600_IT_SURFACE_BASE_UPDATE 0x00007300 1166 1167 #define RADEON_CP_PACKET_MASK 0xC0000000 1168 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1169 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1170 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1171 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1172 1173 #define RADEON_VTX_Z_PRESENT (1 << 31) 1174 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1175 1176 #define RADEON_PRIM_TYPE_NONE (0 << 0) 1177 #define RADEON_PRIM_TYPE_POINT (1 << 0) 1178 #define RADEON_PRIM_TYPE_LINE (2 << 0) 1179 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1180 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1181 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1182 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1183 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1184 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1185 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1186 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1187 #define RADEON_PRIM_TYPE_MASK 0xf 1188 #define RADEON_PRIM_WALK_IND (1 << 4) 1189 #define RADEON_PRIM_WALK_LIST (2 << 4) 1190 #define RADEON_PRIM_WALK_RING (3 << 4) 1191 #define RADEON_COLOR_ORDER_BGRA (0 << 6) 1192 #define RADEON_COLOR_ORDER_RGBA (1 << 6) 1193 #define RADEON_MAOS_ENABLE (1 << 7) 1194 #define RADEON_VTX_FMT_R128_MODE (0 << 8) 1195 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1196 #define RADEON_NUM_VERTICES_SHIFT 16 1197 1198 #define RADEON_COLOR_FORMAT_CI8 2 1199 #define RADEON_COLOR_FORMAT_ARGB1555 3 1200 #define RADEON_COLOR_FORMAT_RGB565 4 1201 #define RADEON_COLOR_FORMAT_ARGB8888 6 1202 #define RADEON_COLOR_FORMAT_RGB332 7 1203 #define RADEON_COLOR_FORMAT_RGB8 9 1204 #define RADEON_COLOR_FORMAT_ARGB4444 15 1205 1206 #define RADEON_TXFORMAT_I8 0 1207 #define RADEON_TXFORMAT_AI88 1 1208 #define RADEON_TXFORMAT_RGB332 2 1209 #define RADEON_TXFORMAT_ARGB1555 3 1210 #define RADEON_TXFORMAT_RGB565 4 1211 #define RADEON_TXFORMAT_ARGB4444 5 1212 #define RADEON_TXFORMAT_ARGB8888 6 1213 #define RADEON_TXFORMAT_RGBA8888 7 1214 #define RADEON_TXFORMAT_Y8 8 1215 #define RADEON_TXFORMAT_VYUY422 10 1216 #define RADEON_TXFORMAT_YVYU422 11 1217 #define RADEON_TXFORMAT_DXT1 12 1218 #define RADEON_TXFORMAT_DXT23 14 1219 #define RADEON_TXFORMAT_DXT45 15 1220 1221 #define R200_PP_TXCBLEND_0 0x2f00 1222 #define R200_PP_TXCBLEND_1 0x2f10 1223 #define R200_PP_TXCBLEND_2 0x2f20 1224 #define R200_PP_TXCBLEND_3 0x2f30 1225 #define R200_PP_TXCBLEND_4 0x2f40 1226 #define R200_PP_TXCBLEND_5 0x2f50 1227 #define R200_PP_TXCBLEND_6 0x2f60 1228 #define R200_PP_TXCBLEND_7 0x2f70 1229 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1230 #define R200_PP_TFACTOR_0 0x2ee0 1231 #define R200_SE_VTX_FMT_0 0x2088 1232 #define R200_SE_VAP_CNTL 0x2080 1233 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 1234 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1235 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1236 #define R200_PP_TXFILTER_5 0x2ca0 1237 #define R200_PP_TXFILTER_4 0x2c80 1238 #define R200_PP_TXFILTER_3 0x2c60 1239 #define R200_PP_TXFILTER_2 0x2c40 1240 #define R200_PP_TXFILTER_1 0x2c20 1241 #define R200_PP_TXFILTER_0 0x2c00 1242 #define R200_PP_TXOFFSET_5 0x2d78 1243 #define R200_PP_TXOFFSET_4 0x2d60 1244 #define R200_PP_TXOFFSET_3 0x2d48 1245 #define R200_PP_TXOFFSET_2 0x2d30 1246 #define R200_PP_TXOFFSET_1 0x2d18 1247 #define R200_PP_TXOFFSET_0 0x2d00 1248 1249 #define R200_PP_CUBIC_FACES_0 0x2c18 1250 #define R200_PP_CUBIC_FACES_1 0x2c38 1251 #define R200_PP_CUBIC_FACES_2 0x2c58 1252 #define R200_PP_CUBIC_FACES_3 0x2c78 1253 #define R200_PP_CUBIC_FACES_4 0x2c98 1254 #define R200_PP_CUBIC_FACES_5 0x2cb8 1255 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1256 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1257 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1258 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1259 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1260 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1261 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1262 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1263 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1264 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1265 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1266 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1267 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1268 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1269 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1270 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1271 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1272 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1273 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1274 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1275 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1276 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1277 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1278 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1279 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1280 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1281 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1282 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1283 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1284 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1285 1286 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1287 #define R200_SE_VTE_CNTL 0x20b0 1288 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1289 #define R200_PP_TAM_DEBUG3 0x2d9c 1290 #define R200_PP_CNTL_X 0x2cc4 1291 #define R200_SE_VAP_CNTL_STATUS 0x2140 1292 #define R200_RE_SCISSOR_TL_0 0x1cd8 1293 #define R200_RE_SCISSOR_TL_1 0x1ce0 1294 #define R200_RE_SCISSOR_TL_2 0x1ce8 1295 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1296 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1297 #define R200_SE_VTX_STATE_CNTL 0x2180 1298 #define R200_RE_POINTSIZE 0x2648 1299 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1300 1301 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1302 #define RADEON_PP_TEX_SIZE_1 0x1d0c 1303 #define RADEON_PP_TEX_SIZE_2 0x1d14 1304 1305 #define RADEON_PP_CUBIC_FACES_0 0x1d24 1306 #define RADEON_PP_CUBIC_FACES_1 0x1d28 1307 #define RADEON_PP_CUBIC_FACES_2 0x1d2c 1308 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1309 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1310 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1311 1312 #define RADEON_SE_TCL_STATE_FLUSH 0x2284 1313 1314 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1315 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1316 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1317 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1318 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1319 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1320 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1321 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1322 #define R200_3D_DRAW_IMMD_2 0xC0003500 1323 #define R200_SE_VTX_FMT_1 0x208c 1324 #define R200_RE_CNTL 0x1c50 1325 1326 #define R200_RB3D_BLENDCOLOR 0x3218 1327 1328 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1329 1330 #define R200_PP_TRI_PERF 0x2cf8 1331 1332 #define R200_PP_AFS_0 0x2f80 1333 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1334 1335 #define R200_VAP_PVS_CNTL_1 0x22D0 1336 1337 #define RADEON_CRTC_CRNT_FRAME 0x0214 1338 #define RADEON_CRTC2_CRNT_FRAME 0x0314 1339 1340 #define R500_D1CRTC_STATUS 0x609c 1341 #define R500_D2CRTC_STATUS 0x689c 1342 #define R500_CRTC_V_BLANK (1<<0) 1343 1344 #define R500_D1CRTC_FRAME_COUNT 0x60a4 1345 #define R500_D2CRTC_FRAME_COUNT 0x68a4 1346 1347 #define R500_D1MODE_V_COUNTER 0x6530 1348 #define R500_D2MODE_V_COUNTER 0x6d30 1349 1350 #define R500_D1MODE_VBLANK_STATUS 0x6534 1351 #define R500_D2MODE_VBLANK_STATUS 0x6d34 1352 #define R500_VBLANK_OCCURED (1<<0) 1353 #define R500_VBLANK_ACK (1<<4) 1354 #define R500_VBLANK_STAT (1<<12) 1355 #define R500_VBLANK_INT (1<<16) 1356 1357 #define R500_DxMODE_INT_MASK 0x6540 1358 #define R500_D1MODE_INT_MASK (1<<0) 1359 #define R500_D2MODE_INT_MASK (1<<8) 1360 1361 #define R500_DISP_INTERRUPT_STATUS 0x7edc 1362 #define R500_D1_VBLANK_INTERRUPT (1 << 4) 1363 #define R500_D2_VBLANK_INTERRUPT (1 << 5) 1364 1365 /* R6xx/R7xx registers */ 1366 #define R600_MC_VM_FB_LOCATION 0x2180 1367 #define R600_MC_VM_AGP_TOP 0x2184 1368 #define R600_MC_VM_AGP_BOT 0x2188 1369 #define R600_MC_VM_AGP_BASE 0x218c 1370 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1371 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1372 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1373 1374 #define R700_MC_VM_FB_LOCATION 0x2024 1375 #define R700_MC_VM_AGP_TOP 0x2028 1376 #define R700_MC_VM_AGP_BOT 0x202c 1377 #define R700_MC_VM_AGP_BASE 0x2030 1378 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1379 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1380 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1381 1382 #define R600_MCD_RD_A_CNTL 0x219c 1383 #define R600_MCD_RD_B_CNTL 0x21a0 1384 1385 #define R600_MCD_WR_A_CNTL 0x21a4 1386 #define R600_MCD_WR_B_CNTL 0x21a8 1387 1388 #define R600_MCD_RD_SYS_CNTL 0x2200 1389 #define R600_MCD_WR_SYS_CNTL 0x2214 1390 1391 #define R600_MCD_RD_GFX_CNTL 0x21fc 1392 #define R600_MCD_RD_HDP_CNTL 0x2204 1393 #define R600_MCD_RD_PDMA_CNTL 0x2208 1394 #define R600_MCD_RD_SEM_CNTL 0x220c 1395 #define R600_MCD_WR_GFX_CNTL 0x2210 1396 #define R600_MCD_WR_HDP_CNTL 0x2218 1397 #define R600_MCD_WR_PDMA_CNTL 0x221c 1398 #define R600_MCD_WR_SEM_CNTL 0x2220 1399 1400 # define R600_MCD_L1_TLB (1 << 0) 1401 # define R600_MCD_L1_FRAG_PROC (1 << 1) 1402 # define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1403 1404 # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1405 # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1406 # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1407 # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1408 # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1409 1410 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1411 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1412 1413 # define R600_MCD_SEMAPHORE_MODE (1 << 10) 1414 # define R600_MCD_WAIT_L2_QUERY (1 << 11) 1415 # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1416 # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1417 1418 #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1419 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1420 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1421 1422 #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1423 #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1424 #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1425 #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1426 1427 # define R700_ENABLE_L1_TLB (1 << 0) 1428 # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1429 # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1430 # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1431 # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1432 # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1433 1434 #define R700_MC_ARB_RAMCFG 0x2760 1435 # define R700_NOOFBANK_SHIFT 0 1436 # define R700_NOOFBANK_MASK 0x3 1437 # define R700_NOOFRANK_SHIFT 2 1438 # define R700_NOOFRANK_MASK 0x1 1439 # define R700_NOOFROWS_SHIFT 3 1440 # define R700_NOOFROWS_MASK 0x7 1441 # define R700_NOOFCOLS_SHIFT 6 1442 # define R700_NOOFCOLS_MASK 0x3 1443 # define R700_CHANSIZE_SHIFT 8 1444 # define R700_CHANSIZE_MASK 0x1 1445 # define R700_BURSTLENGTH_SHIFT 9 1446 # define R700_BURSTLENGTH_MASK 0x1 1447 #define R600_RAMCFG 0x2408 1448 # define R600_NOOFBANK_SHIFT 0 1449 # define R600_NOOFBANK_MASK 0x1 1450 # define R600_NOOFRANK_SHIFT 1 1451 # define R600_NOOFRANK_MASK 0x1 1452 # define R600_NOOFROWS_SHIFT 2 1453 # define R600_NOOFROWS_MASK 0x7 1454 # define R600_NOOFCOLS_SHIFT 5 1455 # define R600_NOOFCOLS_MASK 0x3 1456 # define R600_CHANSIZE_SHIFT 7 1457 # define R600_CHANSIZE_MASK 0x1 1458 # define R600_BURSTLENGTH_SHIFT 8 1459 # define R600_BURSTLENGTH_MASK 0x1 1460 1461 #define R600_VM_L2_CNTL 0x1400 1462 # define R600_VM_L2_CACHE_EN (1 << 0) 1463 # define R600_VM_L2_FRAG_PROC (1 << 1) 1464 # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1465 # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1466 # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1467 1468 #define R600_VM_L2_CNTL2 0x1404 1469 # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1470 # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1471 #define R600_VM_L2_CNTL3 0x1408 1472 # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1473 # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1474 # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1475 # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1476 # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1477 1478 #define R600_VM_L2_STATUS 0x140c 1479 1480 #define R600_VM_CONTEXT0_CNTL 0x1410 1481 # define R600_VM_ENABLE_CONTEXT (1 << 0) 1482 # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1483 1484 #define R600_VM_CONTEXT0_CNTL2 0x1430 1485 #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1486 #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1487 #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1488 #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1489 #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1490 #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1491 1492 #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1493 #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1494 #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1495 1496 #define R600_HDP_HOST_PATH_CNTL 0x2c00 1497 1498 #define R600_GRBM_CNTL 0x8000 1499 # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1500 1501 #define R600_GRBM_STATUS 0x8010 1502 # define R600_CMDFIFO_AVAIL_MASK 0x1f 1503 # define R700_CMDFIFO_AVAIL_MASK 0xf 1504 # define R600_GUI_ACTIVE (1 << 31) 1505 #define R600_GRBM_STATUS2 0x8014 1506 #define R600_GRBM_SOFT_RESET 0x8020 1507 # define R600_SOFT_RESET_CP (1 << 0) 1508 #define R600_WAIT_UNTIL 0x8040 1509 1510 #define R600_CP_SEM_WAIT_TIMER 0x85bc 1511 #define R600_CP_ME_CNTL 0x86d8 1512 # define R600_CP_ME_HALT (1 << 28) 1513 #define R600_CP_QUEUE_THRESHOLDS 0x8760 1514 # define R600_ROQ_IB1_START(x) ((x) << 0) 1515 # define R600_ROQ_IB2_START(x) ((x) << 8) 1516 #define R600_CP_MEQ_THRESHOLDS 0x8764 1517 # define R700_STQ_SPLIT(x) ((x) << 0) 1518 # define R600_MEQ_END(x) ((x) << 16) 1519 # define R600_ROQ_END(x) ((x) << 24) 1520 #define R600_CP_PERFMON_CNTL 0x87fc 1521 #define R600_CP_RB_BASE 0xc100 1522 #define R600_CP_RB_CNTL 0xc104 1523 # define R600_RB_BUFSZ(x) ((x) << 0) 1524 # define R600_RB_BLKSZ(x) ((x) << 8) 1525 # define R600_BUF_SWAP_32BIT (2 << 16) 1526 # define R600_RB_NO_UPDATE (1 << 27) 1527 # define R600_RB_RPTR_WR_ENA (1 << 31) 1528 #define R600_CP_RB_RPTR_WR 0xc108 1529 #define R600_CP_RB_RPTR_ADDR 0xc10c 1530 #define R600_CP_RB_RPTR_ADDR_HI 0xc110 1531 #define R600_CP_RB_WPTR 0xc114 1532 #define R600_CP_RB_WPTR_ADDR 0xc118 1533 #define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1534 #define R600_CP_RB_RPTR 0x8700 1535 #define R600_CP_RB_WPTR_DELAY 0x8704 1536 #define R600_CP_PFP_UCODE_ADDR 0xc150 1537 #define R600_CP_PFP_UCODE_DATA 0xc154 1538 #define R600_CP_ME_RAM_RADDR 0xc158 1539 #define R600_CP_ME_RAM_WADDR 0xc15c 1540 #define R600_CP_ME_RAM_DATA 0xc160 1541 #define R600_CP_DEBUG 0xc1fc 1542 1543 #define R600_PA_CL_ENHANCE 0x8a14 1544 # define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1545 # define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1546 #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1547 #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1548 #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1549 # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1550 # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1551 #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1552 #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1553 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1554 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1555 # define R600_S0_X(x) ((x) << 0) 1556 # define R600_S0_Y(x) ((x) << 4) 1557 # define R600_S1_X(x) ((x) << 8) 1558 # define R600_S1_Y(x) ((x) << 12) 1559 # define R600_S2_X(x) ((x) << 16) 1560 # define R600_S2_Y(x) ((x) << 20) 1561 # define R600_S3_X(x) ((x) << 24) 1562 # define R600_S3_Y(x) ((x) << 28) 1563 # define R600_S4_X(x) ((x) << 0) 1564 # define R600_S4_Y(x) ((x) << 4) 1565 # define R600_S5_X(x) ((x) << 8) 1566 # define R600_S5_Y(x) ((x) << 12) 1567 # define R600_S6_X(x) ((x) << 16) 1568 # define R600_S6_Y(x) ((x) << 20) 1569 # define R600_S7_X(x) ((x) << 24) 1570 # define R600_S7_Y(x) ((x) << 28) 1571 #define R600_PA_SC_FIFO_SIZE 0x8bd0 1572 # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1573 # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1574 # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1575 #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1576 # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1577 # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1578 # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1579 #define R600_PA_SC_ENHANCE 0x8bf0 1580 # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1581 # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1582 #define R600_PA_SC_CLIPRECT_RULE 0x2820c 1583 #define R700_PA_SC_EDGERULE 0x28230 1584 #define R600_PA_SC_LINE_STIPPLE 0x28a0c 1585 #define R600_PA_SC_MODE_CNTL 0x28a4c 1586 #define R600_PA_SC_AA_CONFIG 0x28c04 1587 1588 #define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1589 # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1590 # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1591 # define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1592 #define R600_SX_DEBUG_1 0x9054 1593 # define R600_SMX_EVENT_RELEASE (1 << 0) 1594 # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1595 #define R700_SX_DEBUG_1 0x9058 1596 # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1597 #define R600_SX_MISC 0x28350 1598 1599 #define R600_DB_DEBUG 0x9830 1600 # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 1601 #define R600_DB_WATERMARKS 0x9838 1602 # define R600_DEPTH_FREE(x) ((x) << 0) 1603 # define R600_DEPTH_FLUSH(x) ((x) << 5) 1604 # define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1605 # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1606 #define R700_DB_DEBUG3 0x98b0 1607 # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1608 #define RV700_DB_DEBUG4 0x9b8c 1609 # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1610 1611 #define R600_VGT_CACHE_INVALIDATION 0x88c4 1612 # define R600_CACHE_INVALIDATION(x) ((x) << 0) 1613 # define R600_VC_ONLY 0 1614 # define R600_TC_ONLY 1 1615 # define R600_VC_AND_TC 2 1616 # define R700_AUTO_INVLD_EN(x) ((x) << 6) 1617 # define R700_NO_AUTO 0 1618 # define R700_ES_AUTO 1 1619 # define R700_GS_AUTO 2 1620 # define R700_ES_AND_GS_AUTO 3 1621 #define R600_VGT_GS_PER_ES 0x88c8 1622 #define R600_VGT_ES_PER_GS 0x88cc 1623 #define R600_VGT_GS_PER_VS 0x88e8 1624 #define R600_VGT_GS_VERTEX_REUSE 0x88d4 1625 #define R600_VGT_NUM_INSTANCES 0x8974 1626 #define R600_VGT_STRMOUT_EN 0x28ab0 1627 #define R600_VGT_EVENT_INITIATOR 0x28a90 1628 # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1629 #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1630 # define R600_VTX_REUSE_DEPTH_MASK 0xff 1631 #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1632 # define R600_DEALLOC_DIST_MASK 0x7f 1633 1634 #define R600_CB_COLOR0_BASE 0x28040 1635 #define R600_CB_COLOR1_BASE 0x28044 1636 #define R600_CB_COLOR2_BASE 0x28048 1637 #define R600_CB_COLOR3_BASE 0x2804c 1638 #define R600_CB_COLOR4_BASE 0x28050 1639 #define R600_CB_COLOR5_BASE 0x28054 1640 #define R600_CB_COLOR6_BASE 0x28058 1641 #define R600_CB_COLOR7_BASE 0x2805c 1642 #define R600_CB_COLOR7_FRAG 0x280fc 1643 1644 #define R600_CB_COLOR0_SIZE 0x28060 1645 #define R600_CB_COLOR0_VIEW 0x28080 1646 #define R600_CB_COLOR0_INFO 0x280a0 1647 #define R600_CB_COLOR0_TILE 0x280c0 1648 #define R600_CB_COLOR0_FRAG 0x280e0 1649 #define R600_CB_COLOR0_MASK 0x28100 1650 1651 #define AVIVO_D1MODE_VLINE_START_END 0x6538 1652 #define AVIVO_D2MODE_VLINE_START_END 0x6d38 1653 #define R600_CP_COHER_BASE 0x85f8 1654 #define R600_DB_DEPTH_BASE 0x2800c 1655 #define R600_SQ_PGM_START_FS 0x28894 1656 #define R600_SQ_PGM_START_ES 0x28880 1657 #define R600_SQ_PGM_START_VS 0x28858 1658 #define R600_SQ_PGM_RESOURCES_VS 0x28868 1659 #define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 1660 #define R600_SQ_PGM_START_GS 0x2886c 1661 #define R600_SQ_PGM_START_PS 0x28840 1662 #define R600_SQ_PGM_RESOURCES_PS 0x28850 1663 #define R600_SQ_PGM_EXPORTS_PS 0x28854 1664 #define R600_SQ_PGM_CF_OFFSET_PS 0x288cc 1665 #define R600_VGT_DMA_BASE 0x287e8 1666 #define R600_VGT_DMA_BASE_HI 0x287e4 1667 #define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 1668 #define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 1669 #define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 1670 #define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c 1671 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 1672 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 1673 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c 1674 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 1675 #define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 1676 #define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 1677 #define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 1678 #define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 1679 #define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc 1680 #define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec 1681 #define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc 1682 #define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c 1683 1684 #define R600_VGT_PRIMITIVE_TYPE 0x8958 1685 1686 #define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 1687 #define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 1688 #define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 1689 1690 #define R600_TC_CNTL 0x9608 1691 # define R600_TC_L2_SIZE(x) ((x) << 5) 1692 # define R600_L2_DISABLE_LATE_HIT (1 << 9) 1693 1694 #define R600_ARB_POP 0x2418 1695 # define R600_ENABLE_TC128 (1 << 30) 1696 #define R600_ARB_GDEC_RD_CNTL 0x246c 1697 1698 #define R600_TA_CNTL_AUX 0x9508 1699 # define R600_DISABLE_CUBE_WRAP (1 << 0) 1700 # define R600_DISABLE_CUBE_ANISO (1 << 1) 1701 # define R700_GETLOD_SELECT(x) ((x) << 2) 1702 # define R600_SYNC_GRADIENT (1 << 24) 1703 # define R600_SYNC_WALKER (1 << 25) 1704 # define R600_SYNC_ALIGNER (1 << 26) 1705 # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1706 # define R600_BILINEAR_PRECISION_8_BIT (1 << 31) 1707 1708 #define R700_TCP_CNTL 0x9610 1709 1710 #define R600_SMX_DC_CTL0 0xa020 1711 # define R700_USE_HASH_FUNCTION (1 << 0) 1712 # define R700_CACHE_DEPTH(x) ((x) << 1) 1713 # define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1714 # define R700_STALL_ON_EVENT (1 << 11) 1715 #define R700_SMX_EVENT_CTL 0xa02c 1716 # define R700_ES_FLUSH_CTL(x) ((x) << 0) 1717 # define R700_GS_FLUSH_CTL(x) ((x) << 3) 1718 # define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1719 # define R700_SYNC_FLUSH_CTL (1 << 8) 1720 1721 #define R600_SQ_CONFIG 0x8c00 1722 # define R600_VC_ENABLE (1 << 0) 1723 # define R600_EXPORT_SRC_C (1 << 1) 1724 # define R600_DX9_CONSTS (1 << 2) 1725 # define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1726 # define R600_DX10_CLAMP (1 << 4) 1727 # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1728 # define R600_PS_PRIO(x) ((x) << 24) 1729 # define R600_VS_PRIO(x) ((x) << 26) 1730 # define R600_GS_PRIO(x) ((x) << 28) 1731 # define R600_ES_PRIO(x) ((x) << 30) 1732 #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1733 # define R600_NUM_PS_GPRS(x) ((x) << 0) 1734 # define R600_NUM_VS_GPRS(x) ((x) << 16) 1735 # define R700_DYN_GPR_ENABLE (1 << 27) 1736 # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1737 #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1738 # define R600_NUM_GS_GPRS(x) ((x) << 0) 1739 # define R600_NUM_ES_GPRS(x) ((x) << 16) 1740 #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1741 # define R600_NUM_PS_THREADS(x) ((x) << 0) 1742 # define R600_NUM_VS_THREADS(x) ((x) << 8) 1743 # define R600_NUM_GS_THREADS(x) ((x) << 16) 1744 # define R600_NUM_ES_THREADS(x) ((x) << 24) 1745 #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1746 # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1747 # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1748 #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1749 # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1750 # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1751 #define R600_SQ_MS_FIFO_SIZES 0x8cf0 1752 # define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1753 # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1754 # define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1755 # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1756 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1757 # define R700_SIMDA_RING0(x) ((x) << 0) 1758 # define R700_SIMDA_RING1(x) ((x) << 8) 1759 # define R700_SIMDB_RING0(x) ((x) << 16) 1760 # define R700_SIMDB_RING1(x) ((x) << 24) 1761 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1762 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1763 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1764 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1765 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1766 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1767 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1768 1769 #define R600_SPI_PS_IN_CONTROL_0 0x286cc 1770 # define R600_NUM_INTERP(x) ((x) << 0) 1771 # define R600_POSITION_ENA (1 << 8) 1772 # define R600_POSITION_CENTROID (1 << 9) 1773 # define R600_POSITION_ADDR(x) ((x) << 10) 1774 # define R600_PARAM_GEN(x) ((x) << 15) 1775 # define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1776 # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1777 # define R600_PERSP_GRADIENT_ENA (1 << 28) 1778 # define R600_LINEAR_GRADIENT_ENA (1 << 29) 1779 # define R600_POSITION_SAMPLE (1 << 30) 1780 # define R600_BARYC_AT_SAMPLE_ENA (1 << 31) 1781 #define R600_SPI_PS_IN_CONTROL_1 0x286d0 1782 # define R600_GEN_INDEX_PIX (1 << 0) 1783 # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1784 # define R600_FRONT_FACE_ENA (1 << 8) 1785 # define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1786 # define R600_FRONT_FACE_ALL_BITS (1 << 11) 1787 # define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1788 # define R600_FOG_ADDR(x) ((x) << 17) 1789 # define R600_FIXED_PT_POSITION_ENA (1 << 24) 1790 # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1791 # define R700_POSITION_ULC (1 << 30) 1792 #define R600_SPI_INPUT_Z 0x286d8 1793 1794 #define R600_SPI_CONFIG_CNTL 0x9100 1795 # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1796 # define R600_DISABLE_INTERP_1 (1 << 5) 1797 #define R600_SPI_CONFIG_CNTL_1 0x913c 1798 # define R600_VTX_DONE_DELAY(x) ((x) << 0) 1799 # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1800 1801 #define R600_GB_TILING_CONFIG 0x98f0 1802 # define R600_PIPE_TILING(x) ((x) << 1) 1803 # define R600_BANK_TILING(x) ((x) << 4) 1804 # define R600_GROUP_SIZE(x) ((x) << 6) 1805 # define R600_ROW_TILING(x) ((x) << 8) 1806 # define R600_BANK_SWAPS(x) ((x) << 11) 1807 # define R600_SAMPLE_SPLIT(x) ((x) << 14) 1808 # define R600_BACKEND_MAP(x) ((x) << 16) 1809 #define R600_DCP_TILING_CONFIG 0x6ca0 1810 #define R600_HDP_TILING_CONFIG 0x2f3c 1811 1812 #define R600_CC_RB_BACKEND_DISABLE 0x98f4 1813 #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1814 # define R600_BACKEND_DISABLE(x) ((x) << 16) 1815 1816 #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1817 #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1818 # define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1819 # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1820 # define R600_INACTIVE_SIMDS(x) ((x) << 16) 1821 # define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1822 1823 #define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1824 #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1825 #define R700_CGTS_TCC_DISABLE 0x9148 1826 #define R700_CGTS_USER_TCC_DISABLE 0x914c 1827 1828 /* Constants */ 1829 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1830 1831 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1832 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1833 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1834 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1835 #define RADEON_LAST_DISPATCH 1 1836 1837 #define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1838 #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1839 #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1840 #define R600_LAST_SWI_REG R600_SCRATCH_REG3 1841 1842 #define RADEON_MAX_VB_AGE 0x7fffffff 1843 #define RADEON_MAX_VB_VERTS (0xffff) 1844 1845 #define RADEON_RING_HIGH_MARK 128 1846 1847 #define RADEON_PCIGART_TABLE_SIZE (32*1024) 1848 1849 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1850 #define RADEON_WRITE(reg, val) \ 1851 do { \ 1852 if (reg < 0x10000) { \ 1853 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1854 } else { \ 1855 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1856 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1857 } \ 1858 } while (0) 1859 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1860 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1861 1862 #define RADEON_WRITE_PLL(addr, val) \ 1863 do { \ 1864 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1865 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1866 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1867 } while (0) 1868 1869 #define RADEON_WRITE_PCIE(addr, val) \ 1870 do { \ 1871 RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1872 ((addr) & 0xff)); \ 1873 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1874 } while (0) 1875 1876 #define R500_WRITE_MCIND(addr, val) \ 1877 do { \ 1878 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1879 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1880 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1881 } while (0) 1882 1883 #define RS480_WRITE_MCIND(addr, val) \ 1884 do { \ 1885 RADEON_WRITE(RS480_NB_MC_INDEX, \ 1886 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1887 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1888 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1889 } while (0) 1890 1891 #define RS690_WRITE_MCIND(addr, val) \ 1892 do { \ 1893 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1894 RADEON_WRITE(RS690_MC_DATA, val); \ 1895 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1896 } while (0) 1897 1898 #define RS600_WRITE_MCIND(addr, val) \ 1899 do { \ 1900 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1901 RADEON_WRITE(RS600_MC_DATA, val); \ 1902 } while (0) 1903 1904 #define IGP_WRITE_MCIND(addr, val) \ 1905 do { \ 1906 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1907 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1908 RS690_WRITE_MCIND(addr, val); \ 1909 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1910 RS600_WRITE_MCIND(addr, val); \ 1911 else \ 1912 RS480_WRITE_MCIND(addr, val); \ 1913 } while (0) 1914 1915 #define CP_PACKET0( reg, n ) \ 1916 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1917 #define CP_PACKET0_TABLE( reg, n ) \ 1918 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1919 #define CP_PACKET1( reg0, reg1 ) \ 1920 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1921 #define CP_PACKET2() \ 1922 (RADEON_CP_PACKET2) 1923 #define CP_PACKET3( pkt, n ) \ 1924 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1925 1926 /* ================================================================ 1927 * Engine control helper macros 1928 */ 1929 1930 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1931 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1932 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1933 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1934 } while (0) 1935 1936 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1937 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1938 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1939 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1940 } while (0) 1941 1942 #define RADEON_WAIT_UNTIL_IDLE() do { \ 1943 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1944 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1945 RADEON_WAIT_3D_IDLECLEAN | \ 1946 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1947 } while (0) 1948 1949 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1950 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1951 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1952 } while (0) 1953 1954 #define RADEON_FLUSH_CACHE() do { \ 1955 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1956 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1957 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1958 } else { \ 1959 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1960 OUT_RING(R300_RB3D_DC_FLUSH); \ 1961 } \ 1962 } while (0) 1963 1964 #define RADEON_PURGE_CACHE() do { \ 1965 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1966 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1967 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1968 } else { \ 1969 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1970 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1971 } \ 1972 } while (0) 1973 1974 #define RADEON_FLUSH_ZCACHE() do { \ 1975 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1976 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1977 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1978 } else { \ 1979 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1980 OUT_RING(R300_ZC_FLUSH); \ 1981 } \ 1982 } while (0) 1983 1984 #define RADEON_PURGE_ZCACHE() do { \ 1985 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1986 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1987 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1988 } else { \ 1989 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1990 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1991 } \ 1992 } while (0) 1993 1994 /* ================================================================ 1995 * Misc helper macros 1996 */ 1997 1998 /* Perfbox functionality only. 1999 */ 2000 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 2001 do { \ 2002 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 2003 u32 head = GET_RING_HEAD( dev_priv ); \ 2004 if (head == dev_priv->ring.tail) \ 2005 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 2006 } \ 2007 } while (0) 2008 2009 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 2010 do { \ 2011 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv; \ 2012 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \ 2013 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 2014 int __ret; \ 2015 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 2016 __ret = r600_do_cp_idle(dev_priv); \ 2017 else \ 2018 __ret = radeon_do_cp_idle(dev_priv); \ 2019 if ( __ret ) return __ret; \ 2020 sarea_priv->last_dispatch = 0; \ 2021 radeon_freelist_reset( dev ); \ 2022 } \ 2023 } while (0) 2024 2025 #define RADEON_DISPATCH_AGE( age ) do { \ 2026 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2027 OUT_RING( age ); \ 2028 } while (0) 2029 2030 #define RADEON_FRAME_AGE( age ) do { \ 2031 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2032 OUT_RING( age ); \ 2033 } while (0) 2034 2035 #define RADEON_CLEAR_AGE( age ) do { \ 2036 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2037 OUT_RING( age ); \ 2038 } while (0) 2039 2040 #define R600_DISPATCH_AGE(age) do { \ 2041 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2042 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2043 OUT_RING(age); \ 2044 } while (0) 2045 2046 #define R600_FRAME_AGE(age) do { \ 2047 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2048 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2049 OUT_RING(age); \ 2050 } while (0) 2051 2052 #define R600_CLEAR_AGE(age) do { \ 2053 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2054 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2055 OUT_RING(age); \ 2056 } while (0) 2057 2058 /* ================================================================ 2059 * Ring control 2060 */ 2061 2062 #define RADEON_VERBOSE 0 2063 2064 #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2065 2066 #define RADEON_RING_ALIGN 16 2067 2068 #define BEGIN_RING( n ) do { \ 2069 if ( RADEON_VERBOSE ) { \ 2070 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2071 } \ 2072 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \ 2073 _align_nr += n; \ 2074 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \ 2075 COMMIT_RING(); \ 2076 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \ 2077 } \ 2078 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2079 ring = dev_priv->ring.start; \ 2080 write = dev_priv->ring.tail; \ 2081 mask = dev_priv->ring.tail_mask; \ 2082 } while (0) 2083 2084 #define ADVANCE_RING() do { \ 2085 if ( RADEON_VERBOSE ) { \ 2086 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 2087 write, dev_priv->ring.tail ); \ 2088 } \ 2089 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2090 DRM_ERROR( \ 2091 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2092 ((dev_priv->ring.tail + _nr) & mask), \ 2093 write, __LINE__); \ 2094 } else \ 2095 dev_priv->ring.tail = write; \ 2096 } while (0) 2097 2098 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 2099 2100 #define COMMIT_RING() do { \ 2101 radeon_commit_ring(dev_priv); \ 2102 } while(0) 2103 2104 #define OUT_RING( x ) do { \ 2105 if ( RADEON_VERBOSE ) { \ 2106 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2107 (unsigned int)(x), write ); \ 2108 } \ 2109 ring[write++] = (x); \ 2110 write &= mask; \ 2111 } while (0) 2112 2113 #define OUT_RING_REG( reg, val ) do { \ 2114 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2115 OUT_RING( val ); \ 2116 } while (0) 2117 2118 #define OUT_RING_TABLE( tab, sz ) do { \ 2119 int _size = (sz); \ 2120 int *_tab = (int *)(tab); \ 2121 \ 2122 if (write + _size > mask) { \ 2123 int _i = (mask+1) - write; \ 2124 _size -= _i; \ 2125 while (_i > 0 ) { \ 2126 *(int *)(ring + write) = *_tab++; \ 2127 write++; \ 2128 _i--; \ 2129 } \ 2130 write = 0; \ 2131 _tab += _i; \ 2132 } \ 2133 while (_size > 0) { \ 2134 *(ring + write) = *_tab++; \ 2135 write++; \ 2136 _size--; \ 2137 } \ 2138 write &= mask; \ 2139 } while (0) 2140 2141 /** 2142 * Copy given number of dwords from drm buffer to the ring buffer. 2143 */ 2144 #define OUT_RING_DRM_BUFFER(buf, sz) do { \ 2145 int _size = (sz) * 4; \ 2146 struct drm_buffer *_buf = (buf); \ 2147 int _part_size; \ 2148 while (_size > 0) { \ 2149 _part_size = _size; \ 2150 \ 2151 if (write + _part_size/4 > mask) \ 2152 _part_size = ((mask + 1) - write)*4; \ 2153 \ 2154 if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \ 2155 _part_size = PAGE_SIZE - drm_buffer_index(_buf);\ 2156 \ 2157 \ 2158 \ 2159 memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \ 2160 [drm_buffer_index(_buf)], _part_size); \ 2161 \ 2162 _size -= _part_size; \ 2163 write = (write + _part_size/4) & mask; \ 2164 drm_buffer_advance(_buf, _part_size); \ 2165 } \ 2166 } while (0) 2167 2168 2169 #endif /* CONFIG_DRM_RADEON_UMS */ 2170 2171 #endif /* __RADEON_DRV_H__ */ 2172