1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_drv.h 254885 2013-08-25 19:37:15Z dumbbell $ 31 */ 32 33 #ifndef __RADEON_DRV_H__ 34 #define __RADEON_DRV_H__ 35 36 #include "radeon_family.h" 37 38 /* General customization: 39 */ 40 41 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 42 43 #define DRIVER_NAME "radeon" 44 #define DRIVER_DESC "ATI Radeon" 45 #define DRIVER_DATE "20080528" 46 47 /* Interface history: 48 * 49 * 1.1 - ?? 50 * 1.2 - Add vertex2 ioctl (keith) 51 * - Add stencil capability to clear ioctl (gareth, keith) 52 * - Increase MAX_TEXTURE_LEVELS (brian) 53 * 1.3 - Add cmdbuf ioctl (keith) 54 * - Add support for new radeon packets (keith) 55 * - Add getparam ioctl (keith) 56 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 57 * 1.4 - Add scratch registers to get_param ioctl. 58 * 1.5 - Add r200 packets to cmdbuf ioctl 59 * - Add r200 function to init ioctl 60 * - Add 'scalar2' instruction to cmdbuf 61 * 1.6 - Add static GART memory manager 62 * Add irq handler (won't be turned on unless X server knows to) 63 * Add irq ioctls and irq_active getparam. 64 * Add wait command for cmdbuf ioctl 65 * Add GART offset query for getparam 66 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 67 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 68 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 69 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 70 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 71 * Add 'GET' queries for starting additional clients on different VT's. 72 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 73 * Add texture rectangle support for r100. 74 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 75 * clients use to tell the DRM where they think the framebuffer is 76 * located in the card's address space 77 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 78 * and GL_EXT_blend_[func|equation]_separate on r200 79 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 80 * (No 3D support yet - just microcode loading). 81 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 82 * - Add hyperz support, add hyperz flags to clear ioctl. 83 * 1.14- Add support for color tiling 84 * - Add R100/R200 surface allocation/free support 85 * 1.15- Add support for texture micro tiling 86 * - Add support for r100 cube maps 87 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 88 * texture filtering on r200 89 * 1.17- Add initial support for R300 (3D). 90 * 1.18- Add support for GL_ATI_fragment_shader, new packets 91 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 92 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 93 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 94 * 1.19- Add support for gart table in FB memory and PCIE r300 95 * 1.20- Add support for r300 texrect 96 * 1.21- Add support for card type getparam 97 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 98 * 1.23- Add new radeon memory map work from benh 99 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 100 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 101 * new packet type) 102 * 1.26- Add support for variable size PCI(E) gart aperture 103 * 1.27- Add support for IGP GART 104 * 1.28- Add support for VBL on CRTC2 105 * 1.29- R500 3D cmd buffer support 106 * 1.30- Add support for occlusion queries 107 * 1.31- Add support for num Z pipes from GET_PARAM 108 * 1.32- fixes for rv740 setup 109 * 1.33- Add r6xx/r7xx const buffer support 110 */ 111 #define DRIVER_MAJOR 1 112 #define DRIVER_MINOR 33 113 #define DRIVER_PATCHLEVEL 0 114 115 /* The rest of the file is DEPRECATED! */ 116 #ifdef CONFIG_DRM_RADEON_UMS 117 118 enum radeon_cp_microcode_version { 119 UCODE_R100, 120 UCODE_R200, 121 UCODE_R300, 122 }; 123 124 typedef struct drm_radeon_freelist { 125 unsigned int age; 126 struct drm_buf *buf; 127 struct drm_radeon_freelist *next; 128 struct drm_radeon_freelist *prev; 129 } drm_radeon_freelist_t; 130 131 typedef struct drm_radeon_ring_buffer { 132 u32 *start; 133 u32 *end; 134 int size; 135 int size_l2qw; 136 137 int rptr_update; /* Double Words */ 138 int rptr_update_l2qw; /* log2 Quad Words */ 139 140 int fetch_size; /* Double Words */ 141 int fetch_size_l2ow; /* log2 Oct Words */ 142 143 u32 tail; 144 u32 tail_mask; 145 int space; 146 147 int high_mark; 148 } drm_radeon_ring_buffer_t; 149 150 typedef struct drm_radeon_depth_clear_t { 151 u32 rb3d_cntl; 152 u32 rb3d_zstencilcntl; 153 u32 se_cntl; 154 } drm_radeon_depth_clear_t; 155 156 struct drm_radeon_driver_file_fields { 157 int64_t radeon_fb_delta; 158 }; 159 160 struct mem_block { 161 struct mem_block *next; 162 struct mem_block *prev; 163 int start; 164 int size; 165 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 166 }; 167 168 struct radeon_surface { 169 int refcount; 170 u32 lower; 171 u32 upper; 172 u32 flags; 173 }; 174 175 struct radeon_virt_surface { 176 int surface_index; 177 u32 lower; 178 u32 upper; 179 u32 flags; 180 struct drm_file *file_priv; 181 #define PCIGART_FILE_PRIV ((void *) -1L) 182 }; 183 184 #define RADEON_FLUSH_EMITED (1 << 0) 185 #define RADEON_PURGE_EMITED (1 << 1) 186 187 struct drm_radeon_master_private { 188 drm_local_map_t *sarea; 189 drm_radeon_sarea_t *sarea_priv; 190 }; 191 192 typedef struct drm_radeon_private { 193 drm_radeon_ring_buffer_t ring; 194 195 u32 fb_location; 196 u32 fb_size; 197 int new_memmap; 198 199 int gart_size; 200 u32 gart_vm_start; 201 unsigned long gart_buffers_offset; 202 203 int cp_mode; 204 int cp_running; 205 206 drm_radeon_freelist_t *head; 207 drm_radeon_freelist_t *tail; 208 int last_buf; 209 int writeback_works; 210 211 int usec_timeout; 212 213 int microcode_version; 214 215 struct { 216 u32 boxes; 217 int freelist_timeouts; 218 int freelist_loops; 219 int requested_bufs; 220 int last_frame_reads; 221 int last_clear_reads; 222 int clears; 223 int texture_uploads; 224 } stats; 225 226 int do_boxes; 227 int page_flipping; 228 229 u32 color_fmt; 230 unsigned int front_offset; 231 unsigned int front_pitch; 232 unsigned int back_offset; 233 unsigned int back_pitch; 234 235 u32 depth_fmt; 236 unsigned int depth_offset; 237 unsigned int depth_pitch; 238 239 u32 front_pitch_offset; 240 u32 back_pitch_offset; 241 u32 depth_pitch_offset; 242 243 drm_radeon_depth_clear_t depth_clear; 244 245 unsigned long ring_offset; 246 unsigned long ring_rptr_offset; 247 unsigned long buffers_offset; 248 unsigned long gart_textures_offset; 249 250 drm_local_map_t *sarea; 251 drm_local_map_t *cp_ring; 252 drm_local_map_t *ring_rptr; 253 drm_local_map_t *gart_textures; 254 255 struct mem_block *gart_heap; 256 struct mem_block *fb_heap; 257 258 /* SW interrupt */ 259 wait_queue_head_t swi_queue; 260 atomic_t swi_emitted; 261 int vblank_crtc; 262 uint32_t irq_enable_reg; 263 uint32_t r500_disp_irq_reg; 264 265 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 266 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 267 268 unsigned long pcigart_offset; 269 unsigned int pcigart_offset_set; 270 struct drm_ati_pcigart_info gart_info; 271 272 u32 scratch_ages[5]; 273 274 int have_z_offset; 275 276 /* starting from here on, data is preserved across an open */ 277 uint32_t flags; /* see radeon_chip_flags */ 278 resource_size_t fb_aper_offset; 279 280 int num_gb_pipes; 281 int num_z_pipes; 282 int track_flush; 283 drm_local_map_t *mmio; 284 285 /* r6xx/r7xx pipe/shader config */ 286 int r600_max_pipes; 287 int r600_max_tile_pipes; 288 int r600_max_simds; 289 int r600_max_backends; 290 int r600_max_gprs; 291 int r600_max_threads; 292 int r600_max_stack_entries; 293 int r600_max_hw_contexts; 294 int r600_max_gs_threads; 295 int r600_sx_max_export_size; 296 int r600_sx_max_export_pos_size; 297 int r600_sx_max_export_smx_size; 298 int r600_sq_num_cf_insts; 299 int r700_sx_num_of_sets; 300 int r700_sc_prim_fifo_size; 301 int r700_sc_hiz_tile_fifo_size; 302 int r700_sc_earlyz_tile_fifo_fize; 303 int r600_group_size; 304 int r600_npipes; 305 int r600_nbanks; 306 307 struct lock cs_mutex; 308 u32 cs_id_scnt; 309 u32 cs_id_wcnt; 310 /* r6xx/r7xx drm blit vertex buffer */ 311 struct drm_buf *blit_vb; 312 313 /* firmware */ 314 const struct firmware *me_fw, *pfp_fw; 315 } drm_radeon_private_t; 316 317 typedef struct drm_radeon_buf_priv { 318 u32 age; 319 } drm_radeon_buf_priv_t; 320 321 struct drm_buffer; 322 323 typedef struct drm_radeon_kcmd_buffer { 324 int bufsz; 325 struct drm_buffer *buffer; 326 int nbox; 327 struct drm_clip_rect __user *boxes; 328 } drm_radeon_kcmd_buffer_t; 329 330 extern int radeon_no_wb; 331 extern struct drm_ioctl_desc radeon_ioctls[]; 332 extern int radeon_max_ioctl; 333 334 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 335 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 336 337 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 338 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 339 340 /* Check whether the given hardware address is inside the framebuffer or the 341 * GART area. 342 */ 343 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 344 u64 off) 345 { 346 u32 fb_start = dev_priv->fb_location; 347 u32 fb_end = fb_start + dev_priv->fb_size - 1; 348 u32 gart_start = dev_priv->gart_vm_start; 349 u32 gart_end = gart_start + dev_priv->gart_size - 1; 350 351 return ((off >= fb_start && off <= fb_end) || 352 (off >= gart_start && off <= gart_end)); 353 } 354 355 /* radeon_state.c */ 356 extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); 357 358 /* radeon_cp.c */ 359 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 360 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 361 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 362 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 363 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 364 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 365 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 366 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 367 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 368 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 369 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 370 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 371 372 extern void radeon_freelist_reset(struct drm_device * dev); 373 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 374 375 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 376 377 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 378 379 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 380 extern int radeon_presetup(struct drm_device *dev); 381 extern int radeon_driver_postcleanup(struct drm_device *dev); 382 383 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 384 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 385 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 386 extern void radeon_mem_takedown(struct mem_block **heap); 387 extern void radeon_mem_release(struct drm_file *file_priv, 388 struct mem_block *heap); 389 390 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 391 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 392 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 393 394 /* radeon_irq.c */ 395 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 396 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 397 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 398 399 extern void radeon_do_release(struct drm_device * dev); 400 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 401 extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 402 extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 403 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 404 extern void radeon_driver_irq_preinstall(struct drm_device * dev); 405 extern int radeon_driver_irq_postinstall(struct drm_device *dev); 406 extern void radeon_driver_irq_uninstall(struct drm_device * dev); 407 extern void radeon_enable_interrupt(struct drm_device *dev); 408 extern int radeon_vblank_crtc_get(struct drm_device *dev); 409 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 410 411 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 412 extern int radeon_driver_unload(struct drm_device *dev); 413 extern int radeon_driver_firstopen(struct drm_device *dev); 414 extern void radeon_driver_preclose(struct drm_device *dev, 415 struct drm_file *file_priv); 416 extern void radeon_driver_postclose(struct drm_device *dev, 417 struct drm_file *file_priv); 418 extern void radeon_driver_lastclose(struct drm_device * dev); 419 extern int radeon_driver_open(struct drm_device *dev, 420 struct drm_file *file_priv); 421 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 422 unsigned long arg); 423 424 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); 425 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); 426 extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master); 427 /* r300_cmdbuf.c */ 428 extern void r300_init_reg_flags(struct drm_device *dev); 429 430 extern int r300_do_cp_cmdbuf(struct drm_device *dev, 431 struct drm_file *file_priv, 432 drm_radeon_kcmd_buffer_t *cmdbuf); 433 434 /* r600_cp.c */ 435 extern int r600_do_engine_reset(struct drm_device *dev); 436 extern int r600_do_cleanup_cp(struct drm_device *dev); 437 extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 438 struct drm_file *file_priv); 439 extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 440 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 441 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 442 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 443 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 444 extern int r600_cp_dispatch_indirect(struct drm_device *dev, 445 struct drm_buf *buf, int start, int end); 446 extern int r600_page_table_init(struct drm_device *dev); 447 extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 448 extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 449 extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); 450 extern int r600_cp_dispatch_texture(struct drm_device *dev, 451 struct drm_file *file_priv, 452 drm_radeon_texture_t *tex, 453 drm_radeon_tex_image_t *image); 454 /* r600_blit.c */ 455 extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); 456 extern void r600_done_blit_copy(struct drm_device *dev); 457 extern void r600_blit_copy(struct drm_device *dev, 458 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 459 int size_bytes); 460 extern void r600_blit_swap(struct drm_device *dev, 461 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 462 int sx, int sy, int dx, int dy, 463 int w, int h, int src_pitch, int dst_pitch, int cpp); 464 465 /* Flags for stats.boxes 466 */ 467 #define RADEON_BOX_DMA_IDLE 0x1 468 #define RADEON_BOX_RING_FULL 0x2 469 #define RADEON_BOX_FLIP 0x4 470 #define RADEON_BOX_WAIT_IDLE 0x8 471 #define RADEON_BOX_TEXTURE_LOAD 0x10 472 473 /* Register definitions, register access macros and drmAddMap constants 474 * for Radeon kernel driver. 475 */ 476 #define RADEON_MM_INDEX 0x0000 477 #define RADEON_MM_DATA 0x0004 478 479 #define RADEON_AGP_COMMAND 0x0f60 480 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 481 # define RADEON_AGP_ENABLE (1<<8) 482 #define RADEON_AUX_SCISSOR_CNTL 0x26f0 483 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 484 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 485 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 486 # define RADEON_SCISSOR_0_ENABLE (1 << 28) 487 # define RADEON_SCISSOR_1_ENABLE (1 << 29) 488 # define RADEON_SCISSOR_2_ENABLE (1 << 30) 489 490 /* 491 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 492 * don't have an explicit bus mastering disable bit. It's handled 493 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 494 * handling, not bus mastering itself. 495 */ 496 #define RADEON_BUS_CNTL 0x0030 497 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 498 # define RADEON_BUS_MASTER_DIS (1 << 6) 499 /* rs600/rs690/rs740 */ 500 # define RS600_BUS_MASTER_DIS (1 << 14) 501 # define RS600_MSI_REARM (1 << 20) 502 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 503 504 #define RADEON_BUS_CNTL1 0x0034 505 # define RADEON_PMI_BM_DIS (1 << 2) 506 # define RADEON_PMI_INT_DIS (1 << 3) 507 508 #define RV370_BUS_CNTL 0x004c 509 # define RV370_PMI_BM_DIS (1 << 5) 510 # define RV370_PMI_INT_DIS (1 << 6) 511 512 #define RADEON_MSI_REARM_EN 0x0160 513 /* rv370/rv380, rv410, r423/r430/r480, r5xx */ 514 # define RV370_MSI_REARM_EN (1 << 0) 515 516 #define RADEON_CLOCK_CNTL_DATA 0x000c 517 # define RADEON_PLL_WR_EN (1 << 7) 518 #define RADEON_CLOCK_CNTL_INDEX 0x0008 519 #define RADEON_CONFIG_APER_SIZE 0x0108 520 #define RADEON_CONFIG_MEMSIZE 0x00f8 521 #define RADEON_CRTC_OFFSET 0x0224 522 #define RADEON_CRTC_OFFSET_CNTL 0x0228 523 # define RADEON_CRTC_TILE_EN (1 << 15) 524 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 525 #define RADEON_CRTC2_OFFSET 0x0324 526 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 527 528 #define RADEON_PCIE_INDEX 0x0030 529 #define RADEON_PCIE_DATA 0x0034 530 #define RADEON_PCIE_TX_GART_CNTL 0x10 531 # define RADEON_PCIE_TX_GART_EN (1 << 0) 532 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 533 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 534 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 535 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 536 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 537 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 538 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 539 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 540 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 541 #define RADEON_PCIE_TX_GART_BASE 0x13 542 #define RADEON_PCIE_TX_GART_START_LO 0x14 543 #define RADEON_PCIE_TX_GART_START_HI 0x15 544 #define RADEON_PCIE_TX_GART_END_LO 0x16 545 #define RADEON_PCIE_TX_GART_END_HI 0x17 546 547 #define RS480_NB_MC_INDEX 0x168 548 # define RS480_NB_MC_IND_WR_EN (1 << 8) 549 #define RS480_NB_MC_DATA 0x16c 550 551 #define RS690_MC_INDEX 0x78 552 # define RS690_MC_INDEX_MASK 0x1ff 553 # define RS690_MC_INDEX_WR_EN (1 << 9) 554 # define RS690_MC_INDEX_WR_ACK 0x7f 555 #define RS690_MC_DATA 0x7c 556 557 /* MC indirect registers */ 558 #define RS480_MC_MISC_CNTL 0x18 559 # define RS480_DISABLE_GTW (1 << 1) 560 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 561 # define RS480_GART_INDEX_REG_EN (1 << 12) 562 # define RS690_BLOCK_GFX_D3_EN (1 << 14) 563 #define RS480_K8_FB_LOCATION 0x1e 564 #define RS480_GART_FEATURE_ID 0x2b 565 # define RS480_HANG_EN (1 << 11) 566 # define RS480_TLB_ENABLE (1 << 18) 567 # define RS480_P2P_ENABLE (1 << 19) 568 # define RS480_GTW_LAC_EN (1 << 25) 569 # define RS480_2LEVEL_GART (0 << 30) 570 # define RS480_1LEVEL_GART (1 << 30) 571 # define RS480_PDC_EN (1 << 31) 572 #define RS480_GART_BASE 0x2c 573 #define RS480_GART_CACHE_CNTRL 0x2e 574 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 575 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 576 # define RS480_GART_EN (1 << 0) 577 # define RS480_VA_SIZE_32MB (0 << 1) 578 # define RS480_VA_SIZE_64MB (1 << 1) 579 # define RS480_VA_SIZE_128MB (2 << 1) 580 # define RS480_VA_SIZE_256MB (3 << 1) 581 # define RS480_VA_SIZE_512MB (4 << 1) 582 # define RS480_VA_SIZE_1GB (5 << 1) 583 # define RS480_VA_SIZE_2GB (6 << 1) 584 #define RS480_AGP_MODE_CNTL 0x39 585 # define RS480_POST_GART_Q_SIZE (1 << 18) 586 # define RS480_NONGART_SNOOP (1 << 19) 587 # define RS480_AGP_RD_BUF_SIZE (1 << 20) 588 # define RS480_REQ_TYPE_SNOOP_SHIFT 22 589 # define RS480_REQ_TYPE_SNOOP_MASK 0x3 590 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 591 #define RS480_MC_MISC_UMA_CNTL 0x5f 592 #define RS480_MC_MCLK_CNTL 0x7a 593 #define RS480_MC_UMA_DUALCH_CNTL 0x86 594 595 #define RS690_MC_FB_LOCATION 0x100 596 #define RS690_MC_AGP_LOCATION 0x101 597 #define RS690_MC_AGP_BASE 0x102 598 #define RS690_MC_AGP_BASE_2 0x103 599 600 #define RS600_MC_INDEX 0x70 601 # define RS600_MC_ADDR_MASK 0xffff 602 # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 603 # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 604 # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 605 # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 606 # define RS600_MC_IND_AIC_RBS (1 << 20) 607 # define RS600_MC_IND_CITF_ARB0 (1 << 21) 608 # define RS600_MC_IND_CITF_ARB1 (1 << 22) 609 # define RS600_MC_IND_WR_EN (1 << 23) 610 #define RS600_MC_DATA 0x74 611 612 #define RS600_MC_STATUS 0x0 613 # define RS600_MC_IDLE (1 << 1) 614 #define RS600_MC_FB_LOCATION 0x4 615 #define RS600_MC_AGP_LOCATION 0x5 616 #define RS600_AGP_BASE 0x6 617 #define RS600_AGP_BASE_2 0x7 618 #define RS600_MC_CNTL1 0x9 619 # define RS600_ENABLE_PAGE_TABLES (1 << 26) 620 #define RS600_MC_PT0_CNTL 0x100 621 # define RS600_ENABLE_PT (1 << 0) 622 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 623 # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 624 # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 625 # define RS600_INVALIDATE_L2_CACHE (1 << 29) 626 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 627 # define RS600_ENABLE_PAGE_TABLE (1 << 0) 628 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 629 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 630 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 631 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 632 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 633 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 634 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 635 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c 636 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 637 # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 638 # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 639 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 640 # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 641 # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 642 # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 643 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 644 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 645 # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 646 # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 647 # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 648 # define RS600_INVALIDATE_L1_TLB (1 << 20) 649 650 #define R520_MC_IND_INDEX 0x70 651 #define R520_MC_IND_WR_EN (1 << 24) 652 #define R520_MC_IND_DATA 0x74 653 654 #define RV515_MC_FB_LOCATION 0x01 655 #define RV515_MC_AGP_LOCATION 0x02 656 #define RV515_MC_AGP_BASE 0x03 657 #define RV515_MC_AGP_BASE_2 0x04 658 659 #define R520_MC_FB_LOCATION 0x04 660 #define R520_MC_AGP_LOCATION 0x05 661 #define R520_MC_AGP_BASE 0x06 662 #define R520_MC_AGP_BASE_2 0x07 663 664 #define RADEON_MPP_TB_CONFIG 0x01c0 665 #define RADEON_MEM_CNTL 0x0140 666 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 667 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 668 #define RS480_AGP_BASE_2 0x0164 669 #define RADEON_AGP_BASE 0x0170 670 671 /* pipe config regs */ 672 #define R400_GB_PIPE_SELECT 0x402c 673 #define RV530_GB_PIPE_SELECT2 0x4124 674 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 675 #define R300_GB_TILE_CONFIG 0x4018 676 # define R300_ENABLE_TILING (1 << 0) 677 # define R300_PIPE_COUNT_RV350 (0 << 1) 678 # define R300_PIPE_COUNT_R300 (3 << 1) 679 # define R300_PIPE_COUNT_R420_3P (6 << 1) 680 # define R300_PIPE_COUNT_R420 (7 << 1) 681 # define R300_TILE_SIZE_8 (0 << 4) 682 # define R300_TILE_SIZE_16 (1 << 4) 683 # define R300_TILE_SIZE_32 (2 << 4) 684 # define R300_SUBPIXEL_1_12 (0 << 16) 685 # define R300_SUBPIXEL_1_16 (1 << 16) 686 #define R300_DST_PIPE_CONFIG 0x170c 687 # define R300_PIPE_AUTO_CONFIG (1 << 31) 688 #define R300_RB2D_DSTCACHE_MODE 0x3428 689 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 690 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 691 692 #define RADEON_RB3D_COLOROFFSET 0x1c40 693 #define RADEON_RB3D_COLORPITCH 0x1c48 694 695 #define RADEON_SRC_X_Y 0x1590 696 697 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 698 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 699 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 700 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 701 # define RADEON_GMC_BRUSH_NONE (15 << 4) 702 # define RADEON_GMC_DST_16BPP (4 << 8) 703 # define RADEON_GMC_DST_24BPP (5 << 8) 704 # define RADEON_GMC_DST_32BPP (6 << 8) 705 # define RADEON_GMC_DST_DATATYPE_SHIFT 8 706 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 707 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 708 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 709 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 710 # define RADEON_GMC_WR_MSK_DIS (1 << 30) 711 # define RADEON_ROP3_S 0x00cc0000 712 # define RADEON_ROP3_P 0x00f00000 713 #define RADEON_DP_WRITE_MASK 0x16cc 714 #define RADEON_SRC_PITCH_OFFSET 0x1428 715 #define RADEON_DST_PITCH_OFFSET 0x142c 716 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 717 # define RADEON_DST_TILE_LINEAR (0 << 30) 718 # define RADEON_DST_TILE_MACRO (1 << 30) 719 # define RADEON_DST_TILE_MICRO (2 << 30) 720 # define RADEON_DST_TILE_BOTH (3 << 30) 721 722 #define RADEON_SCRATCH_REG0 0x15e0 723 #define RADEON_SCRATCH_REG1 0x15e4 724 #define RADEON_SCRATCH_REG2 0x15e8 725 #define RADEON_SCRATCH_REG3 0x15ec 726 #define RADEON_SCRATCH_REG4 0x15f0 727 #define RADEON_SCRATCH_REG5 0x15f4 728 #define RADEON_SCRATCH_UMSK 0x0770 729 #define RADEON_SCRATCH_ADDR 0x0774 730 731 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 732 733 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 734 735 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 736 737 #define R600_SCRATCH_REG0 0x8500 738 #define R600_SCRATCH_REG1 0x8504 739 #define R600_SCRATCH_REG2 0x8508 740 #define R600_SCRATCH_REG3 0x850c 741 #define R600_SCRATCH_REG4 0x8510 742 #define R600_SCRATCH_REG5 0x8514 743 #define R600_SCRATCH_REG6 0x8518 744 #define R600_SCRATCH_REG7 0x851c 745 #define R600_SCRATCH_UMSK 0x8540 746 #define R600_SCRATCH_ADDR 0x8544 747 748 #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 749 750 #define RADEON_GEN_INT_CNTL 0x0040 751 # define RADEON_CRTC_VBLANK_MASK (1 << 0) 752 # define RADEON_CRTC2_VBLANK_MASK (1 << 9) 753 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 754 # define RADEON_SW_INT_ENABLE (1 << 25) 755 756 #define RADEON_GEN_INT_STATUS 0x0044 757 # define RADEON_CRTC_VBLANK_STAT (1 << 0) 758 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 759 # define RADEON_CRTC2_VBLANK_STAT (1 << 9) 760 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 761 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 762 # define RADEON_SW_INT_TEST (1 << 25) 763 # define RADEON_SW_INT_TEST_ACK (1 << 25) 764 # define RADEON_SW_INT_FIRE (1 << 26) 765 # define R500_DISPLAY_INT_STATUS (1 << 0) 766 767 #define RADEON_HOST_PATH_CNTL 0x0130 768 # define RADEON_HDP_SOFT_RESET (1 << 26) 769 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 770 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 771 772 #define RADEON_ISYNC_CNTL 0x1724 773 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 774 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 775 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 776 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 777 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 778 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 779 780 #define RADEON_RBBM_GUICNTL 0x172c 781 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 782 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 783 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 784 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 785 786 #define RADEON_MC_AGP_LOCATION 0x014c 787 #define RADEON_MC_FB_LOCATION 0x0148 788 #define RADEON_MCLK_CNTL 0x0012 789 # define RADEON_FORCEON_MCLKA (1 << 16) 790 # define RADEON_FORCEON_MCLKB (1 << 17) 791 # define RADEON_FORCEON_YCLKA (1 << 18) 792 # define RADEON_FORCEON_YCLKB (1 << 19) 793 # define RADEON_FORCEON_MC (1 << 20) 794 # define RADEON_FORCEON_AIC (1 << 21) 795 796 #define RADEON_PP_BORDER_COLOR_0 0x1d40 797 #define RADEON_PP_BORDER_COLOR_1 0x1d44 798 #define RADEON_PP_BORDER_COLOR_2 0x1d48 799 #define RADEON_PP_CNTL 0x1c38 800 # define RADEON_SCISSOR_ENABLE (1 << 1) 801 #define RADEON_PP_LUM_MATRIX 0x1d00 802 #define RADEON_PP_MISC 0x1c14 803 #define RADEON_PP_ROT_MATRIX_0 0x1d58 804 #define RADEON_PP_TXFILTER_0 0x1c54 805 #define RADEON_PP_TXOFFSET_0 0x1c5c 806 #define RADEON_PP_TXFILTER_1 0x1c6c 807 #define RADEON_PP_TXFILTER_2 0x1c84 808 809 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 810 #define R300_DSTCACHE_CTLSTAT 0x1714 811 # define R300_RB2D_DC_FLUSH (3 << 0) 812 # define R300_RB2D_DC_FREE (3 << 2) 813 # define R300_RB2D_DC_FLUSH_ALL 0xf 814 # define R300_RB2D_DC_BUSY (1 << 31) 815 #define RADEON_RB3D_CNTL 0x1c3c 816 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 817 # define RADEON_PLANE_MASK_ENABLE (1 << 1) 818 # define RADEON_DITHER_ENABLE (1 << 2) 819 # define RADEON_ROUND_ENABLE (1 << 3) 820 # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 821 # define RADEON_DITHER_INIT (1 << 5) 822 # define RADEON_ROP_ENABLE (1 << 6) 823 # define RADEON_STENCIL_ENABLE (1 << 7) 824 # define RADEON_Z_ENABLE (1 << 8) 825 # define RADEON_ZBLOCK16 (1 << 15) 826 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 827 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 828 #define RADEON_RB3D_DEPTHPITCH 0x1c28 829 #define RADEON_RB3D_PLANEMASK 0x1d84 830 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 831 #define RADEON_RB3D_ZCACHE_MODE 0x3250 832 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 833 # define RADEON_RB3D_ZC_FLUSH (1 << 0) 834 # define RADEON_RB3D_ZC_FREE (1 << 2) 835 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 836 # define RADEON_RB3D_ZC_BUSY (1 << 31) 837 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 838 # define R300_ZC_FLUSH (1 << 0) 839 # define R300_ZC_FREE (1 << 1) 840 # define R300_ZC_BUSY (1 << 31) 841 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 842 # define RADEON_RB3D_DC_FLUSH (3 << 0) 843 # define RADEON_RB3D_DC_FREE (3 << 2) 844 # define RADEON_RB3D_DC_FLUSH_ALL 0xf 845 # define RADEON_RB3D_DC_BUSY (1 << 31) 846 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 847 # define R300_RB3D_DC_FLUSH (2 << 0) 848 # define R300_RB3D_DC_FREE (2 << 2) 849 # define R300_RB3D_DC_FINISH (1 << 4) 850 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 851 # define RADEON_Z_TEST_MASK (7 << 4) 852 # define RADEON_Z_TEST_ALWAYS (7 << 4) 853 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 854 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 855 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 856 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 857 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 858 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 859 # define RADEON_FORCE_Z_DIRTY (1 << 29) 860 # define RADEON_Z_WRITE_ENABLE (1 << 30) 861 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 862 #define RADEON_RBBM_SOFT_RESET 0x00f0 863 # define RADEON_SOFT_RESET_CP (1 << 0) 864 # define RADEON_SOFT_RESET_HI (1 << 1) 865 # define RADEON_SOFT_RESET_SE (1 << 2) 866 # define RADEON_SOFT_RESET_RE (1 << 3) 867 # define RADEON_SOFT_RESET_PP (1 << 4) 868 # define RADEON_SOFT_RESET_E2 (1 << 5) 869 # define RADEON_SOFT_RESET_RB (1 << 6) 870 # define RADEON_SOFT_RESET_HDP (1 << 7) 871 /* 872 * 6:0 Available slots in the FIFO 873 * 8 Host Interface active 874 * 9 CP request active 875 * 10 FIFO request active 876 * 11 Host Interface retry active 877 * 12 CP retry active 878 * 13 FIFO retry active 879 * 14 FIFO pipeline busy 880 * 15 Event engine busy 881 * 16 CP command stream busy 882 * 17 2D engine busy 883 * 18 2D portion of render backend busy 884 * 20 3D setup engine busy 885 * 26 GA engine busy 886 * 27 CBA 2D engine busy 887 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 888 * command stream queue not empty or Ring Buffer not empty 889 */ 890 #define RADEON_RBBM_STATUS 0x0e40 891 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 892 /* #define RADEON_RBBM_STATUS 0x1740 */ 893 /* bits 6:0 are dword slots available in the cmd fifo */ 894 # define RADEON_RBBM_FIFOCNT_MASK 0x007f 895 # define RADEON_HIRQ_ON_RBB (1 << 8) 896 # define RADEON_CPRQ_ON_RBB (1 << 9) 897 # define RADEON_CFRQ_ON_RBB (1 << 10) 898 # define RADEON_HIRQ_IN_RTBUF (1 << 11) 899 # define RADEON_CPRQ_IN_RTBUF (1 << 12) 900 # define RADEON_CFRQ_IN_RTBUF (1 << 13) 901 # define RADEON_PIPE_BUSY (1 << 14) 902 # define RADEON_ENG_EV_BUSY (1 << 15) 903 # define RADEON_CP_CMDSTRM_BUSY (1 << 16) 904 # define RADEON_E2_BUSY (1 << 17) 905 # define RADEON_RB2D_BUSY (1 << 18) 906 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 907 # define RADEON_VAP_BUSY (1 << 20) 908 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 909 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 910 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 911 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 912 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 913 # define RADEON_GA_BUSY (1 << 26) 914 # define RADEON_CBA2D_BUSY (1 << 27) 915 # define RADEON_RBBM_ACTIVE (1 << 31) 916 #define RADEON_RE_LINE_PATTERN 0x1cd0 917 #define RADEON_RE_MISC 0x26c4 918 #define RADEON_RE_TOP_LEFT 0x26c0 919 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 920 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 921 #define RADEON_RE_STIPPLE_DATA 0x1ccc 922 923 #define RADEON_SCISSOR_TL_0 0x1cd8 924 #define RADEON_SCISSOR_BR_0 0x1cdc 925 #define RADEON_SCISSOR_TL_1 0x1ce0 926 #define RADEON_SCISSOR_BR_1 0x1ce4 927 #define RADEON_SCISSOR_TL_2 0x1ce8 928 #define RADEON_SCISSOR_BR_2 0x1cec 929 #define RADEON_SE_COORD_FMT 0x1c50 930 #define RADEON_SE_CNTL 0x1c4c 931 # define RADEON_FFACE_CULL_CW (0 << 0) 932 # define RADEON_BFACE_SOLID (3 << 1) 933 # define RADEON_FFACE_SOLID (3 << 3) 934 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 935 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 936 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 937 # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 938 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 939 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 940 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 941 # define RADEON_FOG_SHADE_FLAT (1 << 14) 942 # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 943 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 944 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 945 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 946 # define RADEON_ROUND_MODE_TRUNC (0 << 28) 947 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 948 #define RADEON_SE_CNTL_STATUS 0x2140 949 #define RADEON_SE_LINE_WIDTH 0x1db8 950 #define RADEON_SE_VPORT_XSCALE 0x1d98 951 #define RADEON_SE_ZBIAS_FACTOR 0x1db0 952 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 953 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 954 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 955 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 956 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 957 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 958 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 959 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 960 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 961 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 962 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc 963 #define RADEON_SURFACE_CNTL 0x0b00 964 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 965 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 966 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 967 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 968 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 969 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 970 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 971 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 972 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 973 #define RADEON_SURFACE0_INFO 0x0b0c 974 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 975 # define RADEON_SURF_TILE_MODE_MASK (3 << 16) 976 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 977 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 978 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 979 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 980 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 981 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 982 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 983 #define RADEON_SURFACE1_INFO 0x0b1c 984 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 985 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 986 #define RADEON_SURFACE2_INFO 0x0b2c 987 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 988 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 989 #define RADEON_SURFACE3_INFO 0x0b3c 990 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 991 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 992 #define RADEON_SURFACE4_INFO 0x0b4c 993 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 994 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 995 #define RADEON_SURFACE5_INFO 0x0b5c 996 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 997 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 998 #define RADEON_SURFACE6_INFO 0x0b6c 999 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1000 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1001 #define RADEON_SURFACE7_INFO 0x0b7c 1002 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1003 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1004 #define RADEON_SW_SEMAPHORE 0x013c 1005 1006 #define RADEON_WAIT_UNTIL 0x1720 1007 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1008 # define RADEON_WAIT_2D_IDLE (1 << 14) 1009 # define RADEON_WAIT_3D_IDLE (1 << 15) 1010 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1011 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1012 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1013 1014 #define RADEON_RB3D_ZMASKOFFSET 0x3234 1015 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1016 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1017 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1018 1019 /* CP registers */ 1020 #define RADEON_CP_ME_RAM_ADDR 0x07d4 1021 #define RADEON_CP_ME_RAM_RADDR 0x07d8 1022 #define RADEON_CP_ME_RAM_DATAH 0x07dc 1023 #define RADEON_CP_ME_RAM_DATAL 0x07e0 1024 1025 #define RADEON_CP_RB_BASE 0x0700 1026 #define RADEON_CP_RB_CNTL 0x0704 1027 # define RADEON_BUF_SWAP_32BIT (2 << 16) 1028 # define RADEON_RB_NO_UPDATE (1 << 27) 1029 # define RADEON_RB_RPTR_WR_ENA (1 << 31) 1030 #define RADEON_CP_RB_RPTR_ADDR 0x070c 1031 #define RADEON_CP_RB_RPTR 0x0710 1032 #define RADEON_CP_RB_WPTR 0x0714 1033 1034 #define RADEON_CP_RB_WPTR_DELAY 0x0718 1035 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 1036 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1037 1038 #define RADEON_CP_IB_BASE 0x0738 1039 1040 #define RADEON_CP_CSQ_CNTL 0x0740 1041 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1042 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1043 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1044 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1045 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1046 # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1047 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1048 1049 #define R300_CP_RESYNC_ADDR 0x0778 1050 #define R300_CP_RESYNC_DATA 0x077c 1051 1052 #define RADEON_AIC_CNTL 0x01d0 1053 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1054 # define RS400_MSI_REARM (1 << 3) 1055 #define RADEON_AIC_STAT 0x01d4 1056 #define RADEON_AIC_PT_BASE 0x01d8 1057 #define RADEON_AIC_LO_ADDR 0x01dc 1058 #define RADEON_AIC_HI_ADDR 0x01e0 1059 #define RADEON_AIC_TLB_ADDR 0x01e4 1060 #define RADEON_AIC_TLB_DATA 0x01e8 1061 1062 /* CP command packets */ 1063 #define RADEON_CP_PACKET0 0x00000000 1064 # define RADEON_ONE_REG_WR (1 << 15) 1065 #define RADEON_CP_PACKET1 0x40000000 1066 #define RADEON_CP_PACKET2 0x80000000 1067 #define RADEON_CP_PACKET3 0xC0000000 1068 # define RADEON_CP_NOP 0x00001000 1069 # define RADEON_CP_NEXT_CHAR 0x00001900 1070 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1071 # define RADEON_CP_SET_SCISSORS 0x00001E00 1072 /* GEN_INDX_PRIM is unsupported starting with R300 */ 1073 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1074 # define RADEON_WAIT_FOR_IDLE 0x00002600 1075 # define RADEON_3D_DRAW_VBUF 0x00002800 1076 # define RADEON_3D_DRAW_IMMD 0x00002900 1077 # define RADEON_3D_DRAW_INDX 0x00002A00 1078 # define RADEON_CP_LOAD_PALETTE 0x00002C00 1079 # define RADEON_3D_LOAD_VBPNTR 0x00002F00 1080 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1081 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1082 # define RADEON_3D_CLEAR_ZMASK 0x00003200 1083 # define RADEON_CP_INDX_BUFFER 0x00003300 1084 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1085 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1086 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1087 # define RADEON_3D_CLEAR_HIZ 0x00003700 1088 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1089 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1090 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 1091 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1092 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1093 1094 # define R600_IT_INDIRECT_BUFFER_END 0x00001700 1095 # define R600_IT_SET_PREDICATION 0x00002000 1096 # define R600_IT_REG_RMW 0x00002100 1097 # define R600_IT_COND_EXEC 0x00002200 1098 # define R600_IT_PRED_EXEC 0x00002300 1099 # define R600_IT_START_3D_CMDBUF 0x00002400 1100 # define R600_IT_DRAW_INDEX_2 0x00002700 1101 # define R600_IT_CONTEXT_CONTROL 0x00002800 1102 # define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 1103 # define R600_IT_INDEX_TYPE 0x00002A00 1104 # define R600_IT_DRAW_INDEX 0x00002B00 1105 # define R600_IT_DRAW_INDEX_AUTO 0x00002D00 1106 # define R600_IT_DRAW_INDEX_IMMD 0x00002E00 1107 # define R600_IT_NUM_INSTANCES 0x00002F00 1108 # define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 1109 # define R600_IT_INDIRECT_BUFFER_MP 0x00003800 1110 # define R600_IT_MEM_SEMAPHORE 0x00003900 1111 # define R600_IT_MPEG_INDEX 0x00003A00 1112 # define R600_IT_WAIT_REG_MEM 0x00003C00 1113 # define R600_IT_MEM_WRITE 0x00003D00 1114 # define R600_IT_INDIRECT_BUFFER 0x00003200 1115 # define R600_IT_SURFACE_SYNC 0x00004300 1116 # define R600_CB0_DEST_BASE_ENA (1 << 6) 1117 # define R600_TC_ACTION_ENA (1 << 23) 1118 # define R600_VC_ACTION_ENA (1 << 24) 1119 # define R600_CB_ACTION_ENA (1 << 25) 1120 # define R600_DB_ACTION_ENA (1 << 26) 1121 # define R600_SH_ACTION_ENA (1 << 27) 1122 # define R600_SMX_ACTION_ENA (1 << 28) 1123 # define R600_IT_ME_INITIALIZE 0x00004400 1124 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1125 # define R600_IT_COND_WRITE 0x00004500 1126 # define R600_IT_EVENT_WRITE 0x00004600 1127 # define R600_IT_EVENT_WRITE_EOP 0x00004700 1128 # define R600_IT_ONE_REG_WRITE 0x00005700 1129 # define R600_IT_SET_CONFIG_REG 0x00006800 1130 # define R600_SET_CONFIG_REG_OFFSET 0x00008000 1131 # define R600_SET_CONFIG_REG_END 0x0000ac00 1132 # define R600_IT_SET_CONTEXT_REG 0x00006900 1133 # define R600_SET_CONTEXT_REG_OFFSET 0x00028000 1134 # define R600_SET_CONTEXT_REG_END 0x00029000 1135 # define R600_IT_SET_ALU_CONST 0x00006A00 1136 # define R600_SET_ALU_CONST_OFFSET 0x00030000 1137 # define R600_SET_ALU_CONST_END 0x00032000 1138 # define R600_IT_SET_BOOL_CONST 0x00006B00 1139 # define R600_SET_BOOL_CONST_OFFSET 0x0003e380 1140 # define R600_SET_BOOL_CONST_END 0x00040000 1141 # define R600_IT_SET_LOOP_CONST 0x00006C00 1142 # define R600_SET_LOOP_CONST_OFFSET 0x0003e200 1143 # define R600_SET_LOOP_CONST_END 0x0003e380 1144 # define R600_IT_SET_RESOURCE 0x00006D00 1145 # define R600_SET_RESOURCE_OFFSET 0x00038000 1146 # define R600_SET_RESOURCE_END 0x0003c000 1147 # define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 1148 # define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 1149 # define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 1150 # define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 1151 # define R600_IT_SET_SAMPLER 0x00006E00 1152 # define R600_SET_SAMPLER_OFFSET 0x0003c000 1153 # define R600_SET_SAMPLER_END 0x0003cff0 1154 # define R600_IT_SET_CTL_CONST 0x00006F00 1155 # define R600_SET_CTL_CONST_OFFSET 0x0003cff0 1156 # define R600_SET_CTL_CONST_END 0x0003e200 1157 # define R600_IT_SURFACE_BASE_UPDATE 0x00007300 1158 1159 #define RADEON_CP_PACKET_MASK 0xC0000000 1160 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1161 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1162 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1163 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1164 1165 #define RADEON_VTX_Z_PRESENT (1 << 31) 1166 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1167 1168 #define RADEON_PRIM_TYPE_NONE (0 << 0) 1169 #define RADEON_PRIM_TYPE_POINT (1 << 0) 1170 #define RADEON_PRIM_TYPE_LINE (2 << 0) 1171 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1172 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1173 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1174 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1175 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1176 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1177 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1178 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1179 #define RADEON_PRIM_TYPE_MASK 0xf 1180 #define RADEON_PRIM_WALK_IND (1 << 4) 1181 #define RADEON_PRIM_WALK_LIST (2 << 4) 1182 #define RADEON_PRIM_WALK_RING (3 << 4) 1183 #define RADEON_COLOR_ORDER_BGRA (0 << 6) 1184 #define RADEON_COLOR_ORDER_RGBA (1 << 6) 1185 #define RADEON_MAOS_ENABLE (1 << 7) 1186 #define RADEON_VTX_FMT_R128_MODE (0 << 8) 1187 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1188 #define RADEON_NUM_VERTICES_SHIFT 16 1189 1190 #define RADEON_COLOR_FORMAT_CI8 2 1191 #define RADEON_COLOR_FORMAT_ARGB1555 3 1192 #define RADEON_COLOR_FORMAT_RGB565 4 1193 #define RADEON_COLOR_FORMAT_ARGB8888 6 1194 #define RADEON_COLOR_FORMAT_RGB332 7 1195 #define RADEON_COLOR_FORMAT_RGB8 9 1196 #define RADEON_COLOR_FORMAT_ARGB4444 15 1197 1198 #define RADEON_TXFORMAT_I8 0 1199 #define RADEON_TXFORMAT_AI88 1 1200 #define RADEON_TXFORMAT_RGB332 2 1201 #define RADEON_TXFORMAT_ARGB1555 3 1202 #define RADEON_TXFORMAT_RGB565 4 1203 #define RADEON_TXFORMAT_ARGB4444 5 1204 #define RADEON_TXFORMAT_ARGB8888 6 1205 #define RADEON_TXFORMAT_RGBA8888 7 1206 #define RADEON_TXFORMAT_Y8 8 1207 #define RADEON_TXFORMAT_VYUY422 10 1208 #define RADEON_TXFORMAT_YVYU422 11 1209 #define RADEON_TXFORMAT_DXT1 12 1210 #define RADEON_TXFORMAT_DXT23 14 1211 #define RADEON_TXFORMAT_DXT45 15 1212 1213 #define R200_PP_TXCBLEND_0 0x2f00 1214 #define R200_PP_TXCBLEND_1 0x2f10 1215 #define R200_PP_TXCBLEND_2 0x2f20 1216 #define R200_PP_TXCBLEND_3 0x2f30 1217 #define R200_PP_TXCBLEND_4 0x2f40 1218 #define R200_PP_TXCBLEND_5 0x2f50 1219 #define R200_PP_TXCBLEND_6 0x2f60 1220 #define R200_PP_TXCBLEND_7 0x2f70 1221 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1222 #define R200_PP_TFACTOR_0 0x2ee0 1223 #define R200_SE_VTX_FMT_0 0x2088 1224 #define R200_SE_VAP_CNTL 0x2080 1225 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 1226 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1227 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1228 #define R200_PP_TXFILTER_5 0x2ca0 1229 #define R200_PP_TXFILTER_4 0x2c80 1230 #define R200_PP_TXFILTER_3 0x2c60 1231 #define R200_PP_TXFILTER_2 0x2c40 1232 #define R200_PP_TXFILTER_1 0x2c20 1233 #define R200_PP_TXFILTER_0 0x2c00 1234 #define R200_PP_TXOFFSET_5 0x2d78 1235 #define R200_PP_TXOFFSET_4 0x2d60 1236 #define R200_PP_TXOFFSET_3 0x2d48 1237 #define R200_PP_TXOFFSET_2 0x2d30 1238 #define R200_PP_TXOFFSET_1 0x2d18 1239 #define R200_PP_TXOFFSET_0 0x2d00 1240 1241 #define R200_PP_CUBIC_FACES_0 0x2c18 1242 #define R200_PP_CUBIC_FACES_1 0x2c38 1243 #define R200_PP_CUBIC_FACES_2 0x2c58 1244 #define R200_PP_CUBIC_FACES_3 0x2c78 1245 #define R200_PP_CUBIC_FACES_4 0x2c98 1246 #define R200_PP_CUBIC_FACES_5 0x2cb8 1247 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1248 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1249 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1250 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1251 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1252 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1253 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1254 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1255 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1256 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1257 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1258 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1259 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1260 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1261 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1262 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1263 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1264 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1265 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1266 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1267 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1268 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1269 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1270 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1271 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1272 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1273 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1274 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1275 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1276 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1277 1278 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1279 #define R200_SE_VTE_CNTL 0x20b0 1280 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1281 #define R200_PP_TAM_DEBUG3 0x2d9c 1282 #define R200_PP_CNTL_X 0x2cc4 1283 #define R200_SE_VAP_CNTL_STATUS 0x2140 1284 #define R200_RE_SCISSOR_TL_0 0x1cd8 1285 #define R200_RE_SCISSOR_TL_1 0x1ce0 1286 #define R200_RE_SCISSOR_TL_2 0x1ce8 1287 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1288 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1289 #define R200_SE_VTX_STATE_CNTL 0x2180 1290 #define R200_RE_POINTSIZE 0x2648 1291 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1292 1293 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1294 #define RADEON_PP_TEX_SIZE_1 0x1d0c 1295 #define RADEON_PP_TEX_SIZE_2 0x1d14 1296 1297 #define RADEON_PP_CUBIC_FACES_0 0x1d24 1298 #define RADEON_PP_CUBIC_FACES_1 0x1d28 1299 #define RADEON_PP_CUBIC_FACES_2 0x1d2c 1300 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1301 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1302 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1303 1304 #define RADEON_SE_TCL_STATE_FLUSH 0x2284 1305 1306 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1307 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1308 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1309 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1310 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1311 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1312 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1313 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1314 #define R200_3D_DRAW_IMMD_2 0xC0003500 1315 #define R200_SE_VTX_FMT_1 0x208c 1316 #define R200_RE_CNTL 0x1c50 1317 1318 #define R200_RB3D_BLENDCOLOR 0x3218 1319 1320 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1321 1322 #define R200_PP_TRI_PERF 0x2cf8 1323 1324 #define R200_PP_AFS_0 0x2f80 1325 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1326 1327 #define R200_VAP_PVS_CNTL_1 0x22D0 1328 1329 #define RADEON_CRTC_CRNT_FRAME 0x0214 1330 #define RADEON_CRTC2_CRNT_FRAME 0x0314 1331 1332 #define R500_D1CRTC_STATUS 0x609c 1333 #define R500_D2CRTC_STATUS 0x689c 1334 #define R500_CRTC_V_BLANK (1<<0) 1335 1336 #define R500_D1CRTC_FRAME_COUNT 0x60a4 1337 #define R500_D2CRTC_FRAME_COUNT 0x68a4 1338 1339 #define R500_D1MODE_V_COUNTER 0x6530 1340 #define R500_D2MODE_V_COUNTER 0x6d30 1341 1342 #define R500_D1MODE_VBLANK_STATUS 0x6534 1343 #define R500_D2MODE_VBLANK_STATUS 0x6d34 1344 #define R500_VBLANK_OCCURED (1<<0) 1345 #define R500_VBLANK_ACK (1<<4) 1346 #define R500_VBLANK_STAT (1<<12) 1347 #define R500_VBLANK_INT (1<<16) 1348 1349 #define R500_DxMODE_INT_MASK 0x6540 1350 #define R500_D1MODE_INT_MASK (1<<0) 1351 #define R500_D2MODE_INT_MASK (1<<8) 1352 1353 #define R500_DISP_INTERRUPT_STATUS 0x7edc 1354 #define R500_D1_VBLANK_INTERRUPT (1 << 4) 1355 #define R500_D2_VBLANK_INTERRUPT (1 << 5) 1356 1357 /* R6xx/R7xx registers */ 1358 #define R600_MC_VM_FB_LOCATION 0x2180 1359 #define R600_MC_VM_AGP_TOP 0x2184 1360 #define R600_MC_VM_AGP_BOT 0x2188 1361 #define R600_MC_VM_AGP_BASE 0x218c 1362 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1363 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1364 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1365 1366 #define R700_MC_VM_FB_LOCATION 0x2024 1367 #define R700_MC_VM_AGP_TOP 0x2028 1368 #define R700_MC_VM_AGP_BOT 0x202c 1369 #define R700_MC_VM_AGP_BASE 0x2030 1370 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1371 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1372 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1373 1374 #define R600_MCD_RD_A_CNTL 0x219c 1375 #define R600_MCD_RD_B_CNTL 0x21a0 1376 1377 #define R600_MCD_WR_A_CNTL 0x21a4 1378 #define R600_MCD_WR_B_CNTL 0x21a8 1379 1380 #define R600_MCD_RD_SYS_CNTL 0x2200 1381 #define R600_MCD_WR_SYS_CNTL 0x2214 1382 1383 #define R600_MCD_RD_GFX_CNTL 0x21fc 1384 #define R600_MCD_RD_HDP_CNTL 0x2204 1385 #define R600_MCD_RD_PDMA_CNTL 0x2208 1386 #define R600_MCD_RD_SEM_CNTL 0x220c 1387 #define R600_MCD_WR_GFX_CNTL 0x2210 1388 #define R600_MCD_WR_HDP_CNTL 0x2218 1389 #define R600_MCD_WR_PDMA_CNTL 0x221c 1390 #define R600_MCD_WR_SEM_CNTL 0x2220 1391 1392 # define R600_MCD_L1_TLB (1 << 0) 1393 # define R600_MCD_L1_FRAG_PROC (1 << 1) 1394 # define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1395 1396 # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1397 # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1398 # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1399 # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1400 # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1401 1402 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1403 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1404 1405 # define R600_MCD_SEMAPHORE_MODE (1 << 10) 1406 # define R600_MCD_WAIT_L2_QUERY (1 << 11) 1407 # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1408 # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1409 1410 #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1411 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1412 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1413 1414 #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1415 #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1416 #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1417 #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1418 1419 # define R700_ENABLE_L1_TLB (1 << 0) 1420 # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1421 # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1422 # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1423 # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1424 # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1425 1426 #define R700_MC_ARB_RAMCFG 0x2760 1427 # define R700_NOOFBANK_SHIFT 0 1428 # define R700_NOOFBANK_MASK 0x3 1429 # define R700_NOOFRANK_SHIFT 2 1430 # define R700_NOOFRANK_MASK 0x1 1431 # define R700_NOOFROWS_SHIFT 3 1432 # define R700_NOOFROWS_MASK 0x7 1433 # define R700_NOOFCOLS_SHIFT 6 1434 # define R700_NOOFCOLS_MASK 0x3 1435 # define R700_CHANSIZE_SHIFT 8 1436 # define R700_CHANSIZE_MASK 0x1 1437 # define R700_BURSTLENGTH_SHIFT 9 1438 # define R700_BURSTLENGTH_MASK 0x1 1439 #define R600_RAMCFG 0x2408 1440 # define R600_NOOFBANK_SHIFT 0 1441 # define R600_NOOFBANK_MASK 0x1 1442 # define R600_NOOFRANK_SHIFT 1 1443 # define R600_NOOFRANK_MASK 0x1 1444 # define R600_NOOFROWS_SHIFT 2 1445 # define R600_NOOFROWS_MASK 0x7 1446 # define R600_NOOFCOLS_SHIFT 5 1447 # define R600_NOOFCOLS_MASK 0x3 1448 # define R600_CHANSIZE_SHIFT 7 1449 # define R600_CHANSIZE_MASK 0x1 1450 # define R600_BURSTLENGTH_SHIFT 8 1451 # define R600_BURSTLENGTH_MASK 0x1 1452 1453 #define R600_VM_L2_CNTL 0x1400 1454 # define R600_VM_L2_CACHE_EN (1 << 0) 1455 # define R600_VM_L2_FRAG_PROC (1 << 1) 1456 # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1457 # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1458 # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1459 1460 #define R600_VM_L2_CNTL2 0x1404 1461 # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1462 # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1463 #define R600_VM_L2_CNTL3 0x1408 1464 # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1465 # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1466 # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1467 # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1468 # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1469 1470 #define R600_VM_L2_STATUS 0x140c 1471 1472 #define R600_VM_CONTEXT0_CNTL 0x1410 1473 # define R600_VM_ENABLE_CONTEXT (1 << 0) 1474 # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1475 1476 #define R600_VM_CONTEXT0_CNTL2 0x1430 1477 #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1478 #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1479 #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1480 #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1481 #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1482 #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1483 1484 #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1485 #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1486 #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1487 1488 #define R600_HDP_HOST_PATH_CNTL 0x2c00 1489 1490 #define R600_GRBM_CNTL 0x8000 1491 # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1492 1493 #define R600_GRBM_STATUS 0x8010 1494 # define R600_CMDFIFO_AVAIL_MASK 0x1f 1495 # define R700_CMDFIFO_AVAIL_MASK 0xf 1496 # define R600_GUI_ACTIVE (1 << 31) 1497 #define R600_GRBM_STATUS2 0x8014 1498 #define R600_GRBM_SOFT_RESET 0x8020 1499 # define R600_SOFT_RESET_CP (1 << 0) 1500 #define R600_WAIT_UNTIL 0x8040 1501 1502 #define R600_CP_SEM_WAIT_TIMER 0x85bc 1503 #define R600_CP_ME_CNTL 0x86d8 1504 # define R600_CP_ME_HALT (1 << 28) 1505 #define R600_CP_QUEUE_THRESHOLDS 0x8760 1506 # define R600_ROQ_IB1_START(x) ((x) << 0) 1507 # define R600_ROQ_IB2_START(x) ((x) << 8) 1508 #define R600_CP_MEQ_THRESHOLDS 0x8764 1509 # define R700_STQ_SPLIT(x) ((x) << 0) 1510 # define R600_MEQ_END(x) ((x) << 16) 1511 # define R600_ROQ_END(x) ((x) << 24) 1512 #define R600_CP_PERFMON_CNTL 0x87fc 1513 #define R600_CP_RB_BASE 0xc100 1514 #define R600_CP_RB_CNTL 0xc104 1515 # define R600_RB_BUFSZ(x) ((x) << 0) 1516 # define R600_RB_BLKSZ(x) ((x) << 8) 1517 # define R600_BUF_SWAP_32BIT (2 << 16) 1518 # define R600_RB_NO_UPDATE (1 << 27) 1519 # define R600_RB_RPTR_WR_ENA (1 << 31) 1520 #define R600_CP_RB_RPTR_WR 0xc108 1521 #define R600_CP_RB_RPTR_ADDR 0xc10c 1522 #define R600_CP_RB_RPTR_ADDR_HI 0xc110 1523 #define R600_CP_RB_WPTR 0xc114 1524 #define R600_CP_RB_WPTR_ADDR 0xc118 1525 #define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1526 #define R600_CP_RB_RPTR 0x8700 1527 #define R600_CP_RB_WPTR_DELAY 0x8704 1528 #define R600_CP_PFP_UCODE_ADDR 0xc150 1529 #define R600_CP_PFP_UCODE_DATA 0xc154 1530 #define R600_CP_ME_RAM_RADDR 0xc158 1531 #define R600_CP_ME_RAM_WADDR 0xc15c 1532 #define R600_CP_ME_RAM_DATA 0xc160 1533 #define R600_CP_DEBUG 0xc1fc 1534 1535 #define R600_PA_CL_ENHANCE 0x8a14 1536 # define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1537 # define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1538 #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1539 #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1540 #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1541 # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1542 # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1543 #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1544 #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1545 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1546 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1547 # define R600_S0_X(x) ((x) << 0) 1548 # define R600_S0_Y(x) ((x) << 4) 1549 # define R600_S1_X(x) ((x) << 8) 1550 # define R600_S1_Y(x) ((x) << 12) 1551 # define R600_S2_X(x) ((x) << 16) 1552 # define R600_S2_Y(x) ((x) << 20) 1553 # define R600_S3_X(x) ((x) << 24) 1554 # define R600_S3_Y(x) ((x) << 28) 1555 # define R600_S4_X(x) ((x) << 0) 1556 # define R600_S4_Y(x) ((x) << 4) 1557 # define R600_S5_X(x) ((x) << 8) 1558 # define R600_S5_Y(x) ((x) << 12) 1559 # define R600_S6_X(x) ((x) << 16) 1560 # define R600_S6_Y(x) ((x) << 20) 1561 # define R600_S7_X(x) ((x) << 24) 1562 # define R600_S7_Y(x) ((x) << 28) 1563 #define R600_PA_SC_FIFO_SIZE 0x8bd0 1564 # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1565 # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1566 # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1567 #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1568 # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1569 # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1570 # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1571 #define R600_PA_SC_ENHANCE 0x8bf0 1572 # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1573 # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1574 #define R600_PA_SC_CLIPRECT_RULE 0x2820c 1575 #define R700_PA_SC_EDGERULE 0x28230 1576 #define R600_PA_SC_LINE_STIPPLE 0x28a0c 1577 #define R600_PA_SC_MODE_CNTL 0x28a4c 1578 #define R600_PA_SC_AA_CONFIG 0x28c04 1579 1580 #define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1581 # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1582 # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1583 # define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1584 #define R600_SX_DEBUG_1 0x9054 1585 # define R600_SMX_EVENT_RELEASE (1 << 0) 1586 # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1587 #define R700_SX_DEBUG_1 0x9058 1588 # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1589 #define R600_SX_MISC 0x28350 1590 1591 #define R600_DB_DEBUG 0x9830 1592 # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 1593 #define R600_DB_WATERMARKS 0x9838 1594 # define R600_DEPTH_FREE(x) ((x) << 0) 1595 # define R600_DEPTH_FLUSH(x) ((x) << 5) 1596 # define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1597 # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1598 #define R700_DB_DEBUG3 0x98b0 1599 # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1600 #define RV700_DB_DEBUG4 0x9b8c 1601 # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1602 1603 #define R600_VGT_CACHE_INVALIDATION 0x88c4 1604 # define R600_CACHE_INVALIDATION(x) ((x) << 0) 1605 # define R600_VC_ONLY 0 1606 # define R600_TC_ONLY 1 1607 # define R600_VC_AND_TC 2 1608 # define R700_AUTO_INVLD_EN(x) ((x) << 6) 1609 # define R700_NO_AUTO 0 1610 # define R700_ES_AUTO 1 1611 # define R700_GS_AUTO 2 1612 # define R700_ES_AND_GS_AUTO 3 1613 #define R600_VGT_GS_PER_ES 0x88c8 1614 #define R600_VGT_ES_PER_GS 0x88cc 1615 #define R600_VGT_GS_PER_VS 0x88e8 1616 #define R600_VGT_GS_VERTEX_REUSE 0x88d4 1617 #define R600_VGT_NUM_INSTANCES 0x8974 1618 #define R600_VGT_STRMOUT_EN 0x28ab0 1619 #define R600_VGT_EVENT_INITIATOR 0x28a90 1620 # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1621 #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1622 # define R600_VTX_REUSE_DEPTH_MASK 0xff 1623 #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1624 # define R600_DEALLOC_DIST_MASK 0x7f 1625 1626 #define R600_CB_COLOR0_BASE 0x28040 1627 #define R600_CB_COLOR1_BASE 0x28044 1628 #define R600_CB_COLOR2_BASE 0x28048 1629 #define R600_CB_COLOR3_BASE 0x2804c 1630 #define R600_CB_COLOR4_BASE 0x28050 1631 #define R600_CB_COLOR5_BASE 0x28054 1632 #define R600_CB_COLOR6_BASE 0x28058 1633 #define R600_CB_COLOR7_BASE 0x2805c 1634 #define R600_CB_COLOR7_FRAG 0x280fc 1635 1636 #define R600_CB_COLOR0_SIZE 0x28060 1637 #define R600_CB_COLOR0_VIEW 0x28080 1638 #define R600_CB_COLOR0_INFO 0x280a0 1639 #define R600_CB_COLOR0_TILE 0x280c0 1640 #define R600_CB_COLOR0_FRAG 0x280e0 1641 #define R600_CB_COLOR0_MASK 0x28100 1642 1643 #define AVIVO_D1MODE_VLINE_START_END 0x6538 1644 #define AVIVO_D2MODE_VLINE_START_END 0x6d38 1645 #define R600_CP_COHER_BASE 0x85f8 1646 #define R600_DB_DEPTH_BASE 0x2800c 1647 #define R600_SQ_PGM_START_FS 0x28894 1648 #define R600_SQ_PGM_START_ES 0x28880 1649 #define R600_SQ_PGM_START_VS 0x28858 1650 #define R600_SQ_PGM_RESOURCES_VS 0x28868 1651 #define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 1652 #define R600_SQ_PGM_START_GS 0x2886c 1653 #define R600_SQ_PGM_START_PS 0x28840 1654 #define R600_SQ_PGM_RESOURCES_PS 0x28850 1655 #define R600_SQ_PGM_EXPORTS_PS 0x28854 1656 #define R600_SQ_PGM_CF_OFFSET_PS 0x288cc 1657 #define R600_VGT_DMA_BASE 0x287e8 1658 #define R600_VGT_DMA_BASE_HI 0x287e4 1659 #define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 1660 #define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 1661 #define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 1662 #define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c 1663 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 1664 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 1665 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c 1666 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 1667 #define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 1668 #define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 1669 #define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 1670 #define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 1671 #define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc 1672 #define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec 1673 #define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc 1674 #define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c 1675 1676 #define R600_VGT_PRIMITIVE_TYPE 0x8958 1677 1678 #define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 1679 #define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 1680 #define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 1681 1682 #define R600_TC_CNTL 0x9608 1683 # define R600_TC_L2_SIZE(x) ((x) << 5) 1684 # define R600_L2_DISABLE_LATE_HIT (1 << 9) 1685 1686 #define R600_ARB_POP 0x2418 1687 # define R600_ENABLE_TC128 (1 << 30) 1688 #define R600_ARB_GDEC_RD_CNTL 0x246c 1689 1690 #define R600_TA_CNTL_AUX 0x9508 1691 # define R600_DISABLE_CUBE_WRAP (1 << 0) 1692 # define R600_DISABLE_CUBE_ANISO (1 << 1) 1693 # define R700_GETLOD_SELECT(x) ((x) << 2) 1694 # define R600_SYNC_GRADIENT (1 << 24) 1695 # define R600_SYNC_WALKER (1 << 25) 1696 # define R600_SYNC_ALIGNER (1 << 26) 1697 # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1698 # define R600_BILINEAR_PRECISION_8_BIT (1 << 31) 1699 1700 #define R700_TCP_CNTL 0x9610 1701 1702 #define R600_SMX_DC_CTL0 0xa020 1703 # define R700_USE_HASH_FUNCTION (1 << 0) 1704 # define R700_CACHE_DEPTH(x) ((x) << 1) 1705 # define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1706 # define R700_STALL_ON_EVENT (1 << 11) 1707 #define R700_SMX_EVENT_CTL 0xa02c 1708 # define R700_ES_FLUSH_CTL(x) ((x) << 0) 1709 # define R700_GS_FLUSH_CTL(x) ((x) << 3) 1710 # define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1711 # define R700_SYNC_FLUSH_CTL (1 << 8) 1712 1713 #define R600_SQ_CONFIG 0x8c00 1714 # define R600_VC_ENABLE (1 << 0) 1715 # define R600_EXPORT_SRC_C (1 << 1) 1716 # define R600_DX9_CONSTS (1 << 2) 1717 # define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1718 # define R600_DX10_CLAMP (1 << 4) 1719 # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1720 # define R600_PS_PRIO(x) ((x) << 24) 1721 # define R600_VS_PRIO(x) ((x) << 26) 1722 # define R600_GS_PRIO(x) ((x) << 28) 1723 # define R600_ES_PRIO(x) ((x) << 30) 1724 #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1725 # define R600_NUM_PS_GPRS(x) ((x) << 0) 1726 # define R600_NUM_VS_GPRS(x) ((x) << 16) 1727 # define R700_DYN_GPR_ENABLE (1 << 27) 1728 # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1729 #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1730 # define R600_NUM_GS_GPRS(x) ((x) << 0) 1731 # define R600_NUM_ES_GPRS(x) ((x) << 16) 1732 #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1733 # define R600_NUM_PS_THREADS(x) ((x) << 0) 1734 # define R600_NUM_VS_THREADS(x) ((x) << 8) 1735 # define R600_NUM_GS_THREADS(x) ((x) << 16) 1736 # define R600_NUM_ES_THREADS(x) ((x) << 24) 1737 #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1738 # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1739 # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1740 #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1741 # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1742 # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1743 #define R600_SQ_MS_FIFO_SIZES 0x8cf0 1744 # define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1745 # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1746 # define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1747 # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1748 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1749 # define R700_SIMDA_RING0(x) ((x) << 0) 1750 # define R700_SIMDA_RING1(x) ((x) << 8) 1751 # define R700_SIMDB_RING0(x) ((x) << 16) 1752 # define R700_SIMDB_RING1(x) ((x) << 24) 1753 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1754 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1755 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1756 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1757 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1758 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1759 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1760 1761 #define R600_SPI_PS_IN_CONTROL_0 0x286cc 1762 # define R600_NUM_INTERP(x) ((x) << 0) 1763 # define R600_POSITION_ENA (1 << 8) 1764 # define R600_POSITION_CENTROID (1 << 9) 1765 # define R600_POSITION_ADDR(x) ((x) << 10) 1766 # define R600_PARAM_GEN(x) ((x) << 15) 1767 # define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1768 # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1769 # define R600_PERSP_GRADIENT_ENA (1 << 28) 1770 # define R600_LINEAR_GRADIENT_ENA (1 << 29) 1771 # define R600_POSITION_SAMPLE (1 << 30) 1772 # define R600_BARYC_AT_SAMPLE_ENA (1 << 31) 1773 #define R600_SPI_PS_IN_CONTROL_1 0x286d0 1774 # define R600_GEN_INDEX_PIX (1 << 0) 1775 # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1776 # define R600_FRONT_FACE_ENA (1 << 8) 1777 # define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1778 # define R600_FRONT_FACE_ALL_BITS (1 << 11) 1779 # define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1780 # define R600_FOG_ADDR(x) ((x) << 17) 1781 # define R600_FIXED_PT_POSITION_ENA (1 << 24) 1782 # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1783 # define R700_POSITION_ULC (1 << 30) 1784 #define R600_SPI_INPUT_Z 0x286d8 1785 1786 #define R600_SPI_CONFIG_CNTL 0x9100 1787 # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1788 # define R600_DISABLE_INTERP_1 (1 << 5) 1789 #define R600_SPI_CONFIG_CNTL_1 0x913c 1790 # define R600_VTX_DONE_DELAY(x) ((x) << 0) 1791 # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1792 1793 #define R600_GB_TILING_CONFIG 0x98f0 1794 # define R600_PIPE_TILING(x) ((x) << 1) 1795 # define R600_BANK_TILING(x) ((x) << 4) 1796 # define R600_GROUP_SIZE(x) ((x) << 6) 1797 # define R600_ROW_TILING(x) ((x) << 8) 1798 # define R600_BANK_SWAPS(x) ((x) << 11) 1799 # define R600_SAMPLE_SPLIT(x) ((x) << 14) 1800 # define R600_BACKEND_MAP(x) ((x) << 16) 1801 #define R600_DCP_TILING_CONFIG 0x6ca0 1802 #define R600_HDP_TILING_CONFIG 0x2f3c 1803 1804 #define R600_CC_RB_BACKEND_DISABLE 0x98f4 1805 #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1806 # define R600_BACKEND_DISABLE(x) ((x) << 16) 1807 1808 #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1809 #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1810 # define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1811 # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1812 # define R600_INACTIVE_SIMDS(x) ((x) << 16) 1813 # define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1814 1815 #define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1816 #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1817 #define R700_CGTS_TCC_DISABLE 0x9148 1818 #define R700_CGTS_USER_TCC_DISABLE 0x914c 1819 1820 /* Constants */ 1821 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1822 1823 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1824 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1825 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1826 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1827 #define RADEON_LAST_DISPATCH 1 1828 1829 #define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1830 #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1831 #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1832 #define R600_LAST_SWI_REG R600_SCRATCH_REG3 1833 1834 #define RADEON_MAX_VB_AGE 0x7fffffff 1835 #define RADEON_MAX_VB_VERTS (0xffff) 1836 1837 #define RADEON_RING_HIGH_MARK 128 1838 1839 #define RADEON_PCIGART_TABLE_SIZE (32*1024) 1840 1841 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1842 #define RADEON_WRITE(reg, val) \ 1843 do { \ 1844 if (reg < 0x10000) { \ 1845 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1846 } else { \ 1847 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1848 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1849 } \ 1850 } while (0) 1851 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1852 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1853 1854 #define RADEON_WRITE_PLL(addr, val) \ 1855 do { \ 1856 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1857 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1858 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1859 } while (0) 1860 1861 #define RADEON_WRITE_PCIE(addr, val) \ 1862 do { \ 1863 RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1864 ((addr) & 0xff)); \ 1865 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1866 } while (0) 1867 1868 #define R500_WRITE_MCIND(addr, val) \ 1869 do { \ 1870 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1871 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1872 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1873 } while (0) 1874 1875 #define RS480_WRITE_MCIND(addr, val) \ 1876 do { \ 1877 RADEON_WRITE(RS480_NB_MC_INDEX, \ 1878 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1879 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1880 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1881 } while (0) 1882 1883 #define RS690_WRITE_MCIND(addr, val) \ 1884 do { \ 1885 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1886 RADEON_WRITE(RS690_MC_DATA, val); \ 1887 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1888 } while (0) 1889 1890 #define RS600_WRITE_MCIND(addr, val) \ 1891 do { \ 1892 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1893 RADEON_WRITE(RS600_MC_DATA, val); \ 1894 } while (0) 1895 1896 #define IGP_WRITE_MCIND(addr, val) \ 1897 do { \ 1898 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1899 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1900 RS690_WRITE_MCIND(addr, val); \ 1901 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1902 RS600_WRITE_MCIND(addr, val); \ 1903 else \ 1904 RS480_WRITE_MCIND(addr, val); \ 1905 } while (0) 1906 1907 #define CP_PACKET0( reg, n ) \ 1908 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1909 #define CP_PACKET0_TABLE( reg, n ) \ 1910 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1911 #define CP_PACKET1( reg0, reg1 ) \ 1912 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1913 #define CP_PACKET2() \ 1914 (RADEON_CP_PACKET2) 1915 #define CP_PACKET3( pkt, n ) \ 1916 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1917 1918 /* ================================================================ 1919 * Engine control helper macros 1920 */ 1921 1922 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1923 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1924 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1925 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1926 } while (0) 1927 1928 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1929 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1930 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1931 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1932 } while (0) 1933 1934 #define RADEON_WAIT_UNTIL_IDLE() do { \ 1935 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1936 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1937 RADEON_WAIT_3D_IDLECLEAN | \ 1938 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1939 } while (0) 1940 1941 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1943 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1944 } while (0) 1945 1946 #define RADEON_FLUSH_CACHE() do { \ 1947 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1948 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1949 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1950 } else { \ 1951 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1952 OUT_RING(R300_RB3D_DC_FLUSH); \ 1953 } \ 1954 } while (0) 1955 1956 #define RADEON_PURGE_CACHE() do { \ 1957 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1958 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1959 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1960 } else { \ 1961 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1962 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1963 } \ 1964 } while (0) 1965 1966 #define RADEON_FLUSH_ZCACHE() do { \ 1967 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1968 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1969 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1970 } else { \ 1971 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1972 OUT_RING(R300_ZC_FLUSH); \ 1973 } \ 1974 } while (0) 1975 1976 #define RADEON_PURGE_ZCACHE() do { \ 1977 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1978 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1979 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1980 } else { \ 1981 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1982 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1983 } \ 1984 } while (0) 1985 1986 /* ================================================================ 1987 * Misc helper macros 1988 */ 1989 1990 /* Perfbox functionality only. 1991 */ 1992 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1993 do { \ 1994 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1995 u32 head = GET_RING_HEAD( dev_priv ); \ 1996 if (head == dev_priv->ring.tail) \ 1997 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1998 } \ 1999 } while (0) 2000 2001 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 2002 do { \ 2003 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;\ 2004 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \ 2005 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 2006 int __ret; \ 2007 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 2008 __ret = r600_do_cp_idle(dev_priv); \ 2009 else \ 2010 __ret = radeon_do_cp_idle(dev_priv); \ 2011 if ( __ret ) return __ret; \ 2012 sarea_priv->last_dispatch = 0; \ 2013 radeon_freelist_reset( dev ); \ 2014 } \ 2015 } while (0) 2016 2017 #define RADEON_DISPATCH_AGE( age ) do { \ 2018 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2019 OUT_RING( age ); \ 2020 } while (0) 2021 2022 #define RADEON_FRAME_AGE( age ) do { \ 2023 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2024 OUT_RING( age ); \ 2025 } while (0) 2026 2027 #define RADEON_CLEAR_AGE( age ) do { \ 2028 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2029 OUT_RING( age ); \ 2030 } while (0) 2031 2032 #define R600_DISPATCH_AGE(age) do { \ 2033 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2034 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2035 OUT_RING(age); \ 2036 } while (0) 2037 2038 #define R600_FRAME_AGE(age) do { \ 2039 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2040 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2041 OUT_RING(age); \ 2042 } while (0) 2043 2044 #define R600_CLEAR_AGE(age) do { \ 2045 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2046 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2047 OUT_RING(age); \ 2048 } while (0) 2049 2050 /* ================================================================ 2051 * Ring control 2052 */ 2053 2054 #define RADEON_VERBOSE 0 2055 2056 #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2057 2058 #define RADEON_RING_ALIGN 16 2059 2060 #define BEGIN_RING( n ) do { \ 2061 if ( RADEON_VERBOSE ) { \ 2062 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2063 } \ 2064 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \ 2065 _align_nr += n; \ 2066 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \ 2067 COMMIT_RING(); \ 2068 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \ 2069 } \ 2070 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2071 ring = dev_priv->ring.start; \ 2072 write = dev_priv->ring.tail; \ 2073 mask = dev_priv->ring.tail_mask; \ 2074 } while (0) 2075 2076 #define ADVANCE_RING() do { \ 2077 if ( RADEON_VERBOSE ) { \ 2078 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 2079 write, dev_priv->ring.tail ); \ 2080 } \ 2081 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2082 DRM_ERROR( \ 2083 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2084 ((dev_priv->ring.tail + _nr) & mask), \ 2085 write, __LINE__); \ 2086 } else \ 2087 dev_priv->ring.tail = write; \ 2088 } while (0) 2089 2090 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 2091 2092 #define COMMIT_RING() do { \ 2093 radeon_commit_ring(dev_priv); \ 2094 } while(0) 2095 2096 #define OUT_RING( x ) do { \ 2097 if ( RADEON_VERBOSE ) { \ 2098 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2099 (unsigned int)(x), write ); \ 2100 } \ 2101 ring[write++] = (x); \ 2102 write &= mask; \ 2103 } while (0) 2104 2105 #define OUT_RING_REG( reg, val ) do { \ 2106 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2107 OUT_RING( val ); \ 2108 } while (0) 2109 2110 #define OUT_RING_TABLE( tab, sz ) do { \ 2111 int _size = (sz); \ 2112 int *_tab = (int *)(tab); \ 2113 \ 2114 if (write + _size > mask) { \ 2115 int _i = (mask+1) - write; \ 2116 _size -= _i; \ 2117 while (_i > 0 ) { \ 2118 *(int *)(ring + write) = *_tab++; \ 2119 write++; \ 2120 _i--; \ 2121 } \ 2122 write = 0; \ 2123 _tab += _i; \ 2124 } \ 2125 while (_size > 0) { \ 2126 *(ring + write) = *_tab++; \ 2127 write++; \ 2128 _size--; \ 2129 } \ 2130 write &= mask; \ 2131 } while (0) 2132 2133 /** 2134 * Copy given number of dwords from drm buffer to the ring buffer. 2135 */ 2136 #define OUT_RING_DRM_BUFFER(buf, sz) do { \ 2137 int _size = (sz) * 4; \ 2138 struct drm_buffer *_buf = (buf); \ 2139 int _part_size; \ 2140 while (_size > 0) { \ 2141 _part_size = _size; \ 2142 \ 2143 if (write + _part_size/4 > mask) \ 2144 _part_size = ((mask + 1) - write)*4; \ 2145 \ 2146 if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \ 2147 _part_size = PAGE_SIZE - drm_buffer_index(_buf);\ 2148 \ 2149 \ 2150 \ 2151 memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \ 2152 [drm_buffer_index(_buf)], _part_size); \ 2153 \ 2154 _size -= _part_size; \ 2155 write = (write + _part_size/4) & mask; \ 2156 drm_buffer_advance(_buf, _part_size); \ 2157 } \ 2158 } while (0) 2159 2160 2161 #endif /* CONFIG_DRM_RADEON_UMS */ 2162 2163 #endif /* __RADEON_DRV_H__ */ 2164