1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_gart.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "drm/drm_legacy.h" /* for drm_dma_handle_t */ 33 #include <uapi_drm/radeon_drm.h> 34 #include "radeon.h" 35 36 /* 37 * GART 38 * The GART (Graphics Aperture Remapping Table) is an aperture 39 * in the GPU's address space. System pages can be mapped into 40 * the aperture and look like contiguous pages from the GPU's 41 * perspective. A page table maps the pages in the aperture 42 * to the actual backing pages in system memory. 43 * 44 * Radeon GPUs support both an internal GART, as described above, 45 * and AGP. AGP works similarly, but the GART table is configured 46 * and maintained by the northbridge rather than the driver. 47 * Radeon hw has a separate AGP aperture that is programmed to 48 * point to the AGP aperture provided by the northbridge and the 49 * requests are passed through to the northbridge aperture. 50 * Both AGP and internal GART can be used at the same time, however 51 * that is not currently supported by the driver. 52 * 53 * This file handles the common internal GART management. 54 */ 55 56 /* 57 * Common GART table functions. 58 */ 59 /** 60 * radeon_gart_table_ram_alloc - allocate system ram for gart page table 61 * 62 * @rdev: radeon_device pointer 63 * 64 * Allocate system memory for GART page table 65 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 66 * gart table to be in system memory. 67 * Returns 0 for success, -ENOMEM for failure. 68 */ 69 int radeon_gart_table_ram_alloc(struct radeon_device *rdev) 70 { 71 drm_dma_handle_t *dmah; 72 73 dmah = drm_pci_alloc(rdev->ddev, rdev->gart.table_size, 74 PAGE_SIZE); 75 if (dmah == NULL) { 76 return -ENOMEM; 77 } 78 rdev->gart.dmah = dmah; 79 rdev->gart.ptr = dmah->vaddr; 80 #if defined(__i386) || defined(__amd64) 81 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 82 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 83 pmap_change_attr((vm_offset_t)rdev->gart.ptr, 84 rdev->gart.table_size >> PAGE_SHIFT, PAT_UNCACHED); 85 } 86 #endif 87 rdev->gart.table_addr = dmah->busaddr; 88 memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size); 89 return 0; 90 } 91 92 /** 93 * radeon_gart_table_ram_free - free system ram for gart page table 94 * 95 * @rdev: radeon_device pointer 96 * 97 * Free system memory for GART page table 98 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 99 * gart table to be in system memory. 100 */ 101 void radeon_gart_table_ram_free(struct radeon_device *rdev) 102 { 103 if (rdev->gart.ptr == NULL) { 104 return; 105 } 106 #if defined(__i386) || defined(__amd64) 107 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 108 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 109 pmap_change_attr((vm_offset_t)rdev->gart.ptr, 110 rdev->gart.table_size >> PAGE_SHIFT, PAT_WRITE_COMBINING); 111 } 112 #endif 113 drm_pci_free(rdev->ddev, rdev->gart.dmah); 114 rdev->gart.dmah = NULL; 115 rdev->gart.ptr = NULL; 116 rdev->gart.table_addr = 0; 117 } 118 119 /** 120 * radeon_gart_table_vram_alloc - allocate vram for gart page table 121 * 122 * @rdev: radeon_device pointer 123 * 124 * Allocate video memory for GART page table 125 * (pcie r4xx, r5xx+). These asics require the 126 * gart table to be in video memory. 127 * Returns 0 for success, error for failure. 128 */ 129 int radeon_gart_table_vram_alloc(struct radeon_device *rdev) 130 { 131 int r; 132 133 if (rdev->gart.robj == NULL) { 134 r = radeon_bo_create(rdev, rdev->gart.table_size, 135 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 136 0, NULL, &rdev->gart.robj); 137 if (r) { 138 return r; 139 } 140 } 141 return 0; 142 } 143 144 /** 145 * radeon_gart_table_vram_pin - pin gart page table in vram 146 * 147 * @rdev: radeon_device pointer 148 * 149 * Pin the GART page table in vram so it will not be moved 150 * by the memory manager (pcie r4xx, r5xx+). These asics require the 151 * gart table to be in video memory. 152 * Returns 0 for success, error for failure. 153 */ 154 int radeon_gart_table_vram_pin(struct radeon_device *rdev) 155 { 156 u64 gpu_addr; 157 int r; 158 159 r = radeon_bo_reserve(rdev->gart.robj, false); 160 if (unlikely(r != 0)) 161 return r; 162 r = radeon_bo_pin(rdev->gart.robj, 163 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 164 if (r) { 165 radeon_bo_unreserve(rdev->gart.robj); 166 return r; 167 } 168 r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr); 169 if (r) 170 radeon_bo_unpin(rdev->gart.robj); 171 radeon_bo_unreserve(rdev->gart.robj); 172 rdev->gart.table_addr = gpu_addr; 173 return r; 174 } 175 176 /** 177 * radeon_gart_table_vram_unpin - unpin gart page table in vram 178 * 179 * @rdev: radeon_device pointer 180 * 181 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 182 * These asics require the gart table to be in video memory. 183 */ 184 void radeon_gart_table_vram_unpin(struct radeon_device *rdev) 185 { 186 int r; 187 188 if (rdev->gart.robj == NULL) { 189 return; 190 } 191 r = radeon_bo_reserve(rdev->gart.robj, false); 192 if (likely(r == 0)) { 193 radeon_bo_kunmap(rdev->gart.robj); 194 radeon_bo_unpin(rdev->gart.robj); 195 radeon_bo_unreserve(rdev->gart.robj); 196 rdev->gart.ptr = NULL; 197 } 198 } 199 200 /** 201 * radeon_gart_table_vram_free - free gart page table vram 202 * 203 * @rdev: radeon_device pointer 204 * 205 * Free the video memory used for the GART page table 206 * (pcie r4xx, r5xx+). These asics require the gart table to 207 * be in video memory. 208 */ 209 void radeon_gart_table_vram_free(struct radeon_device *rdev) 210 { 211 if (rdev->gart.robj == NULL) { 212 return; 213 } 214 radeon_bo_unref(&rdev->gart.robj); 215 } 216 217 /* 218 * Common gart functions. 219 */ 220 /** 221 * radeon_gart_unbind - unbind pages from the gart page table 222 * 223 * @rdev: radeon_device pointer 224 * @offset: offset into the GPU's gart aperture 225 * @pages: number of pages to unbind 226 * 227 * Unbinds the requested pages from the gart page table and 228 * replaces them with the dummy page (all asics). 229 */ 230 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 231 int pages) 232 { 233 unsigned t; 234 unsigned p; 235 int i, j; 236 u64 page_base; 237 238 if (!rdev->gart.ready) { 239 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 240 return; 241 } 242 t = offset / RADEON_GPU_PAGE_SIZE; 243 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 244 for (i = 0; i < pages; i++, p++) { 245 if (rdev->gart.pages[p]) { 246 rdev->gart.pages[p] = NULL; 247 rdev->gart.pages_addr[p] = rdev->dummy_page.addr; 248 page_base = rdev->gart.pages_addr[p]; 249 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 250 if (rdev->gart.ptr) { 251 radeon_gart_set_page(rdev, t, page_base, 252 RADEON_GART_PAGE_DUMMY); 253 } 254 page_base += RADEON_GPU_PAGE_SIZE; 255 } 256 } 257 } 258 mb(); 259 radeon_gart_tlb_flush(rdev); 260 } 261 262 /** 263 * radeon_gart_bind - bind pages into the gart page table 264 * 265 * @rdev: radeon_device pointer 266 * @offset: offset into the GPU's gart aperture 267 * @pages: number of pages to bind 268 * @pagelist: pages to bind 269 * @dma_addr: DMA addresses of pages 270 * @flags: RADEON_GART_PAGE_* flags 271 * 272 * Binds the requested pages to the gart page table 273 * (all asics). 274 * Returns 0 for success, -EINVAL for failure. 275 */ 276 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 277 int pages, vm_page_t *pagelist, dma_addr_t *dma_addr, 278 uint32_t flags) 279 { 280 unsigned t; 281 unsigned p; 282 uint64_t page_base; 283 int i, j; 284 285 if (!rdev->gart.ready) { 286 WARN(1, "trying to bind memory to uninitialized GART !\n"); 287 return -EINVAL; 288 } 289 t = offset / RADEON_GPU_PAGE_SIZE; 290 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 291 292 for (i = 0; i < pages; i++, p++) { 293 rdev->gart.pages_addr[p] = dma_addr[i]; 294 rdev->gart.pages[p] = pagelist[i]; 295 if (rdev->gart.ptr) { 296 page_base = rdev->gart.pages_addr[p]; 297 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 298 radeon_gart_set_page(rdev, t, page_base, flags); 299 page_base += RADEON_GPU_PAGE_SIZE; 300 } 301 } 302 } 303 mb(); 304 radeon_gart_tlb_flush(rdev); 305 return 0; 306 } 307 308 /** 309 * radeon_gart_init - init the driver info for managing the gart 310 * 311 * @rdev: radeon_device pointer 312 * 313 * Allocate the dummy page and init the gart driver info (all asics). 314 * Returns 0 for success, error for failure. 315 */ 316 int radeon_gart_init(struct radeon_device *rdev) 317 { 318 int r, i; 319 320 if (rdev->gart.pages) { 321 return 0; 322 } 323 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ 324 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { 325 DRM_ERROR("Page size is smaller than GPU page size!\n"); 326 return -EINVAL; 327 } 328 r = radeon_dummy_page_init(rdev); 329 if (r) 330 return r; 331 /* Compute table size */ 332 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; 333 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; 334 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 335 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); 336 /* Allocate pages table */ 337 rdev->gart.pages = kmalloc(sizeof(void *) * rdev->gart.num_cpu_pages, 338 M_DRM, M_ZERO | M_WAITOK); 339 if (rdev->gart.pages == NULL) { 340 radeon_gart_fini(rdev); 341 return -ENOMEM; 342 } 343 rdev->gart.pages_addr = kmalloc(sizeof(dma_addr_t) * rdev->gart.num_cpu_pages, 344 M_DRM, M_ZERO | M_WAITOK); 345 if (rdev->gart.pages_addr == NULL) { 346 radeon_gart_fini(rdev); 347 return -ENOMEM; 348 } 349 /* set GART entry to point to the dummy page by default */ 350 for (i = 0; i < rdev->gart.num_cpu_pages; i++) { 351 rdev->gart.pages_addr[i] = rdev->dummy_page.addr; 352 } 353 return 0; 354 } 355 356 /** 357 * radeon_gart_fini - tear down the driver info for managing the gart 358 * 359 * @rdev: radeon_device pointer 360 * 361 * Tear down the gart driver info and free the dummy page (all asics). 362 */ 363 void radeon_gart_fini(struct radeon_device *rdev) 364 { 365 if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { 366 /* unbind pages */ 367 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); 368 } 369 rdev->gart.ready = false; 370 kfree(rdev->gart.pages); 371 kfree(rdev->gart.pages_addr); 372 rdev->gart.pages = NULL; 373 rdev->gart.pages_addr = NULL; 374 375 radeon_dummy_page_fini(rdev); 376 } 377