1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_i2c.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_edid.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include <bus/iicbus/iic.h> 33 #include <bus/iicbus/iiconf.h> 34 #include <bus/iicbus/iicbus.h> 35 #include <sys/mplock2.h> 36 #include "radeon.h" 37 #include "atom.h" 38 #include "iicbus_if.h" 39 #include "iicbb_if.h" 40 41 /** 42 * radeon_ddc_probe 43 * 44 */ 45 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 46 { 47 u8 out = 0x0; 48 u8 buf[8]; 49 int ret; 50 struct iic_msg msgs[] = { 51 { 52 .slave = DDC_ADDR << 1, 53 .flags = 0, 54 .len = 1, 55 .buf = &out, 56 }, 57 { 58 .slave = DDC_ADDR << 1, 59 .flags = IIC_M_RD, 60 .len = 8, 61 .buf = buf, 62 } 63 }; 64 65 /* on hw with routers, select right port */ 66 if (radeon_connector->router.ddc_valid) 67 radeon_router_select_ddc_port(radeon_connector); 68 69 if (use_aux) { 70 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 71 ret = iicbus_transfer(dig->dp_i2c_bus->adapter, msgs, 2); 72 } else { 73 ret = iicbus_transfer(radeon_connector->ddc_bus->adapter, msgs, 2); 74 } 75 76 if (ret != 0) 77 /* Couldn't find an accessible DDC on this connector */ 78 return false; 79 /* Probe also for valid EDID header 80 * EDID header starts with: 81 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 82 * Only the first 6 bytes must be valid as 83 * drm_edid_block_valid() can fix the last 2 bytes */ 84 if (drm_edid_header_is_valid(buf) < 6) { 85 /* Couldn't find an accessible EDID on this 86 * connector */ 87 return false; 88 } 89 return true; 90 } 91 92 /* bit banging i2c */ 93 94 static int radeon_iicbb_pre_xfer(device_t dev) 95 { 96 struct radeon_i2c_chan *i2c = device_get_softc(dev); 97 struct radeon_device *rdev = i2c->dev->dev_private; 98 struct radeon_i2c_bus_rec *rec = &i2c->rec; 99 uint32_t temp; 100 101 lockmgr(&i2c->mutex, LK_EXCLUSIVE); 102 103 /* RV410 appears to have a bug where the hw i2c in reset 104 * holds the i2c port in a bad state - switch hw i2c away before 105 * doing DDC - do this for all r200s/r300s/r400s for safety sake 106 */ 107 if (rec->hw_capable) { 108 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 109 u32 reg; 110 111 if (rdev->family >= CHIP_RV350) 112 reg = RADEON_GPIO_MONID; 113 else if ((rdev->family == CHIP_R300) || 114 (rdev->family == CHIP_R350)) 115 reg = RADEON_GPIO_DVI_DDC; 116 else 117 reg = RADEON_GPIO_CRT2_DDC; 118 119 lockmgr(&rdev->dc_hw_i2c_mutex, LK_EXCLUSIVE); 120 if (rec->a_clk_reg == reg) { 121 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 122 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 123 } else { 124 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 125 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 126 } 127 lockmgr(&rdev->dc_hw_i2c_mutex, LK_RELEASE); 128 } 129 } 130 131 /* switch the pads to ddc mode */ 132 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 133 temp = RREG32(rec->mask_clk_reg); 134 temp &= ~(1 << 16); 135 WREG32(rec->mask_clk_reg, temp); 136 } 137 138 /* clear the output pin values */ 139 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 140 WREG32(rec->a_clk_reg, temp); 141 142 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 143 WREG32(rec->a_data_reg, temp); 144 145 /* set the pins to input */ 146 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 147 WREG32(rec->en_clk_reg, temp); 148 149 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 150 WREG32(rec->en_data_reg, temp); 151 152 /* mask the gpio pins for software use */ 153 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 154 WREG32(rec->mask_clk_reg, temp); 155 temp = RREG32(rec->mask_clk_reg); 156 157 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 158 WREG32(rec->mask_data_reg, temp); 159 temp = RREG32(rec->mask_data_reg); 160 161 return 0; 162 } 163 164 static void radeon_iicbb_post_xfer(device_t dev) 165 { 166 struct radeon_i2c_chan *i2c = device_get_softc(dev); 167 struct radeon_device *rdev = i2c->dev->dev_private; 168 struct radeon_i2c_bus_rec *rec = &i2c->rec; 169 uint32_t temp; 170 171 /* unmask the gpio pins for software use */ 172 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 173 WREG32(rec->mask_clk_reg, temp); 174 temp = RREG32(rec->mask_clk_reg); 175 176 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 177 WREG32(rec->mask_data_reg, temp); 178 temp = RREG32(rec->mask_data_reg); 179 180 lockmgr(&i2c->mutex, LK_RELEASE); 181 } 182 183 static int radeon_iicbb_get_clock(device_t dev) 184 { 185 struct radeon_i2c_chan *i2c = device_get_softc(dev); 186 struct radeon_device *rdev = i2c->dev->dev_private; 187 struct radeon_i2c_bus_rec *rec = &i2c->rec; 188 uint32_t val; 189 190 /* read the value off the pin */ 191 val = RREG32(rec->y_clk_reg); 192 val &= rec->y_clk_mask; 193 194 return (val != 0); 195 } 196 197 198 static int radeon_iicbb_get_data(device_t dev) 199 { 200 struct radeon_i2c_chan *i2c = device_get_softc(dev); 201 struct radeon_device *rdev = i2c->dev->dev_private; 202 struct radeon_i2c_bus_rec *rec = &i2c->rec; 203 uint32_t val; 204 205 /* read the value off the pin */ 206 val = RREG32(rec->y_data_reg); 207 val &= rec->y_data_mask; 208 209 return (val != 0); 210 } 211 212 static void radeon_iicbb_set_clock(device_t dev, int clock) 213 { 214 struct radeon_i2c_chan *i2c = device_get_softc(dev); 215 struct radeon_device *rdev = i2c->dev->dev_private; 216 struct radeon_i2c_bus_rec *rec = &i2c->rec; 217 uint32_t val; 218 219 /* set pin direction */ 220 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 221 val |= clock ? 0 : rec->en_clk_mask; 222 WREG32(rec->en_clk_reg, val); 223 } 224 225 static void radeon_iicbb_set_data(device_t dev, int data) 226 { 227 struct radeon_i2c_chan *i2c = device_get_softc(dev); 228 struct radeon_device *rdev = i2c->dev->dev_private; 229 struct radeon_i2c_bus_rec *rec = &i2c->rec; 230 uint32_t val; 231 232 /* set pin direction */ 233 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 234 val |= data ? 0 : rec->en_data_mask; 235 WREG32(rec->en_data_reg, val); 236 } 237 238 static int 239 radeon_iicbb_probe(device_t dev) 240 { 241 242 return (BUS_PROBE_DEFAULT); 243 } 244 245 static int 246 radeon_iicbb_attach(device_t dev) 247 { 248 struct radeon_i2c_chan *i2c; 249 device_t iic_dev; 250 251 i2c = device_get_softc(dev); 252 device_set_desc(dev, i2c->name); 253 254 /* add generic bit-banging code */ 255 iic_dev = device_add_child(dev, "iicbb", -1); 256 if (iic_dev == NULL) 257 return (ENXIO); 258 device_quiet(iic_dev); 259 260 /* attach and probe added child */ 261 bus_generic_attach(dev); 262 263 return (0); 264 } 265 266 static int 267 radeon_iicbb_detach(device_t dev) 268 { 269 270 /* detach bit-banding code. */ 271 bus_generic_detach(dev); 272 273 /* delete bit-banding code. */ 274 device_delete_children(dev); 275 return (0); 276 } 277 278 static int 279 radeon_iicbb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 280 { 281 282 /* Not sure what to do here. */ 283 return 0; 284 } 285 286 static device_method_t radeon_iicbb_methods[] = { 287 DEVMETHOD(device_probe, radeon_iicbb_probe), 288 DEVMETHOD(device_attach, radeon_iicbb_attach), 289 DEVMETHOD(device_detach, radeon_iicbb_detach), 290 291 DEVMETHOD(bus_add_child, bus_generic_add_child), 292 DEVMETHOD(bus_print_child, bus_generic_print_child), 293 294 DEVMETHOD(iicbb_reset, radeon_iicbb_reset), 295 DEVMETHOD(iicbb_pre_xfer, radeon_iicbb_pre_xfer), 296 DEVMETHOD(iicbb_post_xfer, radeon_iicbb_post_xfer), 297 DEVMETHOD(iicbb_setsda, radeon_iicbb_set_data), 298 DEVMETHOD(iicbb_setscl, radeon_iicbb_set_clock), 299 DEVMETHOD(iicbb_getsda, radeon_iicbb_get_data), 300 DEVMETHOD(iicbb_getscl, radeon_iicbb_get_clock), 301 DEVMETHOD_END 302 }; 303 304 static driver_t radeon_iicbb_driver = { 305 "radeon_iicbb", 306 radeon_iicbb_methods, 307 0 /* softc will be allocated by parent */ 308 }; 309 static devclass_t radeon_iicbb_devclass; 310 DRIVER_MODULE_ORDERED(radeon_iicbb, drm, radeon_iicbb_driver, 311 radeon_iicbb_devclass, NULL, NULL, SI_ORDER_FIRST); 312 DRIVER_MODULE(iicbb, radeon_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 313 314 /* hw i2c */ 315 316 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 317 { 318 u32 sclk = rdev->pm.current_sclk; 319 u32 prescale = 0; 320 u32 nm; 321 u8 n, m, loop; 322 int i2c_clock; 323 324 switch (rdev->family) { 325 case CHIP_R100: 326 case CHIP_RV100: 327 case CHIP_RS100: 328 case CHIP_RV200: 329 case CHIP_RS200: 330 case CHIP_R200: 331 case CHIP_RV250: 332 case CHIP_RS300: 333 case CHIP_RV280: 334 case CHIP_R300: 335 case CHIP_R350: 336 case CHIP_RV350: 337 i2c_clock = 60; 338 nm = (sclk * 10) / (i2c_clock * 4); 339 for (loop = 1; loop < 255; loop++) { 340 if ((nm / loop) < loop) 341 break; 342 } 343 n = loop - 1; 344 m = loop - 2; 345 prescale = m | (n << 8); 346 break; 347 case CHIP_RV380: 348 case CHIP_RS400: 349 case CHIP_RS480: 350 case CHIP_R420: 351 case CHIP_R423: 352 case CHIP_RV410: 353 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 354 break; 355 case CHIP_RS600: 356 case CHIP_RS690: 357 case CHIP_RS740: 358 /* todo */ 359 break; 360 case CHIP_RV515: 361 case CHIP_R520: 362 case CHIP_RV530: 363 case CHIP_RV560: 364 case CHIP_RV570: 365 case CHIP_R580: 366 i2c_clock = 50; 367 if (rdev->family == CHIP_R520) 368 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 369 else 370 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 371 break; 372 case CHIP_R600: 373 case CHIP_RV610: 374 case CHIP_RV630: 375 case CHIP_RV670: 376 /* todo */ 377 break; 378 case CHIP_RV620: 379 case CHIP_RV635: 380 case CHIP_RS780: 381 case CHIP_RS880: 382 case CHIP_RV770: 383 case CHIP_RV730: 384 case CHIP_RV710: 385 case CHIP_RV740: 386 /* todo */ 387 break; 388 case CHIP_CEDAR: 389 case CHIP_REDWOOD: 390 case CHIP_JUNIPER: 391 case CHIP_CYPRESS: 392 case CHIP_HEMLOCK: 393 /* todo */ 394 break; 395 default: 396 DRM_ERROR("i2c: unhandled radeon chip\n"); 397 break; 398 } 399 return prescale; 400 } 401 402 403 /* hw i2c engine for r1xx-4xx hardware 404 * hw can buffer up to 15 bytes 405 */ 406 static int r100_hw_i2c_xfer(struct radeon_i2c_chan *i2c, 407 struct iic_msg *msgs, int num) 408 { 409 struct radeon_device *rdev = i2c->dev->dev_private; 410 struct radeon_i2c_bus_rec *rec = &i2c->rec; 411 struct iic_msg *p; 412 int i, j, k, ret = 0; 413 u32 prescale; 414 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 415 u32 tmp, reg; 416 417 lockmgr(&rdev->dc_hw_i2c_mutex, LK_EXCLUSIVE); 418 /* take the pm lock since we need a constant sclk */ 419 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE); 420 421 prescale = radeon_get_i2c_prescale(rdev); 422 423 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 424 RADEON_I2C_DRIVE_EN | 425 RADEON_I2C_START | 426 RADEON_I2C_STOP | 427 RADEON_I2C_GO); 428 429 if (rdev->is_atom_bios) { 430 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 431 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 432 } 433 434 if (rec->mm_i2c) { 435 i2c_cntl_0 = RADEON_I2C_CNTL_0; 436 i2c_cntl_1 = RADEON_I2C_CNTL_1; 437 i2c_data = RADEON_I2C_DATA; 438 } else { 439 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 440 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 441 i2c_data = RADEON_DVI_I2C_DATA; 442 443 switch (rdev->family) { 444 case CHIP_R100: 445 case CHIP_RV100: 446 case CHIP_RS100: 447 case CHIP_RV200: 448 case CHIP_RS200: 449 case CHIP_RS300: 450 switch (rec->mask_clk_reg) { 451 case RADEON_GPIO_DVI_DDC: 452 /* no gpio select bit */ 453 break; 454 default: 455 DRM_ERROR("gpio not supported with hw i2c\n"); 456 ret = EINVAL; 457 goto done; 458 } 459 break; 460 case CHIP_R200: 461 /* only bit 4 on r200 */ 462 switch (rec->mask_clk_reg) { 463 case RADEON_GPIO_DVI_DDC: 464 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 465 break; 466 case RADEON_GPIO_MONID: 467 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 468 break; 469 default: 470 DRM_ERROR("gpio not supported with hw i2c\n"); 471 ret = EINVAL; 472 goto done; 473 } 474 break; 475 case CHIP_RV250: 476 case CHIP_RV280: 477 /* bits 3 and 4 */ 478 switch (rec->mask_clk_reg) { 479 case RADEON_GPIO_DVI_DDC: 480 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 481 break; 482 case RADEON_GPIO_VGA_DDC: 483 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 484 break; 485 case RADEON_GPIO_CRT2_DDC: 486 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 487 break; 488 default: 489 DRM_ERROR("gpio not supported with hw i2c\n"); 490 ret = EINVAL; 491 goto done; 492 } 493 break; 494 case CHIP_R300: 495 case CHIP_R350: 496 /* only bit 4 on r300/r350 */ 497 switch (rec->mask_clk_reg) { 498 case RADEON_GPIO_VGA_DDC: 499 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 500 break; 501 case RADEON_GPIO_DVI_DDC: 502 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 503 break; 504 default: 505 DRM_ERROR("gpio not supported with hw i2c\n"); 506 ret = EINVAL; 507 goto done; 508 } 509 break; 510 case CHIP_RV350: 511 case CHIP_RV380: 512 case CHIP_R420: 513 case CHIP_R423: 514 case CHIP_RV410: 515 case CHIP_RS400: 516 case CHIP_RS480: 517 /* bits 3 and 4 */ 518 switch (rec->mask_clk_reg) { 519 case RADEON_GPIO_VGA_DDC: 520 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 521 break; 522 case RADEON_GPIO_DVI_DDC: 523 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 524 break; 525 case RADEON_GPIO_MONID: 526 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 527 break; 528 default: 529 DRM_ERROR("gpio not supported with hw i2c\n"); 530 ret = EINVAL; 531 goto done; 532 } 533 break; 534 default: 535 DRM_ERROR("unsupported asic\n"); 536 ret = EINVAL; 537 goto done; 538 break; 539 } 540 } 541 542 /* check for bus probe */ 543 p = &msgs[0]; 544 if ((num == 1) && (p->len == 0)) { 545 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 546 RADEON_I2C_NACK | 547 RADEON_I2C_HALT | 548 RADEON_I2C_SOFT_RST)); 549 WREG32(i2c_data, (p->slave << 1) & 0xff); 550 WREG32(i2c_data, 0); 551 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 552 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 553 RADEON_I2C_EN | 554 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 555 WREG32(i2c_cntl_0, reg); 556 for (k = 0; k < 32; k++) { 557 udelay(10); 558 tmp = RREG32(i2c_cntl_0); 559 if (tmp & RADEON_I2C_GO) 560 continue; 561 tmp = RREG32(i2c_cntl_0); 562 if (tmp & RADEON_I2C_DONE) 563 break; 564 else { 565 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 566 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 567 ret = EIO; 568 goto done; 569 } 570 } 571 goto done; 572 } 573 574 for (i = 0; i < num; i++) { 575 p = &msgs[i]; 576 for (j = 0; j < p->len; j++) { 577 if (p->flags & IIC_M_RD) { 578 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 579 RADEON_I2C_NACK | 580 RADEON_I2C_HALT | 581 RADEON_I2C_SOFT_RST)); 582 WREG32(i2c_data, ((p->slave << 1) & 0xff) | 0x1); 583 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 584 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 585 RADEON_I2C_EN | 586 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 587 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 588 for (k = 0; k < 32; k++) { 589 udelay(10); 590 tmp = RREG32(i2c_cntl_0); 591 if (tmp & RADEON_I2C_GO) 592 continue; 593 tmp = RREG32(i2c_cntl_0); 594 if (tmp & RADEON_I2C_DONE) 595 break; 596 else { 597 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 598 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 599 ret = EIO; 600 goto done; 601 } 602 } 603 p->buf[j] = RREG32(i2c_data) & 0xff; 604 } else { 605 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 606 RADEON_I2C_NACK | 607 RADEON_I2C_HALT | 608 RADEON_I2C_SOFT_RST)); 609 WREG32(i2c_data, (p->slave << 1) & 0xff); 610 WREG32(i2c_data, p->buf[j]); 611 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 612 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 613 RADEON_I2C_EN | 614 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 615 WREG32(i2c_cntl_0, reg); 616 for (k = 0; k < 32; k++) { 617 udelay(10); 618 tmp = RREG32(i2c_cntl_0); 619 if (tmp & RADEON_I2C_GO) 620 continue; 621 tmp = RREG32(i2c_cntl_0); 622 if (tmp & RADEON_I2C_DONE) 623 break; 624 else { 625 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 626 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 627 ret = EIO; 628 goto done; 629 } 630 } 631 } 632 } 633 } 634 635 done: 636 WREG32(i2c_cntl_0, 0); 637 WREG32(i2c_cntl_1, 0); 638 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 639 RADEON_I2C_NACK | 640 RADEON_I2C_HALT | 641 RADEON_I2C_SOFT_RST)); 642 643 if (rdev->is_atom_bios) { 644 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 645 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 646 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 647 } 648 649 lockmgr(&rdev->pm.mutex, LK_RELEASE); 650 lockmgr(&rdev->dc_hw_i2c_mutex, LK_RELEASE); 651 652 return ret; 653 } 654 655 /* hw i2c engine for r5xx hardware 656 * hw can buffer up to 15 bytes 657 */ 658 static int r500_hw_i2c_xfer(struct radeon_i2c_chan *i2c, 659 struct iic_msg *msgs, int num) 660 { 661 struct radeon_device *rdev = i2c->dev->dev_private; 662 struct radeon_i2c_bus_rec *rec = &i2c->rec; 663 struct iic_msg *p; 664 int i, j, remaining, current_count, buffer_offset, ret = 0; 665 u32 prescale; 666 u32 tmp, reg; 667 u32 saved1, saved2; 668 669 lockmgr(&rdev->dc_hw_i2c_mutex, LK_EXCLUSIVE); 670 /* take the pm lock since we need a constant sclk */ 671 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE); 672 673 prescale = radeon_get_i2c_prescale(rdev); 674 675 /* clear gpio mask bits */ 676 tmp = RREG32(rec->mask_clk_reg); 677 tmp &= ~rec->mask_clk_mask; 678 WREG32(rec->mask_clk_reg, tmp); 679 tmp = RREG32(rec->mask_clk_reg); 680 681 tmp = RREG32(rec->mask_data_reg); 682 tmp &= ~rec->mask_data_mask; 683 WREG32(rec->mask_data_reg, tmp); 684 tmp = RREG32(rec->mask_data_reg); 685 686 /* clear pin values */ 687 tmp = RREG32(rec->a_clk_reg); 688 tmp &= ~rec->a_clk_mask; 689 WREG32(rec->a_clk_reg, tmp); 690 tmp = RREG32(rec->a_clk_reg); 691 692 tmp = RREG32(rec->a_data_reg); 693 tmp &= ~rec->a_data_mask; 694 WREG32(rec->a_data_reg, tmp); 695 tmp = RREG32(rec->a_data_reg); 696 697 /* set the pins to input */ 698 tmp = RREG32(rec->en_clk_reg); 699 tmp &= ~rec->en_clk_mask; 700 WREG32(rec->en_clk_reg, tmp); 701 tmp = RREG32(rec->en_clk_reg); 702 703 tmp = RREG32(rec->en_data_reg); 704 tmp &= ~rec->en_data_mask; 705 WREG32(rec->en_data_reg, tmp); 706 tmp = RREG32(rec->en_data_reg); 707 708 /* */ 709 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 710 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 711 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 712 saved2 = RREG32(0x494); 713 WREG32(0x494, saved2 | 0x1); 714 715 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 716 for (i = 0; i < 50; i++) { 717 udelay(1); 718 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 719 break; 720 } 721 if (i == 50) { 722 DRM_ERROR("failed to get i2c bus\n"); 723 ret = EBUSY; 724 goto done; 725 } 726 727 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 728 switch (rec->mask_clk_reg) { 729 case AVIVO_DC_GPIO_DDC1_MASK: 730 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 731 break; 732 case AVIVO_DC_GPIO_DDC2_MASK: 733 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 734 break; 735 case AVIVO_DC_GPIO_DDC3_MASK: 736 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 737 break; 738 default: 739 DRM_ERROR("gpio not supported with hw i2c\n"); 740 ret = EINVAL; 741 goto done; 742 } 743 744 /* check for bus probe */ 745 p = &msgs[0]; 746 if ((num == 1) && (p->len == 0)) { 747 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 748 AVIVO_DC_I2C_NACK | 749 AVIVO_DC_I2C_HALT)); 750 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 751 udelay(1); 752 WREG32(AVIVO_DC_I2C_RESET, 0); 753 754 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff); 755 WREG32(AVIVO_DC_I2C_DATA, 0); 756 757 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 758 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 759 AVIVO_DC_I2C_DATA_COUNT(1) | 760 (prescale << 16))); 761 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 762 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 763 for (j = 0; j < 200; j++) { 764 udelay(50); 765 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 766 if (tmp & AVIVO_DC_I2C_GO) 767 continue; 768 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 769 if (tmp & AVIVO_DC_I2C_DONE) 770 break; 771 else { 772 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 773 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 774 ret = EIO; 775 goto done; 776 } 777 } 778 goto done; 779 } 780 781 for (i = 0; i < num; i++) { 782 p = &msgs[i]; 783 remaining = p->len; 784 buffer_offset = 0; 785 if (p->flags & IIC_M_RD) { 786 while (remaining) { 787 if (remaining > 15) 788 current_count = 15; 789 else 790 current_count = remaining; 791 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 792 AVIVO_DC_I2C_NACK | 793 AVIVO_DC_I2C_HALT)); 794 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 795 udelay(1); 796 WREG32(AVIVO_DC_I2C_RESET, 0); 797 798 WREG32(AVIVO_DC_I2C_DATA, ((p->slave << 1) & 0xff) | 0x1); 799 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 800 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 801 AVIVO_DC_I2C_DATA_COUNT(current_count) | 802 (prescale << 16))); 803 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 804 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 805 for (j = 0; j < 200; j++) { 806 udelay(50); 807 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 808 if (tmp & AVIVO_DC_I2C_GO) 809 continue; 810 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 811 if (tmp & AVIVO_DC_I2C_DONE) 812 break; 813 else { 814 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 815 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 816 ret = EIO; 817 goto done; 818 } 819 } 820 for (j = 0; j < current_count; j++) 821 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 822 remaining -= current_count; 823 buffer_offset += current_count; 824 } 825 } else { 826 while (remaining) { 827 if (remaining > 15) 828 current_count = 15; 829 else 830 current_count = remaining; 831 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 832 AVIVO_DC_I2C_NACK | 833 AVIVO_DC_I2C_HALT)); 834 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 835 udelay(1); 836 WREG32(AVIVO_DC_I2C_RESET, 0); 837 838 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff); 839 for (j = 0; j < current_count; j++) 840 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 841 842 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 843 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 844 AVIVO_DC_I2C_DATA_COUNT(current_count) | 845 (prescale << 16))); 846 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 847 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 848 for (j = 0; j < 200; j++) { 849 udelay(50); 850 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 851 if (tmp & AVIVO_DC_I2C_GO) 852 continue; 853 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 854 if (tmp & AVIVO_DC_I2C_DONE) 855 break; 856 else { 857 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 858 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 859 ret = EIO; 860 goto done; 861 } 862 } 863 remaining -= current_count; 864 buffer_offset += current_count; 865 } 866 } 867 } 868 869 done: 870 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 871 AVIVO_DC_I2C_NACK | 872 AVIVO_DC_I2C_HALT)); 873 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 874 udelay(1); 875 WREG32(AVIVO_DC_I2C_RESET, 0); 876 877 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 878 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 879 WREG32(0x494, saved2); 880 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 881 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 882 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 883 884 lockmgr(&rdev->pm.mutex, LK_RELEASE); 885 lockmgr(&rdev->dc_hw_i2c_mutex, LK_RELEASE); 886 887 return ret; 888 } 889 890 static int radeon_hw_i2c_xfer(device_t dev, 891 struct iic_msg *msgs, uint32_t num) 892 { 893 struct radeon_i2c_chan *i2c = device_get_softc(dev); 894 struct radeon_device *rdev = i2c->dev->dev_private; 895 struct radeon_i2c_bus_rec *rec = &i2c->rec; 896 int ret = 0; 897 898 lockmgr(&i2c->mutex, LK_EXCLUSIVE); 899 900 switch (rdev->family) { 901 case CHIP_R100: 902 case CHIP_RV100: 903 case CHIP_RS100: 904 case CHIP_RV200: 905 case CHIP_RS200: 906 case CHIP_R200: 907 case CHIP_RV250: 908 case CHIP_RS300: 909 case CHIP_RV280: 910 case CHIP_R300: 911 case CHIP_R350: 912 case CHIP_RV350: 913 case CHIP_RV380: 914 case CHIP_R420: 915 case CHIP_R423: 916 case CHIP_RV410: 917 case CHIP_RS400: 918 case CHIP_RS480: 919 ret = r100_hw_i2c_xfer(i2c, msgs, num); 920 break; 921 case CHIP_RS600: 922 case CHIP_RS690: 923 case CHIP_RS740: 924 /* XXX fill in hw i2c implementation */ 925 break; 926 case CHIP_RV515: 927 case CHIP_R520: 928 case CHIP_RV530: 929 case CHIP_RV560: 930 case CHIP_RV570: 931 case CHIP_R580: 932 if (rec->mm_i2c) 933 ret = r100_hw_i2c_xfer(i2c, msgs, num); 934 else 935 ret = r500_hw_i2c_xfer(i2c, msgs, num); 936 break; 937 case CHIP_R600: 938 case CHIP_RV610: 939 case CHIP_RV630: 940 case CHIP_RV670: 941 /* XXX fill in hw i2c implementation */ 942 break; 943 case CHIP_RV620: 944 case CHIP_RV635: 945 case CHIP_RS780: 946 case CHIP_RS880: 947 case CHIP_RV770: 948 case CHIP_RV730: 949 case CHIP_RV710: 950 case CHIP_RV740: 951 /* XXX fill in hw i2c implementation */ 952 break; 953 case CHIP_CEDAR: 954 case CHIP_REDWOOD: 955 case CHIP_JUNIPER: 956 case CHIP_CYPRESS: 957 case CHIP_HEMLOCK: 958 /* XXX fill in hw i2c implementation */ 959 break; 960 default: 961 DRM_ERROR("i2c: unhandled radeon chip\n"); 962 ret = EIO; 963 break; 964 } 965 966 lockmgr(&i2c->mutex, LK_RELEASE); 967 968 return ret; 969 } 970 971 static int 972 radeon_hw_i2c_probe(device_t dev) 973 { 974 975 return (BUS_PROBE_SPECIFIC); 976 } 977 978 static int 979 radeon_hw_i2c_attach(device_t dev) 980 { 981 struct radeon_i2c_chan *i2c; 982 device_t iic_dev; 983 984 i2c = device_get_softc(dev); 985 device_set_desc(dev, i2c->name); 986 987 /* add generic bit-banging code */ 988 iic_dev = device_add_child(dev, "iicbus", -1); 989 if (iic_dev == NULL) 990 return (ENXIO); 991 device_quiet(iic_dev); 992 993 /* attach and probe added child */ 994 bus_generic_attach(dev); 995 996 return (0); 997 } 998 999 static int 1000 radeon_hw_i2c_detach(device_t dev) 1001 { 1002 1003 /* detach bit-banding code. */ 1004 bus_generic_detach(dev); 1005 1006 /* delete bit-banding code. */ 1007 device_delete_children(dev); 1008 return (0); 1009 } 1010 1011 static int 1012 radeon_hw_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 1013 { 1014 1015 /* Not sure what to do here. */ 1016 return 0; 1017 } 1018 1019 1020 static device_method_t radeon_hw_i2c_methods[] = { 1021 DEVMETHOD(device_probe, radeon_hw_i2c_probe), 1022 DEVMETHOD(device_attach, radeon_hw_i2c_attach), 1023 DEVMETHOD(device_detach, radeon_hw_i2c_detach), 1024 DEVMETHOD(iicbus_reset, radeon_hw_i2c_reset), 1025 DEVMETHOD(iicbus_transfer, radeon_hw_i2c_xfer), 1026 DEVMETHOD_END 1027 }; 1028 1029 static driver_t radeon_hw_i2c_driver = { 1030 "radeon_hw_i2c", 1031 radeon_hw_i2c_methods, 1032 0 /* softc will be allocated by parent */ 1033 }; 1034 1035 static devclass_t radeon_hw_i2c_devclass; 1036 DRIVER_MODULE_ORDERED(radeon_hw_i2c, drm, radeon_hw_i2c_driver, 1037 radeon_hw_i2c_devclass, NULL, NULL, SI_ORDER_FIRST); 1038 DRIVER_MODULE(iicbus, radeon_hw_i2c, iicbus_driver, iicbus_devclass, NULL, NULL); 1039 1040 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 1041 struct radeon_i2c_bus_rec *rec, 1042 const char *name) 1043 { 1044 struct radeon_device *rdev = dev->dev_private; 1045 struct radeon_i2c_chan *i2c; 1046 device_t iicbus_dev; 1047 int ret; 1048 1049 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 1050 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 1051 return NULL; 1052 1053 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1054 if (i2c == NULL) 1055 return NULL; 1056 1057 /* 1058 * Grab Giant before messing with newbus devices, just in case 1059 * we do not hold it already. 1060 */ 1061 get_mplock(); 1062 1063 i2c->rec = *rec; 1064 i2c->dev = dev; 1065 lockinit(&i2c->mutex, "ri2cmtx", 0, LK_CANRECURSE); 1066 if (rec->mm_i2c || 1067 (rec->hw_capable && 1068 radeon_hw_i2c && 1069 ((rdev->family <= CHIP_RS480) || 1070 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 1071 /* set the radeon hw i2c adapter */ 1072 ksnprintf(i2c->name, sizeof(i2c->name), 1073 "Radeon i2c hw bus %s", name); 1074 iicbus_dev = device_add_child(dev->dev, "radeon_hw_i2c", -1); 1075 if (iicbus_dev == NULL) { 1076 DRM_ERROR("Failed to create bridge for hw i2c %s\n", 1077 name); 1078 goto out_free; 1079 } 1080 device_quiet(iicbus_dev); 1081 device_set_softc(iicbus_dev, i2c); 1082 1083 ret = device_probe_and_attach(iicbus_dev); 1084 if (ret != 0) { 1085 DRM_ERROR("Attach failed for bridge for hw i2c %s\n", 1086 name); 1087 device_delete_child(dev->dev, iicbus_dev); 1088 goto out_free; 1089 } 1090 1091 i2c->adapter = device_find_child(iicbus_dev, "iicbus", -1); 1092 if (i2c->adapter == NULL) { 1093 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n"); 1094 device_delete_child(dev->dev, iicbus_dev); 1095 goto out_free; 1096 } 1097 } else if (rec->hw_capable && 1098 radeon_hw_i2c && 1099 ASIC_IS_DCE3(rdev)) { 1100 /* hw i2c using atom */ 1101 ksnprintf(i2c->name, sizeof(i2c->name), 1102 "Radeon i2c hw bus %s", name); 1103 iicbus_dev = device_add_child(dev->dev, "radeon_atom_hw_i2c", -1); 1104 if (iicbus_dev == NULL) { 1105 DRM_ERROR("Failed to create bridge for hw i2c %s\n", 1106 name); 1107 goto out_free; 1108 } 1109 device_quiet(iicbus_dev); 1110 device_set_softc(iicbus_dev, i2c); 1111 1112 ret = device_probe_and_attach(iicbus_dev); 1113 if (ret != 0) { 1114 DRM_ERROR("Attach failed for bridge for hw i2c %s\n", 1115 name); 1116 device_delete_child(dev->dev, iicbus_dev); 1117 goto out_free; 1118 } 1119 1120 i2c->adapter = device_find_child(iicbus_dev, "iicbus", -1); 1121 if (i2c->adapter == NULL) { 1122 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n"); 1123 device_delete_child(dev->dev, iicbus_dev); 1124 goto out_free; 1125 } 1126 } else { 1127 device_t iicbb_dev; 1128 1129 /* set the radeon bit adapter */ 1130 ksnprintf(i2c->name, sizeof(i2c->name), 1131 "Radeon i2c bit bus %s", name); 1132 iicbus_dev = device_add_child(dev->dev, "radeon_iicbb", -1); 1133 if (iicbus_dev == NULL) { 1134 DRM_ERROR("Failed to create bridge for bb i2c %s\n", 1135 name); 1136 goto out_free; 1137 } 1138 device_quiet(iicbus_dev); 1139 device_set_softc(iicbus_dev, i2c); 1140 1141 ret = device_probe_and_attach(iicbus_dev); 1142 if (ret != 0) { 1143 DRM_ERROR("Attach failed for bridge for bb i2c %s\n", 1144 name); 1145 device_delete_child(dev->dev, iicbus_dev); 1146 goto out_free; 1147 } 1148 1149 iicbb_dev = device_find_child(iicbus_dev, "iicbb", -1); 1150 if (iicbb_dev == NULL) { 1151 DRM_ERROR("bb i2c bridge doesn't have iicbb child\n"); 1152 device_delete_child(dev->dev, iicbus_dev); 1153 goto out_free; 1154 } 1155 1156 i2c->adapter = device_find_child(iicbb_dev, "iicbus", -1); 1157 if (i2c->adapter == NULL) { 1158 DRM_ERROR( 1159 "bbbus bridge doesn't have iicbus grandchild\n"); 1160 device_delete_child(dev->dev, iicbus_dev); 1161 goto out_free; 1162 } 1163 } 1164 1165 i2c->iic_bus = iicbus_dev; 1166 1167 rel_mplock(); 1168 1169 return i2c; 1170 out_free: 1171 rel_mplock(); 1172 kfree(i2c); 1173 return NULL; 1174 1175 } 1176 1177 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 1178 struct radeon_i2c_bus_rec *rec, 1179 const char *name) 1180 { 1181 struct radeon_i2c_chan *i2c; 1182 int ret; 1183 1184 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1185 if (i2c == NULL) 1186 return NULL; 1187 1188 i2c->rec = *rec; 1189 i2c->dev = dev; 1190 ksnprintf(i2c->name, sizeof(i2c->name), "Radeon aux bus %s", name); 1191 ret = iic_dp_aux_add_bus(dev->dev, i2c->name, 1192 radeon_dp_i2c_aux_ch, i2c, &i2c->iic_bus, 1193 &i2c->adapter); 1194 if (ret) { 1195 DRM_INFO("Failed to register i2c %s\n", name); 1196 goto out_free; 1197 } 1198 1199 return i2c; 1200 out_free: 1201 kfree(i2c); 1202 return NULL; 1203 1204 } 1205 1206 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1207 { 1208 if (!i2c) 1209 return; 1210 if (i2c->iic_bus != NULL) { 1211 int ret; 1212 1213 get_mplock(); 1214 ret = device_delete_child(i2c->dev->dev, i2c->iic_bus); 1215 rel_mplock(); 1216 KASSERT(ret == 0, ("unable to detach iic bus %s: %d", 1217 i2c->name, ret)); 1218 } 1219 kfree(i2c); 1220 } 1221 1222 /* Add the default buses */ 1223 void radeon_i2c_init(struct radeon_device *rdev) 1224 { 1225 if (radeon_hw_i2c) 1226 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1227 1228 if (rdev->is_atom_bios) 1229 radeon_atombios_i2c_init(rdev); 1230 else 1231 radeon_combios_i2c_init(rdev); 1232 } 1233 1234 /* remove all the buses */ 1235 void radeon_i2c_fini(struct radeon_device *rdev) 1236 { 1237 int i; 1238 1239 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1240 if (rdev->i2c_bus[i]) { 1241 radeon_i2c_destroy(rdev->i2c_bus[i]); 1242 rdev->i2c_bus[i] = NULL; 1243 } 1244 } 1245 } 1246 1247 /* Add additional buses */ 1248 void radeon_i2c_add(struct radeon_device *rdev, 1249 struct radeon_i2c_bus_rec *rec, 1250 const char *name) 1251 { 1252 struct drm_device *dev = rdev->ddev; 1253 int i; 1254 1255 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1256 if (!rdev->i2c_bus[i]) { 1257 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1258 return; 1259 } 1260 } 1261 } 1262 1263 /* looks up bus based on id */ 1264 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1265 struct radeon_i2c_bus_rec *i2c_bus) 1266 { 1267 int i; 1268 1269 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1270 if (rdev->i2c_bus[i] && 1271 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1272 return rdev->i2c_bus[i]; 1273 } 1274 } 1275 return NULL; 1276 } 1277 1278 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1279 u8 slave_addr, 1280 u8 addr, 1281 u8 *val) 1282 { 1283 u8 out_buf[2]; 1284 u8 in_buf[2]; 1285 struct iic_msg msgs[] = { 1286 { 1287 .slave = slave_addr << 1, 1288 .flags = 0, 1289 .len = 1, 1290 .buf = out_buf, 1291 }, 1292 { 1293 .slave = slave_addr << 1, 1294 .flags = IIC_M_RD, 1295 .len = 1, 1296 .buf = in_buf, 1297 } 1298 }; 1299 1300 out_buf[0] = addr; 1301 out_buf[1] = 0; 1302 1303 if (iicbus_transfer(i2c_bus->adapter, msgs, 2) == 0) { 1304 *val = in_buf[0]; 1305 DRM_DEBUG("val = 0x%02x\n", *val); 1306 } else { 1307 *val = 0; /* avoid gcc warning */ 1308 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1309 addr, *val); 1310 } 1311 } 1312 1313 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1314 u8 slave_addr, 1315 u8 addr, 1316 u8 val) 1317 { 1318 uint8_t out_buf[2]; 1319 struct iic_msg msg = { 1320 .slave = slave_addr << 1, 1321 .flags = 0, 1322 .len = 2, 1323 .buf = out_buf, 1324 }; 1325 1326 out_buf[0] = addr; 1327 out_buf[1] = val; 1328 1329 if (iicbus_transfer(i2c_bus->adapter, &msg, 1) != 0) 1330 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1331 addr, val); 1332 } 1333 1334 /* ddc router switching */ 1335 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1336 { 1337 u8 val; 1338 1339 if (!radeon_connector->router.ddc_valid) 1340 return; 1341 1342 if (!radeon_connector->router_bus) 1343 return; 1344 1345 radeon_i2c_get_byte(radeon_connector->router_bus, 1346 radeon_connector->router.i2c_addr, 1347 0x3, &val); 1348 val &= ~radeon_connector->router.ddc_mux_control_pin; 1349 radeon_i2c_put_byte(radeon_connector->router_bus, 1350 radeon_connector->router.i2c_addr, 1351 0x3, val); 1352 radeon_i2c_get_byte(radeon_connector->router_bus, 1353 radeon_connector->router.i2c_addr, 1354 0x1, &val); 1355 val &= ~radeon_connector->router.ddc_mux_control_pin; 1356 val |= radeon_connector->router.ddc_mux_state; 1357 radeon_i2c_put_byte(radeon_connector->router_bus, 1358 radeon_connector->router.i2c_addr, 1359 0x1, val); 1360 } 1361 1362 /* clock/data router switching */ 1363 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1364 { 1365 u8 val; 1366 1367 if (!radeon_connector->router.cd_valid) 1368 return; 1369 1370 if (!radeon_connector->router_bus) 1371 return; 1372 1373 radeon_i2c_get_byte(radeon_connector->router_bus, 1374 radeon_connector->router.i2c_addr, 1375 0x3, &val); 1376 val &= ~radeon_connector->router.cd_mux_control_pin; 1377 radeon_i2c_put_byte(radeon_connector->router_bus, 1378 radeon_connector->router.i2c_addr, 1379 0x3, val); 1380 radeon_i2c_get_byte(radeon_connector->router_bus, 1381 radeon_connector->router.i2c_addr, 1382 0x1, &val); 1383 val &= ~radeon_connector->router.cd_mux_control_pin; 1384 val |= radeon_connector->router.cd_mux_state; 1385 radeon_i2c_put_byte(radeon_connector->router_bus, 1386 radeon_connector->router.i2c_addr, 1387 0x1, val); 1388 } 1389 1390