1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_i2c.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_edid.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include <bus/iicbus/iic.h> 33 #include <bus/iicbus/iiconf.h> 34 #include <bus/iicbus/iicbus.h> 35 #include <sys/mplock2.h> 36 #include "radeon.h" 37 #include "atom.h" 38 #include "iicbus_if.h" 39 #include "iicbb_if.h" 40 41 /** 42 * radeon_ddc_probe 43 * 44 */ 45 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 46 { 47 u8 out = 0x0; 48 u8 buf[8]; 49 int ret; 50 struct iic_msg msgs[] = { 51 { 52 .slave = DDC_ADDR << 1, 53 .flags = 0, 54 .len = 1, 55 .buf = &out, 56 }, 57 { 58 .slave = DDC_ADDR << 1, 59 .flags = IIC_M_RD, 60 .len = 8, 61 .buf = buf, 62 } 63 }; 64 65 /* on hw with routers, select right port */ 66 if (radeon_connector->router.ddc_valid) 67 radeon_router_select_ddc_port(radeon_connector); 68 69 if (use_aux) { 70 ret = iicbus_transfer(radeon_connector->ddc_bus->aux.dev->bsddev, msgs, 2); 71 } else { 72 ret = iicbus_transfer(radeon_connector->ddc_bus->adapter_dev, msgs, 2); 73 } 74 75 if (ret != 0) 76 /* Couldn't find an accessible DDC on this connector */ 77 return false; 78 /* Probe also for valid EDID header 79 * EDID header starts with: 80 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 81 * Only the first 6 bytes must be valid as 82 * drm_edid_block_valid() can fix the last 2 bytes */ 83 if (drm_edid_header_is_valid(buf) < 6) { 84 /* Couldn't find an accessible EDID on this 85 * connector */ 86 return false; 87 } 88 return true; 89 } 90 91 /* bit banging i2c */ 92 93 static int radeon_iicbb_pre_xfer(device_t dev) 94 { 95 struct radeon_i2c_chan *i2c = device_get_softc(dev); 96 struct radeon_device *rdev = i2c->dev->dev_private; 97 struct radeon_i2c_bus_rec *rec = &i2c->rec; 98 uint32_t temp; 99 100 mutex_lock(&i2c->mutex); 101 102 /* RV410 appears to have a bug where the hw i2c in reset 103 * holds the i2c port in a bad state - switch hw i2c away before 104 * doing DDC - do this for all r200s/r300s/r400s for safety sake 105 */ 106 if (rec->hw_capable) { 107 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 108 u32 reg; 109 110 if (rdev->family >= CHIP_RV350) 111 reg = RADEON_GPIO_MONID; 112 else if ((rdev->family == CHIP_R300) || 113 (rdev->family == CHIP_R350)) 114 reg = RADEON_GPIO_DVI_DDC; 115 else 116 reg = RADEON_GPIO_CRT2_DDC; 117 118 mutex_lock(&rdev->dc_hw_i2c_mutex); 119 if (rec->a_clk_reg == reg) { 120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 121 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 122 } else { 123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 124 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 125 } 126 mutex_unlock(&rdev->dc_hw_i2c_mutex); 127 } 128 } 129 130 /* switch the pads to ddc mode */ 131 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 132 temp = RREG32(rec->mask_clk_reg); 133 temp &= ~(1 << 16); 134 WREG32(rec->mask_clk_reg, temp); 135 } 136 137 /* clear the output pin values */ 138 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 139 WREG32(rec->a_clk_reg, temp); 140 141 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 142 WREG32(rec->a_data_reg, temp); 143 144 /* set the pins to input */ 145 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 146 WREG32(rec->en_clk_reg, temp); 147 148 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 149 WREG32(rec->en_data_reg, temp); 150 151 /* mask the gpio pins for software use */ 152 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 153 WREG32(rec->mask_clk_reg, temp); 154 temp = RREG32(rec->mask_clk_reg); 155 156 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 157 WREG32(rec->mask_data_reg, temp); 158 temp = RREG32(rec->mask_data_reg); 159 160 return 0; 161 } 162 163 static void radeon_iicbb_post_xfer(device_t dev) 164 { 165 struct radeon_i2c_chan *i2c = device_get_softc(dev); 166 struct radeon_device *rdev = i2c->dev->dev_private; 167 struct radeon_i2c_bus_rec *rec = &i2c->rec; 168 uint32_t temp; 169 170 /* unmask the gpio pins for software use */ 171 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 172 WREG32(rec->mask_clk_reg, temp); 173 temp = RREG32(rec->mask_clk_reg); 174 175 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 176 WREG32(rec->mask_data_reg, temp); 177 temp = RREG32(rec->mask_data_reg); 178 179 mutex_unlock(&i2c->mutex); 180 } 181 182 static int radeon_iicbb_get_clock(device_t dev) 183 { 184 struct radeon_i2c_chan *i2c = device_get_softc(dev); 185 struct radeon_device *rdev = i2c->dev->dev_private; 186 struct radeon_i2c_bus_rec *rec = &i2c->rec; 187 uint32_t val; 188 189 /* read the value off the pin */ 190 val = RREG32(rec->y_clk_reg); 191 val &= rec->y_clk_mask; 192 193 return (val != 0); 194 } 195 196 197 static int radeon_iicbb_get_data(device_t dev) 198 { 199 struct radeon_i2c_chan *i2c = device_get_softc(dev); 200 struct radeon_device *rdev = i2c->dev->dev_private; 201 struct radeon_i2c_bus_rec *rec = &i2c->rec; 202 uint32_t val; 203 204 /* read the value off the pin */ 205 val = RREG32(rec->y_data_reg); 206 val &= rec->y_data_mask; 207 208 return (val != 0); 209 } 210 211 static void radeon_iicbb_set_clock(device_t dev, int clock) 212 { 213 struct radeon_i2c_chan *i2c = device_get_softc(dev); 214 struct radeon_device *rdev = i2c->dev->dev_private; 215 struct radeon_i2c_bus_rec *rec = &i2c->rec; 216 uint32_t val; 217 218 /* set pin direction */ 219 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 220 val |= clock ? 0 : rec->en_clk_mask; 221 WREG32(rec->en_clk_reg, val); 222 } 223 224 static void radeon_iicbb_set_data(device_t dev, int data) 225 { 226 struct radeon_i2c_chan *i2c = device_get_softc(dev); 227 struct radeon_device *rdev = i2c->dev->dev_private; 228 struct radeon_i2c_bus_rec *rec = &i2c->rec; 229 uint32_t val; 230 231 /* set pin direction */ 232 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 233 val |= data ? 0 : rec->en_data_mask; 234 WREG32(rec->en_data_reg, val); 235 } 236 237 static int 238 radeon_iicbb_probe(device_t dev) 239 { 240 241 return (BUS_PROBE_DEFAULT); 242 } 243 244 static int 245 radeon_iicbb_attach(device_t dev) 246 { 247 struct radeon_i2c_chan *i2c; 248 device_t iic_dev; 249 250 i2c = device_get_softc(dev); 251 device_set_desc(dev, i2c->name); 252 253 /* add generic bit-banging code */ 254 iic_dev = device_add_child(dev, "iicbb", -1); 255 if (iic_dev == NULL) 256 return (ENXIO); 257 device_quiet(iic_dev); 258 259 /* attach and probe added child */ 260 bus_generic_attach(dev); 261 262 return (0); 263 } 264 265 static int 266 radeon_iicbb_detach(device_t dev) 267 { 268 269 /* detach bit-banding code. */ 270 bus_generic_detach(dev); 271 272 /* delete bit-banding code. */ 273 device_delete_children(dev); 274 return (0); 275 } 276 277 static int 278 radeon_iicbb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 279 { 280 281 /* Not sure what to do here. */ 282 return 0; 283 } 284 285 static device_method_t radeon_iicbb_methods[] = { 286 DEVMETHOD(device_probe, radeon_iicbb_probe), 287 DEVMETHOD(device_attach, radeon_iicbb_attach), 288 DEVMETHOD(device_detach, radeon_iicbb_detach), 289 290 DEVMETHOD(bus_add_child, bus_generic_add_child), 291 DEVMETHOD(bus_print_child, bus_generic_print_child), 292 293 DEVMETHOD(iicbb_reset, radeon_iicbb_reset), 294 DEVMETHOD(iicbb_pre_xfer, radeon_iicbb_pre_xfer), 295 DEVMETHOD(iicbb_post_xfer, radeon_iicbb_post_xfer), 296 DEVMETHOD(iicbb_setsda, radeon_iicbb_set_data), 297 DEVMETHOD(iicbb_setscl, radeon_iicbb_set_clock), 298 DEVMETHOD(iicbb_getsda, radeon_iicbb_get_data), 299 DEVMETHOD(iicbb_getscl, radeon_iicbb_get_clock), 300 DEVMETHOD_END 301 }; 302 303 static driver_t radeon_iicbb_driver = { 304 "radeon_iicbb", 305 radeon_iicbb_methods, 306 0 /* softc will be allocated by parent */ 307 }; 308 static devclass_t radeon_iicbb_devclass; 309 DRIVER_MODULE_ORDERED(radeon_iicbb, drm, radeon_iicbb_driver, 310 radeon_iicbb_devclass, NULL, NULL, SI_ORDER_FIRST); 311 DRIVER_MODULE(iicbb, radeon_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 312 313 /* hw i2c */ 314 315 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 316 { 317 u32 sclk = rdev->pm.current_sclk; 318 u32 prescale = 0; 319 u32 nm; 320 u8 n, m, loop; 321 int i2c_clock; 322 323 switch (rdev->family) { 324 case CHIP_R100: 325 case CHIP_RV100: 326 case CHIP_RS100: 327 case CHIP_RV200: 328 case CHIP_RS200: 329 case CHIP_R200: 330 case CHIP_RV250: 331 case CHIP_RS300: 332 case CHIP_RV280: 333 case CHIP_R300: 334 case CHIP_R350: 335 case CHIP_RV350: 336 i2c_clock = 60; 337 nm = (sclk * 10) / (i2c_clock * 4); 338 for (loop = 1; loop < 255; loop++) { 339 if ((nm / loop) < loop) 340 break; 341 } 342 n = loop - 1; 343 m = loop - 2; 344 prescale = m | (n << 8); 345 break; 346 case CHIP_RV380: 347 case CHIP_RS400: 348 case CHIP_RS480: 349 case CHIP_R420: 350 case CHIP_R423: 351 case CHIP_RV410: 352 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 353 break; 354 case CHIP_RS600: 355 case CHIP_RS690: 356 case CHIP_RS740: 357 /* todo */ 358 break; 359 case CHIP_RV515: 360 case CHIP_R520: 361 case CHIP_RV530: 362 case CHIP_RV560: 363 case CHIP_RV570: 364 case CHIP_R580: 365 i2c_clock = 50; 366 if (rdev->family == CHIP_R520) 367 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 368 else 369 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 370 break; 371 case CHIP_R600: 372 case CHIP_RV610: 373 case CHIP_RV630: 374 case CHIP_RV670: 375 /* todo */ 376 break; 377 case CHIP_RV620: 378 case CHIP_RV635: 379 case CHIP_RS780: 380 case CHIP_RS880: 381 case CHIP_RV770: 382 case CHIP_RV730: 383 case CHIP_RV710: 384 case CHIP_RV740: 385 /* todo */ 386 break; 387 case CHIP_CEDAR: 388 case CHIP_REDWOOD: 389 case CHIP_JUNIPER: 390 case CHIP_CYPRESS: 391 case CHIP_HEMLOCK: 392 /* todo */ 393 break; 394 default: 395 DRM_ERROR("i2c: unhandled radeon chip\n"); 396 break; 397 } 398 return prescale; 399 } 400 401 402 /* hw i2c engine for r1xx-4xx hardware 403 * hw can buffer up to 15 bytes 404 */ 405 static int r100_hw_i2c_xfer(struct radeon_i2c_chan *i2c, 406 struct iic_msg *msgs, int num) 407 { 408 struct radeon_device *rdev = i2c->dev->dev_private; 409 struct radeon_i2c_bus_rec *rec = &i2c->rec; 410 struct iic_msg *p; 411 int i, j, k, ret = 0; 412 u32 prescale; 413 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 414 u32 tmp, reg; 415 416 mutex_lock(&rdev->dc_hw_i2c_mutex); 417 /* take the pm lock since we need a constant sclk */ 418 mutex_lock(&rdev->pm.mutex); 419 420 prescale = radeon_get_i2c_prescale(rdev); 421 422 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 423 RADEON_I2C_DRIVE_EN | 424 RADEON_I2C_START | 425 RADEON_I2C_STOP | 426 RADEON_I2C_GO); 427 428 if (rdev->is_atom_bios) { 429 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 430 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 431 } 432 433 if (rec->mm_i2c) { 434 i2c_cntl_0 = RADEON_I2C_CNTL_0; 435 i2c_cntl_1 = RADEON_I2C_CNTL_1; 436 i2c_data = RADEON_I2C_DATA; 437 } else { 438 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 439 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 440 i2c_data = RADEON_DVI_I2C_DATA; 441 442 switch (rdev->family) { 443 case CHIP_R100: 444 case CHIP_RV100: 445 case CHIP_RS100: 446 case CHIP_RV200: 447 case CHIP_RS200: 448 case CHIP_RS300: 449 switch (rec->mask_clk_reg) { 450 case RADEON_GPIO_DVI_DDC: 451 /* no gpio select bit */ 452 break; 453 default: 454 DRM_ERROR("gpio not supported with hw i2c\n"); 455 ret = EINVAL; 456 goto done; 457 } 458 break; 459 case CHIP_R200: 460 /* only bit 4 on r200 */ 461 switch (rec->mask_clk_reg) { 462 case RADEON_GPIO_DVI_DDC: 463 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 464 break; 465 case RADEON_GPIO_MONID: 466 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 467 break; 468 default: 469 DRM_ERROR("gpio not supported with hw i2c\n"); 470 ret = EINVAL; 471 goto done; 472 } 473 break; 474 case CHIP_RV250: 475 case CHIP_RV280: 476 /* bits 3 and 4 */ 477 switch (rec->mask_clk_reg) { 478 case RADEON_GPIO_DVI_DDC: 479 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 480 break; 481 case RADEON_GPIO_VGA_DDC: 482 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 483 break; 484 case RADEON_GPIO_CRT2_DDC: 485 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 486 break; 487 default: 488 DRM_ERROR("gpio not supported with hw i2c\n"); 489 ret = EINVAL; 490 goto done; 491 } 492 break; 493 case CHIP_R300: 494 case CHIP_R350: 495 /* only bit 4 on r300/r350 */ 496 switch (rec->mask_clk_reg) { 497 case RADEON_GPIO_VGA_DDC: 498 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 499 break; 500 case RADEON_GPIO_DVI_DDC: 501 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 502 break; 503 default: 504 DRM_ERROR("gpio not supported with hw i2c\n"); 505 ret = EINVAL; 506 goto done; 507 } 508 break; 509 case CHIP_RV350: 510 case CHIP_RV380: 511 case CHIP_R420: 512 case CHIP_R423: 513 case CHIP_RV410: 514 case CHIP_RS400: 515 case CHIP_RS480: 516 /* bits 3 and 4 */ 517 switch (rec->mask_clk_reg) { 518 case RADEON_GPIO_VGA_DDC: 519 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 520 break; 521 case RADEON_GPIO_DVI_DDC: 522 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 523 break; 524 case RADEON_GPIO_MONID: 525 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 526 break; 527 default: 528 DRM_ERROR("gpio not supported with hw i2c\n"); 529 ret = EINVAL; 530 goto done; 531 } 532 break; 533 default: 534 DRM_ERROR("unsupported asic\n"); 535 ret = EINVAL; 536 goto done; 537 break; 538 } 539 } 540 541 /* check for bus probe */ 542 p = &msgs[0]; 543 if ((num == 1) && (p->len == 0)) { 544 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 545 RADEON_I2C_NACK | 546 RADEON_I2C_HALT | 547 RADEON_I2C_SOFT_RST)); 548 WREG32(i2c_data, (p->slave << 1) & 0xff); 549 WREG32(i2c_data, 0); 550 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 551 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 552 RADEON_I2C_EN | 553 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 554 WREG32(i2c_cntl_0, reg); 555 for (k = 0; k < 32; k++) { 556 udelay(10); 557 tmp = RREG32(i2c_cntl_0); 558 if (tmp & RADEON_I2C_GO) 559 continue; 560 tmp = RREG32(i2c_cntl_0); 561 if (tmp & RADEON_I2C_DONE) 562 break; 563 else { 564 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 565 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 566 ret = EIO; 567 goto done; 568 } 569 } 570 goto done; 571 } 572 573 for (i = 0; i < num; i++) { 574 p = &msgs[i]; 575 for (j = 0; j < p->len; j++) { 576 if (p->flags & IIC_M_RD) { 577 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 578 RADEON_I2C_NACK | 579 RADEON_I2C_HALT | 580 RADEON_I2C_SOFT_RST)); 581 WREG32(i2c_data, ((p->slave << 1) & 0xff) | 0x1); 582 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 583 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 584 RADEON_I2C_EN | 585 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 586 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 587 for (k = 0; k < 32; k++) { 588 udelay(10); 589 tmp = RREG32(i2c_cntl_0); 590 if (tmp & RADEON_I2C_GO) 591 continue; 592 tmp = RREG32(i2c_cntl_0); 593 if (tmp & RADEON_I2C_DONE) 594 break; 595 else { 596 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 597 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 598 ret = EIO; 599 goto done; 600 } 601 } 602 p->buf[j] = RREG32(i2c_data) & 0xff; 603 } else { 604 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 605 RADEON_I2C_NACK | 606 RADEON_I2C_HALT | 607 RADEON_I2C_SOFT_RST)); 608 WREG32(i2c_data, (p->slave << 1) & 0xff); 609 WREG32(i2c_data, p->buf[j]); 610 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 611 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 612 RADEON_I2C_EN | 613 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 614 WREG32(i2c_cntl_0, reg); 615 for (k = 0; k < 32; k++) { 616 udelay(10); 617 tmp = RREG32(i2c_cntl_0); 618 if (tmp & RADEON_I2C_GO) 619 continue; 620 tmp = RREG32(i2c_cntl_0); 621 if (tmp & RADEON_I2C_DONE) 622 break; 623 else { 624 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 625 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 626 ret = EIO; 627 goto done; 628 } 629 } 630 } 631 } 632 } 633 634 done: 635 WREG32(i2c_cntl_0, 0); 636 WREG32(i2c_cntl_1, 0); 637 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 638 RADEON_I2C_NACK | 639 RADEON_I2C_HALT | 640 RADEON_I2C_SOFT_RST)); 641 642 if (rdev->is_atom_bios) { 643 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 644 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 645 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 646 } 647 648 mutex_unlock(&rdev->pm.mutex); 649 mutex_unlock(&rdev->dc_hw_i2c_mutex); 650 651 return ret; 652 } 653 654 /* hw i2c engine for r5xx hardware 655 * hw can buffer up to 15 bytes 656 */ 657 static int r500_hw_i2c_xfer(struct radeon_i2c_chan *i2c, 658 struct iic_msg *msgs, int num) 659 { 660 struct radeon_device *rdev = i2c->dev->dev_private; 661 struct radeon_i2c_bus_rec *rec = &i2c->rec; 662 struct iic_msg *p; 663 int i, j, remaining, current_count, buffer_offset, ret = 0; 664 u32 prescale; 665 u32 tmp, reg; 666 u32 saved1, saved2; 667 668 mutex_lock(&rdev->dc_hw_i2c_mutex); 669 /* take the pm lock since we need a constant sclk */ 670 mutex_lock(&rdev->pm.mutex); 671 672 prescale = radeon_get_i2c_prescale(rdev); 673 674 /* clear gpio mask bits */ 675 tmp = RREG32(rec->mask_clk_reg); 676 tmp &= ~rec->mask_clk_mask; 677 WREG32(rec->mask_clk_reg, tmp); 678 tmp = RREG32(rec->mask_clk_reg); 679 680 tmp = RREG32(rec->mask_data_reg); 681 tmp &= ~rec->mask_data_mask; 682 WREG32(rec->mask_data_reg, tmp); 683 tmp = RREG32(rec->mask_data_reg); 684 685 /* clear pin values */ 686 tmp = RREG32(rec->a_clk_reg); 687 tmp &= ~rec->a_clk_mask; 688 WREG32(rec->a_clk_reg, tmp); 689 tmp = RREG32(rec->a_clk_reg); 690 691 tmp = RREG32(rec->a_data_reg); 692 tmp &= ~rec->a_data_mask; 693 WREG32(rec->a_data_reg, tmp); 694 tmp = RREG32(rec->a_data_reg); 695 696 /* set the pins to input */ 697 tmp = RREG32(rec->en_clk_reg); 698 tmp &= ~rec->en_clk_mask; 699 WREG32(rec->en_clk_reg, tmp); 700 tmp = RREG32(rec->en_clk_reg); 701 702 tmp = RREG32(rec->en_data_reg); 703 tmp &= ~rec->en_data_mask; 704 WREG32(rec->en_data_reg, tmp); 705 tmp = RREG32(rec->en_data_reg); 706 707 /* */ 708 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 709 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 710 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 711 saved2 = RREG32(0x494); 712 WREG32(0x494, saved2 | 0x1); 713 714 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 715 for (i = 0; i < 50; i++) { 716 udelay(1); 717 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 718 break; 719 } 720 if (i == 50) { 721 DRM_ERROR("failed to get i2c bus\n"); 722 ret = EBUSY; 723 goto done; 724 } 725 726 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 727 switch (rec->mask_clk_reg) { 728 case AVIVO_DC_GPIO_DDC1_MASK: 729 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 730 break; 731 case AVIVO_DC_GPIO_DDC2_MASK: 732 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 733 break; 734 case AVIVO_DC_GPIO_DDC3_MASK: 735 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 736 break; 737 default: 738 DRM_ERROR("gpio not supported with hw i2c\n"); 739 ret = EINVAL; 740 goto done; 741 } 742 743 /* check for bus probe */ 744 p = &msgs[0]; 745 if ((num == 1) && (p->len == 0)) { 746 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 747 AVIVO_DC_I2C_NACK | 748 AVIVO_DC_I2C_HALT)); 749 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 750 udelay(1); 751 WREG32(AVIVO_DC_I2C_RESET, 0); 752 753 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff); 754 WREG32(AVIVO_DC_I2C_DATA, 0); 755 756 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 757 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 758 AVIVO_DC_I2C_DATA_COUNT(1) | 759 (prescale << 16))); 760 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 761 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 762 for (j = 0; j < 200; j++) { 763 udelay(50); 764 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 765 if (tmp & AVIVO_DC_I2C_GO) 766 continue; 767 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 768 if (tmp & AVIVO_DC_I2C_DONE) 769 break; 770 else { 771 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 772 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 773 ret = EIO; 774 goto done; 775 } 776 } 777 goto done; 778 } 779 780 for (i = 0; i < num; i++) { 781 p = &msgs[i]; 782 remaining = p->len; 783 buffer_offset = 0; 784 if (p->flags & IIC_M_RD) { 785 while (remaining) { 786 if (remaining > 15) 787 current_count = 15; 788 else 789 current_count = remaining; 790 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 791 AVIVO_DC_I2C_NACK | 792 AVIVO_DC_I2C_HALT)); 793 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 794 udelay(1); 795 WREG32(AVIVO_DC_I2C_RESET, 0); 796 797 WREG32(AVIVO_DC_I2C_DATA, ((p->slave << 1) & 0xff) | 0x1); 798 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 799 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 800 AVIVO_DC_I2C_DATA_COUNT(current_count) | 801 (prescale << 16))); 802 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 803 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 804 for (j = 0; j < 200; j++) { 805 udelay(50); 806 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 807 if (tmp & AVIVO_DC_I2C_GO) 808 continue; 809 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 810 if (tmp & AVIVO_DC_I2C_DONE) 811 break; 812 else { 813 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 814 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 815 ret = EIO; 816 goto done; 817 } 818 } 819 for (j = 0; j < current_count; j++) 820 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 821 remaining -= current_count; 822 buffer_offset += current_count; 823 } 824 } else { 825 while (remaining) { 826 if (remaining > 15) 827 current_count = 15; 828 else 829 current_count = remaining; 830 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 831 AVIVO_DC_I2C_NACK | 832 AVIVO_DC_I2C_HALT)); 833 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 834 udelay(1); 835 WREG32(AVIVO_DC_I2C_RESET, 0); 836 837 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff); 838 for (j = 0; j < current_count; j++) 839 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 840 841 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 842 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 843 AVIVO_DC_I2C_DATA_COUNT(current_count) | 844 (prescale << 16))); 845 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 846 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 847 for (j = 0; j < 200; j++) { 848 udelay(50); 849 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 850 if (tmp & AVIVO_DC_I2C_GO) 851 continue; 852 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 853 if (tmp & AVIVO_DC_I2C_DONE) 854 break; 855 else { 856 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 857 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 858 ret = EIO; 859 goto done; 860 } 861 } 862 remaining -= current_count; 863 buffer_offset += current_count; 864 } 865 } 866 } 867 868 done: 869 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 870 AVIVO_DC_I2C_NACK | 871 AVIVO_DC_I2C_HALT)); 872 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 873 udelay(1); 874 WREG32(AVIVO_DC_I2C_RESET, 0); 875 876 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 877 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 878 WREG32(0x494, saved2); 879 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 880 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 881 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 882 883 mutex_unlock(&rdev->pm.mutex); 884 mutex_unlock(&rdev->dc_hw_i2c_mutex); 885 886 return ret; 887 } 888 889 static int radeon_hw_i2c_xfer(device_t dev, 890 struct iic_msg *msgs, uint32_t num) 891 { 892 struct radeon_i2c_chan *i2c = device_get_softc(dev); 893 struct radeon_device *rdev = i2c->dev->dev_private; 894 struct radeon_i2c_bus_rec *rec = &i2c->rec; 895 int ret = 0; 896 897 mutex_lock(&i2c->mutex); 898 899 switch (rdev->family) { 900 case CHIP_R100: 901 case CHIP_RV100: 902 case CHIP_RS100: 903 case CHIP_RV200: 904 case CHIP_RS200: 905 case CHIP_R200: 906 case CHIP_RV250: 907 case CHIP_RS300: 908 case CHIP_RV280: 909 case CHIP_R300: 910 case CHIP_R350: 911 case CHIP_RV350: 912 case CHIP_RV380: 913 case CHIP_R420: 914 case CHIP_R423: 915 case CHIP_RV410: 916 case CHIP_RS400: 917 case CHIP_RS480: 918 ret = r100_hw_i2c_xfer(i2c, msgs, num); 919 break; 920 case CHIP_RS600: 921 case CHIP_RS690: 922 case CHIP_RS740: 923 /* XXX fill in hw i2c implementation */ 924 break; 925 case CHIP_RV515: 926 case CHIP_R520: 927 case CHIP_RV530: 928 case CHIP_RV560: 929 case CHIP_RV570: 930 case CHIP_R580: 931 if (rec->mm_i2c) 932 ret = r100_hw_i2c_xfer(i2c, msgs, num); 933 else 934 ret = r500_hw_i2c_xfer(i2c, msgs, num); 935 break; 936 case CHIP_R600: 937 case CHIP_RV610: 938 case CHIP_RV630: 939 case CHIP_RV670: 940 /* XXX fill in hw i2c implementation */ 941 break; 942 case CHIP_RV620: 943 case CHIP_RV635: 944 case CHIP_RS780: 945 case CHIP_RS880: 946 case CHIP_RV770: 947 case CHIP_RV730: 948 case CHIP_RV710: 949 case CHIP_RV740: 950 /* XXX fill in hw i2c implementation */ 951 break; 952 case CHIP_CEDAR: 953 case CHIP_REDWOOD: 954 case CHIP_JUNIPER: 955 case CHIP_CYPRESS: 956 case CHIP_HEMLOCK: 957 /* XXX fill in hw i2c implementation */ 958 break; 959 default: 960 DRM_ERROR("i2c: unhandled radeon chip\n"); 961 ret = EIO; 962 break; 963 } 964 965 mutex_unlock(&i2c->mutex); 966 967 return ret; 968 } 969 970 static int 971 radeon_hw_i2c_probe(device_t dev) 972 { 973 974 return (BUS_PROBE_SPECIFIC); 975 } 976 977 static int 978 radeon_hw_i2c_attach(device_t dev) 979 { 980 struct radeon_i2c_chan *i2c; 981 device_t iic_dev; 982 983 i2c = device_get_softc(dev); 984 device_set_desc(dev, i2c->name); 985 986 /* add generic bit-banging code */ 987 iic_dev = device_add_child(dev, "iicbus", -1); 988 if (iic_dev == NULL) 989 return (ENXIO); 990 device_quiet(iic_dev); 991 992 /* attach and probe added child */ 993 bus_generic_attach(dev); 994 995 return (0); 996 } 997 998 static int 999 radeon_hw_i2c_detach(device_t dev) 1000 { 1001 1002 /* detach bit-banding code. */ 1003 bus_generic_detach(dev); 1004 1005 /* delete bit-banding code. */ 1006 device_delete_children(dev); 1007 return (0); 1008 } 1009 1010 static int 1011 radeon_hw_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 1012 { 1013 1014 /* Not sure what to do here. */ 1015 return 0; 1016 } 1017 1018 static device_method_t radeon_hw_i2c_methods[] = { 1019 DEVMETHOD(device_probe, radeon_hw_i2c_probe), 1020 DEVMETHOD(device_attach, radeon_hw_i2c_attach), 1021 DEVMETHOD(device_detach, radeon_hw_i2c_detach), 1022 DEVMETHOD(iicbus_reset, radeon_hw_i2c_reset), 1023 DEVMETHOD(iicbus_transfer, radeon_hw_i2c_xfer), 1024 DEVMETHOD_END 1025 }; 1026 1027 static driver_t radeon_hw_i2c_driver = { 1028 "radeon_hw_i2c", 1029 radeon_hw_i2c_methods, 1030 0 /* softc will be allocated by parent */ 1031 }; 1032 1033 static devclass_t radeon_hw_i2c_devclass; 1034 DRIVER_MODULE_ORDERED(radeon_hw_i2c, drm, radeon_hw_i2c_driver, 1035 radeon_hw_i2c_devclass, NULL, NULL, SI_ORDER_FIRST); 1036 DRIVER_MODULE(iicbus, radeon_hw_i2c, iicbus_driver, iicbus_devclass, NULL, NULL); 1037 1038 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 1039 struct radeon_i2c_bus_rec *rec, 1040 const char *name) 1041 { 1042 struct radeon_device *rdev = dev->dev_private; 1043 struct radeon_i2c_chan *i2c; 1044 device_t iicbus_dev; 1045 int ret; 1046 1047 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 1048 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 1049 return NULL; 1050 1051 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1052 if (i2c == NULL) 1053 return NULL; 1054 1055 /* 1056 * Grab Giant before messing with newbus devices, just in case 1057 * we do not hold it already. 1058 */ 1059 get_mplock(); 1060 1061 i2c->rec = *rec; 1062 #if 0 1063 i2c->adapter.owner = THIS_MODULE; 1064 i2c->adapter.class = I2C_CLASS_DDC; 1065 i2c->adapter.dev.parent = &dev->pdev->dev; 1066 #endif 1067 i2c->dev = dev; 1068 #if 0 1069 i2c_set_adapdata(&i2c->adapter, i2c); 1070 #endif 1071 lockinit(&i2c->mutex, "ri2cmtx", 0, LK_CANRECURSE); 1072 if (rec->mm_i2c || 1073 (rec->hw_capable && 1074 radeon_hw_i2c && 1075 ((rdev->family <= CHIP_RS480) || 1076 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 1077 /* set the radeon hw i2c adapter */ 1078 ksnprintf(i2c->name, sizeof(i2c->name), 1079 "Radeon i2c hw bus %s", name); 1080 iicbus_dev = device_add_child(dev->dev->bsddev, "radeon_hw_i2c", -1); 1081 if (iicbus_dev == NULL) { 1082 DRM_ERROR("Failed to create bridge for hw i2c %s\n", 1083 name); 1084 goto out_free; 1085 } 1086 device_quiet(iicbus_dev); 1087 device_set_softc(iicbus_dev, i2c); 1088 1089 ret = device_probe_and_attach(iicbus_dev); 1090 if (ret != 0) { 1091 DRM_ERROR("Attach failed for bridge for hw i2c %s\n", 1092 name); 1093 device_delete_child(dev->dev->bsddev, iicbus_dev); 1094 goto out_free; 1095 } 1096 1097 i2c->adapter_dev = device_find_child(iicbus_dev, "iicbus", -1); 1098 if (i2c->adapter_dev == NULL) { 1099 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n"); 1100 device_delete_child(dev->dev->bsddev, iicbus_dev); 1101 goto out_free; 1102 } 1103 DRM_INFO("Created radeon_hw_i2c bus\n"); 1104 } else if (rec->hw_capable && 1105 radeon_hw_i2c && 1106 ASIC_IS_DCE3(rdev)) { 1107 /* hw i2c using atom */ 1108 ksnprintf(i2c->name, sizeof(i2c->name), 1109 "Radeon i2c hw bus %s", name); 1110 iicbus_dev = device_add_child(dev->dev->bsddev, "radeon_atom_hw_i2c", -1); 1111 if (iicbus_dev == NULL) { 1112 DRM_ERROR("Failed to create bridge for hw i2c %s\n", 1113 name); 1114 goto out_free; 1115 } 1116 device_quiet(iicbus_dev); 1117 device_set_softc(iicbus_dev, i2c); 1118 1119 ret = device_probe_and_attach(iicbus_dev); 1120 if (ret != 0) { 1121 DRM_ERROR("Attach failed for bridge for hw i2c %s\n", 1122 name); 1123 device_delete_child(dev->dev->bsddev, iicbus_dev); 1124 goto out_free; 1125 } 1126 1127 i2c->adapter_dev = device_find_child(iicbus_dev, "iicbus", -1); 1128 if (i2c->adapter_dev == NULL) { 1129 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n"); 1130 device_delete_child(dev->dev->bsddev, iicbus_dev); 1131 goto out_free; 1132 } 1133 DRM_INFO("Created radeon_atom_hw_bus\n"); 1134 } else { 1135 device_t iicbb_dev; 1136 1137 /* set the radeon bit adapter */ 1138 ksnprintf(i2c->name, sizeof(i2c->name), 1139 "Radeon i2c bit bus %s", name); 1140 iicbus_dev = device_add_child(dev->dev->bsddev, "radeon_iicbb", -1); 1141 if (iicbus_dev == NULL) { 1142 DRM_ERROR("Failed to create bridge for bb i2c %s\n", 1143 name); 1144 goto out_free; 1145 } 1146 device_quiet(iicbus_dev); 1147 device_set_softc(iicbus_dev, i2c); 1148 1149 ret = device_probe_and_attach(iicbus_dev); 1150 if (ret != 0) { 1151 DRM_ERROR("Attach failed for bridge for bb i2c %s\n", 1152 name); 1153 device_delete_child(dev->dev->bsddev, iicbus_dev); 1154 goto out_free; 1155 } 1156 1157 iicbb_dev = device_find_child(iicbus_dev, "iicbb", -1); 1158 if (iicbb_dev == NULL) { 1159 DRM_ERROR("bb i2c bridge doesn't have iicbb child\n"); 1160 device_delete_child(dev->dev->bsddev, iicbus_dev); 1161 goto out_free; 1162 } 1163 1164 i2c->adapter_dev = device_find_child(iicbb_dev, "iicbus", -1); 1165 if (i2c->adapter_dev == NULL) { 1166 DRM_ERROR( 1167 "bbbus bridge doesn't have iicbus grandchild\n"); 1168 device_delete_child(dev->dev->bsddev, iicbus_dev); 1169 goto out_free; 1170 } 1171 DRM_INFO("Created Radeon i2c bit bus for (%s)\n", name); 1172 } 1173 1174 i2c->iic_bus = iicbus_dev; 1175 1176 rel_mplock(); 1177 1178 return i2c; 1179 out_free: 1180 rel_mplock(); 1181 kfree(i2c); 1182 return NULL; 1183 1184 } 1185 1186 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1187 { 1188 if (!i2c) 1189 return; 1190 if (i2c->iic_bus != NULL) { 1191 int ret; 1192 1193 get_mplock(); 1194 ret = device_delete_child(i2c->dev->dev->bsddev, i2c->iic_bus); 1195 rel_mplock(); 1196 KASSERT(ret == 0, ("unable to detach iic bus %s: %d", 1197 i2c->name, ret)); 1198 } 1199 if (i2c->has_aux) 1200 drm_dp_aux_unregister(&i2c->aux); 1201 kfree(i2c); 1202 } 1203 1204 /* Add the default buses */ 1205 void radeon_i2c_init(struct radeon_device *rdev) 1206 { 1207 if (radeon_hw_i2c) 1208 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1209 1210 if (rdev->is_atom_bios) 1211 radeon_atombios_i2c_init(rdev); 1212 else 1213 radeon_combios_i2c_init(rdev); 1214 } 1215 1216 /* remove all the buses */ 1217 void radeon_i2c_fini(struct radeon_device *rdev) 1218 { 1219 int i; 1220 1221 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1222 if (rdev->i2c_bus[i]) { 1223 radeon_i2c_destroy(rdev->i2c_bus[i]); 1224 rdev->i2c_bus[i] = NULL; 1225 } 1226 } 1227 } 1228 1229 /* Add additional buses */ 1230 void radeon_i2c_add(struct radeon_device *rdev, 1231 struct radeon_i2c_bus_rec *rec, 1232 const char *name) 1233 { 1234 struct drm_device *dev = rdev->ddev; 1235 int i; 1236 1237 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1238 if (!rdev->i2c_bus[i]) { 1239 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1240 return; 1241 } 1242 } 1243 } 1244 1245 /* looks up bus based on id */ 1246 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1247 struct radeon_i2c_bus_rec *i2c_bus) 1248 { 1249 int i; 1250 1251 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1252 if (rdev->i2c_bus[i] && 1253 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1254 return rdev->i2c_bus[i]; 1255 } 1256 } 1257 return NULL; 1258 } 1259 1260 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1261 u8 slave_addr, 1262 u8 addr, 1263 u8 *val) 1264 { 1265 u8 out_buf[2]; 1266 u8 in_buf[2]; 1267 struct iic_msg msgs[] = { 1268 { 1269 .slave = slave_addr << 1, 1270 .flags = 0, 1271 .len = 1, 1272 .buf = out_buf, 1273 }, 1274 { 1275 .slave = slave_addr << 1, 1276 .flags = IIC_M_RD, 1277 .len = 1, 1278 .buf = in_buf, 1279 } 1280 }; 1281 1282 out_buf[0] = addr; 1283 out_buf[1] = 0; 1284 1285 if (iicbus_transfer(i2c_bus->adapter_dev, msgs, 2) == 0) { 1286 *val = in_buf[0]; 1287 DRM_DEBUG("val = 0x%02x\n", *val); 1288 } else { 1289 *val = 0; /* avoid gcc warning */ 1290 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1291 addr, *val); 1292 } 1293 } 1294 1295 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1296 u8 slave_addr, 1297 u8 addr, 1298 u8 val) 1299 { 1300 uint8_t out_buf[2]; 1301 struct iic_msg msg = { 1302 .slave = slave_addr << 1, 1303 .flags = 0, 1304 .len = 2, 1305 .buf = out_buf, 1306 }; 1307 1308 out_buf[0] = addr; 1309 out_buf[1] = val; 1310 1311 if (iicbus_transfer(i2c_bus->adapter_dev, &msg, 1) != 0) 1312 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1313 addr, val); 1314 } 1315 1316 /* ddc router switching */ 1317 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1318 { 1319 u8 val; 1320 1321 if (!radeon_connector->router.ddc_valid) 1322 return; 1323 1324 if (!radeon_connector->router_bus) 1325 return; 1326 1327 radeon_i2c_get_byte(radeon_connector->router_bus, 1328 radeon_connector->router.i2c_addr, 1329 0x3, &val); 1330 val &= ~radeon_connector->router.ddc_mux_control_pin; 1331 radeon_i2c_put_byte(radeon_connector->router_bus, 1332 radeon_connector->router.i2c_addr, 1333 0x3, val); 1334 radeon_i2c_get_byte(radeon_connector->router_bus, 1335 radeon_connector->router.i2c_addr, 1336 0x1, &val); 1337 val &= ~radeon_connector->router.ddc_mux_control_pin; 1338 val |= radeon_connector->router.ddc_mux_state; 1339 radeon_i2c_put_byte(radeon_connector->router_bus, 1340 radeon_connector->router.i2c_addr, 1341 0x1, val); 1342 } 1343 1344 /* clock/data router switching */ 1345 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1346 { 1347 u8 val; 1348 1349 if (!radeon_connector->router.cd_valid) 1350 return; 1351 1352 if (!radeon_connector->router_bus) 1353 return; 1354 1355 radeon_i2c_get_byte(radeon_connector->router_bus, 1356 radeon_connector->router.i2c_addr, 1357 0x3, &val); 1358 val &= ~radeon_connector->router.cd_mux_control_pin; 1359 radeon_i2c_put_byte(radeon_connector->router_bus, 1360 radeon_connector->router.i2c_addr, 1361 0x3, val); 1362 radeon_i2c_get_byte(radeon_connector->router_bus, 1363 radeon_connector->router.i2c_addr, 1364 0x1, &val); 1365 val &= ~radeon_connector->router.cd_mux_control_pin; 1366 val |= radeon_connector->router.cd_mux_state; 1367 radeon_i2c_put_byte(radeon_connector->router_bus, 1368 radeon_connector->router.i2c_addr, 1369 0x1, val); 1370 } 1371 1372