1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include <uapi_drm/radeon_drm.h> 31 #include "radeon_asic.h" 32 #include "radeon_kms.h" 33 34 #include <linux/slab.h> 35 #ifdef PM_TODO 36 #include <linux/pm_runtime.h> 37 #endif 38 39 #ifdef PM_TODO 40 #if defined(CONFIG_VGA_SWITCHEROO) 41 bool radeon_has_atpx(void); 42 #else 43 static inline bool radeon_has_atpx(void) { return false; } 44 #endif 45 #endif 46 47 /** 48 * radeon_driver_unload_kms - Main unload function for KMS. 49 * 50 * @dev: drm dev pointer 51 * 52 * This is the main unload function for KMS (all asics). 53 * It calls radeon_modeset_fini() to tear down the 54 * displays, and radeon_device_fini() to tear down 55 * the rest of the device (CP, writeback, etc.). 56 * Returns 0 on success. 57 */ 58 int radeon_driver_unload_kms(struct drm_device *dev) 59 { 60 struct radeon_device *rdev = dev->dev_private; 61 62 /* XXX pending drm update */ 63 drm_fini_pdev(&dev->pdev); 64 65 if (rdev == NULL) 66 return 0; 67 68 if (rdev->rmmio == NULL) 69 goto done_free; 70 71 #ifdef PM_TODO 72 pm_runtime_get_sync(dev->dev); 73 #endif 74 75 radeon_acpi_fini(rdev); 76 radeon_modeset_fini(rdev); 77 radeon_device_fini(rdev); 78 79 done_free: 80 kfree(rdev); 81 dev->dev_private = NULL; 82 return 0; 83 } 84 85 /** 86 * radeon_driver_load_kms - Main load function for KMS. 87 * 88 * @dev: drm dev pointer 89 * @flags: device flags 90 * 91 * This is the main load function for KMS (all asics). 92 * It calls radeon_device_init() to set up the non-display 93 * parts of the chip (asic init, CP, writeback, etc.), and 94 * radeon_modeset_init() to set up the display parts 95 * (crtcs, encoders, hotplug detect, etc.). 96 * Returns 0 on success, error on failure. 97 */ 98 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 99 { 100 struct radeon_device *rdev; 101 int r, acpi_status; 102 103 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 104 if (rdev == NULL) { 105 return -ENOMEM; 106 } 107 dev->dev_private = (void *)rdev; 108 109 /* update BUS flag */ 110 if (drm_device_is_agp(dev)) { 111 DRM_INFO("RADEON_IS_AGP\n"); 112 flags |= RADEON_IS_AGP; 113 } else if (drm_device_is_pcie(dev)) { 114 DRM_INFO("RADEON_IS_PCIE\n"); 115 flags |= RADEON_IS_PCIE; 116 } else { 117 DRM_INFO("RADEON_IS_PCI\n"); 118 flags |= RADEON_IS_PCI; 119 } 120 121 #ifdef PM_TODO 122 if ((radeon_runtime_pm != 0) && 123 radeon_has_atpx() && 124 ((flags & RADEON_IS_IGP) == 0)) 125 #endif 126 127 /* radeon_device_init should report only fatal error 128 * like memory allocation failure or iomapping failure, 129 * or memory manager initialization failure, it must 130 * properly initialize the GPU MC controller and permit 131 * VRAM allocation 132 */ 133 r = radeon_device_init(rdev, dev, dev->pdev, flags); 134 if (r) { 135 dev_err(dev->pdev->dev, "Fatal error during GPU init\n"); 136 goto out; 137 } 138 139 /* Again modeset_init should fail only on fatal error 140 * otherwise it should provide enough functionalities 141 * for shadowfb to run 142 */ 143 r = radeon_modeset_init(rdev); 144 if (r) 145 dev_err(dev->pdev->dev, "Fatal error during modeset init\n"); 146 147 /* Call ACPI methods: require modeset init 148 * but failure is not fatal 149 */ 150 if (!r) { 151 acpi_status = radeon_acpi_init(rdev); 152 if (acpi_status) 153 dev_dbg(dev->pdev->dev, 154 "Error during ACPI methods call\n"); 155 } 156 157 #ifdef PM_TODO 158 if (radeon_is_px(dev)) { 159 pm_runtime_use_autosuspend(dev->dev); 160 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 161 pm_runtime_set_active(dev->dev); 162 pm_runtime_allow(dev->dev); 163 pm_runtime_mark_last_busy(dev->dev); 164 pm_runtime_put_autosuspend(dev->dev); 165 } 166 #endif 167 168 out: 169 if (r) 170 radeon_driver_unload_kms(dev); 171 172 173 return r; 174 } 175 176 /** 177 * radeon_set_filp_rights - Set filp right. 178 * 179 * @dev: drm dev pointer 180 * @owner: drm file 181 * @applier: drm file 182 * @value: value 183 * 184 * Sets the filp rights for the device (all asics). 185 */ 186 static void radeon_set_filp_rights(struct drm_device *dev, 187 struct drm_file **owner, 188 struct drm_file *applier, 189 uint32_t *value) 190 { 191 mutex_lock(&dev->struct_mutex); 192 if (*value == 1) { 193 /* wants rights */ 194 if (!*owner) 195 *owner = applier; 196 } else if (*value == 0) { 197 /* revokes rights */ 198 if (*owner == applier) 199 *owner = NULL; 200 } 201 *value = *owner == applier ? 1 : 0; 202 mutex_unlock(&dev->struct_mutex); 203 } 204 205 /* 206 * Userspace get information ioctl 207 */ 208 /** 209 * radeon_info_ioctl - answer a device specific request. 210 * 211 * @rdev: radeon device pointer 212 * @data: request object 213 * @filp: drm filp 214 * 215 * This function is used to pass device specific parameters to the userspace 216 * drivers. Examples include: pci device id, pipeline parms, tiling params, 217 * etc. (all asics). 218 * Returns 0 on success, -EINVAL on failure. 219 */ 220 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 221 { 222 struct radeon_device *rdev = dev->dev_private; 223 struct drm_radeon_info *info = data; 224 struct radeon_mode_info *minfo = &rdev->mode_info; 225 uint32_t *value, value_tmp, *value_ptr, value_size; 226 uint64_t value64; 227 struct drm_crtc *crtc; 228 int i, found; 229 230 value_ptr = (uint32_t *)((unsigned long)info->value); 231 value = &value_tmp; 232 value_size = sizeof(uint32_t); 233 234 switch (info->request) { 235 case RADEON_INFO_DEVICE_ID: 236 *value = dev->pdev->device; 237 break; 238 case RADEON_INFO_NUM_GB_PIPES: 239 *value = rdev->num_gb_pipes; 240 break; 241 case RADEON_INFO_NUM_Z_PIPES: 242 *value = rdev->num_z_pipes; 243 break; 244 case RADEON_INFO_ACCEL_WORKING: 245 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 246 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 247 *value = false; 248 else 249 *value = rdev->accel_working; 250 break; 251 case RADEON_INFO_CRTC_FROM_ID: 252 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 253 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 254 return -EFAULT; 255 } 256 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 257 crtc = (struct drm_crtc *)minfo->crtcs[i]; 258 if (crtc && crtc->base.id == *value) { 259 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 260 *value = radeon_crtc->crtc_id; 261 found = 1; 262 break; 263 } 264 } 265 if (!found) { 266 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 267 return -EINVAL; 268 } 269 break; 270 case RADEON_INFO_ACCEL_WORKING2: 271 if (rdev->family == CHIP_HAWAII) { 272 if (rdev->accel_working) { 273 if (rdev->new_fw) 274 *value = 3; 275 else 276 *value = 2; 277 } else { 278 *value = 0; 279 } 280 } else { 281 *value = rdev->accel_working; 282 } 283 break; 284 case RADEON_INFO_TILING_CONFIG: 285 if (rdev->family >= CHIP_BONAIRE) 286 *value = rdev->config.cik.tile_config; 287 else if (rdev->family >= CHIP_TAHITI) 288 *value = rdev->config.si.tile_config; 289 else if (rdev->family >= CHIP_CAYMAN) 290 *value = rdev->config.cayman.tile_config; 291 else if (rdev->family >= CHIP_CEDAR) 292 *value = rdev->config.evergreen.tile_config; 293 else if (rdev->family >= CHIP_RV770) 294 *value = rdev->config.rv770.tile_config; 295 else if (rdev->family >= CHIP_R600) 296 *value = rdev->config.r600.tile_config; 297 else { 298 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 299 return -EINVAL; 300 } 301 break; 302 case RADEON_INFO_WANT_HYPERZ: 303 /* The "value" here is both an input and output parameter. 304 * If the input value is 1, filp requests hyper-z access. 305 * If the input value is 0, filp revokes its hyper-z access. 306 * 307 * When returning, the value is 1 if filp owns hyper-z access, 308 * 0 otherwise. */ 309 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 310 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 311 return -EFAULT; 312 } 313 if (*value >= 2) { 314 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 315 return -EINVAL; 316 } 317 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 318 break; 319 case RADEON_INFO_WANT_CMASK: 320 /* The same logic as Hyper-Z. */ 321 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 322 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 323 return -EFAULT; 324 } 325 if (*value >= 2) { 326 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 327 return -EINVAL; 328 } 329 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 330 break; 331 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 332 /* return clock value in KHz */ 333 if (rdev->asic->get_xclk) 334 *value = radeon_get_xclk(rdev) * 10; 335 else 336 *value = rdev->clock.spll.reference_freq * 10; 337 break; 338 case RADEON_INFO_NUM_BACKENDS: 339 if (rdev->family >= CHIP_BONAIRE) 340 *value = rdev->config.cik.max_backends_per_se * 341 rdev->config.cik.max_shader_engines; 342 else if (rdev->family >= CHIP_TAHITI) 343 *value = rdev->config.si.max_backends_per_se * 344 rdev->config.si.max_shader_engines; 345 else if (rdev->family >= CHIP_CAYMAN) 346 *value = rdev->config.cayman.max_backends_per_se * 347 rdev->config.cayman.max_shader_engines; 348 else if (rdev->family >= CHIP_CEDAR) 349 *value = rdev->config.evergreen.max_backends; 350 else if (rdev->family >= CHIP_RV770) 351 *value = rdev->config.rv770.max_backends; 352 else if (rdev->family >= CHIP_R600) 353 *value = rdev->config.r600.max_backends; 354 else { 355 return -EINVAL; 356 } 357 break; 358 case RADEON_INFO_NUM_TILE_PIPES: 359 if (rdev->family >= CHIP_BONAIRE) 360 *value = rdev->config.cik.max_tile_pipes; 361 else if (rdev->family >= CHIP_TAHITI) 362 *value = rdev->config.si.max_tile_pipes; 363 else if (rdev->family >= CHIP_CAYMAN) 364 *value = rdev->config.cayman.max_tile_pipes; 365 else if (rdev->family >= CHIP_CEDAR) 366 *value = rdev->config.evergreen.max_tile_pipes; 367 else if (rdev->family >= CHIP_RV770) 368 *value = rdev->config.rv770.max_tile_pipes; 369 else if (rdev->family >= CHIP_R600) 370 *value = rdev->config.r600.max_tile_pipes; 371 else { 372 return -EINVAL; 373 } 374 break; 375 case RADEON_INFO_FUSION_GART_WORKING: 376 *value = 1; 377 break; 378 case RADEON_INFO_BACKEND_MAP: 379 if (rdev->family >= CHIP_BONAIRE) 380 *value = rdev->config.cik.backend_map; 381 else if (rdev->family >= CHIP_TAHITI) 382 *value = rdev->config.si.backend_map; 383 else if (rdev->family >= CHIP_CAYMAN) 384 *value = rdev->config.cayman.backend_map; 385 else if (rdev->family >= CHIP_CEDAR) 386 *value = rdev->config.evergreen.backend_map; 387 else if (rdev->family >= CHIP_RV770) 388 *value = rdev->config.rv770.backend_map; 389 else if (rdev->family >= CHIP_R600) 390 *value = rdev->config.r600.backend_map; 391 else { 392 return -EINVAL; 393 } 394 break; 395 case RADEON_INFO_VA_START: 396 /* this is where we report if vm is supported or not */ 397 if (rdev->family < CHIP_CAYMAN) 398 return -EINVAL; 399 *value = RADEON_VA_RESERVED_SIZE; 400 break; 401 case RADEON_INFO_IB_VM_MAX_SIZE: 402 /* this is where we report if vm is supported or not */ 403 if (rdev->family < CHIP_CAYMAN) 404 return -EINVAL; 405 *value = RADEON_IB_VM_MAX_SIZE; 406 break; 407 case RADEON_INFO_MAX_PIPES: 408 if (rdev->family >= CHIP_BONAIRE) 409 *value = rdev->config.cik.max_cu_per_sh; 410 else if (rdev->family >= CHIP_TAHITI) 411 *value = rdev->config.si.max_cu_per_sh; 412 else if (rdev->family >= CHIP_CAYMAN) 413 *value = rdev->config.cayman.max_pipes_per_simd; 414 else if (rdev->family >= CHIP_CEDAR) 415 *value = rdev->config.evergreen.max_pipes; 416 else if (rdev->family >= CHIP_RV770) 417 *value = rdev->config.rv770.max_pipes; 418 else if (rdev->family >= CHIP_R600) 419 *value = rdev->config.r600.max_pipes; 420 else { 421 return -EINVAL; 422 } 423 break; 424 case RADEON_INFO_TIMESTAMP: 425 if (rdev->family < CHIP_R600) { 426 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 427 return -EINVAL; 428 } 429 value = (uint32_t*)&value64; 430 value_size = sizeof(uint64_t); 431 value64 = radeon_get_gpu_clock_counter(rdev); 432 break; 433 case RADEON_INFO_MAX_SE: 434 if (rdev->family >= CHIP_BONAIRE) 435 *value = rdev->config.cik.max_shader_engines; 436 else if (rdev->family >= CHIP_TAHITI) 437 *value = rdev->config.si.max_shader_engines; 438 else if (rdev->family >= CHIP_CAYMAN) 439 *value = rdev->config.cayman.max_shader_engines; 440 else if (rdev->family >= CHIP_CEDAR) 441 *value = rdev->config.evergreen.num_ses; 442 else 443 *value = 1; 444 break; 445 case RADEON_INFO_MAX_SH_PER_SE: 446 if (rdev->family >= CHIP_BONAIRE) 447 *value = rdev->config.cik.max_sh_per_se; 448 else if (rdev->family >= CHIP_TAHITI) 449 *value = rdev->config.si.max_sh_per_se; 450 else 451 return -EINVAL; 452 break; 453 case RADEON_INFO_FASTFB_WORKING: 454 *value = rdev->fastfb_working; 455 break; 456 case RADEON_INFO_RING_WORKING: 457 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 458 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 459 return -EFAULT; 460 } 461 switch (*value) { 462 case RADEON_CS_RING_GFX: 463 case RADEON_CS_RING_COMPUTE: 464 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 465 break; 466 case RADEON_CS_RING_DMA: 467 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 468 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 469 break; 470 case RADEON_CS_RING_UVD: 471 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 472 break; 473 case RADEON_CS_RING_VCE: 474 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 475 break; 476 default: 477 return -EINVAL; 478 } 479 break; 480 case RADEON_INFO_SI_TILE_MODE_ARRAY: 481 if (rdev->family >= CHIP_BONAIRE) { 482 value = rdev->config.cik.tile_mode_array; 483 value_size = sizeof(uint32_t)*32; 484 } else if (rdev->family >= CHIP_TAHITI) { 485 value = rdev->config.si.tile_mode_array; 486 value_size = sizeof(uint32_t)*32; 487 } else { 488 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 489 return -EINVAL; 490 } 491 break; 492 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 493 if (rdev->family >= CHIP_BONAIRE) { 494 value = rdev->config.cik.macrotile_mode_array; 495 value_size = sizeof(uint32_t)*16; 496 } else { 497 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 498 return -EINVAL; 499 } 500 break; 501 case RADEON_INFO_SI_CP_DMA_COMPUTE: 502 *value = 1; 503 break; 504 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 505 if (rdev->family >= CHIP_BONAIRE) { 506 *value = rdev->config.cik.backend_enable_mask; 507 } else if (rdev->family >= CHIP_TAHITI) { 508 *value = rdev->config.si.backend_enable_mask; 509 } else { 510 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 511 } 512 break; 513 case RADEON_INFO_MAX_SCLK: 514 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 515 rdev->pm.dpm_enabled) 516 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 517 else 518 *value = rdev->pm.default_sclk * 10; 519 break; 520 case RADEON_INFO_VCE_FW_VERSION: 521 *value = rdev->vce.fw_version; 522 break; 523 case RADEON_INFO_VCE_FB_VERSION: 524 *value = rdev->vce.fb_version; 525 break; 526 case RADEON_INFO_NUM_BYTES_MOVED: 527 value = (uint32_t*)&value64; 528 value_size = sizeof(uint64_t); 529 value64 = atomic64_read(&rdev->num_bytes_moved); 530 break; 531 case RADEON_INFO_VRAM_USAGE: 532 value = (uint32_t*)&value64; 533 value_size = sizeof(uint64_t); 534 value64 = atomic64_read(&rdev->vram_usage); 535 break; 536 case RADEON_INFO_GTT_USAGE: 537 value = (uint32_t*)&value64; 538 value_size = sizeof(uint64_t); 539 value64 = atomic64_read(&rdev->gtt_usage); 540 break; 541 case RADEON_INFO_ACTIVE_CU_COUNT: 542 if (rdev->family >= CHIP_BONAIRE) 543 *value = rdev->config.cik.active_cus; 544 else if (rdev->family >= CHIP_TAHITI) 545 *value = rdev->config.si.active_cus; 546 else if (rdev->family >= CHIP_CAYMAN) 547 *value = rdev->config.cayman.active_simds; 548 else if (rdev->family >= CHIP_CEDAR) 549 *value = rdev->config.evergreen.active_simds; 550 else if (rdev->family >= CHIP_RV770) 551 *value = rdev->config.rv770.active_simds; 552 else if (rdev->family >= CHIP_R600) 553 *value = rdev->config.r600.active_simds; 554 else 555 *value = 1; 556 break; 557 default: 558 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 559 return -EINVAL; 560 } 561 if (copy_to_user(value_ptr, (char*)value, value_size)) { 562 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 563 return -EFAULT; 564 } 565 return 0; 566 } 567 568 569 /* 570 * Outdated mess for old drm with Xorg being in charge (void function now). 571 */ 572 /** 573 * radeon_driver_firstopen_kms - drm callback for last close 574 * 575 * @dev: drm dev pointer 576 * 577 * Switch vga switcheroo state after last close (all asics). 578 */ 579 void radeon_driver_lastclose_kms(struct drm_device *dev) 580 { 581 #ifdef DUMBBELL_WIP 582 vga_switcheroo_process_delayed_switch(); 583 #endif /* DUMBBELL_WIP */ 584 } 585 586 /** 587 * radeon_driver_open_kms - drm callback for open 588 * 589 * @dev: drm dev pointer 590 * @file_priv: drm file 591 * 592 * On device open, init vm on cayman+ (all asics). 593 * Returns 0 on success, error on failure. 594 */ 595 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 596 { 597 struct radeon_device *rdev = dev->dev_private; 598 599 file_priv->driver_priv = NULL; 600 601 #ifdef PM_TODO 602 r = pm_runtime_get_sync(dev->dev); 603 if (r < 0) 604 return r; 605 #endif 606 607 /* new gpu have virtual address space support */ 608 if (rdev->family >= CHIP_CAYMAN) { 609 struct radeon_fpriv *fpriv; 610 struct radeon_vm *vm; 611 int r; 612 613 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 614 if (unlikely(!fpriv)) { 615 return -ENOMEM; 616 } 617 618 vm = &fpriv->vm; 619 r = radeon_vm_init(rdev, vm); 620 if (r) { 621 kfree(fpriv); 622 return r; 623 } 624 625 if (rdev->accel_working) { 626 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 627 if (r) { 628 radeon_vm_fini(rdev, vm); 629 kfree(fpriv); 630 return r; 631 } 632 633 /* map the ib pool buffer read only into 634 * virtual address space */ 635 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 636 rdev->ring_tmp_bo.bo); 637 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 638 RADEON_VA_IB_OFFSET, 639 RADEON_VM_PAGE_READABLE | 640 RADEON_VM_PAGE_SNOOPED); 641 642 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 643 if (r) { 644 radeon_vm_fini(rdev, vm); 645 kfree(fpriv); 646 return r; 647 } 648 } 649 file_priv->driver_priv = fpriv; 650 } 651 652 #ifdef PM_TODO 653 pm_runtime_mark_last_busy(dev->dev); 654 pm_runtime_put_autosuspend(dev->dev); 655 #endif 656 return 0; 657 } 658 659 /** 660 * radeon_driver_postclose_kms - drm callback for post close 661 * 662 * @dev: drm dev pointer 663 * @file_priv: drm file 664 * 665 * On device post close, tear down vm on cayman+ (all asics). 666 */ 667 void radeon_driver_postclose_kms(struct drm_device *dev, 668 struct drm_file *file_priv) 669 { 670 struct radeon_device *rdev = dev->dev_private; 671 672 /* new gpu have virtual address space support */ 673 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 674 struct radeon_fpriv *fpriv = file_priv->driver_priv; 675 struct radeon_vm *vm = &fpriv->vm; 676 int r; 677 678 if (rdev->accel_working) { 679 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 680 if (!r) { 681 if (vm->ib_bo_va) 682 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 683 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 684 } 685 } 686 687 radeon_vm_fini(rdev, vm); 688 kfree(fpriv); 689 file_priv->driver_priv = NULL; 690 } 691 } 692 693 /** 694 * radeon_driver_preclose_kms - drm callback for pre close 695 * 696 * @dev: drm dev pointer 697 * @file_priv: drm file 698 * 699 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 700 * (all asics). 701 */ 702 void radeon_driver_preclose_kms(struct drm_device *dev, 703 struct drm_file *file_priv) 704 { 705 struct radeon_device *rdev = dev->dev_private; 706 if (rdev->hyperz_filp == file_priv) 707 rdev->hyperz_filp = NULL; 708 if (rdev->cmask_filp == file_priv) 709 rdev->cmask_filp = NULL; 710 radeon_uvd_free_handles(rdev, file_priv); 711 radeon_vce_free_handles(rdev, file_priv); 712 } 713 714 /* 715 * VBlank related functions. 716 */ 717 /** 718 * radeon_get_vblank_counter_kms - get frame count 719 * 720 * @dev: drm dev pointer 721 * @crtc: crtc to get the frame count from 722 * 723 * Gets the frame count on the requested crtc (all asics). 724 * Returns frame count on success, -EINVAL on failure. 725 */ 726 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 727 { 728 struct radeon_device *rdev = dev->dev_private; 729 730 if (crtc < 0 || crtc >= rdev->num_crtc) { 731 DRM_ERROR("Invalid crtc %d\n", crtc); 732 return -EINVAL; 733 } 734 735 return radeon_get_vblank_counter(rdev, crtc); 736 } 737 738 /** 739 * radeon_enable_vblank_kms - enable vblank interrupt 740 * 741 * @dev: drm dev pointer 742 * @crtc: crtc to enable vblank interrupt for 743 * 744 * Enable the interrupt on the requested crtc (all asics). 745 * Returns 0 on success, -EINVAL on failure. 746 */ 747 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 748 { 749 struct radeon_device *rdev = dev->dev_private; 750 int r; 751 752 if (crtc < 0 || crtc >= rdev->num_crtc) { 753 DRM_ERROR("Invalid crtc %d\n", crtc); 754 return -EINVAL; 755 } 756 757 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 758 rdev->irq.crtc_vblank_int[crtc] = true; 759 r = radeon_irq_set(rdev); 760 lockmgr(&rdev->irq.lock, LK_RELEASE); 761 return r; 762 } 763 764 /** 765 * radeon_disable_vblank_kms - disable vblank interrupt 766 * 767 * @dev: drm dev pointer 768 * @crtc: crtc to disable vblank interrupt for 769 * 770 * Disable the interrupt on the requested crtc (all asics). 771 */ 772 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 773 { 774 struct radeon_device *rdev = dev->dev_private; 775 776 if (crtc < 0 || crtc >= rdev->num_crtc) { 777 DRM_ERROR("Invalid crtc %d\n", crtc); 778 return; 779 } 780 781 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 782 rdev->irq.crtc_vblank_int[crtc] = false; 783 radeon_irq_set(rdev); 784 lockmgr(&rdev->irq.lock, LK_RELEASE); 785 } 786 787 /** 788 * radeon_get_vblank_timestamp_kms - get vblank timestamp 789 * 790 * @dev: drm dev pointer 791 * @crtc: crtc to get the timestamp for 792 * @max_error: max error 793 * @vblank_time: time value 794 * @flags: flags passed to the driver 795 * 796 * Gets the timestamp on the requested crtc based on the 797 * scanout position. (all asics). 798 * Returns postive status flags on success, negative error on failure. 799 */ 800 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 801 int *max_error, 802 struct timeval *vblank_time, 803 unsigned flags) 804 { 805 struct drm_crtc *drmcrtc; 806 struct radeon_device *rdev = dev->dev_private; 807 808 if (crtc < 0 || crtc >= dev->num_crtcs) { 809 DRM_ERROR("Invalid crtc %d\n", crtc); 810 return -EINVAL; 811 } 812 813 /* Get associated drm_crtc: */ 814 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 815 if (!drmcrtc) 816 return -EINVAL; 817 818 /* Helper routine in DRM core does all the work: */ 819 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 820 vblank_time, flags, 821 drmcrtc, &drmcrtc->hwmode); 822 } 823 824 #define KMS_INVALID_IOCTL(name) \ 825 static int name(struct drm_device *dev, void *data, struct drm_file \ 826 *file_priv) \ 827 { \ 828 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 829 return -EINVAL; \ 830 } 831 832 /* 833 * All these ioctls are invalid in kms world. 834 */ 835 KMS_INVALID_IOCTL(radeon_cp_init_kms) 836 KMS_INVALID_IOCTL(radeon_cp_start_kms) 837 KMS_INVALID_IOCTL(radeon_cp_stop_kms) 838 KMS_INVALID_IOCTL(radeon_cp_reset_kms) 839 KMS_INVALID_IOCTL(radeon_cp_idle_kms) 840 KMS_INVALID_IOCTL(radeon_cp_resume_kms) 841 KMS_INVALID_IOCTL(radeon_engine_reset_kms) 842 KMS_INVALID_IOCTL(radeon_fullscreen_kms) 843 KMS_INVALID_IOCTL(radeon_cp_swap_kms) 844 KMS_INVALID_IOCTL(radeon_cp_clear_kms) 845 KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 846 KMS_INVALID_IOCTL(radeon_cp_indices_kms) 847 KMS_INVALID_IOCTL(radeon_cp_texture_kms) 848 KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 849 KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 850 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 851 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 852 KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 853 KMS_INVALID_IOCTL(radeon_cp_flip_kms) 854 KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 855 KMS_INVALID_IOCTL(radeon_mem_free_kms) 856 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 857 KMS_INVALID_IOCTL(radeon_irq_emit_kms) 858 KMS_INVALID_IOCTL(radeon_irq_wait_kms) 859 KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 860 KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 861 KMS_INVALID_IOCTL(radeon_surface_free_kms) 862 863 864 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 865 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 866 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 867 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 868 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 869 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 870 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 871 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 872 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 873 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 874 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 875 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 876 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 877 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 878 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 879 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 880 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 881 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 882 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 883 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 884 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 885 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 886 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 887 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 888 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 889 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 890 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 891 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 892 /* KMS */ 893 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 894 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 895 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 896 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 897 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 898 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 899 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 900 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 901 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 902 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 903 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 904 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 905 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 906 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 907 }; 908 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 909