1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_kms.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon.h" 33 #include <uapi_drm/radeon_drm.h> 34 #include "radeon_asic.h" 35 #include "radeon_kms.h" 36 37 /** 38 * radeon_driver_unload_kms - Main unload function for KMS. 39 * 40 * @dev: drm dev pointer 41 * 42 * This is the main unload function for KMS (all asics). 43 * It calls radeon_modeset_fini() to tear down the 44 * displays, and radeon_device_fini() to tear down 45 * the rest of the device (CP, writeback, etc.). 46 * Returns 0 on success. 47 */ 48 int radeon_driver_unload_kms(struct drm_device *dev) 49 { 50 struct radeon_device *rdev = dev->dev_private; 51 52 if (rdev == NULL) 53 return 0; 54 radeon_acpi_fini(rdev); 55 radeon_modeset_fini(rdev); 56 radeon_device_fini(rdev); 57 drm_free(rdev, DRM_MEM_DRIVER); 58 dev->dev_private = NULL; 59 return 0; 60 } 61 62 /** 63 * radeon_driver_load_kms - Main load function for KMS. 64 * 65 * @dev: drm dev pointer 66 * @flags: device flags 67 * 68 * This is the main load function for KMS (all asics). 69 * It calls radeon_device_init() to set up the non-display 70 * parts of the chip (asic init, CP, writeback, etc.), and 71 * radeon_modeset_init() to set up the display parts 72 * (crtcs, encoders, hotplug detect, etc.). 73 * Returns 0 on success, error on failure. 74 */ 75 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 76 { 77 struct radeon_device *rdev; 78 int r, acpi_status; 79 80 rdev = kmalloc(sizeof(struct radeon_device), DRM_MEM_DRIVER, 81 M_ZERO | M_WAITOK); 82 if (rdev == NULL) { 83 return -ENOMEM; 84 } 85 dev->dev_private = (void *)rdev; 86 87 /* update BUS flag */ 88 if (drm_device_is_agp(dev)) { 89 DRM_INFO("RADEON_IS_AGP\n"); 90 flags |= RADEON_IS_AGP; 91 } else if (drm_device_is_pcie(dev)) { 92 DRM_INFO("RADEON_IS_PCIE\n"); 93 flags |= RADEON_IS_PCIE; 94 } else { 95 DRM_INFO("RADEON_IS_PCI\n"); 96 flags |= RADEON_IS_PCI; 97 } 98 99 /* radeon_device_init should report only fatal error 100 * like memory allocation failure or iomapping failure, 101 * or memory manager initialization failure, it must 102 * properly initialize the GPU MC controller and permit 103 * VRAM allocation 104 */ 105 r = radeon_device_init(rdev, dev, flags); 106 if (r) { 107 dev_err(dev->device, "Fatal error during GPU init\n"); 108 goto out; 109 } 110 111 /* Again modeset_init should fail only on fatal error 112 * otherwise it should provide enough functionalities 113 * for shadowfb to run 114 */ 115 r = radeon_modeset_init(rdev); 116 if (r) 117 dev_err(dev->device, "Fatal error during modeset init\n"); 118 119 /* Call ACPI methods: require modeset init 120 * but failure is not fatal 121 */ 122 if (!r) { 123 acpi_status = radeon_acpi_init(rdev); 124 if (acpi_status) 125 dev_dbg(dev->device, 126 "Error during ACPI methods call\n"); 127 } 128 129 out: 130 if (r) 131 radeon_driver_unload_kms(dev); 132 return r; 133 } 134 135 /** 136 * radeon_set_filp_rights - Set filp right. 137 * 138 * @dev: drm dev pointer 139 * @owner: drm file 140 * @applier: drm file 141 * @value: value 142 * 143 * Sets the filp rights for the device (all asics). 144 */ 145 static void radeon_set_filp_rights(struct drm_device *dev, 146 struct drm_file **owner, 147 struct drm_file *applier, 148 uint32_t *value) 149 { 150 DRM_LOCK(dev); 151 if (*value == 1) { 152 /* wants rights */ 153 if (!*owner) 154 *owner = applier; 155 } else if (*value == 0) { 156 /* revokes rights */ 157 if (*owner == applier) 158 *owner = NULL; 159 } 160 *value = *owner == applier ? 1 : 0; 161 DRM_UNLOCK(dev); 162 } 163 164 /* 165 * Userspace get information ioctl 166 */ 167 /** 168 * radeon_info_ioctl - answer a device specific request. 169 * 170 * @rdev: radeon device pointer 171 * @data: request object 172 * @filp: drm filp 173 * 174 * This function is used to pass device specific parameters to the userspace 175 * drivers. Examples include: pci device id, pipeline parms, tiling params, 176 * etc. (all asics). 177 * Returns 0 on success, -EINVAL on failure. 178 */ 179 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 180 { 181 struct radeon_device *rdev = dev->dev_private; 182 struct drm_radeon_info *info = data; 183 struct radeon_mode_info *minfo = &rdev->mode_info; 184 uint32_t value, *value_ptr; 185 uint64_t value64, *value_ptr64; 186 struct drm_crtc *crtc; 187 int i, found; 188 189 /* TIMESTAMP is a 64-bit value, needs special handling. */ 190 if (info->request == RADEON_INFO_TIMESTAMP) { 191 if (rdev->family >= CHIP_R600) { 192 value_ptr64 = (uint64_t*)((unsigned long)info->value); 193 if (rdev->family >= CHIP_TAHITI) { 194 value64 = si_get_gpu_clock(rdev); 195 } else { 196 value64 = r600_get_gpu_clock(rdev); 197 } 198 199 if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) { 200 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 201 return -EFAULT; 202 } 203 return 0; 204 } else { 205 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 206 return -EINVAL; 207 } 208 } 209 210 value_ptr = (uint32_t *)((unsigned long)info->value); 211 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) { 212 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 213 return -EFAULT; 214 } 215 216 switch (info->request) { 217 case RADEON_INFO_DEVICE_ID: 218 value = dev->pci_device; 219 break; 220 case RADEON_INFO_NUM_GB_PIPES: 221 value = rdev->num_gb_pipes; 222 break; 223 case RADEON_INFO_NUM_Z_PIPES: 224 value = rdev->num_z_pipes; 225 break; 226 case RADEON_INFO_ACCEL_WORKING: 227 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 228 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 229 value = false; 230 else 231 value = rdev->accel_working; 232 break; 233 case RADEON_INFO_CRTC_FROM_ID: 234 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 235 crtc = (struct drm_crtc *)minfo->crtcs[i]; 236 if (crtc && crtc->base.id == value) { 237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 238 value = radeon_crtc->crtc_id; 239 found = 1; 240 break; 241 } 242 } 243 if (!found) { 244 DRM_DEBUG_KMS("unknown crtc id %d\n", value); 245 return -EINVAL; 246 } 247 break; 248 case RADEON_INFO_ACCEL_WORKING2: 249 value = rdev->accel_working; 250 break; 251 case RADEON_INFO_TILING_CONFIG: 252 if (rdev->family >= CHIP_TAHITI) 253 value = rdev->config.si.tile_config; 254 else if (rdev->family >= CHIP_CAYMAN) 255 value = rdev->config.cayman.tile_config; 256 else if (rdev->family >= CHIP_CEDAR) 257 value = rdev->config.evergreen.tile_config; 258 else if (rdev->family >= CHIP_RV770) 259 value = rdev->config.rv770.tile_config; 260 else if (rdev->family >= CHIP_R600) 261 value = rdev->config.r600.tile_config; 262 else { 263 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 264 return -EINVAL; 265 } 266 break; 267 case RADEON_INFO_WANT_HYPERZ: 268 /* The "value" here is both an input and output parameter. 269 * If the input value is 1, filp requests hyper-z access. 270 * If the input value is 0, filp revokes its hyper-z access. 271 * 272 * When returning, the value is 1 if filp owns hyper-z access, 273 * 0 otherwise. */ 274 if (value >= 2) { 275 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value); 276 return -EINVAL; 277 } 278 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value); 279 break; 280 case RADEON_INFO_WANT_CMASK: 281 /* The same logic as Hyper-Z. */ 282 if (value >= 2) { 283 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value); 284 return -EINVAL; 285 } 286 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); 287 break; 288 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 289 /* return clock value in KHz */ 290 value = rdev->clock.spll.reference_freq * 10; 291 break; 292 case RADEON_INFO_NUM_BACKENDS: 293 if (rdev->family >= CHIP_TAHITI) 294 value = rdev->config.si.max_backends_per_se * 295 rdev->config.si.max_shader_engines; 296 else if (rdev->family >= CHIP_CAYMAN) 297 value = rdev->config.cayman.max_backends_per_se * 298 rdev->config.cayman.max_shader_engines; 299 else if (rdev->family >= CHIP_CEDAR) 300 value = rdev->config.evergreen.max_backends; 301 else if (rdev->family >= CHIP_RV770) 302 value = rdev->config.rv770.max_backends; 303 else if (rdev->family >= CHIP_R600) 304 value = rdev->config.r600.max_backends; 305 else { 306 return -EINVAL; 307 } 308 break; 309 case RADEON_INFO_NUM_TILE_PIPES: 310 if (rdev->family >= CHIP_TAHITI) 311 value = rdev->config.si.max_tile_pipes; 312 else if (rdev->family >= CHIP_CAYMAN) 313 value = rdev->config.cayman.max_tile_pipes; 314 else if (rdev->family >= CHIP_CEDAR) 315 value = rdev->config.evergreen.max_tile_pipes; 316 else if (rdev->family >= CHIP_RV770) 317 value = rdev->config.rv770.max_tile_pipes; 318 else if (rdev->family >= CHIP_R600) 319 value = rdev->config.r600.max_tile_pipes; 320 else { 321 return -EINVAL; 322 } 323 break; 324 case RADEON_INFO_FUSION_GART_WORKING: 325 value = 1; 326 break; 327 case RADEON_INFO_BACKEND_MAP: 328 if (rdev->family >= CHIP_TAHITI) 329 value = rdev->config.si.backend_map; 330 else if (rdev->family >= CHIP_CAYMAN) 331 value = rdev->config.cayman.backend_map; 332 else if (rdev->family >= CHIP_CEDAR) 333 value = rdev->config.evergreen.backend_map; 334 else if (rdev->family >= CHIP_RV770) 335 value = rdev->config.rv770.backend_map; 336 else if (rdev->family >= CHIP_R600) 337 value = rdev->config.r600.backend_map; 338 else { 339 return -EINVAL; 340 } 341 break; 342 case RADEON_INFO_VA_START: 343 /* this is where we report if vm is supported or not */ 344 if (rdev->family < CHIP_CAYMAN) 345 return -EINVAL; 346 value = RADEON_VA_RESERVED_SIZE; 347 break; 348 case RADEON_INFO_IB_VM_MAX_SIZE: 349 /* this is where we report if vm is supported or not */ 350 if (rdev->family < CHIP_CAYMAN) 351 return -EINVAL; 352 value = RADEON_IB_VM_MAX_SIZE; 353 break; 354 case RADEON_INFO_MAX_PIPES: 355 if (rdev->family >= CHIP_TAHITI) 356 value = rdev->config.si.max_cu_per_sh; 357 else if (rdev->family >= CHIP_CAYMAN) 358 value = rdev->config.cayman.max_pipes_per_simd; 359 else if (rdev->family >= CHIP_CEDAR) 360 value = rdev->config.evergreen.max_pipes; 361 else if (rdev->family >= CHIP_RV770) 362 value = rdev->config.rv770.max_pipes; 363 else if (rdev->family >= CHIP_R600) 364 value = rdev->config.r600.max_pipes; 365 else { 366 return -EINVAL; 367 } 368 break; 369 case RADEON_INFO_MAX_SE: 370 if (rdev->family >= CHIP_TAHITI) 371 value = rdev->config.si.max_shader_engines; 372 else if (rdev->family >= CHIP_CAYMAN) 373 value = rdev->config.cayman.max_shader_engines; 374 else if (rdev->family >= CHIP_CEDAR) 375 value = rdev->config.evergreen.num_ses; 376 else 377 value = 1; 378 break; 379 case RADEON_INFO_MAX_SH_PER_SE: 380 if (rdev->family >= CHIP_TAHITI) 381 value = rdev->config.si.max_sh_per_se; 382 else 383 return -EINVAL; 384 break; 385 default: 386 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 387 return -EINVAL; 388 } 389 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { 390 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 391 return -EFAULT; 392 } 393 return 0; 394 } 395 396 397 /* 398 * Outdated mess for old drm with Xorg being in charge (void function now). 399 */ 400 /** 401 * radeon_driver_firstopen_kms - drm callback for first open 402 * 403 * @dev: drm dev pointer 404 * 405 * Nothing to be done for KMS (all asics). 406 * Returns 0 on success. 407 */ 408 int radeon_driver_firstopen_kms(struct drm_device *dev) 409 { 410 return 0; 411 } 412 413 /** 414 * radeon_driver_firstopen_kms - drm callback for last close 415 * 416 * @dev: drm dev pointer 417 * 418 * Switch vga switcheroo state after last close (all asics). 419 */ 420 void radeon_driver_lastclose_kms(struct drm_device *dev) 421 { 422 #ifdef DUMBBELL_WIP 423 vga_switcheroo_process_delayed_switch(); 424 #endif /* DUMBBELL_WIP */ 425 } 426 427 /** 428 * radeon_driver_open_kms - drm callback for open 429 * 430 * @dev: drm dev pointer 431 * @file_priv: drm file 432 * 433 * On device open, init vm on cayman+ (all asics). 434 * Returns 0 on success, error on failure. 435 */ 436 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 437 { 438 struct radeon_device *rdev = dev->dev_private; 439 440 file_priv->driver_priv = NULL; 441 442 /* new gpu have virtual address space support */ 443 if (rdev->family >= CHIP_CAYMAN) { 444 struct radeon_fpriv *fpriv; 445 struct radeon_bo_va *bo_va; 446 int r; 447 448 fpriv = kmalloc(sizeof(*fpriv), DRM_MEM_DRIVER, 449 M_ZERO | M_WAITOK); 450 if (unlikely(!fpriv)) { 451 return -ENOMEM; 452 } 453 454 radeon_vm_init(rdev, &fpriv->vm); 455 456 /* map the ib pool buffer read only into 457 * virtual address space */ 458 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 459 rdev->ring_tmp_bo.bo); 460 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 461 RADEON_VM_PAGE_READABLE | 462 RADEON_VM_PAGE_SNOOPED); 463 if (r) { 464 radeon_vm_fini(rdev, &fpriv->vm); 465 drm_free(fpriv, DRM_MEM_DRIVER); 466 return r; 467 } 468 469 file_priv->driver_priv = fpriv; 470 } 471 return 0; 472 } 473 474 /** 475 * radeon_driver_postclose_kms - drm callback for post close 476 * 477 * @dev: drm dev pointer 478 * @file_priv: drm file 479 * 480 * On device post close, tear down vm on cayman+ (all asics). 481 */ 482 void radeon_driver_postclose_kms(struct drm_device *dev, 483 struct drm_file *file_priv) 484 { 485 struct radeon_device *rdev = dev->dev_private; 486 487 /* new gpu have virtual address space support */ 488 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 489 struct radeon_fpriv *fpriv = file_priv->driver_priv; 490 struct radeon_bo_va *bo_va; 491 int r; 492 493 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 494 if (!r) { 495 bo_va = radeon_vm_bo_find(&fpriv->vm, 496 rdev->ring_tmp_bo.bo); 497 if (bo_va) 498 radeon_vm_bo_rmv(rdev, bo_va); 499 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 500 } 501 502 radeon_vm_fini(rdev, &fpriv->vm); 503 drm_free(fpriv, DRM_MEM_DRIVER); 504 file_priv->driver_priv = NULL; 505 } 506 } 507 508 /** 509 * radeon_driver_preclose_kms - drm callback for pre close 510 * 511 * @dev: drm dev pointer 512 * @file_priv: drm file 513 * 514 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 515 * (all asics). 516 */ 517 void radeon_driver_preclose_kms(struct drm_device *dev, 518 struct drm_file *file_priv) 519 { 520 struct radeon_device *rdev = dev->dev_private; 521 if (rdev->hyperz_filp == file_priv) 522 rdev->hyperz_filp = NULL; 523 if (rdev->cmask_filp == file_priv) 524 rdev->cmask_filp = NULL; 525 } 526 527 /* 528 * VBlank related functions. 529 */ 530 /** 531 * radeon_get_vblank_counter_kms - get frame count 532 * 533 * @dev: drm dev pointer 534 * @crtc: crtc to get the frame count from 535 * 536 * Gets the frame count on the requested crtc (all asics). 537 * Returns frame count on success, -EINVAL on failure. 538 */ 539 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 540 { 541 struct radeon_device *rdev = dev->dev_private; 542 543 if (crtc < 0 || crtc >= rdev->num_crtc) { 544 DRM_ERROR("Invalid crtc %d\n", crtc); 545 return -EINVAL; 546 } 547 548 return radeon_get_vblank_counter(rdev, crtc); 549 } 550 551 /** 552 * radeon_enable_vblank_kms - enable vblank interrupt 553 * 554 * @dev: drm dev pointer 555 * @crtc: crtc to enable vblank interrupt for 556 * 557 * Enable the interrupt on the requested crtc (all asics). 558 * Returns 0 on success, -EINVAL on failure. 559 */ 560 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 561 { 562 struct radeon_device *rdev = dev->dev_private; 563 int r; 564 565 if (crtc < 0 || crtc >= rdev->num_crtc) { 566 DRM_ERROR("Invalid crtc %d\n", crtc); 567 return -EINVAL; 568 } 569 570 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 571 rdev->irq.crtc_vblank_int[crtc] = true; 572 r = radeon_irq_set(rdev); 573 lockmgr(&rdev->irq.lock, LK_RELEASE); 574 return r; 575 } 576 577 /** 578 * radeon_disable_vblank_kms - disable vblank interrupt 579 * 580 * @dev: drm dev pointer 581 * @crtc: crtc to disable vblank interrupt for 582 * 583 * Disable the interrupt on the requested crtc (all asics). 584 */ 585 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 586 { 587 struct radeon_device *rdev = dev->dev_private; 588 589 if (crtc < 0 || crtc >= rdev->num_crtc) { 590 DRM_ERROR("Invalid crtc %d\n", crtc); 591 return; 592 } 593 594 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 595 rdev->irq.crtc_vblank_int[crtc] = false; 596 radeon_irq_set(rdev); 597 lockmgr(&rdev->irq.lock, LK_RELEASE); 598 } 599 600 /** 601 * radeon_get_vblank_timestamp_kms - get vblank timestamp 602 * 603 * @dev: drm dev pointer 604 * @crtc: crtc to get the timestamp for 605 * @max_error: max error 606 * @vblank_time: time value 607 * @flags: flags passed to the driver 608 * 609 * Gets the timestamp on the requested crtc based on the 610 * scanout position. (all asics). 611 * Returns postive status flags on success, negative error on failure. 612 */ 613 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 614 int *max_error, 615 struct timeval *vblank_time, 616 unsigned flags) 617 { 618 struct drm_crtc *drmcrtc; 619 struct radeon_device *rdev = dev->dev_private; 620 621 if (crtc < 0 || crtc >= dev->num_crtcs) { 622 DRM_ERROR("Invalid crtc %d\n", crtc); 623 return -EINVAL; 624 } 625 626 /* Get associated drm_crtc: */ 627 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 628 629 /* Helper routine in DRM core does all the work: */ 630 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 631 vblank_time, flags, 632 drmcrtc); 633 } 634 635 /* 636 * IOCTL. 637 */ 638 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, 639 struct drm_file *file_priv) 640 { 641 /* Not valid in KMS. */ 642 return -EINVAL; 643 } 644 645 #define KMS_INVALID_IOCTL(name) \ 646 static int \ 647 name(struct drm_device *dev, void *data, struct drm_file *file_priv) \ 648 { \ 649 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 650 return -EINVAL; \ 651 } 652 653 /* 654 * All these ioctls are invalid in kms world. 655 */ 656 KMS_INVALID_IOCTL(radeon_cp_init_kms) 657 KMS_INVALID_IOCTL(radeon_cp_start_kms) 658 KMS_INVALID_IOCTL(radeon_cp_stop_kms) 659 KMS_INVALID_IOCTL(radeon_cp_reset_kms) 660 KMS_INVALID_IOCTL(radeon_cp_idle_kms) 661 KMS_INVALID_IOCTL(radeon_cp_resume_kms) 662 KMS_INVALID_IOCTL(radeon_engine_reset_kms) 663 KMS_INVALID_IOCTL(radeon_fullscreen_kms) 664 KMS_INVALID_IOCTL(radeon_cp_swap_kms) 665 KMS_INVALID_IOCTL(radeon_cp_clear_kms) 666 KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 667 KMS_INVALID_IOCTL(radeon_cp_indices_kms) 668 KMS_INVALID_IOCTL(radeon_cp_texture_kms) 669 KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 670 KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 671 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 672 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 673 KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 674 KMS_INVALID_IOCTL(radeon_cp_flip_kms) 675 KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 676 KMS_INVALID_IOCTL(radeon_mem_free_kms) 677 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 678 KMS_INVALID_IOCTL(radeon_irq_emit_kms) 679 KMS_INVALID_IOCTL(radeon_irq_wait_kms) 680 KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 681 KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 682 KMS_INVALID_IOCTL(radeon_surface_free_kms) 683 684 685 struct drm_ioctl_desc radeon_ioctls_kms[] = { 686 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 687 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 688 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 689 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 690 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 691 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 692 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 693 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 694 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 695 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 696 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 697 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 698 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 699 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 700 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 701 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 702 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 703 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 704 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 705 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 706 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 707 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 708 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 709 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 710 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 711 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 712 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 713 /* KMS */ 714 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 715 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), 716 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), 717 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), 718 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 719 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 720 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), 721 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), 722 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 723 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 724 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 725 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 726 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED), 727 }; 728 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); 729