1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_kms.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon.h" 33 #include <uapi_drm/radeon_drm.h> 34 #include "radeon_asic.h" 35 #include "radeon_kms.h" 36 37 #include <linux/slab.h> 38 39 /** 40 * radeon_driver_unload_kms - Main unload function for KMS. 41 * 42 * @dev: drm dev pointer 43 * 44 * This is the main unload function for KMS (all asics). 45 * It calls radeon_modeset_fini() to tear down the 46 * displays, and radeon_device_fini() to tear down 47 * the rest of the device (CP, writeback, etc.). 48 * Returns 0 on success. 49 */ 50 int radeon_driver_unload_kms(struct drm_device *dev) 51 { 52 struct radeon_device *rdev = dev->dev_private; 53 54 if (rdev == NULL) 55 return 0; 56 if (rdev->rmmio == NULL) 57 goto done_free; 58 radeon_acpi_fini(rdev); 59 radeon_modeset_fini(rdev); 60 radeon_device_fini(rdev); 61 62 done_free: 63 kfree(rdev); 64 dev->dev_private = NULL; 65 return 0; 66 } 67 68 /** 69 * radeon_driver_load_kms - Main load function for KMS. 70 * 71 * @dev: drm dev pointer 72 * @flags: device flags 73 * 74 * This is the main load function for KMS (all asics). 75 * It calls radeon_device_init() to set up the non-display 76 * parts of the chip (asic init, CP, writeback, etc.), and 77 * radeon_modeset_init() to set up the display parts 78 * (crtcs, encoders, hotplug detect, etc.). 79 * Returns 0 on success, error on failure. 80 */ 81 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 82 { 83 struct radeon_device *rdev; 84 int r, acpi_status; 85 86 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 87 if (rdev == NULL) { 88 return -ENOMEM; 89 } 90 dev->dev_private = (void *)rdev; 91 92 /* update BUS flag */ 93 if (drm_device_is_agp(dev)) { 94 DRM_INFO("RADEON_IS_AGP\n"); 95 flags |= RADEON_IS_AGP; 96 } else if (drm_device_is_pcie(dev)) { 97 DRM_INFO("RADEON_IS_PCIE\n"); 98 flags |= RADEON_IS_PCIE; 99 } else { 100 DRM_INFO("RADEON_IS_PCI\n"); 101 flags |= RADEON_IS_PCI; 102 } 103 104 /* radeon_device_init should report only fatal error 105 * like memory allocation failure or iomapping failure, 106 * or memory manager initialization failure, it must 107 * properly initialize the GPU MC controller and permit 108 * VRAM allocation 109 */ 110 r = radeon_device_init(rdev, dev, flags); 111 if (r) { 112 dev_err(dev->dev, "Fatal error during GPU init\n"); 113 goto out; 114 } 115 116 /* Again modeset_init should fail only on fatal error 117 * otherwise it should provide enough functionalities 118 * for shadowfb to run 119 */ 120 r = radeon_modeset_init(rdev); 121 if (r) 122 dev_err(dev->dev, "Fatal error during modeset init\n"); 123 124 /* Call ACPI methods: require modeset init 125 * but failure is not fatal 126 */ 127 if (!r) { 128 acpi_status = radeon_acpi_init(rdev); 129 if (acpi_status) 130 dev_dbg(dev->dev, 131 "Error during ACPI methods call\n"); 132 } 133 134 out: 135 if (r) 136 radeon_driver_unload_kms(dev); 137 return r; 138 } 139 140 /** 141 * radeon_set_filp_rights - Set filp right. 142 * 143 * @dev: drm dev pointer 144 * @owner: drm file 145 * @applier: drm file 146 * @value: value 147 * 148 * Sets the filp rights for the device (all asics). 149 */ 150 static void radeon_set_filp_rights(struct drm_device *dev, 151 struct drm_file **owner, 152 struct drm_file *applier, 153 uint32_t *value) 154 { 155 DRM_LOCK(dev); 156 if (*value == 1) { 157 /* wants rights */ 158 if (!*owner) 159 *owner = applier; 160 } else if (*value == 0) { 161 /* revokes rights */ 162 if (*owner == applier) 163 *owner = NULL; 164 } 165 *value = *owner == applier ? 1 : 0; 166 DRM_UNLOCK(dev); 167 } 168 169 /* 170 * Userspace get information ioctl 171 */ 172 /** 173 * radeon_info_ioctl - answer a device specific request. 174 * 175 * @rdev: radeon device pointer 176 * @data: request object 177 * @filp: drm filp 178 * 179 * This function is used to pass device specific parameters to the userspace 180 * drivers. Examples include: pci device id, pipeline parms, tiling params, 181 * etc. (all asics). 182 * Returns 0 on success, -EINVAL on failure. 183 */ 184 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 185 { 186 struct radeon_device *rdev = dev->dev_private; 187 struct drm_radeon_info *info = data; 188 struct radeon_mode_info *minfo = &rdev->mode_info; 189 uint32_t *value, value_tmp, *value_ptr, value_size; 190 uint64_t value64; 191 struct drm_crtc *crtc; 192 int i, found; 193 194 value_ptr = (uint32_t *)((unsigned long)info->value); 195 value = &value_tmp; 196 value_size = sizeof(uint32_t); 197 198 switch (info->request) { 199 case RADEON_INFO_DEVICE_ID: 200 *value = dev->pci_device; 201 break; 202 case RADEON_INFO_NUM_GB_PIPES: 203 *value = rdev->num_gb_pipes; 204 break; 205 case RADEON_INFO_NUM_Z_PIPES: 206 *value = rdev->num_z_pipes; 207 break; 208 case RADEON_INFO_ACCEL_WORKING: 209 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 210 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 211 *value = false; 212 else 213 *value = rdev->accel_working; 214 break; 215 case RADEON_INFO_CRTC_FROM_ID: 216 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 217 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 218 return -EFAULT; 219 } 220 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 221 crtc = (struct drm_crtc *)minfo->crtcs[i]; 222 if (crtc && crtc->base.id == *value) { 223 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 224 *value = radeon_crtc->crtc_id; 225 found = 1; 226 break; 227 } 228 } 229 if (!found) { 230 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 231 return -EINVAL; 232 } 233 break; 234 case RADEON_INFO_ACCEL_WORKING2: 235 *value = rdev->accel_working; 236 break; 237 case RADEON_INFO_TILING_CONFIG: 238 if (rdev->family >= CHIP_BONAIRE) 239 *value = rdev->config.cik.tile_config; 240 else if (rdev->family >= CHIP_TAHITI) 241 *value = rdev->config.si.tile_config; 242 else if (rdev->family >= CHIP_CAYMAN) 243 *value = rdev->config.cayman.tile_config; 244 else if (rdev->family >= CHIP_CEDAR) 245 *value = rdev->config.evergreen.tile_config; 246 else if (rdev->family >= CHIP_RV770) 247 *value = rdev->config.rv770.tile_config; 248 else if (rdev->family >= CHIP_R600) 249 *value = rdev->config.r600.tile_config; 250 else { 251 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 252 return -EINVAL; 253 } 254 break; 255 case RADEON_INFO_WANT_HYPERZ: 256 /* The "value" here is both an input and output parameter. 257 * If the input value is 1, filp requests hyper-z access. 258 * If the input value is 0, filp revokes its hyper-z access. 259 * 260 * When returning, the value is 1 if filp owns hyper-z access, 261 * 0 otherwise. */ 262 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 263 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 264 return -EFAULT; 265 } 266 if (*value >= 2) { 267 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 268 return -EINVAL; 269 } 270 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 271 break; 272 case RADEON_INFO_WANT_CMASK: 273 /* The same logic as Hyper-Z. */ 274 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 275 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 276 return -EFAULT; 277 } 278 if (*value >= 2) { 279 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 280 return -EINVAL; 281 } 282 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 283 break; 284 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 285 /* return clock value in KHz */ 286 if (rdev->asic->get_xclk) 287 *value = radeon_get_xclk(rdev) * 10; 288 else 289 *value = rdev->clock.spll.reference_freq * 10; 290 break; 291 case RADEON_INFO_NUM_BACKENDS: 292 if (rdev->family >= CHIP_BONAIRE) 293 *value = rdev->config.cik.max_backends_per_se * 294 rdev->config.cik.max_shader_engines; 295 else if (rdev->family >= CHIP_TAHITI) 296 *value = rdev->config.si.max_backends_per_se * 297 rdev->config.si.max_shader_engines; 298 else if (rdev->family >= CHIP_CAYMAN) 299 *value = rdev->config.cayman.max_backends_per_se * 300 rdev->config.cayman.max_shader_engines; 301 else if (rdev->family >= CHIP_CEDAR) 302 *value = rdev->config.evergreen.max_backends; 303 else if (rdev->family >= CHIP_RV770) 304 *value = rdev->config.rv770.max_backends; 305 else if (rdev->family >= CHIP_R600) 306 *value = rdev->config.r600.max_backends; 307 else { 308 return -EINVAL; 309 } 310 break; 311 case RADEON_INFO_NUM_TILE_PIPES: 312 if (rdev->family >= CHIP_BONAIRE) 313 *value = rdev->config.cik.max_tile_pipes; 314 else if (rdev->family >= CHIP_TAHITI) 315 *value = rdev->config.si.max_tile_pipes; 316 else if (rdev->family >= CHIP_CAYMAN) 317 *value = rdev->config.cayman.max_tile_pipes; 318 else if (rdev->family >= CHIP_CEDAR) 319 *value = rdev->config.evergreen.max_tile_pipes; 320 else if (rdev->family >= CHIP_RV770) 321 *value = rdev->config.rv770.max_tile_pipes; 322 else if (rdev->family >= CHIP_R600) 323 *value = rdev->config.r600.max_tile_pipes; 324 else { 325 return -EINVAL; 326 } 327 break; 328 case RADEON_INFO_FUSION_GART_WORKING: 329 *value = 1; 330 break; 331 case RADEON_INFO_BACKEND_MAP: 332 if (rdev->family >= CHIP_BONAIRE) 333 return -EINVAL; 334 else if (rdev->family >= CHIP_TAHITI) 335 *value = rdev->config.si.backend_map; 336 else if (rdev->family >= CHIP_CAYMAN) 337 *value = rdev->config.cayman.backend_map; 338 else if (rdev->family >= CHIP_CEDAR) 339 *value = rdev->config.evergreen.backend_map; 340 else if (rdev->family >= CHIP_RV770) 341 *value = rdev->config.rv770.backend_map; 342 else if (rdev->family >= CHIP_R600) 343 *value = rdev->config.r600.backend_map; 344 else { 345 return -EINVAL; 346 } 347 break; 348 case RADEON_INFO_VA_START: 349 /* this is where we report if vm is supported or not */ 350 if (rdev->family < CHIP_CAYMAN) 351 return -EINVAL; 352 *value = RADEON_VA_RESERVED_SIZE; 353 break; 354 case RADEON_INFO_IB_VM_MAX_SIZE: 355 /* this is where we report if vm is supported or not */ 356 if (rdev->family < CHIP_CAYMAN) 357 return -EINVAL; 358 *value = RADEON_IB_VM_MAX_SIZE; 359 break; 360 case RADEON_INFO_MAX_PIPES: 361 if (rdev->family >= CHIP_BONAIRE) 362 *value = rdev->config.cik.max_cu_per_sh; 363 else if (rdev->family >= CHIP_TAHITI) 364 *value = rdev->config.si.max_cu_per_sh; 365 else if (rdev->family >= CHIP_CAYMAN) 366 *value = rdev->config.cayman.max_pipes_per_simd; 367 else if (rdev->family >= CHIP_CEDAR) 368 *value = rdev->config.evergreen.max_pipes; 369 else if (rdev->family >= CHIP_RV770) 370 *value = rdev->config.rv770.max_pipes; 371 else if (rdev->family >= CHIP_R600) 372 *value = rdev->config.r600.max_pipes; 373 else { 374 return -EINVAL; 375 } 376 break; 377 case RADEON_INFO_TIMESTAMP: 378 if (rdev->family < CHIP_R600) { 379 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 380 return -EINVAL; 381 } 382 value = (uint32_t*)&value64; 383 value_size = sizeof(uint64_t); 384 value64 = radeon_get_gpu_clock_counter(rdev); 385 break; 386 case RADEON_INFO_MAX_SE: 387 if (rdev->family >= CHIP_BONAIRE) 388 *value = rdev->config.cik.max_shader_engines; 389 else if (rdev->family >= CHIP_TAHITI) 390 *value = rdev->config.si.max_shader_engines; 391 else if (rdev->family >= CHIP_CAYMAN) 392 *value = rdev->config.cayman.max_shader_engines; 393 else if (rdev->family >= CHIP_CEDAR) 394 *value = rdev->config.evergreen.num_ses; 395 else 396 *value = 1; 397 break; 398 case RADEON_INFO_MAX_SH_PER_SE: 399 if (rdev->family >= CHIP_BONAIRE) 400 *value = rdev->config.cik.max_sh_per_se; 401 else if (rdev->family >= CHIP_TAHITI) 402 *value = rdev->config.si.max_sh_per_se; 403 else 404 return -EINVAL; 405 break; 406 case RADEON_INFO_FASTFB_WORKING: 407 *value = rdev->fastfb_working; 408 break; 409 case RADEON_INFO_RING_WORKING: 410 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 411 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 412 return -EFAULT; 413 } 414 switch (*value) { 415 case RADEON_CS_RING_GFX: 416 case RADEON_CS_RING_COMPUTE: 417 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 418 break; 419 case RADEON_CS_RING_DMA: 420 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 421 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 422 break; 423 case RADEON_CS_RING_UVD: 424 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 425 break; 426 default: 427 return -EINVAL; 428 } 429 break; 430 case RADEON_INFO_SI_TILE_MODE_ARRAY: 431 if (rdev->family >= CHIP_BONAIRE) { 432 value = rdev->config.cik.tile_mode_array; 433 value_size = sizeof(uint32_t)*32; 434 } else if (rdev->family >= CHIP_TAHITI) { 435 value = rdev->config.si.tile_mode_array; 436 value_size = sizeof(uint32_t)*32; 437 } else { 438 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 439 return -EINVAL; 440 } 441 break; 442 default: 443 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 444 return -EINVAL; 445 } 446 if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) { 447 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 448 return -EFAULT; 449 } 450 return 0; 451 } 452 453 454 /* 455 * Outdated mess for old drm with Xorg being in charge (void function now). 456 */ 457 /** 458 * radeon_driver_firstopen_kms - drm callback for first open 459 * 460 * @dev: drm dev pointer 461 * 462 * Nothing to be done for KMS (all asics). 463 * Returns 0 on success. 464 */ 465 int radeon_driver_firstopen_kms(struct drm_device *dev) 466 { 467 return 0; 468 } 469 470 /** 471 * radeon_driver_firstopen_kms - drm callback for last close 472 * 473 * @dev: drm dev pointer 474 * 475 * Switch vga switcheroo state after last close (all asics). 476 */ 477 void radeon_driver_lastclose_kms(struct drm_device *dev) 478 { 479 #ifdef DUMBBELL_WIP 480 vga_switcheroo_process_delayed_switch(); 481 #endif /* DUMBBELL_WIP */ 482 } 483 484 /** 485 * radeon_driver_open_kms - drm callback for open 486 * 487 * @dev: drm dev pointer 488 * @file_priv: drm file 489 * 490 * On device open, init vm on cayman+ (all asics). 491 * Returns 0 on success, error on failure. 492 */ 493 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 494 { 495 struct radeon_device *rdev = dev->dev_private; 496 497 file_priv->driver_priv = NULL; 498 499 /* new gpu have virtual address space support */ 500 if (rdev->family >= CHIP_CAYMAN) { 501 struct radeon_fpriv *fpriv; 502 struct radeon_bo_va *bo_va; 503 int r; 504 505 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 506 if (unlikely(!fpriv)) { 507 return -ENOMEM; 508 } 509 510 radeon_vm_init(rdev, &fpriv->vm); 511 512 /* map the ib pool buffer read only into 513 * virtual address space */ 514 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 515 rdev->ring_tmp_bo.bo); 516 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 517 RADEON_VM_PAGE_READABLE | 518 RADEON_VM_PAGE_SNOOPED); 519 if (r) { 520 radeon_vm_fini(rdev, &fpriv->vm); 521 kfree(fpriv); 522 return r; 523 } 524 525 file_priv->driver_priv = fpriv; 526 } 527 return 0; 528 } 529 530 /** 531 * radeon_driver_postclose_kms - drm callback for post close 532 * 533 * @dev: drm dev pointer 534 * @file_priv: drm file 535 * 536 * On device post close, tear down vm on cayman+ (all asics). 537 */ 538 void radeon_driver_postclose_kms(struct drm_device *dev, 539 struct drm_file *file_priv) 540 { 541 struct radeon_device *rdev = dev->dev_private; 542 543 /* new gpu have virtual address space support */ 544 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 545 struct radeon_fpriv *fpriv = file_priv->driver_priv; 546 struct radeon_bo_va *bo_va; 547 int r; 548 549 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 550 if (!r) { 551 bo_va = radeon_vm_bo_find(&fpriv->vm, 552 rdev->ring_tmp_bo.bo); 553 if (bo_va) 554 radeon_vm_bo_rmv(rdev, bo_va); 555 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 556 } 557 558 radeon_vm_fini(rdev, &fpriv->vm); 559 kfree(fpriv); 560 file_priv->driver_priv = NULL; 561 } 562 } 563 564 /** 565 * radeon_driver_preclose_kms - drm callback for pre close 566 * 567 * @dev: drm dev pointer 568 * @file_priv: drm file 569 * 570 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 571 * (all asics). 572 */ 573 void radeon_driver_preclose_kms(struct drm_device *dev, 574 struct drm_file *file_priv) 575 { 576 struct radeon_device *rdev = dev->dev_private; 577 if (rdev->hyperz_filp == file_priv) 578 rdev->hyperz_filp = NULL; 579 if (rdev->cmask_filp == file_priv) 580 rdev->cmask_filp = NULL; 581 radeon_uvd_free_handles(rdev, file_priv); 582 } 583 584 /* 585 * VBlank related functions. 586 */ 587 /** 588 * radeon_get_vblank_counter_kms - get frame count 589 * 590 * @dev: drm dev pointer 591 * @crtc: crtc to get the frame count from 592 * 593 * Gets the frame count on the requested crtc (all asics). 594 * Returns frame count on success, -EINVAL on failure. 595 */ 596 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 597 { 598 struct radeon_device *rdev = dev->dev_private; 599 600 if (crtc < 0 || crtc >= rdev->num_crtc) { 601 DRM_ERROR("Invalid crtc %d\n", crtc); 602 return -EINVAL; 603 } 604 605 return radeon_get_vblank_counter(rdev, crtc); 606 } 607 608 /** 609 * radeon_enable_vblank_kms - enable vblank interrupt 610 * 611 * @dev: drm dev pointer 612 * @crtc: crtc to enable vblank interrupt for 613 * 614 * Enable the interrupt on the requested crtc (all asics). 615 * Returns 0 on success, -EINVAL on failure. 616 */ 617 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 618 { 619 struct radeon_device *rdev = dev->dev_private; 620 int r; 621 622 if (crtc < 0 || crtc >= rdev->num_crtc) { 623 DRM_ERROR("Invalid crtc %d\n", crtc); 624 return -EINVAL; 625 } 626 627 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 628 rdev->irq.crtc_vblank_int[crtc] = true; 629 r = radeon_irq_set(rdev); 630 lockmgr(&rdev->irq.lock, LK_RELEASE); 631 return r; 632 } 633 634 /** 635 * radeon_disable_vblank_kms - disable vblank interrupt 636 * 637 * @dev: drm dev pointer 638 * @crtc: crtc to disable vblank interrupt for 639 * 640 * Disable the interrupt on the requested crtc (all asics). 641 */ 642 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 643 { 644 struct radeon_device *rdev = dev->dev_private; 645 646 if (crtc < 0 || crtc >= rdev->num_crtc) { 647 DRM_ERROR("Invalid crtc %d\n", crtc); 648 return; 649 } 650 651 lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); 652 rdev->irq.crtc_vblank_int[crtc] = false; 653 radeon_irq_set(rdev); 654 lockmgr(&rdev->irq.lock, LK_RELEASE); 655 } 656 657 /** 658 * radeon_get_vblank_timestamp_kms - get vblank timestamp 659 * 660 * @dev: drm dev pointer 661 * @crtc: crtc to get the timestamp for 662 * @max_error: max error 663 * @vblank_time: time value 664 * @flags: flags passed to the driver 665 * 666 * Gets the timestamp on the requested crtc based on the 667 * scanout position. (all asics). 668 * Returns postive status flags on success, negative error on failure. 669 */ 670 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 671 int *max_error, 672 struct timeval *vblank_time, 673 unsigned flags) 674 { 675 struct drm_crtc *drmcrtc; 676 struct radeon_device *rdev = dev->dev_private; 677 678 if (crtc < 0 || crtc >= dev->num_crtcs) { 679 DRM_ERROR("Invalid crtc %d\n", crtc); 680 return -EINVAL; 681 } 682 683 /* Get associated drm_crtc: */ 684 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 685 686 /* Helper routine in DRM core does all the work: */ 687 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 688 vblank_time, flags, 689 drmcrtc, &drmcrtc->hwmode); 690 } 691 692 /* 693 * IOCTL. 694 */ 695 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, 696 struct drm_file *file_priv) 697 { 698 /* Not valid in KMS. */ 699 return -EINVAL; 700 } 701 702 #define KMS_INVALID_IOCTL(name) \ 703 static int \ 704 name(struct drm_device *dev, void *data, struct drm_file *file_priv) \ 705 { \ 706 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 707 return -EINVAL; \ 708 } 709 710 /* 711 * All these ioctls are invalid in kms world. 712 */ 713 KMS_INVALID_IOCTL(radeon_cp_init_kms) 714 KMS_INVALID_IOCTL(radeon_cp_start_kms) 715 KMS_INVALID_IOCTL(radeon_cp_stop_kms) 716 KMS_INVALID_IOCTL(radeon_cp_reset_kms) 717 KMS_INVALID_IOCTL(radeon_cp_idle_kms) 718 KMS_INVALID_IOCTL(radeon_cp_resume_kms) 719 KMS_INVALID_IOCTL(radeon_engine_reset_kms) 720 KMS_INVALID_IOCTL(radeon_fullscreen_kms) 721 KMS_INVALID_IOCTL(radeon_cp_swap_kms) 722 KMS_INVALID_IOCTL(radeon_cp_clear_kms) 723 KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 724 KMS_INVALID_IOCTL(radeon_cp_indices_kms) 725 KMS_INVALID_IOCTL(radeon_cp_texture_kms) 726 KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 727 KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 728 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 729 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 730 KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 731 KMS_INVALID_IOCTL(radeon_cp_flip_kms) 732 KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 733 KMS_INVALID_IOCTL(radeon_mem_free_kms) 734 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 735 KMS_INVALID_IOCTL(radeon_irq_emit_kms) 736 KMS_INVALID_IOCTL(radeon_irq_wait_kms) 737 KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 738 KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 739 KMS_INVALID_IOCTL(radeon_surface_free_kms) 740 741 742 struct drm_ioctl_desc radeon_ioctls_kms[] = { 743 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 744 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 745 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 746 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 747 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 748 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 749 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 750 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 751 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 752 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 753 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 754 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 755 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 756 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 757 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 758 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 759 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 760 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 761 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 762 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 763 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 764 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 765 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 766 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 767 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 768 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 769 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 770 /* KMS */ 771 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 772 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), 773 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), 774 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), 775 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 776 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 777 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), 778 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), 779 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 780 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 781 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 782 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 783 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED), 784 }; 785 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); 786