1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include <uapi_drm/radeon_drm.h> 31 #include "radeon_asic.h" 32 #include "radeon_kms.h" 33 34 #include <linux/slab.h> 35 #ifdef PM_TODO 36 #include <linux/pm_runtime.h> 37 #endif 38 39 #ifdef PM_TODO 40 #if defined(CONFIG_VGA_SWITCHEROO) 41 bool radeon_has_atpx(void); 42 #else 43 static inline bool radeon_has_atpx(void) { return false; } 44 #endif 45 #endif 46 47 /** 48 * radeon_driver_unload_kms - Main unload function for KMS. 49 * 50 * @dev: drm dev pointer 51 * 52 * This is the main unload function for KMS (all asics). 53 * It calls radeon_modeset_fini() to tear down the 54 * displays, and radeon_device_fini() to tear down 55 * the rest of the device (CP, writeback, etc.). 56 * Returns 0 on success. 57 */ 58 int radeon_driver_unload_kms(struct drm_device *dev) 59 { 60 struct radeon_device *rdev = dev->dev_private; 61 62 if (rdev == NULL) 63 return 0; 64 65 if (rdev->rmmio == NULL) 66 goto done_free; 67 68 #ifdef PM_TODO 69 pm_runtime_get_sync(dev->dev); 70 #endif 71 72 radeon_acpi_fini(rdev); 73 radeon_modeset_fini(rdev); 74 radeon_device_fini(rdev); 75 76 done_free: 77 /* XXX pending drm update, after this accessing pdev is illegal! */ 78 drm_fini_pdev(&dev->pdev); 79 kfree(rdev); 80 dev->dev_private = NULL; 81 return 0; 82 } 83 84 /** 85 * radeon_driver_load_kms - Main load function for KMS. 86 * 87 * @dev: drm dev pointer 88 * @flags: device flags 89 * 90 * This is the main load function for KMS (all asics). 91 * It calls radeon_device_init() to set up the non-display 92 * parts of the chip (asic init, CP, writeback, etc.), and 93 * radeon_modeset_init() to set up the display parts 94 * (crtcs, encoders, hotplug detect, etc.). 95 * Returns 0 on success, error on failure. 96 */ 97 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 98 { 99 struct radeon_device *rdev; 100 int r, acpi_status; 101 102 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 103 if (rdev == NULL) { 104 return -ENOMEM; 105 } 106 dev->dev_private = (void *)rdev; 107 108 /* update BUS flag */ 109 if (drm_pci_device_is_agp(dev)) { 110 DRM_INFO("RADEON_IS_AGP\n"); 111 flags |= RADEON_IS_AGP; 112 } else if (pci_is_pcie(dev->dev->bsddev)) { 113 DRM_INFO("RADEON_IS_PCIE\n"); 114 flags |= RADEON_IS_PCIE; 115 } else { 116 DRM_INFO("RADEON_IS_PCI\n"); 117 flags |= RADEON_IS_PCI; 118 } 119 120 #ifdef PM_TODO 121 if ((radeon_runtime_pm != 0) && 122 radeon_has_atpx() && 123 ((flags & RADEON_IS_IGP) == 0)) 124 flags |= RADEON_IS_PX; 125 #endif 126 127 /* radeon_device_init should report only fatal error 128 * like memory allocation failure or iomapping failure, 129 * or memory manager initialization failure, it must 130 * properly initialize the GPU MC controller and permit 131 * VRAM allocation 132 */ 133 r = radeon_device_init(rdev, dev, dev->pdev, flags); 134 if (r) { 135 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 136 goto out; 137 } 138 139 /* Again modeset_init should fail only on fatal error 140 * otherwise it should provide enough functionalities 141 * for shadowfb to run 142 */ 143 r = radeon_modeset_init(rdev); 144 if (r) 145 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 146 147 /* Call ACPI methods: require modeset init 148 * but failure is not fatal 149 */ 150 if (!r) { 151 acpi_status = radeon_acpi_init(rdev); 152 if (acpi_status) 153 dev_dbg(&dev->pdev->dev, 154 "Error during ACPI methods call\n"); 155 } 156 157 #ifdef PM_TODO 158 if (radeon_is_px(dev)) { 159 pm_runtime_use_autosuspend(dev->dev); 160 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 161 pm_runtime_set_active(dev->dev); 162 pm_runtime_allow(dev->dev); 163 pm_runtime_mark_last_busy(dev->dev); 164 pm_runtime_put_autosuspend(dev->dev); 165 } 166 #endif 167 168 out: 169 if (r) 170 radeon_driver_unload_kms(dev); 171 172 173 return r; 174 } 175 176 /** 177 * radeon_set_filp_rights - Set filp right. 178 * 179 * @dev: drm dev pointer 180 * @owner: drm file 181 * @applier: drm file 182 * @value: value 183 * 184 * Sets the filp rights for the device (all asics). 185 */ 186 static void radeon_set_filp_rights(struct drm_device *dev, 187 struct drm_file **owner, 188 struct drm_file *applier, 189 uint32_t *value) 190 { 191 struct radeon_device *rdev = dev->dev_private; 192 193 mutex_lock(&rdev->gem.mutex); 194 if (*value == 1) { 195 /* wants rights */ 196 if (!*owner) 197 *owner = applier; 198 } else if (*value == 0) { 199 /* revokes rights */ 200 if (*owner == applier) 201 *owner = NULL; 202 } 203 *value = *owner == applier ? 1 : 0; 204 mutex_unlock(&rdev->gem.mutex); 205 } 206 207 /* 208 * Userspace get information ioctl 209 */ 210 /** 211 * radeon_info_ioctl - answer a device specific request. 212 * 213 * @rdev: radeon device pointer 214 * @data: request object 215 * @filp: drm filp 216 * 217 * This function is used to pass device specific parameters to the userspace 218 * drivers. Examples include: pci device id, pipeline parms, tiling params, 219 * etc. (all asics). 220 * Returns 0 on success, -EINVAL on failure. 221 */ 222 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 223 { 224 struct radeon_device *rdev = dev->dev_private; 225 struct drm_radeon_info *info = data; 226 struct radeon_mode_info *minfo = &rdev->mode_info; 227 uint32_t *value, value_tmp, *value_ptr, value_size; 228 uint64_t value64; 229 struct drm_crtc *crtc; 230 int i, found; 231 232 value_ptr = (uint32_t *)((unsigned long)info->value); 233 value = &value_tmp; 234 value_size = sizeof(uint32_t); 235 236 switch (info->request) { 237 case RADEON_INFO_DEVICE_ID: 238 *value = dev->pdev->device; 239 break; 240 case RADEON_INFO_NUM_GB_PIPES: 241 *value = rdev->num_gb_pipes; 242 break; 243 case RADEON_INFO_NUM_Z_PIPES: 244 *value = rdev->num_z_pipes; 245 break; 246 case RADEON_INFO_ACCEL_WORKING: 247 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 248 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 249 *value = false; 250 else 251 *value = rdev->accel_working; 252 break; 253 case RADEON_INFO_CRTC_FROM_ID: 254 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 255 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 256 return -EFAULT; 257 } 258 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 259 crtc = (struct drm_crtc *)minfo->crtcs[i]; 260 if (crtc && crtc->base.id == *value) { 261 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 262 *value = radeon_crtc->crtc_id; 263 found = 1; 264 break; 265 } 266 } 267 if (!found) { 268 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 269 return -EINVAL; 270 } 271 break; 272 case RADEON_INFO_ACCEL_WORKING2: 273 if (rdev->family == CHIP_HAWAII) { 274 if (rdev->accel_working) { 275 if (rdev->new_fw) 276 *value = 3; 277 else 278 *value = 2; 279 } else { 280 *value = 0; 281 } 282 } else { 283 *value = rdev->accel_working; 284 } 285 break; 286 case RADEON_INFO_TILING_CONFIG: 287 if (rdev->family >= CHIP_BONAIRE) 288 *value = rdev->config.cik.tile_config; 289 else if (rdev->family >= CHIP_TAHITI) 290 *value = rdev->config.si.tile_config; 291 else if (rdev->family >= CHIP_CAYMAN) 292 *value = rdev->config.cayman.tile_config; 293 else if (rdev->family >= CHIP_CEDAR) 294 *value = rdev->config.evergreen.tile_config; 295 else if (rdev->family >= CHIP_RV770) 296 *value = rdev->config.rv770.tile_config; 297 else if (rdev->family >= CHIP_R600) 298 *value = rdev->config.r600.tile_config; 299 else { 300 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 301 return -EINVAL; 302 } 303 break; 304 case RADEON_INFO_WANT_HYPERZ: 305 /* The "value" here is both an input and output parameter. 306 * If the input value is 1, filp requests hyper-z access. 307 * If the input value is 0, filp revokes its hyper-z access. 308 * 309 * When returning, the value is 1 if filp owns hyper-z access, 310 * 0 otherwise. */ 311 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 312 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 313 return -EFAULT; 314 } 315 if (*value >= 2) { 316 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 317 return -EINVAL; 318 } 319 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 320 break; 321 case RADEON_INFO_WANT_CMASK: 322 /* The same logic as Hyper-Z. */ 323 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 324 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 325 return -EFAULT; 326 } 327 if (*value >= 2) { 328 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 329 return -EINVAL; 330 } 331 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 332 break; 333 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 334 /* return clock value in KHz */ 335 if (rdev->asic->get_xclk) 336 *value = radeon_get_xclk(rdev) * 10; 337 else 338 *value = rdev->clock.spll.reference_freq * 10; 339 break; 340 case RADEON_INFO_NUM_BACKENDS: 341 if (rdev->family >= CHIP_BONAIRE) 342 *value = rdev->config.cik.max_backends_per_se * 343 rdev->config.cik.max_shader_engines; 344 else if (rdev->family >= CHIP_TAHITI) 345 *value = rdev->config.si.max_backends_per_se * 346 rdev->config.si.max_shader_engines; 347 else if (rdev->family >= CHIP_CAYMAN) 348 *value = rdev->config.cayman.max_backends_per_se * 349 rdev->config.cayman.max_shader_engines; 350 else if (rdev->family >= CHIP_CEDAR) 351 *value = rdev->config.evergreen.max_backends; 352 else if (rdev->family >= CHIP_RV770) 353 *value = rdev->config.rv770.max_backends; 354 else if (rdev->family >= CHIP_R600) 355 *value = rdev->config.r600.max_backends; 356 else { 357 return -EINVAL; 358 } 359 break; 360 case RADEON_INFO_NUM_TILE_PIPES: 361 if (rdev->family >= CHIP_BONAIRE) 362 *value = rdev->config.cik.max_tile_pipes; 363 else if (rdev->family >= CHIP_TAHITI) 364 *value = rdev->config.si.max_tile_pipes; 365 else if (rdev->family >= CHIP_CAYMAN) 366 *value = rdev->config.cayman.max_tile_pipes; 367 else if (rdev->family >= CHIP_CEDAR) 368 *value = rdev->config.evergreen.max_tile_pipes; 369 else if (rdev->family >= CHIP_RV770) 370 *value = rdev->config.rv770.max_tile_pipes; 371 else if (rdev->family >= CHIP_R600) 372 *value = rdev->config.r600.max_tile_pipes; 373 else { 374 return -EINVAL; 375 } 376 break; 377 case RADEON_INFO_FUSION_GART_WORKING: 378 *value = 1; 379 break; 380 case RADEON_INFO_BACKEND_MAP: 381 if (rdev->family >= CHIP_BONAIRE) 382 *value = rdev->config.cik.backend_map; 383 else if (rdev->family >= CHIP_TAHITI) 384 *value = rdev->config.si.backend_map; 385 else if (rdev->family >= CHIP_CAYMAN) 386 *value = rdev->config.cayman.backend_map; 387 else if (rdev->family >= CHIP_CEDAR) 388 *value = rdev->config.evergreen.backend_map; 389 else if (rdev->family >= CHIP_RV770) 390 *value = rdev->config.rv770.backend_map; 391 else if (rdev->family >= CHIP_R600) 392 *value = rdev->config.r600.backend_map; 393 else { 394 return -EINVAL; 395 } 396 break; 397 case RADEON_INFO_VA_START: 398 /* this is where we report if vm is supported or not */ 399 if (rdev->family < CHIP_CAYMAN) 400 return -EINVAL; 401 *value = RADEON_VA_RESERVED_SIZE; 402 break; 403 case RADEON_INFO_IB_VM_MAX_SIZE: 404 /* this is where we report if vm is supported or not */ 405 if (rdev->family < CHIP_CAYMAN) 406 return -EINVAL; 407 *value = RADEON_IB_VM_MAX_SIZE; 408 break; 409 case RADEON_INFO_MAX_PIPES: 410 if (rdev->family >= CHIP_BONAIRE) 411 *value = rdev->config.cik.max_cu_per_sh; 412 else if (rdev->family >= CHIP_TAHITI) 413 *value = rdev->config.si.max_cu_per_sh; 414 else if (rdev->family >= CHIP_CAYMAN) 415 *value = rdev->config.cayman.max_pipes_per_simd; 416 else if (rdev->family >= CHIP_CEDAR) 417 *value = rdev->config.evergreen.max_pipes; 418 else if (rdev->family >= CHIP_RV770) 419 *value = rdev->config.rv770.max_pipes; 420 else if (rdev->family >= CHIP_R600) 421 *value = rdev->config.r600.max_pipes; 422 else { 423 return -EINVAL; 424 } 425 break; 426 case RADEON_INFO_TIMESTAMP: 427 if (rdev->family < CHIP_R600) { 428 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 429 return -EINVAL; 430 } 431 value = (uint32_t*)&value64; 432 value_size = sizeof(uint64_t); 433 value64 = radeon_get_gpu_clock_counter(rdev); 434 break; 435 case RADEON_INFO_MAX_SE: 436 if (rdev->family >= CHIP_BONAIRE) 437 *value = rdev->config.cik.max_shader_engines; 438 else if (rdev->family >= CHIP_TAHITI) 439 *value = rdev->config.si.max_shader_engines; 440 else if (rdev->family >= CHIP_CAYMAN) 441 *value = rdev->config.cayman.max_shader_engines; 442 else if (rdev->family >= CHIP_CEDAR) 443 *value = rdev->config.evergreen.num_ses; 444 else 445 *value = 1; 446 break; 447 case RADEON_INFO_MAX_SH_PER_SE: 448 if (rdev->family >= CHIP_BONAIRE) 449 *value = rdev->config.cik.max_sh_per_se; 450 else if (rdev->family >= CHIP_TAHITI) 451 *value = rdev->config.si.max_sh_per_se; 452 else 453 return -EINVAL; 454 break; 455 case RADEON_INFO_FASTFB_WORKING: 456 *value = rdev->fastfb_working; 457 break; 458 case RADEON_INFO_RING_WORKING: 459 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 460 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 461 return -EFAULT; 462 } 463 switch (*value) { 464 case RADEON_CS_RING_GFX: 465 case RADEON_CS_RING_COMPUTE: 466 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 467 break; 468 case RADEON_CS_RING_DMA: 469 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 470 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 471 break; 472 case RADEON_CS_RING_UVD: 473 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 474 break; 475 case RADEON_CS_RING_VCE: 476 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 477 break; 478 default: 479 return -EINVAL; 480 } 481 break; 482 case RADEON_INFO_SI_TILE_MODE_ARRAY: 483 if (rdev->family >= CHIP_BONAIRE) { 484 value = rdev->config.cik.tile_mode_array; 485 value_size = sizeof(uint32_t)*32; 486 } else if (rdev->family >= CHIP_TAHITI) { 487 value = rdev->config.si.tile_mode_array; 488 value_size = sizeof(uint32_t)*32; 489 } else { 490 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 491 return -EINVAL; 492 } 493 break; 494 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 495 if (rdev->family >= CHIP_BONAIRE) { 496 value = rdev->config.cik.macrotile_mode_array; 497 value_size = sizeof(uint32_t)*16; 498 } else { 499 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 500 return -EINVAL; 501 } 502 break; 503 case RADEON_INFO_SI_CP_DMA_COMPUTE: 504 *value = 1; 505 break; 506 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 507 if (rdev->family >= CHIP_BONAIRE) { 508 *value = rdev->config.cik.backend_enable_mask; 509 } else if (rdev->family >= CHIP_TAHITI) { 510 *value = rdev->config.si.backend_enable_mask; 511 } else { 512 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 513 } 514 break; 515 case RADEON_INFO_MAX_SCLK: 516 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 517 rdev->pm.dpm_enabled) 518 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 519 else 520 *value = rdev->pm.default_sclk * 10; 521 break; 522 case RADEON_INFO_VCE_FW_VERSION: 523 *value = rdev->vce.fw_version; 524 break; 525 case RADEON_INFO_VCE_FB_VERSION: 526 *value = rdev->vce.fb_version; 527 break; 528 case RADEON_INFO_NUM_BYTES_MOVED: 529 value = (uint32_t*)&value64; 530 value_size = sizeof(uint64_t); 531 value64 = atomic64_read(&rdev->num_bytes_moved); 532 break; 533 case RADEON_INFO_VRAM_USAGE: 534 value = (uint32_t*)&value64; 535 value_size = sizeof(uint64_t); 536 value64 = atomic64_read(&rdev->vram_usage); 537 break; 538 case RADEON_INFO_GTT_USAGE: 539 value = (uint32_t*)&value64; 540 value_size = sizeof(uint64_t); 541 value64 = atomic64_read(&rdev->gtt_usage); 542 break; 543 case RADEON_INFO_ACTIVE_CU_COUNT: 544 if (rdev->family >= CHIP_BONAIRE) 545 *value = rdev->config.cik.active_cus; 546 else if (rdev->family >= CHIP_TAHITI) 547 *value = rdev->config.si.active_cus; 548 else if (rdev->family >= CHIP_CAYMAN) 549 *value = rdev->config.cayman.active_simds; 550 else if (rdev->family >= CHIP_CEDAR) 551 *value = rdev->config.evergreen.active_simds; 552 else if (rdev->family >= CHIP_RV770) 553 *value = rdev->config.rv770.active_simds; 554 else if (rdev->family >= CHIP_R600) 555 *value = rdev->config.r600.active_simds; 556 else 557 *value = 1; 558 break; 559 case RADEON_INFO_CURRENT_GPU_TEMP: 560 /* get temperature in millidegrees C */ 561 if (rdev->asic->pm.get_temperature) 562 *value = radeon_get_temperature(rdev); 563 else 564 *value = 0; 565 break; 566 case RADEON_INFO_CURRENT_GPU_SCLK: 567 /* get sclk in Mhz */ 568 if (rdev->pm.dpm_enabled) 569 *value = radeon_dpm_get_current_sclk(rdev) / 100; 570 else 571 *value = rdev->pm.current_sclk / 100; 572 break; 573 case RADEON_INFO_CURRENT_GPU_MCLK: 574 /* get mclk in Mhz */ 575 if (rdev->pm.dpm_enabled) 576 *value = radeon_dpm_get_current_mclk(rdev) / 100; 577 else 578 *value = rdev->pm.current_mclk / 100; 579 break; 580 case RADEON_INFO_READ_REG: 581 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 582 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 583 return -EFAULT; 584 } 585 if (radeon_get_allowed_info_register(rdev, *value, value)) 586 return -EINVAL; 587 break; 588 case RADEON_INFO_GPU_RESET_COUNTER: 589 *value = atomic_read(&rdev->gpu_reset_counter); 590 break; 591 default: 592 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 593 return -EINVAL; 594 } 595 if (copy_to_user(value_ptr, (char*)value, value_size)) { 596 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 597 return -EFAULT; 598 } 599 return 0; 600 } 601 602 603 /* 604 * Outdated mess for old drm with Xorg being in charge (void function now). 605 */ 606 /** 607 * radeon_driver_lastclose_kms - drm callback for last close 608 * 609 * @dev: drm dev pointer 610 * 611 * Switch vga_switcheroo state after last close (all asics). 612 */ 613 void radeon_driver_lastclose_kms(struct drm_device *dev) 614 { 615 struct radeon_device *rdev = dev->dev_private; 616 617 radeon_fbdev_restore_mode(rdev); 618 #ifdef DUMBBELL_WIP 619 vga_switcheroo_process_delayed_switch(); 620 #endif /* DUMBBELL_WIP */ 621 } 622 623 /** 624 * radeon_driver_open_kms - drm callback for open 625 * 626 * @dev: drm dev pointer 627 * @file_priv: drm file 628 * 629 * On device open, init vm on cayman+ (all asics). 630 * Returns 0 on success, error on failure. 631 */ 632 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 633 { 634 struct radeon_device *rdev = dev->dev_private; 635 636 file_priv->driver_priv = NULL; 637 638 #ifdef PM_TODO 639 r = pm_runtime_get_sync(dev->dev); 640 if (r < 0) 641 return r; 642 #endif 643 644 /* new gpu have virtual address space support */ 645 if (rdev->family >= CHIP_CAYMAN) { 646 struct radeon_fpriv *fpriv; 647 struct radeon_vm *vm; 648 int r; 649 650 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 651 if (unlikely(!fpriv)) { 652 return -ENOMEM; 653 } 654 655 if (rdev->accel_working) { 656 vm = &fpriv->vm; 657 r = radeon_vm_init(rdev, vm); 658 if (r) { 659 kfree(fpriv); 660 return r; 661 } 662 663 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 664 if (r) { 665 radeon_vm_fini(rdev, vm); 666 kfree(fpriv); 667 return r; 668 } 669 670 /* map the ib pool buffer read only into 671 * virtual address space */ 672 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 673 rdev->ring_tmp_bo.bo); 674 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 675 RADEON_VA_IB_OFFSET, 676 RADEON_VM_PAGE_READABLE | 677 RADEON_VM_PAGE_SNOOPED); 678 679 if (r) { 680 radeon_vm_fini(rdev, vm); 681 kfree(fpriv); 682 return r; 683 } 684 } 685 file_priv->driver_priv = fpriv; 686 } 687 688 #ifdef PM_TODO 689 pm_runtime_mark_last_busy(dev->dev); 690 pm_runtime_put_autosuspend(dev->dev); 691 #endif 692 return 0; 693 } 694 695 /** 696 * radeon_driver_postclose_kms - drm callback for post close 697 * 698 * @dev: drm dev pointer 699 * @file_priv: drm file 700 * 701 * On device post close, tear down vm on cayman+ (all asics). 702 */ 703 void radeon_driver_postclose_kms(struct drm_device *dev, 704 struct drm_file *file_priv) 705 { 706 struct radeon_device *rdev = dev->dev_private; 707 708 /* new gpu have virtual address space support */ 709 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 710 struct radeon_fpriv *fpriv = file_priv->driver_priv; 711 struct radeon_vm *vm = &fpriv->vm; 712 int r; 713 714 if (rdev->accel_working) { 715 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 716 if (!r) { 717 if (vm->ib_bo_va) 718 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 719 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 720 } 721 radeon_vm_fini(rdev, vm); 722 } 723 724 kfree(fpriv); 725 file_priv->driver_priv = NULL; 726 } 727 } 728 729 /** 730 * radeon_driver_preclose_kms - drm callback for pre close 731 * 732 * @dev: drm dev pointer 733 * @file_priv: drm file 734 * 735 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 736 * (all asics). 737 */ 738 void radeon_driver_preclose_kms(struct drm_device *dev, 739 struct drm_file *file_priv) 740 { 741 struct radeon_device *rdev = dev->dev_private; 742 743 mutex_lock(&rdev->gem.mutex); 744 if (rdev->hyperz_filp == file_priv) 745 rdev->hyperz_filp = NULL; 746 if (rdev->cmask_filp == file_priv) 747 rdev->cmask_filp = NULL; 748 mutex_unlock(&rdev->gem.mutex); 749 750 radeon_uvd_free_handles(rdev, file_priv); 751 radeon_vce_free_handles(rdev, file_priv); 752 } 753 754 /* 755 * VBlank related functions. 756 */ 757 /** 758 * radeon_get_vblank_counter_kms - get frame count 759 * 760 * @dev: drm dev pointer 761 * @pipe: crtc to get the frame count from 762 * 763 * Gets the frame count on the requested crtc (all asics). 764 * Returns frame count on success, -EINVAL on failure. 765 */ 766 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 767 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 768 { 769 int vpos, hpos, stat; 770 u32 count; 771 struct radeon_device *rdev = dev->dev_private; 772 773 if (pipe >= rdev->num_crtc) { 774 DRM_ERROR("Invalid crtc %u\n", pipe); 775 return -EINVAL; 776 } 777 778 /* The hw increments its frame counter at start of vsync, not at start 779 * of vblank, as is required by DRM core vblank counter handling. 780 * Cook the hw count here to make it appear to the caller as if it 781 * incremented at start of vblank. We measure distance to start of 782 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 783 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 784 * result by 1 to give the proper appearance to caller. 785 */ 786 if (rdev->mode_info.crtcs[pipe]) { 787 /* Repeat readout if needed to provide stable result if 788 * we cross start of vsync during the queries. 789 */ 790 do { 791 count = radeon_get_vblank_counter(rdev, pipe); 792 /* Ask radeon_get_crtc_scanoutpos to return vpos as 793 * distance to start of vblank, instead of regular 794 * vertical scanout pos. 795 */ 796 stat = radeon_get_crtc_scanoutpos( 797 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 798 &vpos, &hpos, NULL, NULL, 799 &rdev->mode_info.crtcs[pipe]->base.hwmode); 800 } while (count != radeon_get_vblank_counter(rdev, pipe)); 801 802 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 803 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 804 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 805 } 806 else { 807 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", 808 pipe, vpos); 809 810 /* Bump counter if we are at >= leading edge of vblank, 811 * but before vsync where vpos would turn negative and 812 * the hw counter really increments. 813 */ 814 if (vpos >= 0) 815 count++; 816 } 817 } 818 else { 819 /* Fallback to use value as is. */ 820 count = radeon_get_vblank_counter(rdev, pipe); 821 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 822 } 823 824 return count; 825 } 826 827 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); 828 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); 829 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 830 int *max_error, 831 struct timeval *vblank_time, 832 unsigned flags); 833 834 /** 835 * radeon_enable_vblank_kms - enable vblank interrupt 836 * 837 * @dev: drm dev pointer 838 * @crtc: crtc to enable vblank interrupt for 839 * 840 * Enable the interrupt on the requested crtc (all asics). 841 * Returns 0 on success, -EINVAL on failure. 842 */ 843 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 844 { 845 struct radeon_device *rdev = dev->dev_private; 846 unsigned long irqflags; 847 int r; 848 849 if (crtc < 0 || crtc >= rdev->num_crtc) { 850 DRM_ERROR("Invalid crtc %d\n", crtc); 851 return -EINVAL; 852 } 853 854 spin_lock_irqsave(&rdev->irq.lock, irqflags); 855 rdev->irq.crtc_vblank_int[crtc] = true; 856 r = radeon_irq_set(rdev); 857 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 858 return r; 859 } 860 861 /** 862 * radeon_disable_vblank_kms - disable vblank interrupt 863 * 864 * @dev: drm dev pointer 865 * @crtc: crtc to disable vblank interrupt for 866 * 867 * Disable the interrupt on the requested crtc (all asics). 868 */ 869 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 870 { 871 struct radeon_device *rdev = dev->dev_private; 872 unsigned long irqflags; 873 874 if (crtc < 0 || crtc >= rdev->num_crtc) { 875 DRM_ERROR("Invalid crtc %d\n", crtc); 876 return; 877 } 878 879 spin_lock_irqsave(&rdev->irq.lock, irqflags); 880 rdev->irq.crtc_vblank_int[crtc] = false; 881 radeon_irq_set(rdev); 882 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 883 } 884 885 /** 886 * radeon_get_vblank_timestamp_kms - get vblank timestamp 887 * 888 * @dev: drm dev pointer 889 * @crtc: crtc to get the timestamp for 890 * @max_error: max error 891 * @vblank_time: time value 892 * @flags: flags passed to the driver 893 * 894 * Gets the timestamp on the requested crtc based on the 895 * scanout position. (all asics). 896 * Returns postive status flags on success, negative error on failure. 897 */ 898 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 899 int *max_error, 900 struct timeval *vblank_time, 901 unsigned flags) 902 { 903 struct drm_crtc *drmcrtc; 904 struct radeon_device *rdev = dev->dev_private; 905 906 if (crtc < 0 || crtc >= dev->num_crtcs) { 907 DRM_ERROR("Invalid crtc %d\n", crtc); 908 return -EINVAL; 909 } 910 911 /* Get associated drm_crtc: */ 912 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 913 if (!drmcrtc) 914 return -EINVAL; 915 916 /* Helper routine in DRM core does all the work: */ 917 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 918 vblank_time, flags, 919 &drmcrtc->hwmode); 920 } 921 922 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 923 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 924 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 925 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 926 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 927 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 928 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 929 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 930 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 931 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 932 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 933 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 934 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 935 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 936 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 937 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 938 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 939 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 940 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 941 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 942 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 943 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 944 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 945 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 946 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 947 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 948 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 949 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 950 /* KMS */ 951 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 952 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 953 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 954 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 955 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 956 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 957 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 958 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 959 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 960 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 961 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 962 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 963 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 964 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 965 #if 0 966 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 967 #endif 968 }; 969 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 970