1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include <drm/radeon_drm.h> 31 #include "radeon_asic.h" 32 #include "radeon_kms.h" 33 34 #include <linux/vga_switcheroo.h> 35 #include <linux/slab.h> 36 #include <linux/pm_runtime.h> 37 38 #include "radeon_kfd.h" 39 40 #if defined(CONFIG_VGA_SWITCHEROO) 41 bool radeon_has_atpx(void); 42 #else 43 static inline bool radeon_has_atpx(void) { return false; } 44 #endif 45 46 /** 47 * radeon_driver_unload_kms - Main unload function for KMS. 48 * 49 * @dev: drm dev pointer 50 * 51 * This is the main unload function for KMS (all asics). 52 * It calls radeon_modeset_fini() to tear down the 53 * displays, and radeon_device_fini() to tear down 54 * the rest of the device (CP, writeback, etc.). 55 * Returns 0 on success. 56 */ 57 int radeon_driver_unload_kms(struct drm_device *dev) 58 { 59 struct radeon_device *rdev = dev->dev_private; 60 61 if (rdev == NULL) 62 return 0; 63 64 if (rdev->rmmio == NULL) 65 goto done_free; 66 67 #ifdef PM_TODO 68 if (radeon_is_px(dev)) { 69 pm_runtime_get_sync(dev->dev); 70 pm_runtime_forbid(dev->dev); 71 } 72 #endif 73 74 radeon_kfd_device_fini(rdev); 75 76 radeon_acpi_fini(rdev); 77 radeon_modeset_fini(rdev); 78 radeon_device_fini(rdev); 79 80 done_free: 81 /* XXX pending drm update, after this accessing pdev is illegal! */ 82 drm_fini_pdev(&dev->pdev); 83 kfree(rdev); 84 dev->dev_private = NULL; 85 return 0; 86 } 87 88 /** 89 * radeon_driver_load_kms - Main load function for KMS. 90 * 91 * @dev: drm dev pointer 92 * @flags: device flags 93 * 94 * This is the main load function for KMS (all asics). 95 * It calls radeon_device_init() to set up the non-display 96 * parts of the chip (asic init, CP, writeback, etc.), and 97 * radeon_modeset_init() to set up the display parts 98 * (crtcs, encoders, hotplug detect, etc.). 99 * Returns 0 on success, error on failure. 100 */ 101 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 102 { 103 struct radeon_device *rdev; 104 int r, acpi_status; 105 106 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 107 if (rdev == NULL) { 108 return -ENOMEM; 109 } 110 dev->dev_private = (void *)rdev; 111 112 /* update BUS flag */ 113 if (drm_pci_device_is_agp(dev)) { 114 DRM_INFO("RADEON_IS_AGP\n"); 115 flags |= RADEON_IS_AGP; 116 } else if (pci_is_pcie(dev->dev->bsddev)) { 117 DRM_INFO("RADEON_IS_PCIE\n"); 118 flags |= RADEON_IS_PCIE; 119 } else { 120 DRM_INFO("RADEON_IS_PCI\n"); 121 flags |= RADEON_IS_PCI; 122 } 123 124 #ifdef PM_TODO 125 if ((radeon_runtime_pm != 0) && 126 radeon_has_atpx() && 127 ((flags & RADEON_IS_IGP) == 0)) 128 #endif 129 130 /* radeon_device_init should report only fatal error 131 * like memory allocation failure or iomapping failure, 132 * or memory manager initialization failure, it must 133 * properly initialize the GPU MC controller and permit 134 * VRAM allocation 135 */ 136 r = radeon_device_init(rdev, dev, dev->pdev, flags); 137 if (r) { 138 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 139 goto out; 140 } 141 142 /* Again modeset_init should fail only on fatal error 143 * otherwise it should provide enough functionalities 144 * for shadowfb to run 145 */ 146 r = radeon_modeset_init(rdev); 147 if (r) 148 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 149 150 /* Call ACPI methods: require modeset init 151 * but failure is not fatal 152 */ 153 if (!r) { 154 acpi_status = radeon_acpi_init(rdev); 155 if (acpi_status) 156 dev_dbg(&dev->pdev->dev, 157 "Error during ACPI methods call\n"); 158 } 159 160 radeon_kfd_device_probe(rdev); 161 radeon_kfd_device_init(rdev); 162 163 #ifdef PM_TODO 164 if (radeon_is_px(dev)) { 165 pm_runtime_use_autosuspend(dev->dev); 166 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 167 pm_runtime_set_active(dev->dev); 168 pm_runtime_allow(dev->dev); 169 pm_runtime_mark_last_busy(dev->dev); 170 pm_runtime_put_autosuspend(dev->dev); 171 } 172 #endif 173 174 out: 175 if (r) 176 radeon_driver_unload_kms(dev); 177 178 179 return r; 180 } 181 182 /** 183 * radeon_set_filp_rights - Set filp right. 184 * 185 * @dev: drm dev pointer 186 * @owner: drm file 187 * @applier: drm file 188 * @value: value 189 * 190 * Sets the filp rights for the device (all asics). 191 */ 192 static void radeon_set_filp_rights(struct drm_device *dev, 193 struct drm_file **owner, 194 struct drm_file *applier, 195 uint32_t *value) 196 { 197 struct radeon_device *rdev = dev->dev_private; 198 199 mutex_lock(&rdev->gem.mutex); 200 if (*value == 1) { 201 /* wants rights */ 202 if (!*owner) 203 *owner = applier; 204 } else if (*value == 0) { 205 /* revokes rights */ 206 if (*owner == applier) 207 *owner = NULL; 208 } 209 *value = *owner == applier ? 1 : 0; 210 mutex_unlock(&rdev->gem.mutex); 211 } 212 213 /* 214 * Userspace get information ioctl 215 */ 216 /** 217 * radeon_info_ioctl - answer a device specific request. 218 * 219 * @rdev: radeon device pointer 220 * @data: request object 221 * @filp: drm filp 222 * 223 * This function is used to pass device specific parameters to the userspace 224 * drivers. Examples include: pci device id, pipeline parms, tiling params, 225 * etc. (all asics). 226 * Returns 0 on success, -EINVAL on failure. 227 */ 228 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 229 { 230 struct radeon_device *rdev = dev->dev_private; 231 struct drm_radeon_info *info = data; 232 struct radeon_mode_info *minfo = &rdev->mode_info; 233 uint32_t *value, value_tmp, *value_ptr, value_size; 234 uint64_t value64; 235 struct drm_crtc *crtc; 236 int i, found; 237 238 value_ptr = (uint32_t *)((unsigned long)info->value); 239 value = &value_tmp; 240 value_size = sizeof(uint32_t); 241 242 switch (info->request) { 243 case RADEON_INFO_DEVICE_ID: 244 *value = dev->pdev->device; 245 break; 246 case RADEON_INFO_NUM_GB_PIPES: 247 *value = rdev->num_gb_pipes; 248 break; 249 case RADEON_INFO_NUM_Z_PIPES: 250 *value = rdev->num_z_pipes; 251 break; 252 case RADEON_INFO_ACCEL_WORKING: 253 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 254 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 255 *value = false; 256 else 257 *value = rdev->accel_working; 258 break; 259 case RADEON_INFO_CRTC_FROM_ID: 260 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 261 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 262 return -EFAULT; 263 } 264 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 265 crtc = (struct drm_crtc *)minfo->crtcs[i]; 266 if (crtc && crtc->base.id == *value) { 267 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 268 *value = radeon_crtc->crtc_id; 269 found = 1; 270 break; 271 } 272 } 273 if (!found) { 274 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 275 return -EINVAL; 276 } 277 break; 278 case RADEON_INFO_ACCEL_WORKING2: 279 if (rdev->family == CHIP_HAWAII) { 280 if (rdev->accel_working) { 281 if (rdev->new_fw) 282 *value = 3; 283 else 284 *value = 2; 285 } else { 286 *value = 0; 287 } 288 } else { 289 *value = rdev->accel_working; 290 } 291 break; 292 case RADEON_INFO_TILING_CONFIG: 293 if (rdev->family >= CHIP_BONAIRE) 294 *value = rdev->config.cik.tile_config; 295 else if (rdev->family >= CHIP_TAHITI) 296 *value = rdev->config.si.tile_config; 297 else if (rdev->family >= CHIP_CAYMAN) 298 *value = rdev->config.cayman.tile_config; 299 else if (rdev->family >= CHIP_CEDAR) 300 *value = rdev->config.evergreen.tile_config; 301 else if (rdev->family >= CHIP_RV770) 302 *value = rdev->config.rv770.tile_config; 303 else if (rdev->family >= CHIP_R600) 304 *value = rdev->config.r600.tile_config; 305 else { 306 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 307 return -EINVAL; 308 } 309 break; 310 case RADEON_INFO_WANT_HYPERZ: 311 /* The "value" here is both an input and output parameter. 312 * If the input value is 1, filp requests hyper-z access. 313 * If the input value is 0, filp revokes its hyper-z access. 314 * 315 * When returning, the value is 1 if filp owns hyper-z access, 316 * 0 otherwise. */ 317 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 318 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 319 return -EFAULT; 320 } 321 if (*value >= 2) { 322 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 323 return -EINVAL; 324 } 325 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 326 break; 327 case RADEON_INFO_WANT_CMASK: 328 /* The same logic as Hyper-Z. */ 329 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 330 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 331 return -EFAULT; 332 } 333 if (*value >= 2) { 334 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 335 return -EINVAL; 336 } 337 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 338 break; 339 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 340 /* return clock value in KHz */ 341 if (rdev->asic->get_xclk) 342 *value = radeon_get_xclk(rdev) * 10; 343 else 344 *value = rdev->clock.spll.reference_freq * 10; 345 break; 346 case RADEON_INFO_NUM_BACKENDS: 347 if (rdev->family >= CHIP_BONAIRE) 348 *value = rdev->config.cik.max_backends_per_se * 349 rdev->config.cik.max_shader_engines; 350 else if (rdev->family >= CHIP_TAHITI) 351 *value = rdev->config.si.max_backends_per_se * 352 rdev->config.si.max_shader_engines; 353 else if (rdev->family >= CHIP_CAYMAN) 354 *value = rdev->config.cayman.max_backends_per_se * 355 rdev->config.cayman.max_shader_engines; 356 else if (rdev->family >= CHIP_CEDAR) 357 *value = rdev->config.evergreen.max_backends; 358 else if (rdev->family >= CHIP_RV770) 359 *value = rdev->config.rv770.max_backends; 360 else if (rdev->family >= CHIP_R600) 361 *value = rdev->config.r600.max_backends; 362 else { 363 return -EINVAL; 364 } 365 break; 366 case RADEON_INFO_NUM_TILE_PIPES: 367 if (rdev->family >= CHIP_BONAIRE) 368 *value = rdev->config.cik.max_tile_pipes; 369 else if (rdev->family >= CHIP_TAHITI) 370 *value = rdev->config.si.max_tile_pipes; 371 else if (rdev->family >= CHIP_CAYMAN) 372 *value = rdev->config.cayman.max_tile_pipes; 373 else if (rdev->family >= CHIP_CEDAR) 374 *value = rdev->config.evergreen.max_tile_pipes; 375 else if (rdev->family >= CHIP_RV770) 376 *value = rdev->config.rv770.max_tile_pipes; 377 else if (rdev->family >= CHIP_R600) 378 *value = rdev->config.r600.max_tile_pipes; 379 else { 380 return -EINVAL; 381 } 382 break; 383 case RADEON_INFO_FUSION_GART_WORKING: 384 *value = 1; 385 break; 386 case RADEON_INFO_BACKEND_MAP: 387 if (rdev->family >= CHIP_BONAIRE) 388 *value = rdev->config.cik.backend_map; 389 else if (rdev->family >= CHIP_TAHITI) 390 *value = rdev->config.si.backend_map; 391 else if (rdev->family >= CHIP_CAYMAN) 392 *value = rdev->config.cayman.backend_map; 393 else if (rdev->family >= CHIP_CEDAR) 394 *value = rdev->config.evergreen.backend_map; 395 else if (rdev->family >= CHIP_RV770) 396 *value = rdev->config.rv770.backend_map; 397 else if (rdev->family >= CHIP_R600) 398 *value = rdev->config.r600.backend_map; 399 else { 400 return -EINVAL; 401 } 402 break; 403 case RADEON_INFO_VA_START: 404 /* this is where we report if vm is supported or not */ 405 if (rdev->family < CHIP_CAYMAN) 406 return -EINVAL; 407 *value = RADEON_VA_RESERVED_SIZE; 408 break; 409 case RADEON_INFO_IB_VM_MAX_SIZE: 410 /* this is where we report if vm is supported or not */ 411 if (rdev->family < CHIP_CAYMAN) 412 return -EINVAL; 413 *value = RADEON_IB_VM_MAX_SIZE; 414 break; 415 case RADEON_INFO_MAX_PIPES: 416 if (rdev->family >= CHIP_BONAIRE) 417 *value = rdev->config.cik.max_cu_per_sh; 418 else if (rdev->family >= CHIP_TAHITI) 419 *value = rdev->config.si.max_cu_per_sh; 420 else if (rdev->family >= CHIP_CAYMAN) 421 *value = rdev->config.cayman.max_pipes_per_simd; 422 else if (rdev->family >= CHIP_CEDAR) 423 *value = rdev->config.evergreen.max_pipes; 424 else if (rdev->family >= CHIP_RV770) 425 *value = rdev->config.rv770.max_pipes; 426 else if (rdev->family >= CHIP_R600) 427 *value = rdev->config.r600.max_pipes; 428 else { 429 return -EINVAL; 430 } 431 break; 432 case RADEON_INFO_TIMESTAMP: 433 if (rdev->family < CHIP_R600) { 434 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 435 return -EINVAL; 436 } 437 value = (uint32_t*)&value64; 438 value_size = sizeof(uint64_t); 439 value64 = radeon_get_gpu_clock_counter(rdev); 440 break; 441 case RADEON_INFO_MAX_SE: 442 if (rdev->family >= CHIP_BONAIRE) 443 *value = rdev->config.cik.max_shader_engines; 444 else if (rdev->family >= CHIP_TAHITI) 445 *value = rdev->config.si.max_shader_engines; 446 else if (rdev->family >= CHIP_CAYMAN) 447 *value = rdev->config.cayman.max_shader_engines; 448 else if (rdev->family >= CHIP_CEDAR) 449 *value = rdev->config.evergreen.num_ses; 450 else 451 *value = 1; 452 break; 453 case RADEON_INFO_MAX_SH_PER_SE: 454 if (rdev->family >= CHIP_BONAIRE) 455 *value = rdev->config.cik.max_sh_per_se; 456 else if (rdev->family >= CHIP_TAHITI) 457 *value = rdev->config.si.max_sh_per_se; 458 else 459 return -EINVAL; 460 break; 461 case RADEON_INFO_FASTFB_WORKING: 462 *value = rdev->fastfb_working; 463 break; 464 case RADEON_INFO_RING_WORKING: 465 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 466 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 467 return -EFAULT; 468 } 469 switch (*value) { 470 case RADEON_CS_RING_GFX: 471 case RADEON_CS_RING_COMPUTE: 472 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 473 break; 474 case RADEON_CS_RING_DMA: 475 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 476 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 477 break; 478 case RADEON_CS_RING_UVD: 479 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 480 break; 481 case RADEON_CS_RING_VCE: 482 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 483 break; 484 default: 485 return -EINVAL; 486 } 487 break; 488 case RADEON_INFO_SI_TILE_MODE_ARRAY: 489 if (rdev->family >= CHIP_BONAIRE) { 490 value = rdev->config.cik.tile_mode_array; 491 value_size = sizeof(uint32_t)*32; 492 } else if (rdev->family >= CHIP_TAHITI) { 493 value = rdev->config.si.tile_mode_array; 494 value_size = sizeof(uint32_t)*32; 495 } else { 496 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 497 return -EINVAL; 498 } 499 break; 500 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 501 if (rdev->family >= CHIP_BONAIRE) { 502 value = rdev->config.cik.macrotile_mode_array; 503 value_size = sizeof(uint32_t)*16; 504 } else { 505 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 506 return -EINVAL; 507 } 508 break; 509 case RADEON_INFO_SI_CP_DMA_COMPUTE: 510 *value = 1; 511 break; 512 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 513 if (rdev->family >= CHIP_BONAIRE) { 514 *value = rdev->config.cik.backend_enable_mask; 515 } else if (rdev->family >= CHIP_TAHITI) { 516 *value = rdev->config.si.backend_enable_mask; 517 } else { 518 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 519 } 520 break; 521 case RADEON_INFO_MAX_SCLK: 522 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 523 rdev->pm.dpm_enabled) 524 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 525 else 526 *value = rdev->pm.default_sclk * 10; 527 break; 528 case RADEON_INFO_VCE_FW_VERSION: 529 *value = rdev->vce.fw_version; 530 break; 531 case RADEON_INFO_VCE_FB_VERSION: 532 *value = rdev->vce.fb_version; 533 break; 534 case RADEON_INFO_NUM_BYTES_MOVED: 535 value = (uint32_t*)&value64; 536 value_size = sizeof(uint64_t); 537 value64 = atomic64_read(&rdev->num_bytes_moved); 538 break; 539 case RADEON_INFO_VRAM_USAGE: 540 value = (uint32_t*)&value64; 541 value_size = sizeof(uint64_t); 542 value64 = atomic64_read(&rdev->vram_usage); 543 break; 544 case RADEON_INFO_GTT_USAGE: 545 value = (uint32_t*)&value64; 546 value_size = sizeof(uint64_t); 547 value64 = atomic64_read(&rdev->gtt_usage); 548 break; 549 case RADEON_INFO_ACTIVE_CU_COUNT: 550 if (rdev->family >= CHIP_BONAIRE) 551 *value = rdev->config.cik.active_cus; 552 else if (rdev->family >= CHIP_TAHITI) 553 *value = rdev->config.si.active_cus; 554 else if (rdev->family >= CHIP_CAYMAN) 555 *value = rdev->config.cayman.active_simds; 556 else if (rdev->family >= CHIP_CEDAR) 557 *value = rdev->config.evergreen.active_simds; 558 else if (rdev->family >= CHIP_RV770) 559 *value = rdev->config.rv770.active_simds; 560 else if (rdev->family >= CHIP_R600) 561 *value = rdev->config.r600.active_simds; 562 else 563 *value = 1; 564 break; 565 case RADEON_INFO_CURRENT_GPU_TEMP: 566 /* get temperature in millidegrees C */ 567 if (rdev->asic->pm.get_temperature) 568 *value = radeon_get_temperature(rdev); 569 else 570 *value = 0; 571 break; 572 case RADEON_INFO_CURRENT_GPU_SCLK: 573 /* get sclk in Mhz */ 574 if (rdev->pm.dpm_enabled) 575 *value = radeon_dpm_get_current_sclk(rdev) / 100; 576 else 577 *value = rdev->pm.current_sclk / 100; 578 break; 579 case RADEON_INFO_CURRENT_GPU_MCLK: 580 /* get mclk in Mhz */ 581 if (rdev->pm.dpm_enabled) 582 *value = radeon_dpm_get_current_mclk(rdev) / 100; 583 else 584 *value = rdev->pm.current_mclk / 100; 585 break; 586 case RADEON_INFO_READ_REG: 587 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 588 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 589 return -EFAULT; 590 } 591 if (radeon_get_allowed_info_register(rdev, *value, value)) 592 return -EINVAL; 593 break; 594 case RADEON_INFO_GPU_RESET_COUNTER: 595 *value = atomic_read(&rdev->gpu_reset_counter); 596 break; 597 default: 598 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 599 return -EINVAL; 600 } 601 if (copy_to_user(value_ptr, (char*)value, value_size)) { 602 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 603 return -EFAULT; 604 } 605 return 0; 606 } 607 608 609 /* 610 * Outdated mess for old drm with Xorg being in charge (void function now). 611 */ 612 /** 613 * radeon_driver_lastclose_kms - drm callback for last close 614 * 615 * @dev: drm dev pointer 616 * 617 * Switch vga_switcheroo state after last close (all asics). 618 */ 619 void radeon_driver_lastclose_kms(struct drm_device *dev) 620 { 621 struct radeon_device *rdev = dev->dev_private; 622 623 radeon_fbdev_restore_mode(rdev); 624 vga_switcheroo_process_delayed_switch(); 625 } 626 627 /** 628 * radeon_driver_open_kms - drm callback for open 629 * 630 * @dev: drm dev pointer 631 * @file_priv: drm file 632 * 633 * On device open, init vm on cayman+ (all asics). 634 * Returns 0 on success, error on failure. 635 */ 636 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 637 { 638 struct radeon_device *rdev = dev->dev_private; 639 int r; 640 641 file_priv->driver_priv = NULL; 642 643 r = pm_runtime_get_sync(dev->dev); 644 if (r < 0) 645 return r; 646 647 /* new gpu have virtual address space support */ 648 if (rdev->family >= CHIP_CAYMAN) { 649 struct radeon_fpriv *fpriv; 650 struct radeon_vm *vm; 651 652 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 653 if (unlikely(!fpriv)) { 654 r = -ENOMEM; 655 goto out_suspend; 656 } 657 658 if (rdev->accel_working) { 659 vm = &fpriv->vm; 660 r = radeon_vm_init(rdev, vm); 661 if (r) { 662 kfree(fpriv); 663 goto out_suspend; 664 } 665 666 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 667 if (r) { 668 radeon_vm_fini(rdev, vm); 669 kfree(fpriv); 670 goto out_suspend; 671 } 672 673 /* map the ib pool buffer read only into 674 * virtual address space */ 675 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 676 rdev->ring_tmp_bo.bo); 677 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 678 RADEON_VA_IB_OFFSET, 679 RADEON_VM_PAGE_READABLE | 680 RADEON_VM_PAGE_SNOOPED); 681 if (r) { 682 radeon_vm_fini(rdev, vm); 683 kfree(fpriv); 684 goto out_suspend; 685 } 686 } 687 file_priv->driver_priv = fpriv; 688 } 689 690 out_suspend: 691 pm_runtime_mark_last_busy(dev->dev); 692 pm_runtime_put_autosuspend(dev->dev); 693 return r; 694 } 695 696 /** 697 * radeon_driver_postclose_kms - drm callback for post close 698 * 699 * @dev: drm dev pointer 700 * @file_priv: drm file 701 * 702 * On device post close, tear down vm on cayman+ (all asics). 703 */ 704 void radeon_driver_postclose_kms(struct drm_device *dev, 705 struct drm_file *file_priv) 706 { 707 struct radeon_device *rdev = dev->dev_private; 708 709 /* new gpu have virtual address space support */ 710 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 711 struct radeon_fpriv *fpriv = file_priv->driver_priv; 712 struct radeon_vm *vm = &fpriv->vm; 713 int r; 714 715 if (rdev->accel_working) { 716 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 717 if (!r) { 718 if (vm->ib_bo_va) 719 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 720 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 721 } 722 radeon_vm_fini(rdev, vm); 723 } 724 725 kfree(fpriv); 726 file_priv->driver_priv = NULL; 727 } 728 pm_runtime_mark_last_busy(dev->dev); 729 pm_runtime_put_autosuspend(dev->dev); 730 } 731 732 /** 733 * radeon_driver_preclose_kms - drm callback for pre close 734 * 735 * @dev: drm dev pointer 736 * @file_priv: drm file 737 * 738 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 739 * (all asics). 740 */ 741 void radeon_driver_preclose_kms(struct drm_device *dev, 742 struct drm_file *file_priv) 743 { 744 struct radeon_device *rdev = dev->dev_private; 745 746 pm_runtime_get_sync(dev->dev); 747 748 mutex_lock(&rdev->gem.mutex); 749 if (rdev->hyperz_filp == file_priv) 750 rdev->hyperz_filp = NULL; 751 if (rdev->cmask_filp == file_priv) 752 rdev->cmask_filp = NULL; 753 mutex_unlock(&rdev->gem.mutex); 754 755 radeon_uvd_free_handles(rdev, file_priv); 756 radeon_vce_free_handles(rdev, file_priv); 757 } 758 759 /* 760 * VBlank related functions. 761 */ 762 /** 763 * radeon_get_vblank_counter_kms - get frame count 764 * 765 * @dev: drm dev pointer 766 * @pipe: crtc to get the frame count from 767 * 768 * Gets the frame count on the requested crtc (all asics). 769 * Returns frame count on success, -EINVAL on failure. 770 */ 771 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 772 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 773 { 774 int vpos, hpos, stat; 775 u32 count; 776 struct radeon_device *rdev = dev->dev_private; 777 778 if (pipe >= rdev->num_crtc) { 779 DRM_ERROR("Invalid crtc %u\n", pipe); 780 return -EINVAL; 781 } 782 783 /* The hw increments its frame counter at start of vsync, not at start 784 * of vblank, as is required by DRM core vblank counter handling. 785 * Cook the hw count here to make it appear to the caller as if it 786 * incremented at start of vblank. We measure distance to start of 787 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 788 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 789 * result by 1 to give the proper appearance to caller. 790 */ 791 if (rdev->mode_info.crtcs[pipe]) { 792 /* Repeat readout if needed to provide stable result if 793 * we cross start of vsync during the queries. 794 */ 795 do { 796 count = radeon_get_vblank_counter(rdev, pipe); 797 /* Ask radeon_get_crtc_scanoutpos to return vpos as 798 * distance to start of vblank, instead of regular 799 * vertical scanout pos. 800 */ 801 stat = radeon_get_crtc_scanoutpos( 802 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 803 &vpos, &hpos, NULL, NULL, 804 &rdev->mode_info.crtcs[pipe]->base.hwmode); 805 } while (count != radeon_get_vblank_counter(rdev, pipe)); 806 807 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 808 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 809 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 810 } 811 else { 812 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", 813 pipe, vpos); 814 815 /* Bump counter if we are at >= leading edge of vblank, 816 * but before vsync where vpos would turn negative and 817 * the hw counter really increments. 818 */ 819 if (vpos >= 0) 820 count++; 821 } 822 } 823 else { 824 /* Fallback to use value as is. */ 825 count = radeon_get_vblank_counter(rdev, pipe); 826 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 827 } 828 829 return count; 830 } 831 832 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); 833 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); 834 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 835 int *max_error, 836 struct timeval *vblank_time, 837 unsigned flags); 838 839 /** 840 * radeon_enable_vblank_kms - enable vblank interrupt 841 * 842 * @dev: drm dev pointer 843 * @crtc: crtc to enable vblank interrupt for 844 * 845 * Enable the interrupt on the requested crtc (all asics). 846 * Returns 0 on success, -EINVAL on failure. 847 */ 848 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 849 { 850 struct radeon_device *rdev = dev->dev_private; 851 unsigned long irqflags; 852 int r; 853 854 if (crtc < 0 || crtc >= rdev->num_crtc) { 855 DRM_ERROR("Invalid crtc %d\n", crtc); 856 return -EINVAL; 857 } 858 859 spin_lock_irqsave(&rdev->irq.lock, irqflags); 860 rdev->irq.crtc_vblank_int[crtc] = true; 861 r = radeon_irq_set(rdev); 862 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 863 return r; 864 } 865 866 /** 867 * radeon_disable_vblank_kms - disable vblank interrupt 868 * 869 * @dev: drm dev pointer 870 * @crtc: crtc to disable vblank interrupt for 871 * 872 * Disable the interrupt on the requested crtc (all asics). 873 */ 874 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 875 { 876 struct radeon_device *rdev = dev->dev_private; 877 unsigned long irqflags; 878 879 if (crtc < 0 || crtc >= rdev->num_crtc) { 880 DRM_ERROR("Invalid crtc %d\n", crtc); 881 return; 882 } 883 884 spin_lock_irqsave(&rdev->irq.lock, irqflags); 885 rdev->irq.crtc_vblank_int[crtc] = false; 886 radeon_irq_set(rdev); 887 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 888 } 889 890 /** 891 * radeon_get_vblank_timestamp_kms - get vblank timestamp 892 * 893 * @dev: drm dev pointer 894 * @crtc: crtc to get the timestamp for 895 * @max_error: max error 896 * @vblank_time: time value 897 * @flags: flags passed to the driver 898 * 899 * Gets the timestamp on the requested crtc based on the 900 * scanout position. (all asics). 901 * Returns postive status flags on success, negative error on failure. 902 */ 903 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 904 int *max_error, 905 struct timeval *vblank_time, 906 unsigned flags) 907 { 908 struct drm_crtc *drmcrtc; 909 struct radeon_device *rdev = dev->dev_private; 910 911 if (crtc < 0 || crtc >= dev->num_crtcs) { 912 DRM_ERROR("Invalid crtc %d\n", crtc); 913 return -EINVAL; 914 } 915 916 /* Get associated drm_crtc: */ 917 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 918 if (!drmcrtc) 919 return -EINVAL; 920 921 /* Helper routine in DRM core does all the work: */ 922 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 923 vblank_time, flags, 924 &drmcrtc->hwmode); 925 } 926 927 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 928 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 929 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 930 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 931 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 932 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 933 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 934 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 935 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 936 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 937 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 938 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 939 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 940 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 941 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 942 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 943 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 944 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 945 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 946 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 947 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 948 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 949 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 950 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 951 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 952 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 953 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 954 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 955 /* KMS */ 956 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 957 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 958 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 959 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 960 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 961 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 962 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 963 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 964 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 965 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 966 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 967 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 968 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 969 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 970 #if 0 971 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 972 #endif 973 }; 974 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 975