1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_legacy_encoders.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 36 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) 37 { 38 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 39 struct drm_encoder_helper_funcs *encoder_funcs; 40 41 encoder_funcs = encoder->helper_private; 42 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 43 radeon_encoder->active_device = 0; 44 } 45 46 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) 47 { 48 struct drm_device *dev = encoder->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 51 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 52 int panel_pwr_delay = 2000; 53 bool is_mac = false; 54 uint8_t backlight_level; 55 DRM_DEBUG_KMS("\n"); 56 57 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 58 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 59 60 if (radeon_encoder->enc_priv) { 61 if (rdev->is_atom_bios) { 62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 63 panel_pwr_delay = lvds->panel_pwr_delay; 64 if (lvds->bl_dev) 65 backlight_level = lvds->backlight_level; 66 } else { 67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 68 panel_pwr_delay = lvds->panel_pwr_delay; 69 if (lvds->bl_dev) 70 backlight_level = lvds->backlight_level; 71 } 72 } 73 74 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely 75 * Taken from radeonfb. 76 */ 77 if ((rdev->mode_info.connector_table == CT_IBOOK) || 78 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || 79 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || 80 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) 81 is_mac = true; 82 83 switch (mode) { 84 case DRM_MODE_DPMS_ON: 85 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); 86 disp_pwr_man |= RADEON_AUTO_PWRUP_EN; 87 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); 88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 91 DRM_MDELAY(1); 92 93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 96 97 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | 98 RADEON_LVDS_BL_MOD_LEVEL_MASK); 99 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | 100 RADEON_LVDS_DIGON | RADEON_LVDS_BLON | 101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); 102 if (is_mac) 103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 104 DRM_MDELAY(panel_pwr_delay); 105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 106 break; 107 case DRM_MODE_DPMS_STANDBY: 108 case DRM_MODE_DPMS_SUSPEND: 109 case DRM_MODE_DPMS_OFF: 110 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 111 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 112 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 113 if (is_mac) { 114 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; 115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 116 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 117 } else { 118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 120 } 121 DRM_MDELAY(panel_pwr_delay); 122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 124 DRM_MDELAY(panel_pwr_delay); 125 break; 126 } 127 128 if (rdev->is_atom_bios) 129 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 130 else 131 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 132 133 } 134 135 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) 136 { 137 struct radeon_device *rdev = encoder->dev->dev_private; 138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 139 DRM_DEBUG("\n"); 140 141 if (radeon_encoder->enc_priv) { 142 if (rdev->is_atom_bios) { 143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 144 lvds->dpms_mode = mode; 145 } else { 146 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 147 lvds->dpms_mode = mode; 148 } 149 } 150 151 radeon_legacy_lvds_update(encoder, mode); 152 } 153 154 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) 155 { 156 struct radeon_device *rdev = encoder->dev->dev_private; 157 158 if (rdev->is_atom_bios) 159 radeon_atom_output_lock(encoder, true); 160 else 161 radeon_combios_output_lock(encoder, true); 162 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); 163 } 164 165 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) 166 { 167 struct radeon_device *rdev = encoder->dev->dev_private; 168 169 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); 170 if (rdev->is_atom_bios) 171 radeon_atom_output_lock(encoder, false); 172 else 173 radeon_combios_output_lock(encoder, false); 174 } 175 176 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, 177 struct drm_display_mode *mode, 178 struct drm_display_mode *adjusted_mode) 179 { 180 struct drm_device *dev = encoder->dev; 181 struct radeon_device *rdev = dev->dev_private; 182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 184 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; 185 186 DRM_DEBUG_KMS("\n"); 187 188 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 189 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; 190 191 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 192 if (rdev->is_atom_bios) { 193 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl 194 * need to call that on resume to set up the reg properly. 195 */ 196 radeon_encoder->pixel_clock = adjusted_mode->clock; 197 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 198 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 199 } else { 200 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 201 if (lvds) { 202 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); 203 lvds_gen_cntl = lvds->lvds_gen_cntl; 204 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 205 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 206 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 207 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 208 } else 209 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 210 } 211 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 212 lvds_gen_cntl &= ~(RADEON_LVDS_ON | 213 RADEON_LVDS_BLON | 214 RADEON_LVDS_EN | 215 RADEON_LVDS_RST_FM); 216 217 if (ASIC_IS_R300(rdev)) 218 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); 219 220 if (radeon_crtc->crtc_id == 0) { 221 if (ASIC_IS_R300(rdev)) { 222 if (radeon_encoder->rmx_type != RMX_OFF) 223 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; 224 } else 225 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; 226 } else { 227 if (ASIC_IS_R300(rdev)) 228 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; 229 else 230 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; 231 } 232 233 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 234 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 235 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); 236 237 if (rdev->family == CHIP_RV410) 238 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); 239 240 if (rdev->is_atom_bios) 241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 242 else 243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 244 } 245 246 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, 247 const struct drm_display_mode *mode, 248 struct drm_display_mode *adjusted_mode) 249 { 250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 251 252 /* set the active encoder to connector routing */ 253 radeon_encoder_set_active_device(encoder); 254 drm_mode_set_crtcinfo(adjusted_mode, 0); 255 256 /* get the native mode for LVDS */ 257 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 258 radeon_panel_mode_fixup(encoder, adjusted_mode); 259 260 return true; 261 } 262 263 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { 264 .dpms = radeon_legacy_lvds_dpms, 265 .mode_fixup = radeon_legacy_mode_fixup, 266 .prepare = radeon_legacy_lvds_prepare, 267 .mode_set = radeon_legacy_lvds_mode_set, 268 .commit = radeon_legacy_lvds_commit, 269 .disable = radeon_legacy_encoder_disable, 270 }; 271 272 u8 273 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder) 274 { 275 struct drm_device *dev = radeon_encoder->base.dev; 276 struct radeon_device *rdev = dev->dev_private; 277 u8 backlight_level; 278 279 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 280 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 281 282 return backlight_level; 283 } 284 285 void 286 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 287 { 288 struct drm_device *dev = radeon_encoder->base.dev; 289 struct radeon_device *rdev = dev->dev_private; 290 int dpms_mode = DRM_MODE_DPMS_ON; 291 292 if (radeon_encoder->enc_priv) { 293 if (rdev->is_atom_bios) { 294 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 295 if (lvds->backlight_level > 0) 296 dpms_mode = lvds->dpms_mode; 297 else 298 dpms_mode = DRM_MODE_DPMS_OFF; 299 lvds->backlight_level = level; 300 } else { 301 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 302 if (lvds->backlight_level > 0) 303 dpms_mode = lvds->dpms_mode; 304 else 305 dpms_mode = DRM_MODE_DPMS_OFF; 306 lvds->backlight_level = level; 307 } 308 } 309 310 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); 311 } 312 313 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 314 315 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) 316 { 317 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 318 uint8_t level; 319 320 /* Convert brightness to hardware level */ 321 if (bd->props.brightness < 0) 322 level = 0; 323 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 324 level = RADEON_MAX_BL_LEVEL; 325 else 326 level = bd->props.brightness; 327 328 if (pdata->negative) 329 level = RADEON_MAX_BL_LEVEL - level; 330 331 return level; 332 } 333 334 static int radeon_legacy_backlight_update_status(struct backlight_device *bd) 335 { 336 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 337 struct radeon_encoder *radeon_encoder = pdata->encoder; 338 339 radeon_legacy_set_backlight_level(radeon_encoder, 340 radeon_legacy_lvds_level(bd)); 341 342 return 0; 343 } 344 345 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd) 346 { 347 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 348 struct radeon_encoder *radeon_encoder = pdata->encoder; 349 struct drm_device *dev = radeon_encoder->base.dev; 350 struct radeon_device *rdev = dev->dev_private; 351 uint8_t backlight_level; 352 353 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 354 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 355 356 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level; 357 } 358 359 static const struct backlight_ops radeon_backlight_ops = { 360 .get_brightness = radeon_legacy_backlight_get_brightness, 361 .update_status = radeon_legacy_backlight_update_status, 362 }; 363 364 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 365 struct drm_connector *drm_connector) 366 { 367 struct drm_device *dev = radeon_encoder->base.dev; 368 struct radeon_device *rdev = dev->dev_private; 369 struct backlight_device *bd; 370 struct backlight_properties props; 371 struct radeon_backlight_privdata *pdata; 372 uint8_t backlight_level; 373 char bl_name[16]; 374 375 if (!radeon_encoder->enc_priv) 376 return; 377 378 #ifdef CONFIG_PMAC_BACKLIGHT 379 if (!pmac_has_backlight_type("ati") && 380 !pmac_has_backlight_type("mnca")) 381 return; 382 #endif 383 384 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), 385 DRM_MEM_DRIVER, M_WAITOK); 386 if (!pdata) { 387 DRM_ERROR("Memory allocation failed\n"); 388 goto error; 389 } 390 391 memset(&props, 0, sizeof(props)); 392 props.max_brightness = RADEON_MAX_BL_LEVEL; 393 props.type = BACKLIGHT_RAW; 394 ksnprintf(bl_name, sizeof(bl_name), "radeon_bl%d", 395 dev->primary->index); 396 bd = backlight_device_register(bl_name, &drm_connector->kdev, 397 pdata, &radeon_backlight_ops, &props); 398 if (IS_ERR(bd)) { 399 DRM_ERROR("Backlight registration failed\n"); 400 goto error; 401 } 402 403 pdata->encoder = radeon_encoder; 404 405 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 406 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 407 408 /* First, try to detect backlight level sense based on the assumption 409 * that firmware set it up at full brightness 410 */ 411 if (backlight_level == 0) 412 pdata->negative = true; 413 else if (backlight_level == 0xff) 414 pdata->negative = false; 415 else { 416 /* XXX hack... maybe some day we can figure out in what direction 417 * backlight should work on a given panel? 418 */ 419 pdata->negative = (rdev->family != CHIP_RV200 && 420 rdev->family != CHIP_RV250 && 421 rdev->family != CHIP_RV280 && 422 rdev->family != CHIP_RV350); 423 424 #ifdef CONFIG_PMAC_BACKLIGHT 425 pdata->negative = (pdata->negative || 426 of_machine_is_compatible("PowerBook4,3") || 427 of_machine_is_compatible("PowerBook6,3") || 428 of_machine_is_compatible("PowerBook6,5")); 429 #endif 430 } 431 432 if (rdev->is_atom_bios) { 433 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 434 lvds->bl_dev = bd; 435 } else { 436 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 437 lvds->bl_dev = bd; 438 } 439 440 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd); 441 bd->props.power = FB_BLANK_UNBLANK; 442 backlight_update_status(bd); 443 444 DRM_INFO("radeon legacy LVDS backlight initialized\n"); 445 446 return; 447 448 error: 449 drm_free(pdata, DRM_MEM_DRIVER); 450 return; 451 } 452 453 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) 454 { 455 struct drm_device *dev = radeon_encoder->base.dev; 456 struct radeon_device *rdev = dev->dev_private; 457 struct backlight_device *bd = NULL; 458 459 if (!radeon_encoder->enc_priv) 460 return; 461 462 if (rdev->is_atom_bios) { 463 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 464 bd = lvds->bl_dev; 465 lvds->bl_dev = NULL; 466 } else { 467 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 468 bd = lvds->bl_dev; 469 lvds->bl_dev = NULL; 470 } 471 472 if (bd) { 473 struct radeon_backlight_privdata *pdata; 474 475 pdata = bl_get_data(bd); 476 backlight_device_unregister(bd); 477 drm_free(pdata, DRM_MEM_DRIVER); 478 479 DRM_INFO("radeon legacy LVDS backlight unloaded\n"); 480 } 481 } 482 483 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 484 485 void radeon_legacy_backlight_init(struct radeon_encoder *encoder, 486 struct drm_connector *drm_connector) 487 { 488 } 489 490 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) 491 { 492 } 493 494 #endif 495 496 497 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) 498 { 499 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 500 501 if (radeon_encoder->enc_priv) { 502 radeon_legacy_backlight_exit(radeon_encoder); 503 drm_free(radeon_encoder->enc_priv, DRM_MEM_DRIVER); 504 } 505 drm_encoder_cleanup(encoder); 506 drm_free(radeon_encoder, DRM_MEM_DRIVER); 507 } 508 509 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { 510 .destroy = radeon_lvds_enc_destroy, 511 }; 512 513 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) 514 { 515 struct drm_device *dev = encoder->dev; 516 struct radeon_device *rdev = dev->dev_private; 517 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 518 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); 519 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 520 521 DRM_DEBUG_KMS("\n"); 522 523 switch (mode) { 524 case DRM_MODE_DPMS_ON: 525 crtc_ext_cntl |= RADEON_CRTC_CRT_ON; 526 dac_cntl &= ~RADEON_DAC_PDWN; 527 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | 528 RADEON_DAC_PDWN_G | 529 RADEON_DAC_PDWN_B); 530 break; 531 case DRM_MODE_DPMS_STANDBY: 532 case DRM_MODE_DPMS_SUSPEND: 533 case DRM_MODE_DPMS_OFF: 534 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; 535 dac_cntl |= RADEON_DAC_PDWN; 536 dac_macro_cntl |= (RADEON_DAC_PDWN_R | 537 RADEON_DAC_PDWN_G | 538 RADEON_DAC_PDWN_B); 539 break; 540 } 541 542 /* handled in radeon_crtc_dpms() */ 543 if (!(rdev->flags & RADEON_SINGLE_CRTC)) 544 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 545 WREG32(RADEON_DAC_CNTL, dac_cntl); 546 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 547 548 if (rdev->is_atom_bios) 549 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 550 else 551 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 552 553 } 554 555 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) 556 { 557 struct radeon_device *rdev = encoder->dev->dev_private; 558 559 if (rdev->is_atom_bios) 560 radeon_atom_output_lock(encoder, true); 561 else 562 radeon_combios_output_lock(encoder, true); 563 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 564 } 565 566 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) 567 { 568 struct radeon_device *rdev = encoder->dev->dev_private; 569 570 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); 571 572 if (rdev->is_atom_bios) 573 radeon_atom_output_lock(encoder, false); 574 else 575 radeon_combios_output_lock(encoder, false); 576 } 577 578 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, 579 struct drm_display_mode *mode, 580 struct drm_display_mode *adjusted_mode) 581 { 582 struct drm_device *dev = encoder->dev; 583 struct radeon_device *rdev = dev->dev_private; 584 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 585 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 586 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; 587 588 DRM_DEBUG_KMS("\n"); 589 590 if (radeon_crtc->crtc_id == 0) { 591 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 592 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 593 ~(RADEON_DISP_DAC_SOURCE_MASK); 594 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 595 } else { 596 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); 597 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 598 } 599 } else { 600 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 601 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 602 ~(RADEON_DISP_DAC_SOURCE_MASK); 603 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; 604 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 605 } else { 606 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; 607 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 608 } 609 } 610 611 dac_cntl = (RADEON_DAC_MASK_ALL | 612 RADEON_DAC_VGA_ADR_EN | 613 /* TODO 6-bits */ 614 RADEON_DAC_8BIT_EN); 615 616 WREG32_P(RADEON_DAC_CNTL, 617 dac_cntl, 618 RADEON_DAC_RANGE_CNTL | 619 RADEON_DAC_BLANKING); 620 621 if (radeon_encoder->enc_priv) { 622 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; 623 dac_macro_cntl = p_dac->ps2_pdac_adj; 624 } else 625 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 626 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; 627 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 628 629 if (rdev->is_atom_bios) 630 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 631 else 632 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 633 } 634 635 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, 636 struct drm_connector *connector) 637 { 638 struct drm_device *dev = encoder->dev; 639 struct radeon_device *rdev = dev->dev_private; 640 uint32_t vclk_ecp_cntl, crtc_ext_cntl; 641 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; 642 enum drm_connector_status found = connector_status_disconnected; 643 bool color = true; 644 645 /* just don't bother on RN50 those chip are often connected to remoting 646 * console hw and often we get failure to load detect those. So to make 647 * everyone happy report the encoder as always connected. 648 */ 649 if (ASIC_IS_RN50(rdev)) { 650 return connector_status_connected; 651 } 652 653 /* save the regs we need */ 654 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 655 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 656 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 657 dac_cntl = RREG32(RADEON_DAC_CNTL); 658 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 659 660 tmp = vclk_ecp_cntl & 661 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); 662 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 663 664 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 665 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 666 667 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | 668 RADEON_DAC_FORCE_DATA_EN; 669 670 if (color) 671 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 672 else 673 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 674 675 if (ASIC_IS_R300(rdev)) 676 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 677 else if (ASIC_IS_RV100(rdev)) 678 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT); 679 else 680 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 681 682 WREG32(RADEON_DAC_EXT_CNTL, tmp); 683 684 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); 685 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; 686 WREG32(RADEON_DAC_CNTL, tmp); 687 688 tmp = dac_macro_cntl; 689 tmp &= ~(RADEON_DAC_PDWN_R | 690 RADEON_DAC_PDWN_G | 691 RADEON_DAC_PDWN_B); 692 693 WREG32(RADEON_DAC_MACRO_CNTL, tmp); 694 695 DRM_MDELAY(2); 696 697 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) 698 found = connector_status_connected; 699 700 /* restore the regs we used */ 701 WREG32(RADEON_DAC_CNTL, dac_cntl); 702 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 703 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 704 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 705 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); 706 707 return found; 708 } 709 710 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { 711 .dpms = radeon_legacy_primary_dac_dpms, 712 .mode_fixup = radeon_legacy_mode_fixup, 713 .prepare = radeon_legacy_primary_dac_prepare, 714 .mode_set = radeon_legacy_primary_dac_mode_set, 715 .commit = radeon_legacy_primary_dac_commit, 716 .detect = radeon_legacy_primary_dac_detect, 717 .disable = radeon_legacy_encoder_disable, 718 }; 719 720 721 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { 722 .destroy = radeon_enc_destroy, 723 }; 724 725 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) 726 { 727 struct drm_device *dev = encoder->dev; 728 struct radeon_device *rdev = dev->dev_private; 729 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); 730 DRM_DEBUG_KMS("\n"); 731 732 switch (mode) { 733 case DRM_MODE_DPMS_ON: 734 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); 735 break; 736 case DRM_MODE_DPMS_STANDBY: 737 case DRM_MODE_DPMS_SUSPEND: 738 case DRM_MODE_DPMS_OFF: 739 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 740 break; 741 } 742 743 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 744 745 if (rdev->is_atom_bios) 746 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 747 else 748 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 749 750 } 751 752 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) 753 { 754 struct radeon_device *rdev = encoder->dev->dev_private; 755 756 if (rdev->is_atom_bios) 757 radeon_atom_output_lock(encoder, true); 758 else 759 radeon_combios_output_lock(encoder, true); 760 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); 761 } 762 763 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) 764 { 765 struct radeon_device *rdev = encoder->dev->dev_private; 766 767 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); 768 769 if (rdev->is_atom_bios) 770 radeon_atom_output_lock(encoder, true); 771 else 772 radeon_combios_output_lock(encoder, true); 773 } 774 775 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, 776 struct drm_display_mode *mode, 777 struct drm_display_mode *adjusted_mode) 778 { 779 struct drm_device *dev = encoder->dev; 780 struct radeon_device *rdev = dev->dev_private; 781 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 782 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 783 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; 784 int i; 785 786 DRM_DEBUG_KMS("\n"); 787 788 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); 789 tmp &= 0xfffff; 790 if (rdev->family == CHIP_RV280) { 791 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ 792 tmp ^= (1 << 22); 793 tmds_pll_cntl ^= (1 << 22); 794 } 795 796 if (radeon_encoder->enc_priv) { 797 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; 798 799 for (i = 0; i < 4; i++) { 800 if (tmds->tmds_pll[i].freq == 0) 801 break; 802 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { 803 tmp = tmds->tmds_pll[i].value ; 804 break; 805 } 806 } 807 } 808 809 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { 810 if (tmp & 0xfff00000) 811 tmds_pll_cntl = tmp; 812 else { 813 tmds_pll_cntl &= 0xfff00000; 814 tmds_pll_cntl |= tmp; 815 } 816 } else 817 tmds_pll_cntl = tmp; 818 819 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & 820 ~(RADEON_TMDS_TRANSMITTER_PLLRST); 821 822 if (rdev->family == CHIP_R200 || 823 rdev->family == CHIP_R100 || 824 ASIC_IS_R300(rdev)) 825 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); 826 else /* RV chips got this bit reversed */ 827 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; 828 829 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | 830 (RADEON_FP_CRTC_DONT_SHADOW_VPAR | 831 RADEON_FP_CRTC_DONT_SHADOW_HEND)); 832 833 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 834 835 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | 836 RADEON_FP_DFP_SYNC_SEL | 837 RADEON_FP_CRT_SYNC_SEL | 838 RADEON_FP_CRTC_LOCK_8DOT | 839 RADEON_FP_USE_SHADOW_EN | 840 RADEON_FP_CRTC_USE_SHADOW_VEND | 841 RADEON_FP_CRT_SYNC_ALT); 842 843 if (1) /* FIXME rgbBits == 8 */ 844 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ 845 else 846 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ 847 848 if (radeon_crtc->crtc_id == 0) { 849 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 850 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 851 if (radeon_encoder->rmx_type != RMX_OFF) 852 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 853 else 854 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 855 } else 856 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; 857 } else { 858 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 859 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 860 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; 861 } else 862 fp_gen_cntl |= RADEON_FP_SEL_CRTC2; 863 } 864 865 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); 866 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); 867 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 868 869 if (rdev->is_atom_bios) 870 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 871 else 872 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 873 } 874 875 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { 876 .dpms = radeon_legacy_tmds_int_dpms, 877 .mode_fixup = radeon_legacy_mode_fixup, 878 .prepare = radeon_legacy_tmds_int_prepare, 879 .mode_set = radeon_legacy_tmds_int_mode_set, 880 .commit = radeon_legacy_tmds_int_commit, 881 .disable = radeon_legacy_encoder_disable, 882 }; 883 884 885 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { 886 .destroy = radeon_enc_destroy, 887 }; 888 889 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) 890 { 891 struct drm_device *dev = encoder->dev; 892 struct radeon_device *rdev = dev->dev_private; 893 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 894 DRM_DEBUG_KMS("\n"); 895 896 switch (mode) { 897 case DRM_MODE_DPMS_ON: 898 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; 899 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 900 break; 901 case DRM_MODE_DPMS_STANDBY: 902 case DRM_MODE_DPMS_SUSPEND: 903 case DRM_MODE_DPMS_OFF: 904 fp2_gen_cntl |= RADEON_FP2_BLANK_EN; 905 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 906 break; 907 } 908 909 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 910 911 if (rdev->is_atom_bios) 912 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 913 else 914 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 915 916 } 917 918 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) 919 { 920 struct radeon_device *rdev = encoder->dev->dev_private; 921 922 if (rdev->is_atom_bios) 923 radeon_atom_output_lock(encoder, true); 924 else 925 radeon_combios_output_lock(encoder, true); 926 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); 927 } 928 929 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) 930 { 931 struct radeon_device *rdev = encoder->dev->dev_private; 932 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); 933 934 if (rdev->is_atom_bios) 935 radeon_atom_output_lock(encoder, false); 936 else 937 radeon_combios_output_lock(encoder, false); 938 } 939 940 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, 941 struct drm_display_mode *mode, 942 struct drm_display_mode *adjusted_mode) 943 { 944 struct drm_device *dev = encoder->dev; 945 struct radeon_device *rdev = dev->dev_private; 946 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 947 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 948 uint32_t fp2_gen_cntl; 949 950 DRM_DEBUG_KMS("\n"); 951 952 if (rdev->is_atom_bios) { 953 radeon_encoder->pixel_clock = adjusted_mode->clock; 954 atombios_dvo_setup(encoder, ATOM_ENABLE); 955 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 956 } else { 957 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 958 959 if (1) /* FIXME rgbBits == 8 */ 960 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ 961 else 962 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ 963 964 fp2_gen_cntl &= ~(RADEON_FP2_ON | 965 RADEON_FP2_DVO_EN | 966 RADEON_FP2_DVO_RATE_SEL_SDR); 967 968 /* XXX: these are oem specific */ 969 if (ASIC_IS_R300(rdev)) { 970 if ((dev->pci_device == 0x4850) && 971 (dev->pci_subvendor == 0x1028) && 972 (dev->pci_subdevice == 0x2001)) /* Dell Inspiron 8600 */ 973 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; 974 else 975 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; 976 977 /*if (mode->clock > 165000) 978 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ 979 } 980 if (!radeon_combios_external_tmds_setup(encoder)) 981 radeon_external_tmds_setup(encoder); 982 } 983 984 if (radeon_crtc->crtc_id == 0) { 985 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 986 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 987 if (radeon_encoder->rmx_type != RMX_OFF) 988 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; 989 else 990 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; 991 } else 992 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; 993 } else { 994 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 995 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 996 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 997 } else 998 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; 999 } 1000 1001 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1002 1003 if (rdev->is_atom_bios) 1004 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1005 else 1006 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1007 } 1008 1009 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) 1010 { 1011 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1012 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */ 1013 drm_free(radeon_encoder->enc_priv, DRM_MEM_DRIVER); 1014 drm_encoder_cleanup(encoder); 1015 drm_free(radeon_encoder, DRM_MEM_DRIVER); 1016 } 1017 1018 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { 1019 .dpms = radeon_legacy_tmds_ext_dpms, 1020 .mode_fixup = radeon_legacy_mode_fixup, 1021 .prepare = radeon_legacy_tmds_ext_prepare, 1022 .mode_set = radeon_legacy_tmds_ext_mode_set, 1023 .commit = radeon_legacy_tmds_ext_commit, 1024 .disable = radeon_legacy_encoder_disable, 1025 }; 1026 1027 1028 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { 1029 .destroy = radeon_ext_tmds_enc_destroy, 1030 }; 1031 1032 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) 1033 { 1034 struct drm_device *dev = encoder->dev; 1035 struct radeon_device *rdev = dev->dev_private; 1036 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1037 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; 1038 uint32_t tv_master_cntl = 0; 1039 bool is_tv; 1040 DRM_DEBUG_KMS("\n"); 1041 1042 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1043 1044 if (rdev->family == CHIP_R200) 1045 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1046 else { 1047 if (is_tv) 1048 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1049 else 1050 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1051 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1052 } 1053 1054 switch (mode) { 1055 case DRM_MODE_DPMS_ON: 1056 if (rdev->family == CHIP_R200) { 1057 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1058 } else { 1059 if (is_tv) 1060 tv_master_cntl |= RADEON_TV_ON; 1061 else 1062 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; 1063 1064 if (rdev->family == CHIP_R420 || 1065 rdev->family == CHIP_R423 || 1066 rdev->family == CHIP_RV410) 1067 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | 1068 R420_TV_DAC_GDACPD | 1069 R420_TV_DAC_BDACPD | 1070 RADEON_TV_DAC_BGSLEEP); 1071 else 1072 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | 1073 RADEON_TV_DAC_GDACPD | 1074 RADEON_TV_DAC_BDACPD | 1075 RADEON_TV_DAC_BGSLEEP); 1076 } 1077 break; 1078 case DRM_MODE_DPMS_STANDBY: 1079 case DRM_MODE_DPMS_SUSPEND: 1080 case DRM_MODE_DPMS_OFF: 1081 if (rdev->family == CHIP_R200) 1082 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1083 else { 1084 if (is_tv) 1085 tv_master_cntl &= ~RADEON_TV_ON; 1086 else 1087 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 1088 1089 if (rdev->family == CHIP_R420 || 1090 rdev->family == CHIP_R423 || 1091 rdev->family == CHIP_RV410) 1092 tv_dac_cntl |= (R420_TV_DAC_RDACPD | 1093 R420_TV_DAC_GDACPD | 1094 R420_TV_DAC_BDACPD | 1095 RADEON_TV_DAC_BGSLEEP); 1096 else 1097 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | 1098 RADEON_TV_DAC_GDACPD | 1099 RADEON_TV_DAC_BDACPD | 1100 RADEON_TV_DAC_BGSLEEP); 1101 } 1102 break; 1103 } 1104 1105 if (rdev->family == CHIP_R200) { 1106 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1107 } else { 1108 if (is_tv) 1109 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1110 /* handled in radeon_crtc_dpms() */ 1111 else if (!(rdev->flags & RADEON_SINGLE_CRTC)) 1112 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1113 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1114 } 1115 1116 if (rdev->is_atom_bios) 1117 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1118 else 1119 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1120 1121 } 1122 1123 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) 1124 { 1125 struct radeon_device *rdev = encoder->dev->dev_private; 1126 1127 if (rdev->is_atom_bios) 1128 radeon_atom_output_lock(encoder, true); 1129 else 1130 radeon_combios_output_lock(encoder, true); 1131 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 1132 } 1133 1134 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) 1135 { 1136 struct radeon_device *rdev = encoder->dev->dev_private; 1137 1138 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); 1139 1140 if (rdev->is_atom_bios) 1141 radeon_atom_output_lock(encoder, true); 1142 else 1143 radeon_combios_output_lock(encoder, true); 1144 } 1145 1146 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, 1147 struct drm_display_mode *mode, 1148 struct drm_display_mode *adjusted_mode) 1149 { 1150 struct drm_device *dev = encoder->dev; 1151 struct radeon_device *rdev = dev->dev_private; 1152 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1153 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1154 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1155 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; 1156 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; 1157 bool is_tv = false; 1158 1159 DRM_DEBUG_KMS("\n"); 1160 1161 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1162 1163 if (rdev->family != CHIP_R200) { 1164 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1165 if (rdev->family == CHIP_R420 || 1166 rdev->family == CHIP_R423 || 1167 rdev->family == CHIP_RV410) { 1168 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1169 RADEON_TV_DAC_BGADJ_MASK | 1170 R420_TV_DAC_DACADJ_MASK | 1171 R420_TV_DAC_RDACPD | 1172 R420_TV_DAC_GDACPD | 1173 R420_TV_DAC_BDACPD | 1174 R420_TV_DAC_TVENABLE); 1175 } else { 1176 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1177 RADEON_TV_DAC_BGADJ_MASK | 1178 RADEON_TV_DAC_DACADJ_MASK | 1179 RADEON_TV_DAC_RDACPD | 1180 RADEON_TV_DAC_GDACPD | 1181 RADEON_TV_DAC_BDACPD); 1182 } 1183 1184 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 1185 1186 if (is_tv) { 1187 if (tv_dac->tv_std == TV_STD_NTSC || 1188 tv_dac->tv_std == TV_STD_NTSC_J || 1189 tv_dac->tv_std == TV_STD_PAL_M || 1190 tv_dac->tv_std == TV_STD_PAL_60) 1191 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; 1192 else 1193 tv_dac_cntl |= tv_dac->pal_tvdac_adj; 1194 1195 if (tv_dac->tv_std == TV_STD_NTSC || 1196 tv_dac->tv_std == TV_STD_NTSC_J) 1197 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 1198 else 1199 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 1200 } else 1201 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | 1202 tv_dac->ps2_tvdac_adj); 1203 1204 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1205 } 1206 1207 if (ASIC_IS_R300(rdev)) { 1208 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; 1209 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1210 } else if (rdev->family != CHIP_R200) 1211 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1212 else if (rdev->family == CHIP_R200) 1213 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1214 1215 if (rdev->family >= CHIP_R200) 1216 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); 1217 1218 if (is_tv) { 1219 uint32_t dac_cntl; 1220 1221 dac_cntl = RREG32(RADEON_DAC_CNTL); 1222 dac_cntl &= ~RADEON_DAC_TVO_EN; 1223 WREG32(RADEON_DAC_CNTL, dac_cntl); 1224 1225 if (ASIC_IS_R300(rdev)) 1226 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; 1227 1228 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; 1229 if (radeon_crtc->crtc_id == 0) { 1230 if (ASIC_IS_R300(rdev)) { 1231 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1232 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | 1233 RADEON_DISP_TV_SOURCE_CRTC); 1234 } 1235 if (rdev->family >= CHIP_R200) { 1236 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; 1237 } else { 1238 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1239 } 1240 } else { 1241 if (ASIC_IS_R300(rdev)) { 1242 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1243 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; 1244 } 1245 if (rdev->family >= CHIP_R200) { 1246 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; 1247 } else { 1248 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1249 } 1250 } 1251 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1252 } else { 1253 1254 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; 1255 1256 if (radeon_crtc->crtc_id == 0) { 1257 if (ASIC_IS_R300(rdev)) { 1258 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1259 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; 1260 } else if (rdev->family == CHIP_R200) { 1261 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1262 RADEON_FP2_DVO_RATE_SEL_SDR); 1263 } else 1264 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1265 } else { 1266 if (ASIC_IS_R300(rdev)) { 1267 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1268 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1269 } else if (rdev->family == CHIP_R200) { 1270 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1271 RADEON_FP2_DVO_RATE_SEL_SDR); 1272 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1273 } else 1274 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1275 } 1276 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1277 } 1278 1279 if (ASIC_IS_R300(rdev)) { 1280 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1281 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1282 } else if (rdev->family != CHIP_R200) 1283 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1284 else if (rdev->family == CHIP_R200) 1285 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1286 1287 if (rdev->family >= CHIP_R200) 1288 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); 1289 1290 if (is_tv) 1291 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); 1292 1293 if (rdev->is_atom_bios) 1294 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1295 else 1296 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1297 1298 } 1299 1300 static bool r300_legacy_tv_detect(struct drm_encoder *encoder, 1301 struct drm_connector *connector) 1302 { 1303 struct drm_device *dev = encoder->dev; 1304 struct radeon_device *rdev = dev->dev_private; 1305 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1306 uint32_t disp_output_cntl, gpiopad_a, tmp; 1307 bool found = false; 1308 1309 /* save regs needed */ 1310 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1311 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1312 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1313 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1314 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1315 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1316 1317 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); 1318 1319 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); 1320 1321 WREG32(RADEON_CRTC2_GEN_CNTL, 1322 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); 1323 1324 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1325 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1326 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1327 1328 WREG32(RADEON_DAC_EXT_CNTL, 1329 RADEON_DAC2_FORCE_BLANK_OFF_EN | 1330 RADEON_DAC2_FORCE_DATA_EN | 1331 RADEON_DAC_FORCE_DATA_SEL_RGB | 1332 (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); 1333 1334 WREG32(RADEON_TV_DAC_CNTL, 1335 RADEON_TV_DAC_STD_NTSC | 1336 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1337 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1338 1339 RREG32(RADEON_TV_DAC_CNTL); 1340 DRM_MDELAY(4); 1341 1342 WREG32(RADEON_TV_DAC_CNTL, 1343 RADEON_TV_DAC_NBLANK | 1344 RADEON_TV_DAC_NHOLD | 1345 RADEON_TV_MONITOR_DETECT_EN | 1346 RADEON_TV_DAC_STD_NTSC | 1347 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1348 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1349 1350 RREG32(RADEON_TV_DAC_CNTL); 1351 DRM_MDELAY(6); 1352 1353 tmp = RREG32(RADEON_TV_DAC_CNTL); 1354 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { 1355 found = true; 1356 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1357 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1358 found = true; 1359 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1360 } 1361 1362 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1363 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1364 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1365 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1366 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1367 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1368 return found; 1369 } 1370 1371 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, 1372 struct drm_connector *connector) 1373 { 1374 struct drm_device *dev = encoder->dev; 1375 struct radeon_device *rdev = dev->dev_private; 1376 uint32_t tv_dac_cntl, dac_cntl2; 1377 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; 1378 bool found = false; 1379 1380 if (ASIC_IS_R300(rdev)) 1381 return r300_legacy_tv_detect(encoder, connector); 1382 1383 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1384 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1385 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1386 config_cntl = RREG32(RADEON_CONFIG_CNTL); 1387 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); 1388 1389 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; 1390 WREG32(RADEON_DAC_CNTL2, tmp); 1391 1392 tmp = tv_master_cntl | RADEON_TV_ON; 1393 tmp &= ~(RADEON_TV_ASYNC_RST | 1394 RADEON_RESTART_PHASE_FIX | 1395 RADEON_CRT_FIFO_CE_EN | 1396 RADEON_TV_FIFO_CE_EN | 1397 RADEON_RE_SYNC_NOW_SEL_MASK); 1398 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; 1399 WREG32(RADEON_TV_MASTER_CNTL, tmp); 1400 1401 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | 1402 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | 1403 (8 << RADEON_TV_DAC_BGADJ_SHIFT); 1404 1405 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) 1406 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); 1407 else 1408 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); 1409 WREG32(RADEON_TV_DAC_CNTL, tmp); 1410 1411 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | 1412 RADEON_RED_MX_FORCE_DAC_DATA | 1413 RADEON_GRN_MX_FORCE_DAC_DATA | 1414 RADEON_BLU_MX_FORCE_DAC_DATA | 1415 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); 1416 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); 1417 1418 DRM_MDELAY(3); 1419 tmp = RREG32(RADEON_TV_DAC_CNTL); 1420 if (tmp & RADEON_TV_DAC_GDACDET) { 1421 found = true; 1422 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1423 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1424 found = true; 1425 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1426 } 1427 1428 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); 1429 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1430 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1431 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1432 return found; 1433 } 1434 1435 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, 1436 struct drm_connector *connector) 1437 { 1438 struct drm_device *dev = encoder->dev; 1439 struct radeon_device *rdev = dev->dev_private; 1440 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; 1441 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; 1442 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; 1443 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; 1444 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; 1445 bool found = false; 1446 int i; 1447 1448 /* save the regs we need */ 1449 gpio_monid = RREG32(RADEON_GPIO_MONID); 1450 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1451 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1452 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1453 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A); 1454 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B); 1455 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C); 1456 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D); 1457 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E); 1458 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F); 1459 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP); 1460 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP); 1461 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID); 1462 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID); 1463 1464 tmp = RREG32(RADEON_GPIO_MONID); 1465 tmp &= ~RADEON_GPIO_A_0; 1466 WREG32(RADEON_GPIO_MONID, tmp); 1467 1468 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON | 1469 RADEON_FP2_PANEL_FORMAT | 1470 R200_FP2_SOURCE_SEL_TRANS_UNIT | 1471 RADEON_FP2_DVO_EN | 1472 R200_FP2_DVO_RATE_SEL_SDR)); 1473 1474 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX | 1475 RADEON_DISP_TRANS_MATRIX_GRAPHICS)); 1476 1477 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | 1478 RADEON_CRTC2_DISP_REQ_EN_B)); 1479 1480 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); 1481 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); 1482 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); 1483 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); 1484 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); 1485 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); 1486 1487 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); 1488 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); 1489 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); 1490 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); 1491 1492 for (i = 0; i < 200; i++) { 1493 tmp = RREG32(RADEON_GPIO_MONID); 1494 if (tmp & RADEON_GPIO_Y_0) 1495 found = true; 1496 1497 if (found) 1498 break; 1499 1500 DRM_MDELAY(1); 1501 if (!drm_can_sleep()) 1502 DRM_MDELAY(1); 1503 else 1504 DRM_MSLEEP(1); 1505 } 1506 1507 /* restore the regs we used */ 1508 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); 1509 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); 1510 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); 1511 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); 1512 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); 1513 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); 1514 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); 1515 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); 1516 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); 1517 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); 1518 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1519 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1520 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1521 WREG32(RADEON_GPIO_MONID, gpio_monid); 1522 1523 return found; 1524 } 1525 1526 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, 1527 struct drm_connector *connector) 1528 { 1529 struct drm_device *dev = encoder->dev; 1530 struct radeon_device *rdev = dev->dev_private; 1531 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1532 uint32_t gpiopad_a = 0, pixclks_cntl, tmp; 1533 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0; 1534 enum drm_connector_status found = connector_status_disconnected; 1535 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1536 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1537 bool color = true; 1538 struct drm_crtc *crtc; 1539 1540 /* find out if crtc2 is in use or if this encoder is using it */ 1541 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1542 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1543 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) { 1544 if (encoder->crtc != crtc) { 1545 return connector_status_disconnected; 1546 } 1547 } 1548 } 1549 1550 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || 1551 connector->connector_type == DRM_MODE_CONNECTOR_Composite || 1552 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { 1553 bool tv_detect; 1554 1555 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) 1556 return connector_status_disconnected; 1557 1558 tv_detect = radeon_legacy_tv_detect(encoder, connector); 1559 if (tv_detect && tv_dac) 1560 found = connector_status_connected; 1561 return found; 1562 } 1563 1564 /* don't probe if the encoder is being used for something else not CRT related */ 1565 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { 1566 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); 1567 return connector_status_disconnected; 1568 } 1569 1570 /* R200 uses an external DAC for secondary DAC */ 1571 if (rdev->family == CHIP_R200) { 1572 if (radeon_legacy_ext_dac_detect(encoder, connector)) 1573 found = connector_status_connected; 1574 return found; 1575 } 1576 1577 /* save the regs we need */ 1578 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 1579 1580 if (rdev->flags & RADEON_SINGLE_CRTC) { 1581 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 1582 } else { 1583 if (ASIC_IS_R300(rdev)) { 1584 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1585 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1586 } else { 1587 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1588 } 1589 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1590 } 1591 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1592 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1593 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1594 1595 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb 1596 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 1597 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 1598 1599 if (rdev->flags & RADEON_SINGLE_CRTC) { 1600 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 1601 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 1602 } else { 1603 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; 1604 tmp |= RADEON_CRTC2_CRT2_ON | 1605 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); 1606 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 1607 1608 if (ASIC_IS_R300(rdev)) { 1609 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); 1610 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1611 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1612 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1613 } else { 1614 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; 1615 WREG32(RADEON_DISP_HW_DEBUG, tmp); 1616 } 1617 } 1618 1619 tmp = RADEON_TV_DAC_NBLANK | 1620 RADEON_TV_DAC_NHOLD | 1621 RADEON_TV_MONITOR_DETECT_EN | 1622 RADEON_TV_DAC_STD_PS2; 1623 1624 WREG32(RADEON_TV_DAC_CNTL, tmp); 1625 1626 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | 1627 RADEON_DAC2_FORCE_DATA_EN; 1628 1629 if (color) 1630 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 1631 else 1632 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 1633 1634 if (ASIC_IS_R300(rdev)) 1635 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 1636 else 1637 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 1638 1639 WREG32(RADEON_DAC_EXT_CNTL, tmp); 1640 1641 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; 1642 WREG32(RADEON_DAC_CNTL2, tmp); 1643 1644 DRM_MDELAY(10); 1645 1646 if (ASIC_IS_R300(rdev)) { 1647 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) 1648 found = connector_status_connected; 1649 } else { 1650 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) 1651 found = connector_status_connected; 1652 } 1653 1654 /* restore regs we used */ 1655 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1656 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1657 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1658 1659 if (rdev->flags & RADEON_SINGLE_CRTC) { 1660 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 1661 } else { 1662 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1663 if (ASIC_IS_R300(rdev)) { 1664 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1665 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1666 } else { 1667 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1668 } 1669 } 1670 1671 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1672 1673 return found; 1674 1675 } 1676 1677 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { 1678 .dpms = radeon_legacy_tv_dac_dpms, 1679 .mode_fixup = radeon_legacy_mode_fixup, 1680 .prepare = radeon_legacy_tv_dac_prepare, 1681 .mode_set = radeon_legacy_tv_dac_mode_set, 1682 .commit = radeon_legacy_tv_dac_commit, 1683 .detect = radeon_legacy_tv_dac_detect, 1684 .disable = radeon_legacy_encoder_disable, 1685 }; 1686 1687 1688 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { 1689 .destroy = radeon_enc_destroy, 1690 }; 1691 1692 1693 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) 1694 { 1695 struct drm_device *dev = encoder->base.dev; 1696 struct radeon_device *rdev = dev->dev_private; 1697 struct radeon_encoder_int_tmds *tmds = NULL; 1698 bool ret; 1699 1700 tmds = kmalloc(sizeof(struct radeon_encoder_int_tmds), 1701 DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 1702 1703 if (!tmds) 1704 return NULL; 1705 1706 if (rdev->is_atom_bios) 1707 ret = radeon_atombios_get_tmds_info(encoder, tmds); 1708 else 1709 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); 1710 1711 if (ret == false) 1712 radeon_legacy_get_tmds_info_from_table(encoder, tmds); 1713 1714 return tmds; 1715 } 1716 1717 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) 1718 { 1719 struct drm_device *dev = encoder->base.dev; 1720 struct radeon_device *rdev = dev->dev_private; 1721 struct radeon_encoder_ext_tmds *tmds = NULL; 1722 bool ret; 1723 1724 if (rdev->is_atom_bios) 1725 return NULL; 1726 1727 tmds = kmalloc(sizeof(struct radeon_encoder_ext_tmds), 1728 DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 1729 1730 if (!tmds) 1731 return NULL; 1732 1733 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); 1734 1735 if (ret == false) 1736 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); 1737 1738 return tmds; 1739 } 1740 1741 void 1742 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) 1743 { 1744 struct radeon_device *rdev = dev->dev_private; 1745 struct drm_encoder *encoder; 1746 struct radeon_encoder *radeon_encoder; 1747 1748 /* see if we already added it */ 1749 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1750 radeon_encoder = to_radeon_encoder(encoder); 1751 if (radeon_encoder->encoder_enum == encoder_enum) { 1752 radeon_encoder->devices |= supported_device; 1753 return; 1754 } 1755 1756 } 1757 1758 /* add a new one */ 1759 radeon_encoder = kmalloc(sizeof(struct radeon_encoder), 1760 DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 1761 if (!radeon_encoder) 1762 return; 1763 1764 encoder = &radeon_encoder->base; 1765 if (rdev->flags & RADEON_SINGLE_CRTC) 1766 encoder->possible_crtcs = 0x1; 1767 else 1768 encoder->possible_crtcs = 0x3; 1769 1770 radeon_encoder->enc_priv = NULL; 1771 1772 radeon_encoder->encoder_enum = encoder_enum; 1773 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1774 radeon_encoder->devices = supported_device; 1775 radeon_encoder->rmx_type = RMX_OFF; 1776 1777 switch (radeon_encoder->encoder_id) { 1778 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1779 encoder->possible_crtcs = 0x1; 1780 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS); 1781 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); 1782 if (rdev->is_atom_bios) 1783 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1784 else 1785 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); 1786 radeon_encoder->rmx_type = RMX_FULL; 1787 break; 1788 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1789 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); 1790 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); 1791 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); 1792 break; 1793 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1794 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); 1795 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); 1796 if (rdev->is_atom_bios) 1797 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); 1798 else 1799 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); 1800 break; 1801 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1802 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC); 1803 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); 1804 if (rdev->is_atom_bios) 1805 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); 1806 else 1807 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); 1808 break; 1809 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1810 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS); 1811 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); 1812 if (!rdev->is_atom_bios) 1813 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); 1814 break; 1815 } 1816 } 1817