1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 39 struct radeon_bo; 40 struct radeon_device; 41 42 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 43 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 44 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 45 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 46 47 #define RADEON_MAX_HPD_PINS 7 48 #define RADEON_MAX_CRTCS 6 49 #define RADEON_MAX_AFMT_BLOCKS 7 50 51 enum radeon_rmx_type { 52 RMX_OFF, 53 RMX_FULL, 54 RMX_CENTER, 55 RMX_ASPECT 56 }; 57 58 enum radeon_tv_std { 59 TV_STD_NTSC, 60 TV_STD_PAL, 61 TV_STD_PAL_M, 62 TV_STD_PAL_60, 63 TV_STD_NTSC_J, 64 TV_STD_SCART_PAL, 65 TV_STD_SECAM, 66 TV_STD_PAL_CN, 67 TV_STD_PAL_N, 68 }; 69 70 enum radeon_underscan_type { 71 UNDERSCAN_OFF, 72 UNDERSCAN_ON, 73 UNDERSCAN_AUTO, 74 }; 75 76 enum radeon_hpd_id { 77 RADEON_HPD_1 = 0, 78 RADEON_HPD_2, 79 RADEON_HPD_3, 80 RADEON_HPD_4, 81 RADEON_HPD_5, 82 RADEON_HPD_6, 83 RADEON_HPD_NONE = 0xff, 84 }; 85 86 #define RADEON_MAX_I2C_BUS 16 87 88 /* radeon gpio-based i2c 89 * 1. "mask" reg and bits 90 * grabs the gpio pins for software use 91 * 0=not held 1=held 92 * 2. "a" reg and bits 93 * output pin value 94 * 0=low 1=high 95 * 3. "en" reg and bits 96 * sets the pin direction 97 * 0=input 1=output 98 * 4. "y" reg and bits 99 * input pin value 100 * 0=low 1=high 101 */ 102 struct radeon_i2c_bus_rec { 103 bool valid; 104 /* id used by atom */ 105 uint8_t i2c_id; 106 /* id used by atom */ 107 enum radeon_hpd_id hpd; 108 /* can be used with hw i2c engine */ 109 bool hw_capable; 110 /* uses multi-media i2c engine */ 111 bool mm_i2c; 112 /* regs and bits */ 113 uint32_t mask_clk_reg; 114 uint32_t mask_data_reg; 115 uint32_t a_clk_reg; 116 uint32_t a_data_reg; 117 uint32_t en_clk_reg; 118 uint32_t en_data_reg; 119 uint32_t y_clk_reg; 120 uint32_t y_data_reg; 121 uint32_t mask_clk_mask; 122 uint32_t mask_data_mask; 123 uint32_t a_clk_mask; 124 uint32_t a_data_mask; 125 uint32_t en_clk_mask; 126 uint32_t en_data_mask; 127 uint32_t y_clk_mask; 128 uint32_t y_data_mask; 129 }; 130 131 struct radeon_tmds_pll { 132 uint32_t freq; 133 uint32_t value; 134 }; 135 136 #define RADEON_MAX_BIOS_CONNECTOR 16 137 138 /* pll flags */ 139 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 140 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 141 #define RADEON_PLL_USE_REF_DIV (1 << 2) 142 #define RADEON_PLL_LEGACY (1 << 3) 143 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 144 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 145 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 146 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 147 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 148 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 149 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 150 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 151 #define RADEON_PLL_USE_POST_DIV (1 << 12) 152 #define RADEON_PLL_IS_LCD (1 << 13) 153 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 154 155 struct radeon_pll { 156 /* reference frequency */ 157 uint32_t reference_freq; 158 159 /* fixed dividers */ 160 uint32_t reference_div; 161 uint32_t post_div; 162 163 /* pll in/out limits */ 164 uint32_t pll_in_min; 165 uint32_t pll_in_max; 166 uint32_t pll_out_min; 167 uint32_t pll_out_max; 168 uint32_t lcd_pll_out_min; 169 uint32_t lcd_pll_out_max; 170 uint32_t best_vco; 171 172 /* divider limits */ 173 uint32_t min_ref_div; 174 uint32_t max_ref_div; 175 uint32_t min_post_div; 176 uint32_t max_post_div; 177 uint32_t min_feedback_div; 178 uint32_t max_feedback_div; 179 uint32_t min_frac_feedback_div; 180 uint32_t max_frac_feedback_div; 181 182 /* flags for the current clock */ 183 uint32_t flags; 184 185 /* pll id */ 186 uint32_t id; 187 }; 188 189 struct radeon_i2c_chan { 190 device_t adapter; 191 device_t iic_bus; 192 struct drm_device *dev; 193 struct radeon_i2c_bus_rec rec; 194 char name[48]; 195 }; 196 197 /* mostly for macs, but really any system without connector tables */ 198 enum radeon_connector_table { 199 CT_NONE = 0, 200 CT_GENERIC, 201 CT_IBOOK, 202 CT_POWERBOOK_EXTERNAL, 203 CT_POWERBOOK_INTERNAL, 204 CT_POWERBOOK_VGA, 205 CT_MINI_EXTERNAL, 206 CT_MINI_INTERNAL, 207 CT_IMAC_G5_ISIGHT, 208 CT_EMAC, 209 CT_RN50_POWER, 210 CT_MAC_X800, 211 CT_MAC_G5_9600, 212 CT_SAM440EP, 213 CT_MAC_G4_SILVER 214 }; 215 216 enum radeon_dvo_chip { 217 DVO_SIL164, 218 DVO_SIL1178, 219 }; 220 221 struct radeon_fbdev; 222 223 struct radeon_afmt { 224 bool enabled; 225 int offset; 226 bool last_buffer_filled_status; 227 int id; 228 struct r600_audio_pin *pin; 229 }; 230 231 struct radeon_mode_info { 232 struct atom_context *atom_context; 233 struct card_info *atom_card_info; 234 enum radeon_connector_table connector_table; 235 bool mode_config_initialized; 236 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 237 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 238 /* DVI-I properties */ 239 struct drm_property *coherent_mode_property; 240 /* DAC enable load detect */ 241 struct drm_property *load_detect_property; 242 /* TV standard */ 243 struct drm_property *tv_std_property; 244 /* legacy TMDS PLL detect */ 245 struct drm_property *tmds_pll_property; 246 /* underscan */ 247 struct drm_property *underscan_property; 248 struct drm_property *underscan_hborder_property; 249 struct drm_property *underscan_vborder_property; 250 /* audio */ 251 struct drm_property *audio_property; 252 /* FMT dithering */ 253 struct drm_property *dither_property; 254 /* hardcoded DFP edid from BIOS */ 255 struct edid *bios_hardcoded_edid; 256 int bios_hardcoded_edid_size; 257 258 /* pointer to fbdev info structure */ 259 struct radeon_fbdev *rfbdev; 260 /* firmware flags */ 261 u16 firmware_flags; 262 /* pointer to backlight encoder */ 263 struct radeon_encoder *bl_encoder; 264 }; 265 266 #define RADEON_MAX_BL_LEVEL 0xFF 267 268 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 269 270 struct radeon_backlight_privdata { 271 struct radeon_encoder *encoder; 272 uint8_t negative; 273 }; 274 275 #endif 276 277 #define MAX_H_CODE_TIMING_LEN 32 278 #define MAX_V_CODE_TIMING_LEN 32 279 280 /* need to store these as reading 281 back code tables is excessive */ 282 struct radeon_tv_regs { 283 uint32_t tv_uv_adr; 284 uint32_t timing_cntl; 285 uint32_t hrestart; 286 uint32_t vrestart; 287 uint32_t frestart; 288 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 289 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 290 }; 291 292 struct radeon_atom_ss { 293 uint16_t percentage; 294 uint16_t percentage_divider; 295 uint8_t type; 296 uint16_t step; 297 uint8_t delay; 298 uint8_t range; 299 uint8_t refdiv; 300 /* asic_ss */ 301 uint16_t rate; 302 uint16_t amount; 303 }; 304 305 enum radeon_flip_status { 306 RADEON_FLIP_NONE, 307 RADEON_FLIP_PENDING, 308 RADEON_FLIP_SUBMITTED 309 }; 310 311 struct radeon_crtc { 312 struct drm_crtc base; 313 int crtc_id; 314 u16 lut_r[256], lut_g[256], lut_b[256]; 315 bool enabled; 316 bool can_tile; 317 uint32_t crtc_offset; 318 struct drm_gem_object *cursor_bo; 319 uint64_t cursor_addr; 320 int cursor_width; 321 int cursor_height; 322 int max_cursor_width; 323 int max_cursor_height; 324 uint32_t legacy_display_base_addr; 325 uint32_t legacy_cursor_offset; 326 enum radeon_rmx_type rmx_type; 327 u8 h_border; 328 u8 v_border; 329 fixed20_12 vsc; 330 fixed20_12 hsc; 331 struct drm_display_mode native_mode; 332 int pll_id; 333 /* page flipping */ 334 struct workqueue_struct *flip_queue; 335 struct radeon_flip_work *flip_work; 336 enum radeon_flip_status flip_status; 337 /* pll sharing */ 338 struct radeon_atom_ss ss; 339 bool ss_enabled; 340 u32 adjusted_clock; 341 int bpc; 342 u32 pll_reference_div; 343 u32 pll_post_div; 344 u32 pll_flags; 345 struct drm_encoder *encoder; 346 struct drm_connector *connector; 347 /* for dpm */ 348 u32 line_time; 349 u32 wm_low; 350 u32 wm_high; 351 struct drm_display_mode hw_mode; 352 }; 353 354 struct radeon_encoder_primary_dac { 355 /* legacy primary dac */ 356 uint32_t ps2_pdac_adj; 357 }; 358 359 struct radeon_encoder_lvds { 360 /* legacy lvds */ 361 uint16_t panel_vcc_delay; 362 uint8_t panel_pwr_delay; 363 uint8_t panel_digon_delay; 364 uint8_t panel_blon_delay; 365 uint16_t panel_ref_divider; 366 uint8_t panel_post_divider; 367 uint16_t panel_fb_divider; 368 bool use_bios_dividers; 369 uint32_t lvds_gen_cntl; 370 /* panel mode */ 371 struct drm_display_mode native_mode; 372 struct backlight_device *bl_dev; 373 int dpms_mode; 374 uint8_t backlight_level; 375 }; 376 377 struct radeon_encoder_tv_dac { 378 /* legacy tv dac */ 379 uint32_t ps2_tvdac_adj; 380 uint32_t ntsc_tvdac_adj; 381 uint32_t pal_tvdac_adj; 382 383 int h_pos; 384 int v_pos; 385 int h_size; 386 int supported_tv_stds; 387 bool tv_on; 388 enum radeon_tv_std tv_std; 389 struct radeon_tv_regs tv; 390 }; 391 392 struct radeon_encoder_int_tmds { 393 /* legacy int tmds */ 394 struct radeon_tmds_pll tmds_pll[4]; 395 }; 396 397 struct radeon_encoder_ext_tmds { 398 /* tmds over dvo */ 399 struct radeon_i2c_chan *i2c_bus; 400 uint8_t slave_addr; 401 enum radeon_dvo_chip dvo_chip; 402 }; 403 404 /* spread spectrum */ 405 struct radeon_encoder_atom_dig { 406 bool linkb; 407 /* atom dig */ 408 bool coherent_mode; 409 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 410 /* atom lvds/edp */ 411 uint32_t lcd_misc; 412 uint16_t panel_pwr_delay; 413 uint32_t lcd_ss_id; 414 /* panel mode */ 415 struct drm_display_mode native_mode; 416 struct backlight_device *bl_dev; 417 int dpms_mode; 418 uint8_t backlight_level; 419 int panel_mode; 420 struct radeon_afmt *afmt; 421 }; 422 423 struct radeon_encoder_atom_dac { 424 enum radeon_tv_std tv_std; 425 }; 426 427 struct radeon_encoder { 428 struct drm_encoder base; 429 uint32_t encoder_enum; 430 uint32_t encoder_id; 431 uint32_t devices; 432 uint32_t active_device; 433 uint32_t flags; 434 uint32_t pixel_clock; 435 enum radeon_rmx_type rmx_type; 436 enum radeon_underscan_type underscan_type; 437 uint32_t underscan_hborder; 438 uint32_t underscan_vborder; 439 struct drm_display_mode native_mode; 440 void *enc_priv; 441 int audio_polling_active; 442 bool is_ext_encoder; 443 u16 caps; 444 }; 445 446 struct radeon_connector_atom_dig { 447 uint32_t igp_lane_info; 448 /* displayport */ 449 struct radeon_i2c_chan *dp_i2c_bus; 450 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 451 u8 dp_sink_type; 452 int dp_clock; 453 int dp_lane_count; 454 bool edp_on; 455 }; 456 457 struct radeon_gpio_rec { 458 bool valid; 459 u8 id; 460 u32 reg; 461 u32 mask; 462 }; 463 464 struct radeon_hpd { 465 enum radeon_hpd_id hpd; 466 u8 plugged_state; 467 struct radeon_gpio_rec gpio; 468 }; 469 470 struct radeon_router { 471 u32 router_id; 472 struct radeon_i2c_bus_rec i2c_info; 473 u8 i2c_addr; 474 /* i2c mux */ 475 bool ddc_valid; 476 u8 ddc_mux_type; 477 u8 ddc_mux_control_pin; 478 u8 ddc_mux_state; 479 /* clock/data mux */ 480 bool cd_valid; 481 u8 cd_mux_type; 482 u8 cd_mux_control_pin; 483 u8 cd_mux_state; 484 }; 485 486 enum radeon_connector_audio { 487 RADEON_AUDIO_DISABLE = 0, 488 RADEON_AUDIO_ENABLE = 1, 489 RADEON_AUDIO_AUTO = 2 490 }; 491 492 enum radeon_connector_dither { 493 RADEON_FMT_DITHER_DISABLE = 0, 494 RADEON_FMT_DITHER_ENABLE = 1, 495 }; 496 497 struct radeon_connector { 498 struct drm_connector base; 499 uint32_t connector_id; 500 uint32_t devices; 501 struct radeon_i2c_chan *ddc_bus; 502 /* some systems have an hdmi and vga port with a shared ddc line */ 503 bool shared_ddc; 504 bool use_digital; 505 /* we need to mind the EDID between detect 506 and get modes due to analog/digital/tvencoder */ 507 struct edid *edid; 508 void *con_priv; 509 bool dac_load_detect; 510 bool detected_by_load; /* if the connection status was determined by load */ 511 uint16_t connector_object_id; 512 struct radeon_hpd hpd; 513 struct radeon_router router; 514 struct radeon_i2c_chan *router_bus; 515 enum radeon_connector_audio audio; 516 enum radeon_connector_dither dither; 517 int pixelclock_for_modeset; 518 }; 519 520 struct radeon_framebuffer { 521 struct drm_framebuffer base; 522 struct drm_gem_object *obj; 523 }; 524 525 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 526 ((em) == ATOM_ENCODER_MODE_DP_MST)) 527 528 struct atom_clock_dividers { 529 u32 post_div; 530 union { 531 struct { 532 #ifdef __BIG_ENDIAN 533 u32 reserved : 6; 534 u32 whole_fb_div : 12; 535 u32 frac_fb_div : 14; 536 #else 537 u32 frac_fb_div : 14; 538 u32 whole_fb_div : 12; 539 u32 reserved : 6; 540 #endif 541 }; 542 u32 fb_div; 543 }; 544 u32 ref_div; 545 bool enable_post_div; 546 bool enable_dithen; 547 u32 vco_mode; 548 u32 real_clock; 549 /* added for CI */ 550 u32 post_divider; 551 u32 flags; 552 }; 553 554 struct atom_mpll_param { 555 union { 556 struct { 557 #ifdef __BIG_ENDIAN 558 u32 reserved : 8; 559 u32 clkfrac : 12; 560 u32 clkf : 12; 561 #else 562 u32 clkf : 12; 563 u32 clkfrac : 12; 564 u32 reserved : 8; 565 #endif 566 }; 567 u32 fb_div; 568 }; 569 u32 post_div; 570 u32 bwcntl; 571 u32 dll_speed; 572 u32 vco_mode; 573 u32 yclk_sel; 574 u32 qdr; 575 u32 half_rate; 576 }; 577 578 #define MEM_TYPE_GDDR5 0x50 579 #define MEM_TYPE_GDDR4 0x40 580 #define MEM_TYPE_GDDR3 0x30 581 #define MEM_TYPE_DDR2 0x20 582 #define MEM_TYPE_GDDR1 0x10 583 #define MEM_TYPE_DDR3 0xb0 584 #define MEM_TYPE_MASK 0xf0 585 586 struct atom_memory_info { 587 u8 mem_vendor; 588 u8 mem_type; 589 }; 590 591 #define MAX_AC_TIMING_ENTRIES 16 592 593 struct atom_memory_clock_range_table 594 { 595 u8 num_entries; 596 u8 rsv[3]; 597 u32 mclk[MAX_AC_TIMING_ENTRIES]; 598 }; 599 600 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 601 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 602 603 struct atom_mc_reg_entry { 604 u32 mclk_max; 605 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 606 }; 607 608 struct atom_mc_register_address { 609 u16 s1; 610 u8 pre_reg_data; 611 }; 612 613 struct atom_mc_reg_table { 614 u8 last; 615 u8 num_entries; 616 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 617 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 618 }; 619 620 #define MAX_VOLTAGE_ENTRIES 32 621 622 struct atom_voltage_table_entry 623 { 624 u16 value; 625 u32 smio_low; 626 }; 627 628 struct atom_voltage_table 629 { 630 u32 count; 631 u32 mask_low; 632 u32 phase_delay; 633 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 634 }; 635 636 637 extern void 638 radeon_add_atom_connector(struct drm_device *dev, 639 uint32_t connector_id, 640 uint32_t supported_device, 641 int connector_type, 642 struct radeon_i2c_bus_rec *i2c_bus, 643 uint32_t igp_lane_info, 644 uint16_t connector_object_id, 645 struct radeon_hpd *hpd, 646 struct radeon_router *router); 647 extern void 648 radeon_add_legacy_connector(struct drm_device *dev, 649 uint32_t connector_id, 650 uint32_t supported_device, 651 int connector_type, 652 struct radeon_i2c_bus_rec *i2c_bus, 653 uint16_t connector_object_id, 654 struct radeon_hpd *hpd); 655 extern uint32_t 656 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 657 uint8_t dac); 658 extern void radeon_link_encoder_connector(struct drm_device *dev); 659 660 extern enum radeon_tv_std 661 radeon_combios_get_tv_info(struct radeon_device *rdev); 662 extern enum radeon_tv_std 663 radeon_atombios_get_tv_info(struct radeon_device *rdev); 664 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 665 u16 *vddc, u16 *vddci, u16 *mvdd); 666 667 extern void 668 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 669 struct drm_encoder *encoder, 670 bool connected); 671 extern void 672 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 673 struct drm_encoder *encoder, 674 bool connected); 675 676 extern struct drm_connector * 677 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 678 extern struct drm_connector * 679 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 680 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 681 u32 pixel_clock); 682 683 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 684 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 685 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 686 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 687 688 extern struct edid *radeon_connector_edid(struct drm_connector *connector); 689 690 extern void radeon_connector_hotplug(struct drm_connector *connector); 691 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 692 struct drm_display_mode *mode); 693 extern void radeon_dp_set_link_config(struct drm_connector *connector, 694 const struct drm_display_mode *mode); 695 extern void radeon_dp_link_train(struct drm_encoder *encoder, 696 struct drm_connector *connector); 697 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 698 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 699 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 700 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 701 struct drm_connector *connector); 702 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 703 u8 power_state); 704 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 705 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 706 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 707 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 708 int action, uint8_t lane_num, 709 uint8_t lane_set); 710 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 711 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 712 extern int radeon_dp_i2c_aux_ch(device_t dev, int mode, 713 u8 write_byte, u8 *read_byte); 714 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 715 716 extern void radeon_i2c_init(struct radeon_device *rdev); 717 extern void radeon_i2c_fini(struct radeon_device *rdev); 718 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 719 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 720 extern void radeon_i2c_add(struct radeon_device *rdev, 721 struct radeon_i2c_bus_rec *rec, 722 const char *name); 723 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 724 struct radeon_i2c_bus_rec *i2c_bus); 725 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 726 struct radeon_i2c_bus_rec *rec, 727 const char *name); 728 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 729 struct radeon_i2c_bus_rec *rec, 730 const char *name); 731 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 732 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 733 u8 slave_addr, 734 u8 addr, 735 u8 *val); 736 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 737 u8 slave_addr, 738 u8 addr, 739 u8 val); 740 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 741 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 742 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 743 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 744 745 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 746 747 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 748 struct radeon_atom_ss *ss, 749 int id); 750 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 751 struct radeon_atom_ss *ss, 752 int id, u32 clock); 753 754 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 755 uint64_t freq, 756 uint32_t *dot_clock_p, 757 uint32_t *fb_div_p, 758 uint32_t *frac_fb_div_p, 759 uint32_t *ref_div_p, 760 uint32_t *post_div_p); 761 762 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 763 u32 freq, 764 u32 *dot_clock_p, 765 u32 *fb_div_p, 766 u32 *frac_fb_div_p, 767 u32 *ref_div_p, 768 u32 *post_div_p); 769 770 extern void radeon_setup_encoder_clones(struct drm_device *dev); 771 772 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 773 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 774 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 775 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 776 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 777 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 778 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 779 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 780 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 781 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 782 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 783 784 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 785 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 786 struct drm_framebuffer *old_fb); 787 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 788 struct drm_framebuffer *fb, 789 int x, int y, 790 enum mode_set_atomic state); 791 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 792 struct drm_display_mode *mode, 793 struct drm_display_mode *adjusted_mode, 794 int x, int y, 795 struct drm_framebuffer *old_fb); 796 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 797 798 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 799 struct drm_framebuffer *old_fb); 800 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 801 struct drm_framebuffer *fb, 802 int x, int y, 803 enum mode_set_atomic state); 804 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 805 struct drm_framebuffer *fb, 806 int x, int y, int atomic); 807 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 808 struct drm_file *file_priv, 809 uint32_t handle, 810 uint32_t width, 811 uint32_t height); 812 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 813 int x, int y); 814 815 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 816 unsigned int flags, 817 int *vpos, int *hpos, ktime_t *stime, 818 ktime_t *etime); 819 820 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 821 extern struct edid * 822 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 823 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 824 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 825 extern struct radeon_encoder_atom_dig * 826 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 827 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 828 struct radeon_encoder_int_tmds *tmds); 829 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 830 struct radeon_encoder_int_tmds *tmds); 831 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 832 struct radeon_encoder_int_tmds *tmds); 833 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 834 struct radeon_encoder_ext_tmds *tmds); 835 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 836 struct radeon_encoder_ext_tmds *tmds); 837 extern struct radeon_encoder_primary_dac * 838 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 839 extern struct radeon_encoder_tv_dac * 840 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 841 extern struct radeon_encoder_lvds * 842 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 843 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 844 extern struct radeon_encoder_tv_dac * 845 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 846 extern struct radeon_encoder_primary_dac * 847 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 848 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 849 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 850 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 851 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 852 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 853 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 854 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 855 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 856 extern void 857 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 858 extern void 859 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 860 extern void 861 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 862 extern void 863 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 864 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 865 u16 blue, int regno); 866 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 867 u16 *blue, int regno); 868 int radeon_framebuffer_init(struct drm_device *dev, 869 struct radeon_framebuffer *rfb, 870 struct drm_mode_fb_cmd2 *mode_cmd, 871 struct drm_gem_object *obj); 872 873 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 874 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 875 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 876 void radeon_atombios_init_crtc(struct drm_device *dev, 877 struct radeon_crtc *radeon_crtc); 878 void radeon_legacy_init_crtc(struct drm_device *dev, 879 struct radeon_crtc *radeon_crtc); 880 881 void radeon_get_clock_info(struct drm_device *dev); 882 883 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 884 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 885 886 void radeon_enc_destroy(struct drm_encoder *encoder); 887 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 888 void radeon_combios_asic_init(struct drm_device *dev); 889 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 890 const struct drm_display_mode *mode, 891 struct drm_display_mode *adjusted_mode); 892 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 893 struct drm_display_mode *adjusted_mode); 894 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 895 896 /* legacy tv */ 897 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 898 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 899 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 900 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 901 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 902 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 903 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 904 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 905 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 906 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 907 struct drm_display_mode *mode, 908 struct drm_display_mode *adjusted_mode); 909 910 /* fmt blocks */ 911 void avivo_program_fmt(struct drm_encoder *encoder); 912 void dce3_program_fmt(struct drm_encoder *encoder); 913 void dce4_program_fmt(struct drm_encoder *encoder); 914 void dce8_program_fmt(struct drm_encoder *encoder); 915 916 /* fbdev layer */ 917 int radeon_fbdev_init(struct radeon_device *rdev); 918 void radeon_fbdev_fini(struct radeon_device *rdev); 919 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 920 int radeon_fbdev_total_size(struct radeon_device *rdev); 921 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 922 923 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 924 925 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 926 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 927 928 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 929 #endif 930