1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 * 29 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_mode.h 254885 2013-08-25 19:37:15Z dumbbell $ 30 */ 31 32 #ifndef RADEON_MODE_H 33 #define RADEON_MODE_H 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_fixed.h> 39 #include <drm/drm_crtc_helper.h> 40 41 struct radeon_bo; 42 struct radeon_device; 43 44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48 49 enum radeon_rmx_type { 50 RMX_OFF, 51 RMX_FULL, 52 RMX_CENTER, 53 RMX_ASPECT 54 }; 55 56 enum radeon_tv_std { 57 TV_STD_NTSC, 58 TV_STD_PAL, 59 TV_STD_PAL_M, 60 TV_STD_PAL_60, 61 TV_STD_NTSC_J, 62 TV_STD_SCART_PAL, 63 TV_STD_SECAM, 64 TV_STD_PAL_CN, 65 TV_STD_PAL_N, 66 }; 67 68 enum radeon_underscan_type { 69 UNDERSCAN_OFF, 70 UNDERSCAN_ON, 71 UNDERSCAN_AUTO, 72 }; 73 74 enum radeon_hpd_id { 75 RADEON_HPD_1 = 0, 76 RADEON_HPD_2, 77 RADEON_HPD_3, 78 RADEON_HPD_4, 79 RADEON_HPD_5, 80 RADEON_HPD_6, 81 RADEON_HPD_NONE = 0xff, 82 }; 83 84 #define RADEON_MAX_I2C_BUS 16 85 86 /* radeon gpio-based i2c 87 * 1. "mask" reg and bits 88 * grabs the gpio pins for software use 89 * 0=not held 1=held 90 * 2. "a" reg and bits 91 * output pin value 92 * 0=low 1=high 93 * 3. "en" reg and bits 94 * sets the pin direction 95 * 0=input 1=output 96 * 4. "y" reg and bits 97 * input pin value 98 * 0=low 1=high 99 */ 100 struct radeon_i2c_bus_rec { 101 bool valid; 102 /* id used by atom */ 103 uint8_t i2c_id; 104 /* id used by atom */ 105 enum radeon_hpd_id hpd; 106 /* can be used with hw i2c engine */ 107 bool hw_capable; 108 /* uses multi-media i2c engine */ 109 bool mm_i2c; 110 /* regs and bits */ 111 uint32_t mask_clk_reg; 112 uint32_t mask_data_reg; 113 uint32_t a_clk_reg; 114 uint32_t a_data_reg; 115 uint32_t en_clk_reg; 116 uint32_t en_data_reg; 117 uint32_t y_clk_reg; 118 uint32_t y_data_reg; 119 uint32_t mask_clk_mask; 120 uint32_t mask_data_mask; 121 uint32_t a_clk_mask; 122 uint32_t a_data_mask; 123 uint32_t en_clk_mask; 124 uint32_t en_data_mask; 125 uint32_t y_clk_mask; 126 uint32_t y_data_mask; 127 }; 128 129 struct radeon_tmds_pll { 130 uint32_t freq; 131 uint32_t value; 132 }; 133 134 #define RADEON_MAX_BIOS_CONNECTOR 16 135 136 /* pll flags */ 137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139 #define RADEON_PLL_USE_REF_DIV (1 << 2) 140 #define RADEON_PLL_LEGACY (1 << 3) 141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149 #define RADEON_PLL_USE_POST_DIV (1 << 12) 150 #define RADEON_PLL_IS_LCD (1 << 13) 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152 153 struct radeon_pll { 154 /* reference frequency */ 155 uint32_t reference_freq; 156 157 /* fixed dividers */ 158 uint32_t reference_div; 159 uint32_t post_div; 160 161 /* pll in/out limits */ 162 uint32_t pll_in_min; 163 uint32_t pll_in_max; 164 uint32_t pll_out_min; 165 uint32_t pll_out_max; 166 uint32_t lcd_pll_out_min; 167 uint32_t lcd_pll_out_max; 168 uint32_t best_vco; 169 170 /* divider limits */ 171 uint32_t min_ref_div; 172 uint32_t max_ref_div; 173 uint32_t min_post_div; 174 uint32_t max_post_div; 175 uint32_t min_feedback_div; 176 uint32_t max_feedback_div; 177 uint32_t min_frac_feedback_div; 178 uint32_t max_frac_feedback_div; 179 180 /* flags for the current clock */ 181 uint32_t flags; 182 183 /* pll id */ 184 uint32_t id; 185 }; 186 187 struct radeon_i2c_chan { 188 device_t adapter; 189 device_t iic_bus; 190 struct drm_device *dev; 191 struct radeon_i2c_bus_rec rec; 192 char name[48]; 193 }; 194 195 /* mostly for macs, but really any system without connector tables */ 196 enum radeon_connector_table { 197 CT_NONE = 0, 198 CT_GENERIC, 199 CT_IBOOK, 200 CT_POWERBOOK_EXTERNAL, 201 CT_POWERBOOK_INTERNAL, 202 CT_POWERBOOK_VGA, 203 CT_MINI_EXTERNAL, 204 CT_MINI_INTERNAL, 205 CT_IMAC_G5_ISIGHT, 206 CT_EMAC, 207 CT_RN50_POWER, 208 CT_MAC_X800, 209 CT_MAC_G5_9600, 210 CT_SAM440EP, 211 CT_MAC_G4_SILVER 212 }; 213 214 enum radeon_dvo_chip { 215 DVO_SIL164, 216 DVO_SIL1178, 217 }; 218 219 struct radeon_fbdev; 220 221 struct radeon_afmt { 222 bool enabled; 223 int offset; 224 bool last_buffer_filled_status; 225 int id; 226 }; 227 228 struct radeon_mode_info { 229 struct atom_context *atom_context; 230 struct card_info *atom_card_info; 231 enum radeon_connector_table connector_table; 232 bool mode_config_initialized; 233 struct radeon_crtc *crtcs[6]; 234 struct radeon_afmt *afmt[6]; 235 /* DVI-I properties */ 236 struct drm_property *coherent_mode_property; 237 /* DAC enable load detect */ 238 struct drm_property *load_detect_property; 239 /* TV standard */ 240 struct drm_property *tv_std_property; 241 /* legacy TMDS PLL detect */ 242 struct drm_property *tmds_pll_property; 243 /* underscan */ 244 struct drm_property *underscan_property; 245 struct drm_property *underscan_hborder_property; 246 struct drm_property *underscan_vborder_property; 247 /* hardcoded DFP edid from BIOS */ 248 struct edid *bios_hardcoded_edid; 249 int bios_hardcoded_edid_size; 250 251 /* pointer to fbdev info structure */ 252 struct radeon_fbdev *rfbdev; 253 /* firmware flags */ 254 u16 firmware_flags; 255 /* pointer to backlight encoder */ 256 struct radeon_encoder *bl_encoder; 257 }; 258 259 #define RADEON_MAX_BL_LEVEL 0xFF 260 261 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 262 263 struct radeon_backlight_privdata { 264 struct radeon_encoder *encoder; 265 uint8_t negative; 266 }; 267 268 #endif 269 270 #define MAX_H_CODE_TIMING_LEN 32 271 #define MAX_V_CODE_TIMING_LEN 32 272 273 /* need to store these as reading 274 back code tables is excessive */ 275 struct radeon_tv_regs { 276 uint32_t tv_uv_adr; 277 uint32_t timing_cntl; 278 uint32_t hrestart; 279 uint32_t vrestart; 280 uint32_t frestart; 281 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 282 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 283 }; 284 285 struct radeon_atom_ss { 286 uint16_t percentage; 287 uint8_t type; 288 uint16_t step; 289 uint8_t delay; 290 uint8_t range; 291 uint8_t refdiv; 292 /* asic_ss */ 293 uint16_t rate; 294 uint16_t amount; 295 }; 296 297 struct radeon_crtc { 298 struct drm_crtc base; 299 int crtc_id; 300 u16 lut_r[256], lut_g[256], lut_b[256]; 301 bool enabled; 302 bool can_tile; 303 uint32_t crtc_offset; 304 struct drm_gem_object *cursor_bo; 305 uint64_t cursor_addr; 306 int cursor_width; 307 int cursor_height; 308 int max_cursor_width; 309 int max_cursor_height; 310 uint32_t legacy_display_base_addr; 311 uint32_t legacy_cursor_offset; 312 enum radeon_rmx_type rmx_type; 313 u8 h_border; 314 u8 v_border; 315 fixed20_12 vsc; 316 fixed20_12 hsc; 317 struct drm_display_mode native_mode; 318 int pll_id; 319 /* page flipping */ 320 struct radeon_unpin_work *unpin_work; 321 int deferred_flip_completion; 322 /* pll sharing */ 323 struct radeon_atom_ss ss; 324 bool ss_enabled; 325 u32 adjusted_clock; 326 int bpc; 327 u32 pll_reference_div; 328 u32 pll_post_div; 329 u32 pll_flags; 330 struct drm_encoder *encoder; 331 struct drm_connector *connector; 332 /* for dpm */ 333 u32 line_time; 334 u32 wm_low; 335 u32 wm_high; 336 struct drm_display_mode hw_mode; 337 }; 338 339 struct radeon_encoder_primary_dac { 340 /* legacy primary dac */ 341 uint32_t ps2_pdac_adj; 342 }; 343 344 struct radeon_encoder_lvds { 345 /* legacy lvds */ 346 uint16_t panel_vcc_delay; 347 uint8_t panel_pwr_delay; 348 uint8_t panel_digon_delay; 349 uint8_t panel_blon_delay; 350 uint16_t panel_ref_divider; 351 uint8_t panel_post_divider; 352 uint16_t panel_fb_divider; 353 bool use_bios_dividers; 354 uint32_t lvds_gen_cntl; 355 /* panel mode */ 356 struct drm_display_mode native_mode; 357 struct backlight_device *bl_dev; 358 int dpms_mode; 359 uint8_t backlight_level; 360 }; 361 362 struct radeon_encoder_tv_dac { 363 /* legacy tv dac */ 364 uint32_t ps2_tvdac_adj; 365 uint32_t ntsc_tvdac_adj; 366 uint32_t pal_tvdac_adj; 367 368 int h_pos; 369 int v_pos; 370 int h_size; 371 int supported_tv_stds; 372 bool tv_on; 373 enum radeon_tv_std tv_std; 374 struct radeon_tv_regs tv; 375 }; 376 377 struct radeon_encoder_int_tmds { 378 /* legacy int tmds */ 379 struct radeon_tmds_pll tmds_pll[4]; 380 }; 381 382 struct radeon_encoder_ext_tmds { 383 /* tmds over dvo */ 384 struct radeon_i2c_chan *i2c_bus; 385 uint8_t slave_addr; 386 enum radeon_dvo_chip dvo_chip; 387 }; 388 389 /* spread spectrum */ 390 struct radeon_encoder_atom_dig { 391 bool linkb; 392 /* atom dig */ 393 bool coherent_mode; 394 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 395 /* atom lvds/edp */ 396 uint32_t lcd_misc; 397 uint16_t panel_pwr_delay; 398 uint32_t lcd_ss_id; 399 /* panel mode */ 400 struct drm_display_mode native_mode; 401 struct backlight_device *bl_dev; 402 int dpms_mode; 403 uint8_t backlight_level; 404 int panel_mode; 405 struct radeon_afmt *afmt; 406 }; 407 408 struct radeon_encoder_atom_dac { 409 enum radeon_tv_std tv_std; 410 }; 411 412 struct radeon_encoder { 413 struct drm_encoder base; 414 uint32_t encoder_enum; 415 uint32_t encoder_id; 416 uint32_t devices; 417 uint32_t active_device; 418 uint32_t flags; 419 uint32_t pixel_clock; 420 enum radeon_rmx_type rmx_type; 421 enum radeon_underscan_type underscan_type; 422 uint32_t underscan_hborder; 423 uint32_t underscan_vborder; 424 struct drm_display_mode native_mode; 425 void *enc_priv; 426 int audio_polling_active; 427 bool is_ext_encoder; 428 u16 caps; 429 }; 430 431 struct radeon_connector_atom_dig { 432 uint32_t igp_lane_info; 433 /* displayport */ 434 struct radeon_i2c_chan *dp_i2c_bus; 435 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 436 u8 dp_sink_type; 437 int dp_clock; 438 int dp_lane_count; 439 bool edp_on; 440 }; 441 442 struct radeon_gpio_rec { 443 bool valid; 444 u8 id; 445 u32 reg; 446 u32 mask; 447 }; 448 449 struct radeon_hpd { 450 enum radeon_hpd_id hpd; 451 u8 plugged_state; 452 struct radeon_gpio_rec gpio; 453 }; 454 455 struct radeon_router { 456 u32 router_id; 457 struct radeon_i2c_bus_rec i2c_info; 458 u8 i2c_addr; 459 /* i2c mux */ 460 bool ddc_valid; 461 u8 ddc_mux_type; 462 u8 ddc_mux_control_pin; 463 u8 ddc_mux_state; 464 /* clock/data mux */ 465 bool cd_valid; 466 u8 cd_mux_type; 467 u8 cd_mux_control_pin; 468 u8 cd_mux_state; 469 }; 470 471 struct radeon_connector { 472 struct drm_connector base; 473 uint32_t connector_id; 474 uint32_t devices; 475 struct radeon_i2c_chan *ddc_bus; 476 /* some systems have an hdmi and vga port with a shared ddc line */ 477 bool shared_ddc; 478 bool use_digital; 479 /* we need to mind the EDID between detect 480 and get modes due to analog/digital/tvencoder */ 481 struct edid *edid; 482 void *con_priv; 483 bool dac_load_detect; 484 bool detected_by_load; /* if the connection status was determined by load */ 485 uint16_t connector_object_id; 486 struct radeon_hpd hpd; 487 struct radeon_router router; 488 struct radeon_i2c_chan *router_bus; 489 }; 490 491 struct radeon_framebuffer { 492 struct drm_framebuffer base; 493 struct drm_gem_object *obj; 494 }; 495 496 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 497 ((em) == ATOM_ENCODER_MODE_DP_MST)) 498 499 struct atom_clock_dividers { 500 u32 post_div; 501 union { 502 struct { 503 #ifdef __BIG_ENDIAN 504 u32 reserved : 6; 505 u32 whole_fb_div : 12; 506 u32 frac_fb_div : 14; 507 #else 508 u32 frac_fb_div : 14; 509 u32 whole_fb_div : 12; 510 u32 reserved : 6; 511 #endif 512 }; 513 u32 fb_div; 514 }; 515 u32 ref_div; 516 bool enable_post_div; 517 bool enable_dithen; 518 u32 vco_mode; 519 u32 real_clock; 520 /* added for CI */ 521 u32 post_divider; 522 u32 flags; 523 }; 524 525 struct atom_mpll_param { 526 union { 527 struct { 528 #ifdef __BIG_ENDIAN 529 u32 reserved : 8; 530 u32 clkfrac : 12; 531 u32 clkf : 12; 532 #else 533 u32 clkf : 12; 534 u32 clkfrac : 12; 535 u32 reserved : 8; 536 #endif 537 }; 538 u32 fb_div; 539 }; 540 u32 post_div; 541 u32 bwcntl; 542 u32 dll_speed; 543 u32 vco_mode; 544 u32 yclk_sel; 545 u32 qdr; 546 u32 half_rate; 547 }; 548 549 #define MEM_TYPE_GDDR5 0x50 550 #define MEM_TYPE_GDDR4 0x40 551 #define MEM_TYPE_GDDR3 0x30 552 #define MEM_TYPE_DDR2 0x20 553 #define MEM_TYPE_GDDR1 0x10 554 #define MEM_TYPE_DDR3 0xb0 555 #define MEM_TYPE_MASK 0xf0 556 557 struct atom_memory_info { 558 u8 mem_vendor; 559 u8 mem_type; 560 }; 561 562 #define MAX_AC_TIMING_ENTRIES 16 563 564 struct atom_memory_clock_range_table 565 { 566 u8 num_entries; 567 u8 rsv[3]; 568 u32 mclk[MAX_AC_TIMING_ENTRIES]; 569 }; 570 571 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 572 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 573 574 struct atom_mc_reg_entry { 575 u32 mclk_max; 576 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 577 }; 578 579 struct atom_mc_register_address { 580 u16 s1; 581 u8 pre_reg_data; 582 }; 583 584 struct atom_mc_reg_table { 585 u8 last; 586 u8 num_entries; 587 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 588 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 589 }; 590 591 #define MAX_VOLTAGE_ENTRIES 32 592 593 struct atom_voltage_table_entry 594 { 595 u16 value; 596 u32 smio_low; 597 }; 598 599 struct atom_voltage_table 600 { 601 u32 count; 602 u32 mask_low; 603 u32 phase_delay; 604 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 605 }; 606 607 extern enum radeon_tv_std 608 radeon_combios_get_tv_info(struct radeon_device *rdev); 609 extern enum radeon_tv_std 610 radeon_atombios_get_tv_info(struct radeon_device *rdev); 611 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 612 u16 *vddc, u16 *vddci, u16 *mvdd); 613 614 extern struct drm_connector * 615 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 616 extern struct drm_connector * 617 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 618 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 619 u32 pixel_clock); 620 621 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 622 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 623 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 624 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 625 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 626 627 extern void radeon_connector_hotplug(struct drm_connector *connector); 628 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 629 struct drm_display_mode *mode); 630 extern void radeon_dp_set_link_config(struct drm_connector *connector, 631 const struct drm_display_mode *mode); 632 extern void radeon_dp_link_train(struct drm_encoder *encoder, 633 struct drm_connector *connector); 634 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 635 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 636 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 637 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 638 struct drm_connector *connector); 639 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 640 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 641 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 642 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 643 int action, uint8_t lane_num, 644 uint8_t lane_set); 645 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 646 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 647 extern int radeon_dp_i2c_aux_ch(device_t dev, int mode, 648 u8 write_byte, u8 *read_byte); 649 650 extern void radeon_i2c_init(struct radeon_device *rdev); 651 extern void radeon_i2c_fini(struct radeon_device *rdev); 652 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 653 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 654 extern void radeon_i2c_add(struct radeon_device *rdev, 655 struct radeon_i2c_bus_rec *rec, 656 const char *name); 657 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 658 struct radeon_i2c_bus_rec *i2c_bus); 659 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 660 struct radeon_i2c_bus_rec *rec, 661 const char *name); 662 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 663 struct radeon_i2c_bus_rec *rec, 664 const char *name); 665 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 666 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 667 u8 slave_addr, 668 u8 addr, 669 u8 *val); 670 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 671 u8 slave_addr, 672 u8 addr, 673 u8 val); 674 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 675 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 676 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 677 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 678 679 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 680 681 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 682 struct radeon_atom_ss *ss, 683 int id); 684 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 685 struct radeon_atom_ss *ss, 686 int id, u32 clock); 687 688 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 689 uint64_t freq, 690 uint32_t *dot_clock_p, 691 uint32_t *fb_div_p, 692 uint32_t *frac_fb_div_p, 693 uint32_t *ref_div_p, 694 uint32_t *post_div_p); 695 696 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 697 u32 freq, 698 u32 *dot_clock_p, 699 u32 *fb_div_p, 700 u32 *frac_fb_div_p, 701 u32 *ref_div_p, 702 u32 *post_div_p); 703 704 extern void radeon_setup_encoder_clones(struct drm_device *dev); 705 706 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 707 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 708 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 709 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 710 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 711 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 712 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 713 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 714 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 715 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 716 717 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 718 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 719 struct drm_framebuffer *old_fb); 720 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 721 struct drm_framebuffer *fb, 722 int x, int y, 723 enum mode_set_atomic state); 724 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 725 struct drm_display_mode *mode, 726 struct drm_display_mode *adjusted_mode, 727 int x, int y, 728 struct drm_framebuffer *old_fb); 729 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 730 731 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 732 struct drm_framebuffer *old_fb); 733 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 734 struct drm_framebuffer *fb, 735 int x, int y, 736 enum mode_set_atomic state); 737 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 738 struct drm_framebuffer *fb, 739 int x, int y, int atomic); 740 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 741 struct drm_file *file_priv, 742 uint32_t handle, 743 uint32_t width, 744 uint32_t height); 745 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 746 int x, int y); 747 748 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 749 unsigned int flags, 750 int *vpos, int *hpos, ktime_t *stime, 751 ktime_t *etime); 752 753 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 754 extern struct edid * 755 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 756 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 757 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 758 extern struct radeon_encoder_atom_dig * 759 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 760 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 761 struct radeon_encoder_int_tmds *tmds); 762 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 763 struct radeon_encoder_int_tmds *tmds); 764 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 765 struct radeon_encoder_int_tmds *tmds); 766 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 767 struct radeon_encoder_ext_tmds *tmds); 768 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 769 struct radeon_encoder_ext_tmds *tmds); 770 extern struct radeon_encoder_primary_dac * 771 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 772 extern struct radeon_encoder_tv_dac * 773 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 774 extern struct radeon_encoder_lvds * 775 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 776 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 777 extern struct radeon_encoder_tv_dac * 778 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 779 extern struct radeon_encoder_primary_dac * 780 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 781 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 782 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 783 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 784 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 785 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 786 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 787 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 788 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 789 extern void 790 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 791 extern void 792 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 793 extern void 794 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 795 extern void 796 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 797 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 798 u16 blue, int regno); 799 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 800 u16 *blue, int regno); 801 int radeon_framebuffer_init(struct drm_device *dev, 802 struct radeon_framebuffer *rfb, 803 struct drm_mode_fb_cmd2 *mode_cmd, 804 struct drm_gem_object *obj); 805 806 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 807 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 808 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 809 void radeon_atombios_init_crtc(struct drm_device *dev, 810 struct radeon_crtc *radeon_crtc); 811 void radeon_legacy_init_crtc(struct drm_device *dev, 812 struct radeon_crtc *radeon_crtc); 813 814 void radeon_get_clock_info(struct drm_device *dev); 815 816 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 817 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 818 819 void radeon_enc_destroy(struct drm_encoder *encoder); 820 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 821 void radeon_combios_asic_init(struct drm_device *dev); 822 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 823 const struct drm_display_mode *mode, 824 struct drm_display_mode *adjusted_mode); 825 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 826 struct drm_display_mode *adjusted_mode); 827 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 828 829 /* legacy tv */ 830 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 831 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 832 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 833 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 834 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 835 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 836 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 837 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 838 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 839 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 840 struct drm_display_mode *mode, 841 struct drm_display_mode *adjusted_mode); 842 843 /* fbdev layer */ 844 int radeon_fbdev_init(struct radeon_device *rdev); 845 void radeon_fbdev_fini(struct radeon_device *rdev); 846 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 847 int radeon_fbdev_total_size(struct radeon_device *rdev); 848 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 849 850 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 851 852 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 853 854 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 855 #endif 856