1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 * 32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_object.c 254885 2013-08-25 19:37:15Z dumbbell $ 33 */ 34 35 #include <drm/drmP.h> 36 #include <uapi_drm/radeon_drm.h> 37 #include "radeon.h" 38 #ifdef DUMBBELL_WIP 39 #include "radeon_trace.h" 40 #endif /* DUMBBELL_WIP */ 41 42 43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 44 45 /* 46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 47 * function are calling it. 48 */ 49 50 static void radeon_bo_clear_va(struct radeon_bo *bo) 51 { 52 struct radeon_bo_va *bo_va, *tmp; 53 54 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { 55 /* remove from all vm address space */ 56 radeon_vm_bo_rmv(bo->rdev, bo_va); 57 } 58 } 59 60 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 61 { 62 struct radeon_bo *bo; 63 64 bo = container_of(tbo, struct radeon_bo, tbo); 65 spin_lock(&bo->rdev->gem.mutex); 66 list_del_init(&bo->list); 67 spin_unlock(&bo->rdev->gem.mutex); 68 radeon_bo_clear_surface_reg(bo); 69 radeon_bo_clear_va(bo); 70 drm_gem_object_release(&bo->gem_base); 71 drm_free(bo, DRM_MEM_DRIVER); 72 } 73 74 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 75 { 76 if (bo->destroy == &radeon_ttm_bo_destroy) 77 return true; 78 return false; 79 } 80 81 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 82 { 83 u32 c = 0; 84 85 rbo->placement.fpfn = 0; 86 rbo->placement.lpfn = 0; 87 rbo->placement.placement = rbo->placements; 88 rbo->placement.busy_placement = rbo->placements; 89 if (domain & RADEON_GEM_DOMAIN_VRAM) 90 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 91 TTM_PL_FLAG_VRAM; 92 if (domain & RADEON_GEM_DOMAIN_GTT) { 93 if (rbo->rdev->flags & RADEON_IS_AGP) { 94 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT; 95 } else { 96 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 97 } 98 } 99 if (domain & RADEON_GEM_DOMAIN_CPU) { 100 if (rbo->rdev->flags & RADEON_IS_AGP) { 101 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM; 102 } else { 103 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 104 } 105 } 106 if (!c) 107 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 108 rbo->placement.num_placement = c; 109 rbo->placement.num_busy_placement = c; 110 } 111 112 int radeon_bo_create(struct radeon_device *rdev, 113 unsigned long size, int byte_align, bool kernel, u32 domain, 114 struct sg_table *sg, struct radeon_bo **bo_ptr) 115 { 116 struct radeon_bo *bo; 117 enum ttm_bo_type type; 118 unsigned long page_align = roundup2(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 119 size_t acc_size; 120 int r; 121 122 size = roundup2(size, PAGE_SIZE); 123 124 if (kernel) { 125 type = ttm_bo_type_kernel; 126 } else if (sg) { 127 type = ttm_bo_type_sg; 128 } else { 129 type = ttm_bo_type_device; 130 } 131 *bo_ptr = NULL; 132 133 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 134 sizeof(struct radeon_bo)); 135 136 bo = kmalloc(sizeof(struct radeon_bo), DRM_MEM_DRIVER, 137 M_ZERO | M_WAITOK); 138 if (bo == NULL) 139 return -ENOMEM; 140 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 141 if (unlikely(r)) { 142 drm_free(bo, DRM_MEM_DRIVER); 143 return r; 144 } 145 bo->rdev = rdev; 146 bo->gem_base.driver_private = NULL; 147 bo->surface_reg = -1; 148 INIT_LIST_HEAD(&bo->list); 149 INIT_LIST_HEAD(&bo->va); 150 radeon_ttm_placement_from_domain(bo, domain); 151 /* Kernel allocation are uninterruptible */ 152 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 153 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 154 &bo->placement, page_align, !kernel, NULL, 155 acc_size, sg, &radeon_ttm_bo_destroy); 156 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 157 if (unlikely(r != 0)) { 158 return r; 159 } 160 *bo_ptr = bo; 161 162 #ifdef DUMBBELL_WIP 163 trace_radeon_bo_create(bo); 164 #endif /* DUMBBELL_WIP */ 165 166 return 0; 167 } 168 169 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 170 { 171 bool is_iomem; 172 int r; 173 174 if (bo->kptr) { 175 if (ptr) { 176 *ptr = bo->kptr; 177 } 178 return 0; 179 } 180 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 181 if (r) { 182 return r; 183 } 184 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 185 if (ptr) { 186 *ptr = bo->kptr; 187 } 188 radeon_bo_check_tiling(bo, 0, 0); 189 return 0; 190 } 191 192 void radeon_bo_kunmap(struct radeon_bo *bo) 193 { 194 if (bo->kptr == NULL) 195 return; 196 bo->kptr = NULL; 197 radeon_bo_check_tiling(bo, 0, 0); 198 ttm_bo_kunmap(&bo->kmap); 199 } 200 201 void radeon_bo_unref(struct radeon_bo **bo) 202 { 203 struct ttm_buffer_object *tbo; 204 struct radeon_device *rdev; 205 206 if ((*bo) == NULL) 207 return; 208 rdev = (*bo)->rdev; 209 tbo = &((*bo)->tbo); 210 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 211 ttm_bo_unref(&tbo); 212 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 213 if (tbo == NULL) 214 *bo = NULL; 215 } 216 217 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 218 u64 *gpu_addr) 219 { 220 int r, i; 221 222 if (bo->pin_count) { 223 bo->pin_count++; 224 if (gpu_addr) 225 *gpu_addr = radeon_bo_gpu_offset(bo); 226 227 if (max_offset != 0) { 228 u64 domain_start; 229 230 if (domain == RADEON_GEM_DOMAIN_VRAM) 231 domain_start = bo->rdev->mc.vram_start; 232 else 233 domain_start = bo->rdev->mc.gtt_start; 234 if (max_offset < (radeon_bo_gpu_offset(bo) - domain_start)) { 235 DRM_ERROR("radeon_bo_pin_restricted: " 236 "max_offset(%ju) < " 237 "(radeon_bo_gpu_offset(%ju) - " 238 "domain_start(%ju)", 239 (uintmax_t)max_offset, (uintmax_t)radeon_bo_gpu_offset(bo), 240 (uintmax_t)domain_start); 241 } 242 } 243 244 return 0; 245 } 246 radeon_ttm_placement_from_domain(bo, domain); 247 if (domain == RADEON_GEM_DOMAIN_VRAM) { 248 /* force to pin into visible video ram */ 249 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 250 } 251 if (max_offset) { 252 u64 lpfn = max_offset >> PAGE_SHIFT; 253 254 if (!bo->placement.lpfn) 255 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; 256 257 if (lpfn < bo->placement.lpfn) 258 bo->placement.lpfn = lpfn; 259 } 260 for (i = 0; i < bo->placement.num_placement; i++) 261 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 262 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 263 if (likely(r == 0)) { 264 bo->pin_count = 1; 265 if (gpu_addr != NULL) 266 *gpu_addr = radeon_bo_gpu_offset(bo); 267 } 268 if (unlikely(r != 0)) 269 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 270 return r; 271 } 272 273 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 274 { 275 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 276 } 277 278 int radeon_bo_unpin(struct radeon_bo *bo) 279 { 280 int r, i; 281 282 if (!bo->pin_count) { 283 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 284 return 0; 285 } 286 bo->pin_count--; 287 if (bo->pin_count) 288 return 0; 289 for (i = 0; i < bo->placement.num_placement; i++) 290 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 291 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 292 if (unlikely(r != 0)) 293 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 294 return r; 295 } 296 297 int radeon_bo_evict_vram(struct radeon_device *rdev) 298 { 299 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 300 if (0 && (rdev->flags & RADEON_IS_IGP)) { 301 if (rdev->mc.igp_sideport_enabled == false) 302 /* Useless to evict on IGP chips */ 303 return 0; 304 } 305 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 306 } 307 308 void radeon_bo_force_delete(struct radeon_device *rdev) 309 { 310 struct radeon_bo *bo, *n; 311 312 if (list_empty(&rdev->gem.objects)) { 313 return; 314 } 315 dev_err(rdev->dev, "Userspace still has active objects !\n"); 316 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 317 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 318 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 319 *((unsigned long *)&bo->gem_base.refcount)); 320 spin_lock(&bo->rdev->gem.mutex); 321 list_del_init(&bo->list); 322 spin_unlock(&bo->rdev->gem.mutex); 323 /* this should unref the ttm bo */ 324 drm_gem_object_unreference(&bo->gem_base); 325 } 326 } 327 328 int radeon_bo_init(struct radeon_device *rdev) 329 { 330 /* Add an MTRR for the VRAM */ 331 rdev->mc.vram_mtrr = drm_mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 332 DRM_MTRR_WC); 333 DRM_INFO("Detected VRAM RAM=%juM, BAR=%juM\n", 334 (uintmax_t)rdev->mc.mc_vram_size >> 20, 335 (uintmax_t)rdev->mc.aper_size >> 20); 336 DRM_INFO("RAM width %dbits %cDR\n", 337 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 338 return radeon_ttm_init(rdev); 339 } 340 341 void radeon_bo_fini(struct radeon_device *rdev) 342 { 343 radeon_ttm_fini(rdev); 344 } 345 346 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 347 struct list_head *head) 348 { 349 if (lobj->wdomain) { 350 list_add(&lobj->tv.head, head); 351 } else { 352 list_add_tail(&lobj->tv.head, head); 353 } 354 } 355 356 int radeon_bo_list_validate(struct list_head *head) 357 { 358 struct radeon_bo_list *lobj; 359 struct radeon_bo *bo; 360 u32 domain; 361 int r; 362 363 r = ttm_eu_reserve_buffers(head); 364 if (unlikely(r != 0)) { 365 return r; 366 } 367 list_for_each_entry(lobj, head, tv.head) { 368 bo = lobj->bo; 369 if (!bo->pin_count) { 370 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 371 372 retry: 373 radeon_ttm_placement_from_domain(bo, domain); 374 r = ttm_bo_validate(&bo->tbo, &bo->placement, 375 true, false); 376 if (unlikely(r)) { 377 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 378 domain |= RADEON_GEM_DOMAIN_GTT; 379 goto retry; 380 } 381 return r; 382 } 383 } 384 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 385 lobj->tiling_flags = bo->tiling_flags; 386 } 387 return 0; 388 } 389 390 #ifdef DUMBBELL_WIP 391 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 392 struct vm_area_struct *vma) 393 { 394 return ttm_fbdev_mmap(vma, &bo->tbo); 395 } 396 #endif /* DUMBBELL_WIP */ 397 398 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 399 { 400 struct radeon_device *rdev = bo->rdev; 401 struct radeon_surface_reg *reg; 402 struct radeon_bo *old_object; 403 int steal; 404 int i; 405 406 KASSERT(radeon_bo_is_reserved(bo), 407 ("radeon_bo_get_surface_reg: radeon_bo is not reserved")); 408 409 if (!bo->tiling_flags) 410 return 0; 411 412 if (bo->surface_reg >= 0) { 413 reg = &rdev->surface_regs[bo->surface_reg]; 414 i = bo->surface_reg; 415 goto out; 416 } 417 418 steal = -1; 419 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 420 421 reg = &rdev->surface_regs[i]; 422 if (!reg->bo) 423 break; 424 425 old_object = reg->bo; 426 if (old_object->pin_count == 0) 427 steal = i; 428 } 429 430 /* if we are all out */ 431 if (i == RADEON_GEM_MAX_SURFACES) { 432 if (steal == -1) 433 return -ENOMEM; 434 /* find someone with a surface reg and nuke their BO */ 435 reg = &rdev->surface_regs[steal]; 436 old_object = reg->bo; 437 /* blow away the mapping */ 438 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 439 ttm_bo_unmap_virtual(&old_object->tbo); 440 old_object->surface_reg = -1; 441 i = steal; 442 } 443 444 bo->surface_reg = i; 445 reg->bo = bo; 446 447 out: 448 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 449 bo->tbo.mem.start << PAGE_SHIFT, 450 bo->tbo.num_pages << PAGE_SHIFT); 451 return 0; 452 } 453 454 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 455 { 456 struct radeon_device *rdev = bo->rdev; 457 struct radeon_surface_reg *reg; 458 459 if (bo->surface_reg == -1) 460 return; 461 462 reg = &rdev->surface_regs[bo->surface_reg]; 463 radeon_clear_surface_reg(rdev, bo->surface_reg); 464 465 reg->bo = NULL; 466 bo->surface_reg = -1; 467 } 468 469 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 470 uint32_t tiling_flags, uint32_t pitch) 471 { 472 struct radeon_device *rdev = bo->rdev; 473 int r; 474 475 if (rdev->family >= CHIP_CEDAR) { 476 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 477 478 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 479 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 480 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 481 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 482 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 483 switch (bankw) { 484 case 0: 485 case 1: 486 case 2: 487 case 4: 488 case 8: 489 break; 490 default: 491 return -EINVAL; 492 } 493 switch (bankh) { 494 case 0: 495 case 1: 496 case 2: 497 case 4: 498 case 8: 499 break; 500 default: 501 return -EINVAL; 502 } 503 switch (mtaspect) { 504 case 0: 505 case 1: 506 case 2: 507 case 4: 508 case 8: 509 break; 510 default: 511 return -EINVAL; 512 } 513 if (tilesplit > 6) { 514 return -EINVAL; 515 } 516 if (stilesplit > 6) { 517 return -EINVAL; 518 } 519 } 520 r = radeon_bo_reserve(bo, false); 521 if (unlikely(r != 0)) 522 return r; 523 bo->tiling_flags = tiling_flags; 524 bo->pitch = pitch; 525 radeon_bo_unreserve(bo); 526 return 0; 527 } 528 529 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 530 uint32_t *tiling_flags, 531 uint32_t *pitch) 532 { 533 KASSERT(radeon_bo_is_reserved(bo), 534 ("radeon_bo_get_tiling_flags: radeon_bo is not reserved")); 535 if (tiling_flags) 536 *tiling_flags = bo->tiling_flags; 537 if (pitch) 538 *pitch = bo->pitch; 539 } 540 541 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 542 bool force_drop) 543 { 544 KASSERT((radeon_bo_is_reserved(bo) || force_drop), 545 ("radeon_bo_check_tiling: radeon_bo is not reserved && !force_drop")); 546 547 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 548 return 0; 549 550 if (force_drop) { 551 radeon_bo_clear_surface_reg(bo); 552 return 0; 553 } 554 555 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 556 if (!has_moved) 557 return 0; 558 559 if (bo->surface_reg >= 0) 560 radeon_bo_clear_surface_reg(bo); 561 return 0; 562 } 563 564 if ((bo->surface_reg >= 0) && !has_moved) 565 return 0; 566 567 return radeon_bo_get_surface_reg(bo); 568 } 569 570 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 571 struct ttm_mem_reg *mem) 572 { 573 struct radeon_bo *rbo; 574 if (!radeon_ttm_bo_is_radeon_bo(bo)) 575 return; 576 rbo = container_of(bo, struct radeon_bo, tbo); 577 radeon_bo_check_tiling(rbo, 0, 1); 578 radeon_vm_bo_invalidate(rbo->rdev, rbo); 579 } 580 581 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 582 { 583 struct radeon_device *rdev; 584 struct radeon_bo *rbo; 585 unsigned long offset, size; 586 int r; 587 588 if (!radeon_ttm_bo_is_radeon_bo(bo)) 589 return 0; 590 rbo = container_of(bo, struct radeon_bo, tbo); 591 radeon_bo_check_tiling(rbo, 0, 0); 592 rdev = rbo->rdev; 593 if (bo->mem.mem_type == TTM_PL_VRAM) { 594 size = bo->mem.num_pages << PAGE_SHIFT; 595 offset = bo->mem.start << PAGE_SHIFT; 596 if ((offset + size) > rdev->mc.visible_vram_size) { 597 /* hurrah the memory is not visible ! */ 598 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 599 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 600 r = ttm_bo_validate(bo, &rbo->placement, false, false); 601 if (unlikely(r != 0)) 602 return r; 603 offset = bo->mem.start << PAGE_SHIFT; 604 /* this should not happen */ 605 if ((offset + size) > rdev->mc.visible_vram_size) 606 return -EINVAL; 607 } 608 } 609 return 0; 610 } 611 612 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 613 { 614 int r; 615 616 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 617 if (unlikely(r != 0)) 618 return r; 619 lockmgr(&bo->tbo.bdev->fence_lock, LK_EXCLUSIVE); 620 if (mem_type) 621 *mem_type = bo->tbo.mem.mem_type; 622 if (bo->tbo.sync_obj) 623 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 624 lockmgr(&bo->tbo.bdev->fence_lock, LK_RELEASE); 625 ttm_bo_unreserve(&bo->tbo); 626 return r; 627 } 628 629 630 /** 631 * radeon_bo_reserve - reserve bo 632 * @bo: bo structure 633 * @no_intr: don't return -ERESTARTSYS on pending signal 634 * 635 * Returns: 636 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 637 * a signal. Release all buffer reservations and return to user-space. 638 */ 639 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr) 640 { 641 int r; 642 643 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); 644 if (unlikely(r != 0)) { 645 if (r != -ERESTARTSYS) 646 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 647 return r; 648 } 649 return 0; 650 } 651