1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include <drm/drmP.h> 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #include "r600_dpm.h" 28 #include <linux/power_supply.h> 29 #include <linux/hwmon.h> 30 31 #include <sys/power.h> 32 #include <sys/sensors.h> 33 34 #define RADEON_IDLE_LOOP_MS 100 35 #define RADEON_RECLOCK_DELAY_MS 200 36 #define RADEON_WAIT_VBLANK_TIMEOUT 200 37 38 static const char *radeon_pm_state_type_name[5] = { 39 "", 40 "Powersave", 41 "Battery", 42 "Balanced", 43 "Performance", 44 }; 45 46 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 47 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 48 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 50 static void radeon_pm_update_profile(struct radeon_device *rdev); 51 static void radeon_pm_set_clocks(struct radeon_device *rdev); 52 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev); 53 54 int radeon_pm_get_type_index(struct radeon_device *rdev, 55 enum radeon_pm_state_type ps_type, 56 int instance) 57 { 58 int i; 59 int found_instance = -1; 60 61 for (i = 0; i < rdev->pm.num_power_states; i++) { 62 if (rdev->pm.power_state[i].type == ps_type) { 63 found_instance++; 64 if (found_instance == instance) 65 return i; 66 } 67 } 68 /* return default if no match */ 69 return rdev->pm.default_power_state_index; 70 } 71 72 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 73 { 74 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 75 mutex_lock(&rdev->pm.mutex); 76 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) 77 rdev->pm.dpm.ac_power = true; 78 else 79 rdev->pm.dpm.ac_power = false; 80 if (rdev->family == CHIP_ARUBA) { 81 if (rdev->asic->dpm.enable_bapm) 82 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 83 } 84 mutex_unlock(&rdev->pm.mutex); 85 /* allow new DPM state to be picked */ 86 radeon_pm_compute_clocks_dpm(rdev); 87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 88 if (rdev->pm.profile == PM_PROFILE_AUTO) { 89 mutex_lock(&rdev->pm.mutex); 90 radeon_pm_update_profile(rdev); 91 radeon_pm_set_clocks(rdev); 92 mutex_unlock(&rdev->pm.mutex); 93 } 94 } 95 } 96 97 static void radeon_pm_update_profile(struct radeon_device *rdev) 98 { 99 switch (rdev->pm.profile) { 100 case PM_PROFILE_DEFAULT: 101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 102 break; 103 case PM_PROFILE_AUTO: 104 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) { 105 if (rdev->pm.active_crtc_count > 1) 106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 107 else 108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 109 } else { 110 if (rdev->pm.active_crtc_count > 1) 111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 112 else 113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 114 } 115 break; 116 case PM_PROFILE_LOW: 117 if (rdev->pm.active_crtc_count > 1) 118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 119 else 120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 121 break; 122 case PM_PROFILE_MID: 123 if (rdev->pm.active_crtc_count > 1) 124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 125 else 126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 127 break; 128 case PM_PROFILE_HIGH: 129 if (rdev->pm.active_crtc_count > 1) 130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 131 else 132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 133 break; 134 } 135 136 if (rdev->pm.active_crtc_count == 0) { 137 rdev->pm.requested_power_state_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 139 rdev->pm.requested_clock_mode_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 141 } else { 142 rdev->pm.requested_power_state_index = 143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 144 rdev->pm.requested_clock_mode_index = 145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 146 } 147 } 148 149 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 150 { 151 struct radeon_bo *bo, *n; 152 153 if (list_empty(&rdev->gem.objects)) 154 return; 155 156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 157 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 158 ttm_bo_unmap_virtual(&bo->tbo); 159 } 160 } 161 162 static void radeon_sync_with_vblank(struct radeon_device *rdev) 163 { 164 if (rdev->pm.active_crtcs) { 165 rdev->pm.vblank_sync = false; 166 #ifdef DUMBBELL_WIP 167 wait_event_timeout( 168 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 169 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 170 #endif /* DUMBBELL_WIP */ 171 } 172 } 173 174 static void radeon_set_power_state(struct radeon_device *rdev) 175 { 176 u32 sclk, mclk; 177 bool misc_after = false; 178 179 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 180 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 181 return; 182 183 if (radeon_gui_idle(rdev)) { 184 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 185 clock_info[rdev->pm.requested_clock_mode_index].sclk; 186 if (sclk > rdev->pm.default_sclk) 187 sclk = rdev->pm.default_sclk; 188 189 /* starting with BTC, there is one state that is used for both 190 * MH and SH. Difference is that we always use the high clock index for 191 * mclk and vddci. 192 */ 193 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 194 (rdev->family >= CHIP_BARTS) && 195 rdev->pm.active_crtc_count && 196 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 197 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 198 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 199 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 200 else 201 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 202 clock_info[rdev->pm.requested_clock_mode_index].mclk; 203 204 if (mclk > rdev->pm.default_mclk) 205 mclk = rdev->pm.default_mclk; 206 207 /* upvolt before raising clocks, downvolt after lowering clocks */ 208 if (sclk < rdev->pm.current_sclk) 209 misc_after = true; 210 211 radeon_sync_with_vblank(rdev); 212 213 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 214 if (!radeon_pm_in_vbl(rdev)) 215 return; 216 } 217 218 radeon_pm_prepare(rdev); 219 220 if (!misc_after) 221 /* voltage, pcie lanes, etc.*/ 222 radeon_pm_misc(rdev); 223 224 /* set engine clock */ 225 if (sclk != rdev->pm.current_sclk) { 226 radeon_pm_debug_check_in_vbl(rdev, false); 227 radeon_set_engine_clock(rdev, sclk); 228 radeon_pm_debug_check_in_vbl(rdev, true); 229 rdev->pm.current_sclk = sclk; 230 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 231 } 232 233 /* set memory clock */ 234 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 235 radeon_pm_debug_check_in_vbl(rdev, false); 236 radeon_set_memory_clock(rdev, mclk); 237 radeon_pm_debug_check_in_vbl(rdev, true); 238 rdev->pm.current_mclk = mclk; 239 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 240 } 241 242 if (misc_after) 243 /* voltage, pcie lanes, etc.*/ 244 radeon_pm_misc(rdev); 245 246 radeon_pm_finish(rdev); 247 248 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 249 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 250 } else 251 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 252 } 253 254 static void radeon_pm_set_clocks(struct radeon_device *rdev) 255 { 256 struct drm_crtc *crtc; 257 int i, r; 258 259 /* no need to take locks, etc. if nothing's going to change */ 260 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 261 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 262 return; 263 264 down_write(&rdev->pm.mclk_lock); 265 mutex_lock(&rdev->ring_lock); 266 267 /* wait for the rings to drain */ 268 for (i = 0; i < RADEON_NUM_RINGS; i++) { 269 struct radeon_ring *ring = &rdev->ring[i]; 270 if (!ring->ready) { 271 continue; 272 } 273 r = radeon_fence_wait_empty(rdev, i); 274 if (r) { 275 /* needs a GPU reset dont reset here */ 276 mutex_unlock(&rdev->ring_lock); 277 up_write(&rdev->pm.mclk_lock); 278 return; 279 } 280 } 281 282 radeon_unmap_vram_bos(rdev); 283 284 if (rdev->irq.installed) { 285 i = 0; 286 drm_for_each_crtc(crtc, rdev->ddev) { 287 if (rdev->pm.active_crtcs & (1 << i)) { 288 /* This can fail if a modeset is in progress */ 289 if (drm_crtc_vblank_get(crtc) == 0) 290 rdev->pm.req_vblank |= (1 << i); 291 else 292 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 293 i); 294 } 295 i++; 296 } 297 } 298 299 radeon_set_power_state(rdev); 300 301 if (rdev->irq.installed) { 302 i = 0; 303 drm_for_each_crtc(crtc, rdev->ddev) { 304 if (rdev->pm.req_vblank & (1 << i)) { 305 rdev->pm.req_vblank &= ~(1 << i); 306 drm_crtc_vblank_put(crtc); 307 } 308 i++; 309 } 310 } 311 312 /* update display watermarks based on new power state */ 313 radeon_update_bandwidth_info(rdev); 314 if (rdev->pm.active_crtc_count) 315 radeon_bandwidth_update(rdev); 316 317 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 318 319 mutex_unlock(&rdev->ring_lock); 320 up_write(&rdev->pm.mclk_lock); 321 } 322 323 static void radeon_pm_print_states(struct radeon_device *rdev) 324 { 325 int i, j; 326 struct radeon_power_state *power_state; 327 struct radeon_pm_clock_info *clock_info; 328 329 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 330 for (i = 0; i < rdev->pm.num_power_states; i++) { 331 power_state = &rdev->pm.power_state[i]; 332 DRM_DEBUG_DRIVER("State %d: %s\n", i, 333 radeon_pm_state_type_name[power_state->type]); 334 if (i == rdev->pm.default_power_state_index) 335 DRM_DEBUG_DRIVER("\tDefault"); 336 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 337 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 338 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 339 DRM_DEBUG_DRIVER("\tSingle display only\n"); 340 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 341 for (j = 0; j < power_state->num_clock_modes; j++) { 342 clock_info = &(power_state->clock_info[j]); 343 if (rdev->flags & RADEON_IS_IGP) 344 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 345 j, 346 clock_info->sclk * 10); 347 else 348 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 349 j, 350 clock_info->sclk * 10, 351 clock_info->mclk * 10, 352 clock_info->voltage.voltage); 353 } 354 } 355 } 356 357 #ifdef DUMBBELL_WIP 358 static ssize_t radeon_get_pm_profile(struct device *dev, 359 struct device_attribute *attr, 360 char *buf) 361 { 362 struct drm_device *ddev = dev_get_drvdata(dev); 363 struct radeon_device *rdev = ddev->dev_private; 364 int cp = rdev->pm.profile; 365 366 return ksnprintf(buf, PAGE_SIZE, "%s\n", 367 (cp == PM_PROFILE_AUTO) ? "auto" : 368 (cp == PM_PROFILE_LOW) ? "low" : 369 (cp == PM_PROFILE_MID) ? "mid" : 370 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 371 } 372 373 static ssize_t radeon_set_pm_profile(struct device *dev, 374 struct device_attribute *attr, 375 const char *buf, 376 size_t count) 377 { 378 struct drm_device *ddev = dev_get_drvdata(dev); 379 struct radeon_device *rdev = ddev->dev_private; 380 381 /* Can't set profile when the card is off */ 382 if ((rdev->flags & RADEON_IS_PX) && 383 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 384 return -EINVAL; 385 386 mutex_lock(&rdev->pm.mutex); 387 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 388 if (strncmp("default", buf, strlen("default")) == 0) 389 rdev->pm.profile = PM_PROFILE_DEFAULT; 390 else if (strncmp("auto", buf, strlen("auto")) == 0) 391 rdev->pm.profile = PM_PROFILE_AUTO; 392 else if (strncmp("low", buf, strlen("low")) == 0) 393 rdev->pm.profile = PM_PROFILE_LOW; 394 else if (strncmp("mid", buf, strlen("mid")) == 0) 395 rdev->pm.profile = PM_PROFILE_MID; 396 else if (strncmp("high", buf, strlen("high")) == 0) 397 rdev->pm.profile = PM_PROFILE_HIGH; 398 else { 399 count = -EINVAL; 400 goto fail; 401 } 402 radeon_pm_update_profile(rdev); 403 radeon_pm_set_clocks(rdev); 404 } else 405 count = -EINVAL; 406 407 fail: 408 mutex_unlock(&rdev->pm.mutex); 409 410 return count; 411 } 412 413 static ssize_t radeon_get_pm_method(struct device *dev, 414 struct device_attribute *attr, 415 char *buf) 416 { 417 struct drm_device *ddev = dev_get_drvdata(dev); 418 struct radeon_device *rdev = ddev->dev_private; 419 int pm = rdev->pm.pm_method; 420 421 return ksnprintf(buf, PAGE_SIZE, "%s\n", 422 (pm == PM_METHOD_DYNPM) ? "dynpm" : 423 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 424 } 425 426 static ssize_t radeon_set_pm_method(struct device *dev, 427 struct device_attribute *attr, 428 const char *buf, 429 size_t count) 430 { 431 struct drm_device *ddev = dev_get_drvdata(dev); 432 struct radeon_device *rdev = ddev->dev_private; 433 434 /* Can't set method when the card is off */ 435 if ((rdev->flags & RADEON_IS_PX) && 436 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 437 count = -EINVAL; 438 goto fail; 439 } 440 441 /* we don't support the legacy modes with dpm */ 442 if (rdev->pm.pm_method == PM_METHOD_DPM) { 443 count = -EINVAL; 444 goto fail; 445 } 446 447 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 448 mutex_lock(&rdev->pm.mutex); 449 rdev->pm.pm_method = PM_METHOD_DYNPM; 450 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 451 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 452 mutex_unlock(&rdev->pm.mutex); 453 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 454 mutex_lock(&rdev->pm.mutex); 455 /* disable dynpm */ 456 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 457 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 458 rdev->pm.pm_method = PM_METHOD_PROFILE; 459 mutex_unlock(&rdev->pm.mutex); 460 #ifdef DUMBBELL_WIP 461 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 462 #endif /* DUMBBELL_WIP */ 463 } else { 464 count = -EINVAL; 465 goto fail; 466 } 467 radeon_pm_compute_clocks(rdev); 468 fail: 469 return count; 470 } 471 472 static ssize_t radeon_get_dpm_state(struct device *dev, 473 struct device_attribute *attr, 474 char *buf) 475 { 476 struct drm_device *ddev = dev_get_drvdata(dev); 477 struct radeon_device *rdev = ddev->dev_private; 478 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 479 480 return snprintf(buf, PAGE_SIZE, "%s\n", 481 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 482 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 483 } 484 485 static ssize_t radeon_set_dpm_state(struct device *dev, 486 struct device_attribute *attr, 487 const char *buf, 488 size_t count) 489 { 490 struct drm_device *ddev = dev_get_drvdata(dev); 491 struct radeon_device *rdev = ddev->dev_private; 492 493 mutex_lock(&rdev->pm.mutex); 494 if (strncmp("battery", buf, strlen("battery")) == 0) 495 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 496 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 497 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 498 else if (strncmp("performance", buf, strlen("performance")) == 0) 499 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 500 else { 501 mutex_unlock(&rdev->pm.mutex); 502 count = -EINVAL; 503 goto fail; 504 } 505 mutex_unlock(&rdev->pm.mutex); 506 507 /* Can't set dpm state when the card is off */ 508 if (!(rdev->flags & RADEON_IS_PX) || 509 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 510 radeon_pm_compute_clocks(rdev); 511 512 fail: 513 return count; 514 } 515 516 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 517 struct device_attribute *attr, 518 char *buf) 519 { 520 struct drm_device *ddev = dev_get_drvdata(dev); 521 struct radeon_device *rdev = ddev->dev_private; 522 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 523 524 if ((rdev->flags & RADEON_IS_PX) && 525 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 526 return ksnprintf(buf, PAGE_SIZE, "off\n"); 527 528 return snprintf(buf, PAGE_SIZE, "%s\n", 529 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 530 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 531 } 532 533 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 534 struct device_attribute *attr, 535 const char *buf, 536 size_t count) 537 { 538 struct drm_device *ddev = dev_get_drvdata(dev); 539 struct radeon_device *rdev = ddev->dev_private; 540 enum radeon_dpm_forced_level level; 541 int ret = 0; 542 543 /* Can't force performance level when the card is off */ 544 if ((rdev->flags & RADEON_IS_PX) && 545 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 546 return -EINVAL; 547 548 mutex_lock(&rdev->pm.mutex); 549 if (strncmp("low", buf, strlen("low")) == 0) { 550 level = RADEON_DPM_FORCED_LEVEL_LOW; 551 } else if (strncmp("high", buf, strlen("high")) == 0) { 552 level = RADEON_DPM_FORCED_LEVEL_HIGH; 553 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 554 level = RADEON_DPM_FORCED_LEVEL_AUTO; 555 } else { 556 count = -EINVAL; 557 goto fail; 558 } 559 if (rdev->asic->dpm.force_performance_level) { 560 if (rdev->pm.dpm.thermal_active) { 561 count = -EINVAL; 562 goto fail; 563 } 564 ret = radeon_dpm_force_performance_level(rdev, level); 565 if (ret) 566 count = -EINVAL; 567 } 568 fail: 569 mutex_unlock(&rdev->pm.mutex); 570 571 return count; 572 } 573 574 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 575 struct device_attribute *attr, 576 char *buf) 577 { 578 struct radeon_device *rdev = dev_get_drvdata(dev); 579 u32 pwm_mode = 0; 580 581 if (rdev->asic->dpm.fan_ctrl_get_mode) 582 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 583 584 /* never 0 (full-speed), fuse or smc-controlled always */ 585 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 586 } 587 588 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 589 struct device_attribute *attr, 590 const char *buf, 591 size_t count) 592 { 593 struct radeon_device *rdev = dev_get_drvdata(dev); 594 int err; 595 int value; 596 597 if(!rdev->asic->dpm.fan_ctrl_set_mode) 598 return -EINVAL; 599 600 err = kstrtoint(buf, 10, &value); 601 if (err) 602 return err; 603 604 switch (value) { 605 case 1: /* manual, percent-based */ 606 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 607 break; 608 default: /* disable */ 609 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 610 break; 611 } 612 613 return count; 614 } 615 616 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 617 struct device_attribute *attr, 618 char *buf) 619 { 620 return sprintf(buf, "%i\n", 0); 621 } 622 623 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 624 struct device_attribute *attr, 625 char *buf) 626 { 627 return sprintf(buf, "%i\n", 255); 628 } 629 630 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 631 struct device_attribute *attr, 632 const char *buf, size_t count) 633 { 634 struct radeon_device *rdev = dev_get_drvdata(dev); 635 int err; 636 u32 value; 637 638 err = kstrtou32(buf, 10, &value); 639 if (err) 640 return err; 641 642 value = (value * 100) / 255; 643 644 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 645 if (err) 646 return err; 647 648 return count; 649 } 650 651 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 652 struct device_attribute *attr, 653 char *buf) 654 { 655 struct radeon_device *rdev = dev_get_drvdata(dev); 656 int err; 657 u32 speed; 658 659 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 660 if (err) 661 return err; 662 663 speed = (speed * 255) / 100; 664 665 return sprintf(buf, "%i\n", speed); 666 } 667 668 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 669 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 670 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 671 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 672 radeon_get_dpm_forced_performance_level, 673 radeon_set_dpm_forced_performance_level); 674 675 static ssize_t radeon_hwmon_show_temp(struct device *dev, 676 struct device_attribute *attr, 677 char *buf) 678 { 679 struct radeon_device *rdev = dev_get_drvdata(dev); 680 struct drm_device *ddev = rdev->ddev; 681 int temp; 682 683 /* Can't get temperature when the card is off */ 684 if ((rdev->flags & RADEON_IS_PX) && 685 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 686 return -EINVAL; 687 688 if (rdev->asic->pm.get_temperature) 689 temp = radeon_get_temperature(rdev); 690 else 691 temp = 0; 692 693 return ksnprintf(buf, PAGE_SIZE, "%d\n", temp); 694 } 695 696 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 697 struct device_attribute *attr, 698 char *buf) 699 { 700 struct radeon_device *rdev = dev_get_drvdata(dev); 701 int hyst = to_sensor_dev_attr(attr)->index; 702 int temp; 703 704 if (hyst) 705 temp = rdev->pm.dpm.thermal.min_temp; 706 else 707 temp = rdev->pm.dpm.thermal.max_temp; 708 709 return ksnprintf(buf, PAGE_SIZE, "%d\n", temp); 710 } 711 712 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 713 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 714 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 715 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 716 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 717 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 718 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 719 720 721 static struct attribute *hwmon_attributes[] = { 722 &sensor_dev_attr_temp1_input.dev_attr.attr, 723 &sensor_dev_attr_temp1_crit.dev_attr.attr, 724 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 725 &sensor_dev_attr_pwm1.dev_attr.attr, 726 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 727 &sensor_dev_attr_pwm1_min.dev_attr.attr, 728 &sensor_dev_attr_pwm1_max.dev_attr.attr, 729 NULL 730 }; 731 732 static umode_t hwmon_attributes_visible(struct kobject *kobj, 733 struct attribute *attr, int index) 734 { 735 struct device *dev = kobj_to_dev(kobj); 736 struct radeon_device *rdev = dev_get_drvdata(dev); 737 umode_t effective_mode = attr->mode; 738 739 /* Skip attributes if DPM is not enabled */ 740 if (rdev->pm.pm_method != PM_METHOD_DPM && 741 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 742 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 743 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 744 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 745 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 746 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 747 return 0; 748 749 /* Skip fan attributes if fan is not present */ 750 if (rdev->pm.no_fan && 751 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 752 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 753 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 754 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 755 return 0; 756 757 /* mask fan attributes if we have no bindings for this asic to expose */ 758 if ((!rdev->asic->dpm.get_fan_speed_percent && 759 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 760 (!rdev->asic->dpm.fan_ctrl_get_mode && 761 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 762 effective_mode &= ~S_IRUGO; 763 764 if ((!rdev->asic->dpm.set_fan_speed_percent && 765 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 766 (!rdev->asic->dpm.fan_ctrl_set_mode && 767 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 768 effective_mode &= ~S_IWUSR; 769 770 /* hide max/min values if we can't both query and manage the fan */ 771 if ((!rdev->asic->dpm.set_fan_speed_percent && 772 !rdev->asic->dpm.get_fan_speed_percent) && 773 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 774 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 775 return 0; 776 777 return effective_mode; 778 } 779 780 static const struct attribute_group hwmon_attrgroup = { 781 .attrs = hwmon_attributes, 782 .is_visible = hwmon_attributes_visible, 783 }; 784 785 static const struct attribute_group *hwmon_groups[] = { 786 &hwmon_attrgroup, 787 NULL 788 }; 789 #endif /* DUMBBELL_WIP */ 790 791 static void 792 radeon_hwmon_refresh(void *arg) 793 { 794 struct radeon_device *rdev = (struct radeon_device *)arg; 795 struct drm_device *ddev = rdev->ddev; 796 struct ksensor *s = rdev->pm.int_sensor; 797 int temp; 798 enum sensor_status stat; 799 800 /* Can't get temperature when the card is off */ 801 if ((rdev->flags & RADEON_IS_PX) && 802 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 803 sensor_set_unknown(s); 804 s->status = SENSOR_S_OK; 805 return; 806 } 807 808 if (rdev->asic->pm.get_temperature == NULL) { 809 sensor_set_invalid(s); 810 return; 811 } 812 813 temp = radeon_get_temperature(rdev); 814 if (temp >= rdev->pm.dpm.thermal.max_temp) 815 stat = SENSOR_S_CRIT; 816 else if (temp >= rdev->pm.dpm.thermal.min_temp) 817 stat = SENSOR_S_WARN; 818 else 819 stat = SENSOR_S_OK; 820 821 sensor_set(s, temp * 1000 + 273150000, stat); 822 } 823 824 static int radeon_hwmon_init(struct radeon_device *rdev) 825 { 826 int err = 0; 827 828 rdev->pm.int_sensor = NULL; 829 rdev->pm.int_sensordev = NULL; 830 831 switch (rdev->pm.int_thermal_type) { 832 case THERMAL_TYPE_RV6XX: 833 case THERMAL_TYPE_RV770: 834 case THERMAL_TYPE_EVERGREEN: 835 case THERMAL_TYPE_NI: 836 case THERMAL_TYPE_SUMO: 837 case THERMAL_TYPE_SI: 838 case THERMAL_TYPE_CI: 839 case THERMAL_TYPE_KV: 840 if (rdev->asic->pm.get_temperature == NULL) 841 return err; 842 843 rdev->pm.int_sensor = kmalloc(sizeof(*rdev->pm.int_sensor), 844 M_DRM, M_ZERO | M_WAITOK); 845 rdev->pm.int_sensordev = kmalloc( 846 sizeof(*rdev->pm.int_sensordev), M_DRM, 847 M_ZERO | M_WAITOK); 848 strlcpy(rdev->pm.int_sensordev->xname, 849 device_get_nameunit(rdev->dev->bsddev), 850 sizeof(rdev->pm.int_sensordev->xname)); 851 rdev->pm.int_sensor->type = SENSOR_TEMP; 852 rdev->pm.int_sensor->flags |= SENSOR_FINVALID; 853 sensor_attach(rdev->pm.int_sensordev, rdev->pm.int_sensor); 854 sensor_task_register(rdev, radeon_hwmon_refresh, 5); 855 sensordev_install(rdev->pm.int_sensordev); 856 break; 857 default: 858 break; 859 } 860 861 return err; 862 } 863 864 static void radeon_hwmon_fini(struct radeon_device *rdev) 865 { 866 if (rdev->pm.int_sensor != NULL && rdev->pm.int_sensordev != NULL) { 867 sensordev_deinstall(rdev->pm.int_sensordev); 868 sensor_task_unregister(rdev); 869 kfree(rdev->pm.int_sensor); 870 kfree(rdev->pm.int_sensordev); 871 rdev->pm.int_sensor = NULL; 872 rdev->pm.int_sensordev = NULL; 873 } 874 } 875 876 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 877 { 878 struct radeon_device *rdev = 879 container_of(work, struct radeon_device, 880 pm.dpm.thermal.work); 881 /* switch to the thermal state */ 882 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 883 884 if (!rdev->pm.dpm_enabled) 885 return; 886 887 if (rdev->asic->pm.get_temperature) { 888 int temp = radeon_get_temperature(rdev); 889 890 if (temp < rdev->pm.dpm.thermal.min_temp) 891 /* switch back the user state */ 892 dpm_state = rdev->pm.dpm.user_state; 893 } else { 894 if (rdev->pm.dpm.thermal.high_to_low) 895 /* switch back the user state */ 896 dpm_state = rdev->pm.dpm.user_state; 897 } 898 mutex_lock(&rdev->pm.mutex); 899 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 900 rdev->pm.dpm.thermal_active = true; 901 else 902 rdev->pm.dpm.thermal_active = false; 903 rdev->pm.dpm.state = dpm_state; 904 mutex_unlock(&rdev->pm.mutex); 905 906 radeon_pm_compute_clocks(rdev); 907 } 908 909 static bool radeon_dpm_single_display(struct radeon_device *rdev) 910 { 911 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 912 true : false; 913 914 /* check if the vblank period is too short to adjust the mclk */ 915 if (single_display && rdev->asic->dpm.vblank_too_short) { 916 if (radeon_dpm_vblank_too_short(rdev)) 917 single_display = false; 918 } 919 920 return single_display; 921 } 922 923 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 924 enum radeon_pm_state_type dpm_state) 925 { 926 int i; 927 struct radeon_ps *ps; 928 u32 ui_class; 929 bool single_display = radeon_dpm_single_display(rdev); 930 931 /* 120hz tends to be problematic even if they are under the 932 * vblank limit. 933 */ 934 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 935 single_display = false; 936 937 /* certain older asics have a separare 3D performance state, 938 * so try that first if the user selected performance 939 */ 940 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 941 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 942 /* balanced states don't exist at the moment */ 943 if (dpm_state == POWER_STATE_TYPE_BALANCED) 944 dpm_state = rdev->pm.dpm.ac_power ? 945 POWER_STATE_TYPE_PERFORMANCE : POWER_STATE_TYPE_BATTERY; 946 947 restart_search: 948 /* Pick the best power state based on current conditions */ 949 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 950 ps = &rdev->pm.dpm.ps[i]; 951 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 952 switch (dpm_state) { 953 /* user states */ 954 case POWER_STATE_TYPE_BATTERY: 955 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 956 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 957 if (single_display) 958 return ps; 959 } else 960 return ps; 961 } 962 break; 963 case POWER_STATE_TYPE_BALANCED: 964 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 965 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 966 if (single_display) 967 return ps; 968 } else 969 return ps; 970 } 971 break; 972 case POWER_STATE_TYPE_PERFORMANCE: 973 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 974 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 975 if (single_display) 976 return ps; 977 } else 978 return ps; 979 } 980 break; 981 /* internal states */ 982 case POWER_STATE_TYPE_INTERNAL_UVD: 983 if (rdev->pm.dpm.uvd_ps) 984 return rdev->pm.dpm.uvd_ps; 985 else 986 break; 987 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 988 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 989 return ps; 990 break; 991 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 992 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 993 return ps; 994 break; 995 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 996 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 997 return ps; 998 break; 999 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 1000 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 1001 return ps; 1002 break; 1003 case POWER_STATE_TYPE_INTERNAL_BOOT: 1004 return rdev->pm.dpm.boot_ps; 1005 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1006 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 1007 return ps; 1008 break; 1009 case POWER_STATE_TYPE_INTERNAL_ACPI: 1010 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 1011 return ps; 1012 break; 1013 case POWER_STATE_TYPE_INTERNAL_ULV: 1014 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 1015 return ps; 1016 break; 1017 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1018 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 1019 return ps; 1020 break; 1021 default: 1022 break; 1023 } 1024 } 1025 /* use a fallback state if we didn't match */ 1026 switch (dpm_state) { 1027 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 1028 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1029 goto restart_search; 1030 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 1031 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 1032 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 1033 if (rdev->pm.dpm.uvd_ps) { 1034 return rdev->pm.dpm.uvd_ps; 1035 } else { 1036 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1037 goto restart_search; 1038 } 1039 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1040 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 1041 goto restart_search; 1042 case POWER_STATE_TYPE_INTERNAL_ACPI: 1043 dpm_state = POWER_STATE_TYPE_BATTERY; 1044 goto restart_search; 1045 case POWER_STATE_TYPE_BATTERY: 1046 case POWER_STATE_TYPE_BALANCED: 1047 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1048 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1049 goto restart_search; 1050 default: 1051 break; 1052 } 1053 1054 return NULL; 1055 } 1056 1057 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 1058 { 1059 int i; 1060 struct radeon_ps *ps; 1061 enum radeon_pm_state_type dpm_state; 1062 int ret; 1063 bool single_display = radeon_dpm_single_display(rdev); 1064 1065 /* if dpm init failed */ 1066 if (!rdev->pm.dpm_enabled) 1067 return; 1068 1069 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1070 /* add other state override checks here */ 1071 if ((!rdev->pm.dpm.thermal_active) && 1072 (!rdev->pm.dpm.uvd_active)) 1073 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1074 } 1075 dpm_state = rdev->pm.dpm.state; 1076 1077 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1078 if (ps) 1079 rdev->pm.dpm.requested_ps = ps; 1080 else 1081 return; 1082 1083 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1084 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1085 /* vce just modifies an existing state so force a change */ 1086 if (ps->vce_active != rdev->pm.dpm.vce_active) 1087 goto force; 1088 /* user has made a display change (such as timing) */ 1089 if (rdev->pm.dpm.single_display != single_display) 1090 goto force; 1091 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1092 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1093 * all we need to do is update the display configuration. 1094 */ 1095 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1096 /* update display watermarks based on new power state */ 1097 radeon_bandwidth_update(rdev); 1098 /* update displays */ 1099 radeon_dpm_display_configuration_changed(rdev); 1100 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1101 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1102 } 1103 return; 1104 } else { 1105 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1106 * nothing to do, if the num crtcs is > 1 and state is the same, 1107 * update display configuration. 1108 */ 1109 if (rdev->pm.dpm.new_active_crtcs == 1110 rdev->pm.dpm.current_active_crtcs) { 1111 return; 1112 } else { 1113 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1114 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1115 /* update display watermarks based on new power state */ 1116 radeon_bandwidth_update(rdev); 1117 /* update displays */ 1118 radeon_dpm_display_configuration_changed(rdev); 1119 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1120 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1121 return; 1122 } 1123 } 1124 } 1125 } 1126 1127 force: 1128 if (radeon_dpm == 1) { 1129 printk("switching from power state:\n"); 1130 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1131 printk("switching to power state:\n"); 1132 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1133 } 1134 1135 down_write(&rdev->pm.mclk_lock); 1136 mutex_lock(&rdev->ring_lock); 1137 1138 /* update whether vce is active */ 1139 ps->vce_active = rdev->pm.dpm.vce_active; 1140 1141 ret = radeon_dpm_pre_set_power_state(rdev); 1142 if (ret) 1143 goto done; 1144 1145 /* update display watermarks based on new power state */ 1146 radeon_bandwidth_update(rdev); 1147 1148 /* wait for the rings to drain */ 1149 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1150 struct radeon_ring *ring = &rdev->ring[i]; 1151 if (ring->ready) 1152 radeon_fence_wait_empty(rdev, i); 1153 } 1154 1155 /* program the new power state */ 1156 radeon_dpm_set_power_state(rdev); 1157 1158 /* update current power state */ 1159 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1160 1161 radeon_dpm_post_set_power_state(rdev); 1162 1163 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1164 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1165 rdev->pm.dpm.single_display = single_display; 1166 1167 /* update displays */ 1168 radeon_dpm_display_configuration_changed(rdev); 1169 1170 if (rdev->asic->dpm.force_performance_level) { 1171 if (rdev->pm.dpm.thermal_active) { 1172 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1173 /* force low perf level for thermal */ 1174 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1175 /* save the user's level */ 1176 rdev->pm.dpm.forced_level = level; 1177 } else { 1178 /* otherwise, user selected level */ 1179 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1180 } 1181 } 1182 1183 done: 1184 mutex_unlock(&rdev->ring_lock); 1185 up_write(&rdev->pm.mclk_lock); 1186 } 1187 1188 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1189 { 1190 enum radeon_pm_state_type dpm_state; 1191 1192 if (rdev->asic->dpm.powergate_uvd) { 1193 mutex_lock(&rdev->pm.mutex); 1194 /* don't powergate anything if we 1195 have active but pause streams */ 1196 enable |= rdev->pm.dpm.sd > 0; 1197 enable |= rdev->pm.dpm.hd > 0; 1198 /* enable/disable UVD */ 1199 radeon_dpm_powergate_uvd(rdev, !enable); 1200 mutex_unlock(&rdev->pm.mutex); 1201 } else { 1202 if (enable) { 1203 mutex_lock(&rdev->pm.mutex); 1204 rdev->pm.dpm.uvd_active = true; 1205 /* disable this for now */ 1206 #if 0 1207 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1208 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1209 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1210 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1211 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1212 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1213 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1214 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1215 else 1216 #endif 1217 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1218 rdev->pm.dpm.state = dpm_state; 1219 mutex_unlock(&rdev->pm.mutex); 1220 } else { 1221 mutex_lock(&rdev->pm.mutex); 1222 rdev->pm.dpm.uvd_active = false; 1223 mutex_unlock(&rdev->pm.mutex); 1224 } 1225 1226 radeon_pm_compute_clocks(rdev); 1227 } 1228 } 1229 1230 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1231 { 1232 if (enable) { 1233 mutex_lock(&rdev->pm.mutex); 1234 rdev->pm.dpm.vce_active = true; 1235 /* XXX select vce level based on ring/task */ 1236 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1237 mutex_unlock(&rdev->pm.mutex); 1238 } else { 1239 mutex_lock(&rdev->pm.mutex); 1240 rdev->pm.dpm.vce_active = false; 1241 mutex_unlock(&rdev->pm.mutex); 1242 } 1243 1244 radeon_pm_compute_clocks(rdev); 1245 } 1246 1247 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1248 { 1249 mutex_lock(&rdev->pm.mutex); 1250 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1251 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1252 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1253 } 1254 mutex_unlock(&rdev->pm.mutex); 1255 1256 #ifdef DUMBBELL_WIP 1257 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1258 #endif /* DUMBBELL_WIP */ 1259 } 1260 1261 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1262 { 1263 mutex_lock(&rdev->pm.mutex); 1264 /* disable dpm */ 1265 radeon_dpm_disable(rdev); 1266 /* reset the power state */ 1267 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1268 rdev->pm.dpm_enabled = false; 1269 mutex_unlock(&rdev->pm.mutex); 1270 } 1271 1272 void radeon_pm_suspend(struct radeon_device *rdev) 1273 { 1274 if (rdev->pm.pm_method == PM_METHOD_DPM) 1275 radeon_pm_suspend_dpm(rdev); 1276 else 1277 radeon_pm_suspend_old(rdev); 1278 } 1279 1280 static void radeon_pm_resume_old(struct radeon_device *rdev) 1281 { 1282 /* set up the default clocks if the MC ucode is loaded */ 1283 if ((rdev->family >= CHIP_BARTS) && 1284 (rdev->family <= CHIP_CAYMAN) && 1285 rdev->mc_fw) { 1286 if (rdev->pm.default_vddc) 1287 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1288 SET_VOLTAGE_TYPE_ASIC_VDDC); 1289 if (rdev->pm.default_vddci) 1290 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1291 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1292 if (rdev->pm.default_sclk) 1293 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1294 if (rdev->pm.default_mclk) 1295 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1296 } 1297 /* asic init will reset the default power state */ 1298 mutex_lock(&rdev->pm.mutex); 1299 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1300 rdev->pm.current_clock_mode_index = 0; 1301 rdev->pm.current_sclk = rdev->pm.default_sclk; 1302 rdev->pm.current_mclk = rdev->pm.default_mclk; 1303 if (rdev->pm.power_state) { 1304 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1305 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1306 } 1307 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1308 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1309 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1310 #ifdef DUMBBELL_WIP 1311 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1312 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1313 #endif /* DUMBBELL_WIP */ 1314 } 1315 mutex_unlock(&rdev->pm.mutex); 1316 radeon_pm_compute_clocks(rdev); 1317 } 1318 1319 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1320 { 1321 int ret; 1322 1323 /* asic init will reset to the boot state */ 1324 mutex_lock(&rdev->pm.mutex); 1325 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1326 radeon_dpm_setup_asic(rdev); 1327 ret = radeon_dpm_enable(rdev); 1328 mutex_unlock(&rdev->pm.mutex); 1329 if (ret) 1330 goto dpm_resume_fail; 1331 rdev->pm.dpm_enabled = true; 1332 return; 1333 1334 dpm_resume_fail: 1335 DRM_ERROR("radeon: dpm resume failed\n"); 1336 if ((rdev->family >= CHIP_BARTS) && 1337 (rdev->family <= CHIP_CAYMAN) && 1338 rdev->mc_fw) { 1339 if (rdev->pm.default_vddc) 1340 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1341 SET_VOLTAGE_TYPE_ASIC_VDDC); 1342 if (rdev->pm.default_vddci) 1343 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1344 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1345 if (rdev->pm.default_sclk) 1346 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1347 if (rdev->pm.default_mclk) 1348 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1349 } 1350 } 1351 1352 void radeon_pm_resume(struct radeon_device *rdev) 1353 { 1354 if (rdev->pm.pm_method == PM_METHOD_DPM) 1355 radeon_pm_resume_dpm(rdev); 1356 else 1357 radeon_pm_resume_old(rdev); 1358 } 1359 1360 static int radeon_pm_init_old(struct radeon_device *rdev) 1361 { 1362 int ret; 1363 1364 rdev->pm.profile = PM_PROFILE_DEFAULT; 1365 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1366 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1367 rdev->pm.dynpm_can_upclock = true; 1368 rdev->pm.dynpm_can_downclock = true; 1369 rdev->pm.default_sclk = rdev->clock.default_sclk; 1370 rdev->pm.default_mclk = rdev->clock.default_mclk; 1371 rdev->pm.current_sclk = rdev->clock.default_sclk; 1372 rdev->pm.current_mclk = rdev->clock.default_mclk; 1373 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1374 1375 if (rdev->bios) { 1376 if (rdev->is_atom_bios) 1377 radeon_atombios_get_power_modes(rdev); 1378 else 1379 radeon_combios_get_power_modes(rdev); 1380 radeon_pm_print_states(rdev); 1381 radeon_pm_init_profile(rdev); 1382 /* set up the default clocks if the MC ucode is loaded */ 1383 if ((rdev->family >= CHIP_BARTS) && 1384 (rdev->family <= CHIP_CAYMAN) && 1385 rdev->mc_fw) { 1386 if (rdev->pm.default_vddc) 1387 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1388 SET_VOLTAGE_TYPE_ASIC_VDDC); 1389 if (rdev->pm.default_vddci) 1390 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1391 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1392 if (rdev->pm.default_sclk) 1393 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1394 if (rdev->pm.default_mclk) 1395 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1396 } 1397 } 1398 1399 /* set up the internal thermal sensor if applicable */ 1400 ret = radeon_hwmon_init(rdev); 1401 if (ret) 1402 return ret; 1403 1404 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1405 1406 if (rdev->pm.num_power_states > 1) { 1407 if (radeon_debugfs_pm_init(rdev)) { 1408 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1409 } 1410 1411 DRM_INFO("radeon: power management initialized\n"); 1412 } 1413 1414 return 0; 1415 } 1416 1417 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1418 { 1419 int i; 1420 1421 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1422 printk("== power state %d ==\n", i); 1423 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1424 } 1425 } 1426 1427 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1428 { 1429 int ret; 1430 1431 /* default to balanced state */ 1432 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1433 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1434 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1435 rdev->pm.default_sclk = rdev->clock.default_sclk; 1436 rdev->pm.default_mclk = rdev->clock.default_mclk; 1437 rdev->pm.current_sclk = rdev->clock.default_sclk; 1438 rdev->pm.current_mclk = rdev->clock.default_mclk; 1439 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1440 1441 if (rdev->bios && rdev->is_atom_bios) 1442 radeon_atombios_get_power_modes(rdev); 1443 else 1444 return -EINVAL; 1445 1446 /* set up the internal thermal sensor if applicable */ 1447 ret = radeon_hwmon_init(rdev); 1448 if (ret) 1449 return ret; 1450 1451 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1452 mutex_lock(&rdev->pm.mutex); 1453 radeon_dpm_init(rdev); 1454 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1455 if (radeon_dpm == 1) 1456 radeon_dpm_print_power_states(rdev); 1457 radeon_dpm_setup_asic(rdev); 1458 ret = radeon_dpm_enable(rdev); 1459 mutex_unlock(&rdev->pm.mutex); 1460 if (ret) 1461 goto dpm_failed; 1462 rdev->pm.dpm_enabled = true; 1463 1464 #ifdef TODO_DEVICE_FILE 1465 if (radeon_debugfs_pm_init(rdev)) { 1466 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1467 } 1468 #endif 1469 1470 DRM_INFO("radeon: dpm initialized\n"); 1471 1472 return 0; 1473 1474 dpm_failed: 1475 rdev->pm.dpm_enabled = false; 1476 if ((rdev->family >= CHIP_BARTS) && 1477 (rdev->family <= CHIP_CAYMAN) && 1478 rdev->mc_fw) { 1479 if (rdev->pm.default_vddc) 1480 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1481 SET_VOLTAGE_TYPE_ASIC_VDDC); 1482 if (rdev->pm.default_vddci) 1483 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1484 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1485 if (rdev->pm.default_sclk) 1486 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1487 if (rdev->pm.default_mclk) 1488 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1489 } 1490 DRM_ERROR("radeon: dpm initialization failed\n"); 1491 return ret; 1492 } 1493 1494 struct radeon_dpm_quirk { 1495 u32 chip_vendor; 1496 u32 chip_device; 1497 u32 subsys_vendor; 1498 u32 subsys_device; 1499 }; 1500 1501 /* cards with dpm stability problems */ 1502 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1503 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1504 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1505 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1506 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1507 { 0, 0, 0, 0 }, 1508 }; 1509 1510 int radeon_pm_init(struct radeon_device *rdev) 1511 { 1512 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1513 bool disable_dpm = false; 1514 1515 /* Apply dpm quirks */ 1516 while (p && p->chip_device != 0) { 1517 if (rdev->pdev->vendor == p->chip_vendor && 1518 rdev->pdev->device == p->chip_device && 1519 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1520 rdev->pdev->subsystem_device == p->subsys_device) { 1521 disable_dpm = true; 1522 break; 1523 } 1524 ++p; 1525 } 1526 1527 /* enable dpm on rv6xx+ */ 1528 switch (rdev->family) { 1529 case CHIP_RV610: 1530 case CHIP_RV630: 1531 case CHIP_RV620: 1532 case CHIP_RV635: 1533 case CHIP_RV670: 1534 case CHIP_RS780: 1535 case CHIP_RS880: 1536 case CHIP_RV770: 1537 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1538 if (!rdev->rlc_fw) 1539 rdev->pm.pm_method = PM_METHOD_PROFILE; 1540 else if ((rdev->family >= CHIP_RV770) && 1541 (!(rdev->flags & RADEON_IS_IGP)) && 1542 (!rdev->smc_fw)) 1543 rdev->pm.pm_method = PM_METHOD_PROFILE; 1544 else if (radeon_dpm == 1) 1545 rdev->pm.pm_method = PM_METHOD_DPM; 1546 else 1547 rdev->pm.pm_method = PM_METHOD_PROFILE; 1548 break; 1549 case CHIP_RV730: 1550 case CHIP_RV710: 1551 case CHIP_RV740: 1552 case CHIP_CEDAR: 1553 case CHIP_REDWOOD: 1554 case CHIP_JUNIPER: 1555 case CHIP_CYPRESS: 1556 case CHIP_HEMLOCK: 1557 case CHIP_PALM: 1558 case CHIP_SUMO: 1559 case CHIP_SUMO2: 1560 case CHIP_BARTS: 1561 case CHIP_TURKS: 1562 case CHIP_CAICOS: 1563 case CHIP_CAYMAN: 1564 case CHIP_ARUBA: 1565 case CHIP_TAHITI: 1566 case CHIP_PITCAIRN: 1567 case CHIP_VERDE: 1568 case CHIP_OLAND: 1569 case CHIP_HAINAN: 1570 case CHIP_BONAIRE: 1571 case CHIP_KABINI: 1572 case CHIP_KAVERI: 1573 case CHIP_HAWAII: 1574 case CHIP_MULLINS: 1575 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1576 if (!rdev->rlc_fw) 1577 rdev->pm.pm_method = PM_METHOD_PROFILE; 1578 else if ((rdev->family >= CHIP_RV770) && 1579 (!(rdev->flags & RADEON_IS_IGP)) && 1580 (!rdev->smc_fw)) 1581 rdev->pm.pm_method = PM_METHOD_PROFILE; 1582 else if (disable_dpm && (radeon_dpm == -1)) 1583 rdev->pm.pm_method = PM_METHOD_PROFILE; 1584 else if (radeon_dpm == 0) 1585 rdev->pm.pm_method = PM_METHOD_PROFILE; 1586 else 1587 rdev->pm.pm_method = PM_METHOD_DPM; 1588 break; 1589 default: 1590 /* default to profile method */ 1591 rdev->pm.pm_method = PM_METHOD_PROFILE; 1592 break; 1593 } 1594 1595 if (rdev->pm.pm_method == PM_METHOD_DPM) 1596 return radeon_pm_init_dpm(rdev); 1597 else 1598 return radeon_pm_init_old(rdev); 1599 } 1600 1601 int radeon_pm_late_init(struct radeon_device *rdev) 1602 { 1603 int ret = 0; 1604 1605 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1606 if (rdev->pm.dpm_enabled) { 1607 if (!rdev->pm.sysfs_initialized) { 1608 #if 0 1609 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1610 if (ret) 1611 DRM_ERROR("failed to create device file for dpm state\n"); 1612 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1613 if (ret) 1614 DRM_ERROR("failed to create device file for dpm state\n"); 1615 /* XXX: these are noops for dpm but are here for backwards compat */ 1616 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1617 if (ret) 1618 DRM_ERROR("failed to create device file for power profile\n"); 1619 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1620 if (ret) 1621 DRM_ERROR("failed to create device file for power method\n"); 1622 #endif 1623 rdev->pm.sysfs_initialized = true; 1624 } 1625 1626 mutex_lock(&rdev->pm.mutex); 1627 ret = radeon_dpm_late_enable(rdev); 1628 mutex_unlock(&rdev->pm.mutex); 1629 if (ret) { 1630 rdev->pm.dpm_enabled = false; 1631 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1632 } else { 1633 /* set the dpm state for PX since there won't be 1634 * a modeset to call this. 1635 */ 1636 radeon_pm_compute_clocks(rdev); 1637 } 1638 } 1639 } else { 1640 if ((rdev->pm.num_power_states > 1) && 1641 (!rdev->pm.sysfs_initialized)) { 1642 /* where's the best place to put these? */ 1643 #if 0 1644 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1645 if (ret) 1646 DRM_ERROR("failed to create device file for power profile\n"); 1647 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1648 if (ret) 1649 DRM_ERROR("failed to create device file for power method\n"); 1650 if (!ret) 1651 rdev->pm.sysfs_initialized = true; 1652 #endif 1653 } 1654 } 1655 return ret; 1656 } 1657 1658 static void radeon_pm_fini_old(struct radeon_device *rdev) 1659 { 1660 if (rdev->pm.num_power_states > 1) { 1661 mutex_lock(&rdev->pm.mutex); 1662 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1663 rdev->pm.profile = PM_PROFILE_DEFAULT; 1664 radeon_pm_update_profile(rdev); 1665 radeon_pm_set_clocks(rdev); 1666 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1667 /* reset default clocks */ 1668 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1669 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1670 radeon_pm_set_clocks(rdev); 1671 } 1672 mutex_unlock(&rdev->pm.mutex); 1673 1674 #ifdef DUMBBELL_WIP 1675 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1676 1677 device_remove_file(rdev->dev, &dev_attr_power_profile); 1678 device_remove_file(rdev->dev, &dev_attr_power_method); 1679 #endif /* DUMBBELL_WIP */ 1680 } 1681 1682 if (rdev->pm.power_state) { 1683 int i; 1684 for (i = 0; i < rdev->pm.num_power_states; ++i) { 1685 kfree(rdev->pm.power_state[i].clock_info); 1686 } 1687 kfree(rdev->pm.power_state); 1688 rdev->pm.power_state = NULL; 1689 rdev->pm.num_power_states = 0; 1690 } 1691 1692 radeon_hwmon_fini(rdev); 1693 } 1694 1695 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1696 { 1697 if (rdev->pm.num_power_states > 1) { 1698 mutex_lock(&rdev->pm.mutex); 1699 radeon_dpm_disable(rdev); 1700 mutex_unlock(&rdev->pm.mutex); 1701 1702 #ifdef TODO_DEVICE_FILE 1703 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1704 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1705 /* XXX backwards compat */ 1706 device_remove_file(rdev->dev, &dev_attr_power_profile); 1707 device_remove_file(rdev->dev, &dev_attr_power_method); 1708 #endif 1709 } 1710 radeon_dpm_fini(rdev); 1711 1712 /* prevents leaking 440 bytes on OLAND */ 1713 if (rdev->pm.power_state) { 1714 int i; 1715 for (i = 0; i < rdev->pm.num_power_states; ++i) { 1716 kfree(rdev->pm.power_state[i].clock_info); 1717 } 1718 kfree(rdev->pm.power_state); 1719 rdev->pm.power_state = NULL; 1720 rdev->pm.num_power_states = 0; 1721 } 1722 1723 radeon_hwmon_fini(rdev); 1724 } 1725 1726 void radeon_pm_fini(struct radeon_device *rdev) 1727 { 1728 if (rdev->pm.pm_method == PM_METHOD_DPM) 1729 radeon_pm_fini_dpm(rdev); 1730 else 1731 radeon_pm_fini_old(rdev); 1732 } 1733 1734 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1735 { 1736 struct drm_device *ddev = rdev->ddev; 1737 struct drm_crtc *crtc; 1738 struct radeon_crtc *radeon_crtc; 1739 1740 if (rdev->pm.num_power_states < 2) 1741 return; 1742 1743 mutex_lock(&rdev->pm.mutex); 1744 1745 rdev->pm.active_crtcs = 0; 1746 rdev->pm.active_crtc_count = 0; 1747 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1748 list_for_each_entry(crtc, 1749 &ddev->mode_config.crtc_list, head) { 1750 radeon_crtc = to_radeon_crtc(crtc); 1751 if (radeon_crtc->enabled) { 1752 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1753 rdev->pm.active_crtc_count++; 1754 } 1755 } 1756 } 1757 1758 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1759 radeon_pm_update_profile(rdev); 1760 radeon_pm_set_clocks(rdev); 1761 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1762 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1763 if (rdev->pm.active_crtc_count > 1) { 1764 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1765 #ifdef DUMBBELL_WIP 1766 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1767 #endif /* DUMBBELL_WIP */ 1768 1769 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1770 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1771 radeon_pm_get_dynpm_state(rdev); 1772 radeon_pm_set_clocks(rdev); 1773 1774 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1775 } 1776 } else if (rdev->pm.active_crtc_count == 1) { 1777 /* TODO: Increase clocks if needed for current mode */ 1778 1779 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1780 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1781 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1782 radeon_pm_get_dynpm_state(rdev); 1783 radeon_pm_set_clocks(rdev); 1784 1785 #ifdef DUMBBELL_WIP 1786 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1787 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1788 #endif /* DUMBBELL_WIP */ 1789 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1790 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1791 #ifdef DUMBBELL_WIP 1792 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1793 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1794 #endif /* DUMBBELL_WIP */ 1795 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1796 } 1797 } else { /* count == 0 */ 1798 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1799 #ifdef DUMBBELL_WIP 1800 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1801 #endif /* DUMBBELL_WIP */ 1802 1803 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1804 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1805 radeon_pm_get_dynpm_state(rdev); 1806 radeon_pm_set_clocks(rdev); 1807 } 1808 } 1809 } 1810 } 1811 1812 mutex_unlock(&rdev->pm.mutex); 1813 } 1814 1815 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1816 { 1817 struct drm_device *ddev = rdev->ddev; 1818 struct drm_crtc *crtc; 1819 struct radeon_crtc *radeon_crtc; 1820 1821 if (!rdev->pm.dpm_enabled) 1822 return; 1823 1824 mutex_lock(&rdev->pm.mutex); 1825 1826 /* update active crtc counts */ 1827 rdev->pm.dpm.new_active_crtcs = 0; 1828 rdev->pm.dpm.new_active_crtc_count = 0; 1829 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1830 list_for_each_entry(crtc, 1831 &ddev->mode_config.crtc_list, head) { 1832 radeon_crtc = to_radeon_crtc(crtc); 1833 if (crtc->enabled) { 1834 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1835 rdev->pm.dpm.new_active_crtc_count++; 1836 } 1837 } 1838 } 1839 1840 /* update battery/ac status */ 1841 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) 1842 rdev->pm.dpm.ac_power = true; 1843 else 1844 rdev->pm.dpm.ac_power = false; 1845 1846 radeon_dpm_change_power_state_locked(rdev); 1847 1848 mutex_unlock(&rdev->pm.mutex); 1849 1850 } 1851 1852 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1853 { 1854 if (rdev->pm.pm_method == PM_METHOD_DPM) 1855 radeon_pm_compute_clocks_dpm(rdev); 1856 else 1857 radeon_pm_compute_clocks_old(rdev); 1858 } 1859 1860 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1861 { 1862 int crtc, vpos, hpos, vbl_status; 1863 bool in_vbl = true; 1864 1865 /* Iterate over all active crtc's. All crtc's must be in vblank, 1866 * otherwise return in_vbl == false. 1867 */ 1868 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1869 if (rdev->pm.active_crtcs & (1 << crtc)) { 1870 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1871 crtc, 1872 USE_REAL_VBLANKSTART, 1873 &vpos, &hpos, NULL, NULL, 1874 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1875 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1876 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1877 in_vbl = false; 1878 } 1879 } 1880 1881 return in_vbl; 1882 } 1883 1884 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1885 { 1886 u32 stat_crtc = 0; 1887 bool in_vbl = radeon_pm_in_vbl(rdev); 1888 1889 if (in_vbl == false) 1890 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1891 finish ? "exit" : "entry"); 1892 return in_vbl; 1893 } 1894 1895 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1896 { 1897 struct radeon_device *rdev; 1898 int resched; 1899 rdev = container_of(work, struct radeon_device, 1900 pm.dynpm_idle_work.work); 1901 1902 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1903 mutex_lock(&rdev->pm.mutex); 1904 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1905 int not_processed = 0; 1906 int i; 1907 1908 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1909 struct radeon_ring *ring = &rdev->ring[i]; 1910 1911 if (ring->ready) { 1912 not_processed += radeon_fence_count_emitted(rdev, i); 1913 if (not_processed >= 3) 1914 break; 1915 } 1916 } 1917 1918 if (not_processed >= 3) { /* should upclock */ 1919 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1920 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1921 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1922 rdev->pm.dynpm_can_upclock) { 1923 rdev->pm.dynpm_planned_action = 1924 DYNPM_ACTION_UPCLOCK; 1925 rdev->pm.dynpm_action_timeout = jiffies + 1926 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1927 } 1928 } else if (not_processed == 0) { /* should downclock */ 1929 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1930 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1931 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1932 rdev->pm.dynpm_can_downclock) { 1933 rdev->pm.dynpm_planned_action = 1934 DYNPM_ACTION_DOWNCLOCK; 1935 rdev->pm.dynpm_action_timeout = jiffies + 1936 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1937 } 1938 } 1939 1940 /* Note, radeon_pm_set_clocks is called with static_switch set 1941 * to false since we want to wait for vbl to avoid flicker. 1942 */ 1943 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1944 jiffies > rdev->pm.dynpm_action_timeout) { 1945 radeon_pm_get_dynpm_state(rdev); 1946 radeon_pm_set_clocks(rdev); 1947 } 1948 1949 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1950 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1951 } 1952 mutex_unlock(&rdev->pm.mutex); 1953 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1954 } 1955 1956 /* 1957 * Debugfs info 1958 */ 1959 #if defined(CONFIG_DEBUG_FS) 1960 1961 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1962 { 1963 struct drm_info_node *node = (struct drm_info_node *) m->private; 1964 struct drm_device *dev = node->minor->dev; 1965 struct radeon_device *rdev = dev->dev_private; 1966 struct drm_device *ddev = rdev->ddev; 1967 1968 if ((rdev->flags & RADEON_IS_PX) && 1969 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1970 seq_printf(m, "PX asic powered off\n"); 1971 } else if (rdev->pm.dpm_enabled) { 1972 mutex_lock(&rdev->pm.mutex); 1973 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1974 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1975 else 1976 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1977 mutex_unlock(&rdev->pm.mutex); 1978 } else { 1979 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1980 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1981 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1982 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1983 else 1984 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1985 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1986 if (rdev->asic->pm.get_memory_clock) 1987 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1988 if (rdev->pm.current_vddc) 1989 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1990 if (rdev->asic->pm.get_pcie_lanes) 1991 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1992 } 1993 1994 return 0; 1995 } 1996 1997 static struct drm_info_list radeon_pm_info_list[] = { 1998 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1999 }; 2000 #endif 2001 2002 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 2003 { 2004 #if defined(CONFIG_DEBUG_FS) 2005 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 2006 #else 2007 return 0; 2008 #endif 2009 } 2010