1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <drm/drmP.h> 30 #include "radeon.h" 31 32 #ifdef DUMBBELL_WIP 33 /* 34 * Rings 35 * Most engines on the GPU are fed via ring buffers. Ring 36 * buffers are areas of GPU accessible memory that the host 37 * writes commands into and the GPU reads commands out of. 38 * There is a rptr (read pointer) that determines where the 39 * GPU is currently reading, and a wptr (write pointer) 40 * which determines where the host has written. When the 41 * pointers are equal, the ring is idle. When the host 42 * writes commands to the ring buffer, it increments the 43 * wptr. The GPU then starts fetching commands and executes 44 * them until the pointers are equal again. 45 */ 46 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); 47 #endif /* DUMBBELL_WIP */ 48 49 #if defined(DRM_DEBUG_CODE) && DRM_DEBUG_CODE != 0 50 /** 51 * radeon_ring_write - write a value to the ring 52 * 53 * @ring: radeon_ring structure holding ring information 54 * @v: dword (dw) value to write 55 * 56 * Write a value to the requested ring buffer (all asics). 57 */ 58 void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 59 { 60 #if DRM_DEBUG_CODE 61 if (ring->count_dw <= 0) { 62 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 63 } 64 #endif 65 ring->ring[ring->wptr++] = v; 66 ring->wptr &= ring->ptr_mask; 67 ring->count_dw--; 68 ring->ring_free_dw--; 69 } 70 #endif 71 72 /** 73 * radeon_ring_supports_scratch_reg - check if the ring supports 74 * writing to scratch registers 75 * 76 * @rdev: radeon_device pointer 77 * @ring: radeon_ring structure holding ring information 78 * 79 * Check if a specific ring supports writing to scratch registers (all asics). 80 * Returns true if the ring supports writing to scratch regs, false if not. 81 */ 82 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 83 struct radeon_ring *ring) 84 { 85 switch (ring->idx) { 86 case RADEON_RING_TYPE_GFX_INDEX: 87 case CAYMAN_RING_TYPE_CP1_INDEX: 88 case CAYMAN_RING_TYPE_CP2_INDEX: 89 return true; 90 default: 91 return false; 92 } 93 } 94 95 /** 96 * radeon_ring_free_size - update the free size 97 * 98 * @rdev: radeon_device pointer 99 * @ring: radeon_ring structure holding ring information 100 * 101 * Update the free dw slots in the ring buffer (all asics). 102 */ 103 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) 104 { 105 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); 106 107 /* This works because ring_size is a power of 2 */ 108 ring->ring_free_dw = rptr + (ring->ring_size / 4); 109 ring->ring_free_dw -= ring->wptr; 110 ring->ring_free_dw &= ring->ptr_mask; 111 if (!ring->ring_free_dw) { 112 /* this is an empty ring */ 113 ring->ring_free_dw = ring->ring_size / 4; 114 /* update lockup info to avoid false positive */ 115 radeon_ring_lockup_update(rdev, ring); 116 } 117 } 118 119 /** 120 * radeon_ring_alloc - allocate space on the ring buffer 121 * 122 * @rdev: radeon_device pointer 123 * @ring: radeon_ring structure holding ring information 124 * @ndw: number of dwords to allocate in the ring buffer 125 * 126 * Allocate @ndw dwords in the ring buffer (all asics). 127 * Returns 0 on success, error on failure. 128 */ 129 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 130 { 131 int r; 132 133 /* make sure we aren't trying to allocate more space than there is on the ring */ 134 if (ndw > (ring->ring_size / 4)) 135 return -ENOMEM; 136 /* Align requested size with padding so unlock_commit can 137 * pad safely */ 138 radeon_ring_free_size(rdev, ring); 139 ndw = (ndw + ring->align_mask) & ~ring->align_mask; 140 while (ndw > (ring->ring_free_dw - 1)) { 141 radeon_ring_free_size(rdev, ring); 142 if (ndw < ring->ring_free_dw) { 143 break; 144 } 145 r = radeon_fence_wait_next(rdev, ring->idx); 146 if (r) 147 return r; 148 } 149 ring->count_dw = ndw; 150 ring->wptr_old = ring->wptr; 151 return 0; 152 } 153 154 /** 155 * radeon_ring_lock - lock the ring and allocate space on it 156 * 157 * @rdev: radeon_device pointer 158 * @ring: radeon_ring structure holding ring information 159 * @ndw: number of dwords to allocate in the ring buffer 160 * 161 * Lock the ring and allocate @ndw dwords in the ring buffer 162 * (all asics). 163 * Returns 0 on success, error on failure. 164 */ 165 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 166 { 167 int r; 168 169 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE); 170 r = radeon_ring_alloc(rdev, ring, ndw); 171 if (r) { 172 lockmgr(&rdev->ring_lock, LK_RELEASE); 173 return r; 174 } 175 return 0; 176 } 177 178 /** 179 * radeon_ring_commit - tell the GPU to execute the new 180 * commands on the ring buffer 181 * 182 * @rdev: radeon_device pointer 183 * @ring: radeon_ring structure holding ring information 184 * @hdp_flush: Whether or not to perform an HDP cache flush 185 * 186 * Update the wptr (write pointer) to tell the GPU to 187 * execute new commands on the ring buffer (all asics). 188 */ 189 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, 190 bool hdp_flush) 191 { 192 /* If we are emitting the HDP flush via the ring buffer, we need to 193 * do it before padding. 194 */ 195 if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush) 196 rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); 197 /* We pad to match fetch size */ 198 while (ring->wptr & ring->align_mask) { 199 radeon_ring_write(ring, ring->nop); 200 } 201 mb(); 202 /* If we are emitting the HDP flush via MMIO, we need to do it after 203 * all CPU writes to VRAM finished. 204 */ 205 if (hdp_flush && rdev->asic->mmio_hdp_flush) 206 rdev->asic->mmio_hdp_flush(rdev); 207 radeon_ring_set_wptr(rdev, ring); 208 } 209 210 /** 211 * radeon_ring_unlock_commit - tell the GPU to execute the new 212 * commands on the ring buffer and unlock it 213 * 214 * @rdev: radeon_device pointer 215 * @ring: radeon_ring structure holding ring information 216 * @hdp_flush: Whether or not to perform an HDP cache flush 217 * 218 * Call radeon_ring_commit() then unlock the ring (all asics). 219 */ 220 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring, 221 bool hdp_flush) 222 { 223 radeon_ring_commit(rdev, ring, hdp_flush); 224 lockmgr(&rdev->ring_lock, LK_RELEASE); 225 } 226 227 /** 228 * radeon_ring_undo - reset the wptr 229 * 230 * @ring: radeon_ring structure holding ring information 231 * 232 * Reset the driver's copy of the wptr (all asics). 233 */ 234 void radeon_ring_undo(struct radeon_ring *ring) 235 { 236 ring->wptr = ring->wptr_old; 237 } 238 239 /** 240 * radeon_ring_unlock_undo - reset the wptr and unlock the ring 241 * 242 * @ring: radeon_ring structure holding ring information 243 * 244 * Call radeon_ring_undo() then unlock the ring (all asics). 245 */ 246 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) 247 { 248 radeon_ring_undo(ring); 249 lockmgr(&rdev->ring_lock, LK_RELEASE); 250 } 251 252 /** 253 * radeon_ring_lockup_update - update lockup variables 254 * 255 * @ring: radeon_ring structure holding ring information 256 * 257 * Update the last rptr value and timestamp (all asics). 258 */ 259 void radeon_ring_lockup_update(struct radeon_device *rdev, 260 struct radeon_ring *ring) 261 { 262 atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring)); 263 atomic64_set(&ring->last_activity, jiffies_64); 264 } 265 266 /** 267 * radeon_ring_test_lockup() - check if ring is lockedup by recording information 268 * @rdev: radeon device structure 269 * @ring: radeon_ring structure holding ring information 270 * 271 */ 272 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 273 { 274 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); 275 uint64_t last = atomic64_read(&ring->last_activity); 276 uint64_t elapsed; 277 278 if (rptr != atomic_read(&ring->last_rptr)) { 279 /* ring is still working, no lockup */ 280 radeon_ring_lockup_update(rdev, ring); 281 return false; 282 } 283 284 elapsed = jiffies_to_msecs(jiffies_64 - last); 285 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { 286 dev_err(rdev->dev, "ring %d stalled for more than %lumsec\n", 287 ring->idx, elapsed); 288 return true; 289 } 290 /* give a chance to the GPU ... */ 291 return false; 292 } 293 294 /** 295 * radeon_ring_backup - Back up the content of a ring 296 * 297 * @rdev: radeon_device pointer 298 * @ring: the ring we want to back up 299 * 300 * Saves all unprocessed commits from a ring, returns the number of dwords saved. 301 */ 302 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 303 uint32_t **data) 304 { 305 unsigned size, ptr, i; 306 307 /* just in case lock the ring */ 308 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE); 309 *data = NULL; 310 311 if (ring->ring_obj == NULL) { 312 lockmgr(&rdev->ring_lock, LK_RELEASE); 313 return 0; 314 } 315 316 /* it doesn't make sense to save anything if all fences are signaled */ 317 if (!radeon_fence_count_emitted(rdev, ring->idx)) { 318 lockmgr(&rdev->ring_lock, LK_RELEASE); 319 return 0; 320 } 321 322 /* calculate the number of dw on the ring */ 323 if (ring->rptr_save_reg) 324 ptr = RREG32(ring->rptr_save_reg); 325 else if (rdev->wb.enabled) 326 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); 327 else { 328 /* no way to read back the next rptr */ 329 lockmgr(&rdev->ring_lock, LK_RELEASE); 330 return 0; 331 } 332 333 size = ring->wptr + (ring->ring_size / 4); 334 size -= ptr; 335 size &= ring->ptr_mask; 336 if (size == 0) { 337 lockmgr(&rdev->ring_lock, LK_RELEASE); 338 return 0; 339 } 340 341 /* and then save the content of the ring */ 342 *data = kmalloc(size * sizeof(uint32_t), M_DRM, M_WAITOK); 343 if (!*data) { 344 lockmgr(&rdev->ring_lock, LK_RELEASE); 345 return 0; 346 } 347 for (i = 0; i < size; ++i) { 348 (*data)[i] = ring->ring[ptr++]; 349 ptr &= ring->ptr_mask; 350 } 351 352 lockmgr(&rdev->ring_lock, LK_RELEASE); 353 return size; 354 } 355 356 /** 357 * radeon_ring_restore - append saved commands to the ring again 358 * 359 * @rdev: radeon_device pointer 360 * @ring: ring to append commands to 361 * @size: number of dwords we want to write 362 * @data: saved commands 363 * 364 * Allocates space on the ring and restore the previously saved commands. 365 */ 366 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 367 unsigned size, uint32_t *data) 368 { 369 int i, r; 370 371 if (!size || !data) 372 return 0; 373 374 /* restore the saved ring content */ 375 r = radeon_ring_lock(rdev, ring, size); 376 if (r) 377 return r; 378 379 for (i = 0; i < size; ++i) { 380 radeon_ring_write(ring, data[i]); 381 } 382 383 radeon_ring_unlock_commit(rdev, ring, false); 384 kfree(data); 385 return 0; 386 } 387 388 /** 389 * radeon_ring_init - init driver ring struct. 390 * 391 * @rdev: radeon_device pointer 392 * @ring: radeon_ring structure holding ring information 393 * @ring_size: size of the ring 394 * @rptr_offs: offset of the rptr writeback location in the WB buffer 395 * @nop: nop packet for this ring 396 * 397 * Initialize the driver information for the selected ring (all asics). 398 * Returns 0 on success, error on failure. 399 */ 400 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, 401 unsigned rptr_offs, u32 nop) 402 { 403 int r; 404 void *ring_ptr; 405 406 ring->ring_size = ring_size; 407 ring->rptr_offs = rptr_offs; 408 ring->nop = nop; 409 /* Allocate ring buffer */ 410 if (ring->ring_obj == NULL) { 411 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, 412 RADEON_GEM_DOMAIN_GTT, 0, 413 NULL, &ring->ring_obj); 414 if (r) { 415 dev_err(rdev->dev, "(%d) ring create failed\n", r); 416 return r; 417 } 418 r = radeon_bo_reserve(ring->ring_obj, false); 419 if (unlikely(r != 0)) { 420 radeon_bo_unref(&ring->ring_obj); 421 return r; 422 } 423 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, 424 &ring->gpu_addr); 425 if (r) { 426 radeon_bo_unreserve(ring->ring_obj); 427 radeon_bo_unref(&ring->ring_obj); 428 dev_err(rdev->dev, "(%d) ring pin failed\n", r); 429 return r; 430 } 431 ring_ptr = &ring->ring; 432 r = radeon_bo_kmap(ring->ring_obj, 433 ring_ptr); 434 radeon_bo_unreserve(ring->ring_obj); 435 if (r) { 436 dev_err(rdev->dev, "(%d) ring map failed\n", r); 437 radeon_bo_unref(&ring->ring_obj); 438 return r; 439 } 440 } 441 ring->ptr_mask = (ring->ring_size / 4) - 1; 442 ring->ring_free_dw = ring->ring_size / 4; 443 if (rdev->wb.enabled) { 444 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); 445 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; 446 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; 447 } 448 #ifdef DUMBBELL_WIP 449 if (radeon_debugfs_ring_init(rdev, ring)) { 450 DRM_ERROR("Failed to register debugfs file for rings !\n"); 451 } 452 #endif /* DUMBBELL_WIP */ 453 radeon_ring_lockup_update(rdev, ring); 454 return 0; 455 } 456 457 /** 458 * radeon_ring_fini - tear down the driver ring struct. 459 * 460 * @rdev: radeon_device pointer 461 * @ring: radeon_ring structure holding ring information 462 * 463 * Tear down the driver information for the selected ring (all asics). 464 */ 465 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) 466 { 467 int r; 468 struct radeon_bo *ring_obj; 469 470 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE); 471 ring_obj = ring->ring_obj; 472 ring->ready = false; 473 ring->ring = NULL; 474 ring->ring_obj = NULL; 475 lockmgr(&rdev->ring_lock, LK_RELEASE); 476 477 if (ring_obj) { 478 r = radeon_bo_reserve(ring_obj, false); 479 if (likely(r == 0)) { 480 radeon_bo_kunmap(ring_obj); 481 radeon_bo_unpin(ring_obj); 482 radeon_bo_unreserve(ring_obj); 483 } 484 radeon_bo_unref(&ring_obj); 485 } 486 } 487 488 /* 489 * Debugfs info 490 */ 491 #if defined(CONFIG_DEBUG_FS) 492 493 static int radeon_debugfs_ring_info(struct seq_file *m, void *data) 494 { 495 struct drm_info_node *node = (struct drm_info_node *) m->private; 496 struct drm_device *dev = node->minor->dev; 497 struct radeon_device *rdev = dev->dev_private; 498 int ridx = *(int*)node->info_ent->data; 499 struct radeon_ring *ring = &rdev->ring[ridx]; 500 501 uint32_t rptr, wptr, rptr_next; 502 unsigned count, i, j; 503 504 radeon_ring_free_size(rdev, ring); 505 count = (ring->ring_size / 4) - ring->ring_free_dw; 506 507 wptr = radeon_ring_get_wptr(rdev, ring); 508 seq_printf(m, "wptr: 0x%08x [%5d]\n", 509 wptr, wptr); 510 511 rptr = radeon_ring_get_rptr(rdev, ring); 512 seq_printf(m, "rptr: 0x%08x [%5d]\n", 513 rptr, rptr); 514 515 if (ring->rptr_save_reg) { 516 rptr_next = RREG32(ring->rptr_save_reg); 517 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n", 518 ring->rptr_save_reg, rptr_next, rptr_next); 519 } else 520 rptr_next = ~0; 521 522 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", 523 ring->wptr, ring->wptr); 524 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", 525 ring->last_semaphore_signal_addr); 526 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", 527 ring->last_semaphore_wait_addr); 528 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 529 seq_printf(m, "%u dwords in ring\n", count); 530 531 if (!ring->ready) 532 return 0; 533 534 /* print 8 dw before current rptr as often it's the last executed 535 * packet that is the root issue 536 */ 537 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; 538 for (j = 0; j <= (count + 32); j++) { 539 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]); 540 if (rptr == i) 541 seq_puts(m, " *"); 542 if (rptr_next == i) 543 seq_puts(m, " #"); 544 seq_puts(m, "\n"); 545 i = (i + 1) & ring->ptr_mask; 546 } 547 return 0; 548 } 549 550 static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; 551 static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; 552 static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; 553 static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; 554 static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; 555 static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; 556 static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX; 557 static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX; 558 559 static struct drm_info_list radeon_debugfs_ring_info_list[] = { 560 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, 561 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, 562 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, 563 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, 564 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, 565 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, 566 {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index}, 567 {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index}, 568 }; 569 570 #endif 571 572 #ifdef DUMBBELL_WIP 573 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) 574 { 575 #if defined(CONFIG_DEBUG_FS) 576 unsigned i; 577 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { 578 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; 579 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; 580 unsigned r; 581 582 if (&rdev->ring[ridx] != ring) 583 continue; 584 585 r = radeon_debugfs_add_files(rdev, info, 1); 586 if (r) 587 return r; 588 } 589 #endif 590 return 0; 591 } 592 #endif /* DUMBBELL_WIP */ 593