1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <drm/drmP.h> 30 #include "radeon.h" 31 32 #ifdef DUMBBELL_WIP 33 /* 34 * Rings 35 * Most engines on the GPU are fed via ring buffers. Ring 36 * buffers are areas of GPU accessible memory that the host 37 * writes commands into and the GPU reads commands out of. 38 * There is a rptr (read pointer) that determines where the 39 * GPU is currently reading, and a wptr (write pointer) 40 * which determines where the host has written. When the 41 * pointers are equal, the ring is idle. When the host 42 * writes commands to the ring buffer, it increments the 43 * wptr. The GPU then starts fetching commands and executes 44 * them until the pointers are equal again. 45 */ 46 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); 47 #endif /* DUMBBELL_WIP */ 48 49 /** 50 * radeon_ring_supports_scratch_reg - check if the ring supports 51 * writing to scratch registers 52 * 53 * @rdev: radeon_device pointer 54 * @ring: radeon_ring structure holding ring information 55 * 56 * Check if a specific ring supports writing to scratch registers (all asics). 57 * Returns true if the ring supports writing to scratch regs, false if not. 58 */ 59 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 60 struct radeon_ring *ring) 61 { 62 switch (ring->idx) { 63 case RADEON_RING_TYPE_GFX_INDEX: 64 case CAYMAN_RING_TYPE_CP1_INDEX: 65 case CAYMAN_RING_TYPE_CP2_INDEX: 66 return true; 67 default: 68 return false; 69 } 70 } 71 72 /** 73 * radeon_ring_free_size - update the free size 74 * 75 * @rdev: radeon_device pointer 76 * @ring: radeon_ring structure holding ring information 77 * 78 * Update the free dw slots in the ring buffer (all asics). 79 */ 80 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) 81 { 82 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); 83 84 /* This works because ring_size is a power of 2 */ 85 ring->ring_free_dw = rptr + (ring->ring_size / 4); 86 ring->ring_free_dw -= ring->wptr; 87 ring->ring_free_dw &= ring->ptr_mask; 88 if (!ring->ring_free_dw) { 89 /* this is an empty ring */ 90 ring->ring_free_dw = ring->ring_size / 4; 91 /* update lockup info to avoid false positive */ 92 radeon_ring_lockup_update(rdev, ring); 93 } 94 } 95 96 /** 97 * radeon_ring_alloc - allocate space on the ring buffer 98 * 99 * @rdev: radeon_device pointer 100 * @ring: radeon_ring structure holding ring information 101 * @ndw: number of dwords to allocate in the ring buffer 102 * 103 * Allocate @ndw dwords in the ring buffer (all asics). 104 * Returns 0 on success, error on failure. 105 */ 106 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 107 { 108 int r; 109 110 /* make sure we aren't trying to allocate more space than there is on the ring */ 111 if (ndw > (ring->ring_size / 4)) 112 return -ENOMEM; 113 /* Align requested size with padding so unlock_commit can 114 * pad safely */ 115 radeon_ring_free_size(rdev, ring); 116 ndw = (ndw + ring->align_mask) & ~ring->align_mask; 117 while (ndw > (ring->ring_free_dw - 1)) { 118 radeon_ring_free_size(rdev, ring); 119 if (ndw < ring->ring_free_dw) { 120 break; 121 } 122 r = radeon_fence_wait_next(rdev, ring->idx); 123 if (r) 124 return r; 125 } 126 ring->count_dw = ndw; 127 ring->wptr_old = ring->wptr; 128 return 0; 129 } 130 131 /** 132 * radeon_ring_lock - lock the ring and allocate space on it 133 * 134 * @rdev: radeon_device pointer 135 * @ring: radeon_ring structure holding ring information 136 * @ndw: number of dwords to allocate in the ring buffer 137 * 138 * Lock the ring and allocate @ndw dwords in the ring buffer 139 * (all asics). 140 * Returns 0 on success, error on failure. 141 */ 142 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 143 { 144 int r; 145 146 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE); 147 r = radeon_ring_alloc(rdev, ring, ndw); 148 if (r) { 149 lockmgr(&rdev->ring_lock, LK_RELEASE); 150 return r; 151 } 152 return 0; 153 } 154 155 /** 156 * radeon_ring_commit - tell the GPU to execute the new 157 * commands on the ring buffer 158 * 159 * @rdev: radeon_device pointer 160 * @ring: radeon_ring structure holding ring information 161 * @hdp_flush: Whether or not to perform an HDP cache flush 162 * 163 * Update the wptr (write pointer) to tell the GPU to 164 * execute new commands on the ring buffer (all asics). 165 */ 166 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, 167 bool hdp_flush) 168 { 169 /* If we are emitting the HDP flush via the ring buffer, we need to 170 * do it before padding. 171 */ 172 if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush) 173 rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); 174 /* We pad to match fetch size */ 175 while (ring->wptr & ring->align_mask) { 176 radeon_ring_write(ring, ring->nop); 177 } 178 mb(); 179 /* If we are emitting the HDP flush via MMIO, we need to do it after 180 * all CPU writes to VRAM finished. 181 */ 182 if (hdp_flush && rdev->asic->mmio_hdp_flush) 183 rdev->asic->mmio_hdp_flush(rdev); 184 radeon_ring_set_wptr(rdev, ring); 185 } 186 187 /** 188 * radeon_ring_unlock_commit - tell the GPU to execute the new 189 * commands on the ring buffer and unlock it 190 * 191 * @rdev: radeon_device pointer 192 * @ring: radeon_ring structure holding ring information 193 * @hdp_flush: Whether or not to perform an HDP cache flush 194 * 195 * Call radeon_ring_commit() then unlock the ring (all asics). 196 */ 197 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring, 198 bool hdp_flush) 199 { 200 radeon_ring_commit(rdev, ring, hdp_flush); 201 lockmgr(&rdev->ring_lock, LK_RELEASE); 202 } 203 204 /** 205 * radeon_ring_undo - reset the wptr 206 * 207 * @ring: radeon_ring structure holding ring information 208 * 209 * Reset the driver's copy of the wptr (all asics). 210 */ 211 void radeon_ring_undo(struct radeon_ring *ring) 212 { 213 ring->wptr = ring->wptr_old; 214 } 215 216 /** 217 * radeon_ring_unlock_undo - reset the wptr and unlock the ring 218 * 219 * @ring: radeon_ring structure holding ring information 220 * 221 * Call radeon_ring_undo() then unlock the ring (all asics). 222 */ 223 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) 224 { 225 radeon_ring_undo(ring); 226 lockmgr(&rdev->ring_lock, LK_RELEASE); 227 } 228 229 /** 230 * radeon_ring_lockup_update - update lockup variables 231 * 232 * @ring: radeon_ring structure holding ring information 233 * 234 * Update the last rptr value and timestamp (all asics). 235 */ 236 void radeon_ring_lockup_update(struct radeon_device *rdev, 237 struct radeon_ring *ring) 238 { 239 atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring)); 240 atomic64_set(&ring->last_activity, jiffies_64); 241 } 242 243 /** 244 * radeon_ring_test_lockup() - check if ring is lockedup by recording information 245 * @rdev: radeon device structure 246 * @ring: radeon_ring structure holding ring information 247 * 248 */ 249 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 250 { 251 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); 252 uint64_t last = atomic64_read(&ring->last_activity); 253 uint64_t elapsed; 254 255 if (rptr != atomic_read(&ring->last_rptr)) { 256 /* ring is still working, no lockup */ 257 radeon_ring_lockup_update(rdev, ring); 258 return false; 259 } 260 261 elapsed = jiffies_to_msecs(jiffies_64 - last); 262 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { 263 dev_err(rdev->dev, "ring %d stalled for more than %lumsec\n", 264 ring->idx, elapsed); 265 return true; 266 } 267 /* give a chance to the GPU ... */ 268 return false; 269 } 270 271 /** 272 * radeon_ring_backup - Back up the content of a ring 273 * 274 * @rdev: radeon_device pointer 275 * @ring: the ring we want to back up 276 * 277 * Saves all unprocessed commits from a ring, returns the number of dwords saved. 278 */ 279 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 280 uint32_t **data) 281 { 282 unsigned size, ptr, i; 283 284 /* just in case lock the ring */ 285 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE); 286 *data = NULL; 287 288 if (ring->ring_obj == NULL) { 289 lockmgr(&rdev->ring_lock, LK_RELEASE); 290 return 0; 291 } 292 293 /* it doesn't make sense to save anything if all fences are signaled */ 294 if (!radeon_fence_count_emitted(rdev, ring->idx)) { 295 lockmgr(&rdev->ring_lock, LK_RELEASE); 296 return 0; 297 } 298 299 /* calculate the number of dw on the ring */ 300 if (ring->rptr_save_reg) 301 ptr = RREG32(ring->rptr_save_reg); 302 else if (rdev->wb.enabled) 303 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); 304 else { 305 /* no way to read back the next rptr */ 306 lockmgr(&rdev->ring_lock, LK_RELEASE); 307 return 0; 308 } 309 310 size = ring->wptr + (ring->ring_size / 4); 311 size -= ptr; 312 size &= ring->ptr_mask; 313 if (size == 0) { 314 lockmgr(&rdev->ring_lock, LK_RELEASE); 315 return 0; 316 } 317 318 /* and then save the content of the ring */ 319 *data = drm_malloc_ab(size, sizeof(uint32_t)); 320 if (!*data) { 321 lockmgr(&rdev->ring_lock, LK_RELEASE); 322 return 0; 323 } 324 for (i = 0; i < size; ++i) { 325 (*data)[i] = ring->ring[ptr++]; 326 ptr &= ring->ptr_mask; 327 } 328 329 lockmgr(&rdev->ring_lock, LK_RELEASE); 330 return size; 331 } 332 333 /** 334 * radeon_ring_restore - append saved commands to the ring again 335 * 336 * @rdev: radeon_device pointer 337 * @ring: ring to append commands to 338 * @size: number of dwords we want to write 339 * @data: saved commands 340 * 341 * Allocates space on the ring and restore the previously saved commands. 342 */ 343 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 344 unsigned size, uint32_t *data) 345 { 346 int i, r; 347 348 if (!size || !data) 349 return 0; 350 351 /* restore the saved ring content */ 352 r = radeon_ring_lock(rdev, ring, size); 353 if (r) 354 return r; 355 356 for (i = 0; i < size; ++i) { 357 radeon_ring_write(ring, data[i]); 358 } 359 360 radeon_ring_unlock_commit(rdev, ring, false); 361 drm_free_large(data); 362 return 0; 363 } 364 365 /** 366 * radeon_ring_init - init driver ring struct. 367 * 368 * @rdev: radeon_device pointer 369 * @ring: radeon_ring structure holding ring information 370 * @ring_size: size of the ring 371 * @rptr_offs: offset of the rptr writeback location in the WB buffer 372 * @nop: nop packet for this ring 373 * 374 * Initialize the driver information for the selected ring (all asics). 375 * Returns 0 on success, error on failure. 376 */ 377 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, 378 unsigned rptr_offs, u32 nop) 379 { 380 int r; 381 void *ring_ptr; 382 383 ring->ring_size = ring_size; 384 ring->rptr_offs = rptr_offs; 385 ring->nop = nop; 386 /* Allocate ring buffer */ 387 if (ring->ring_obj == NULL) { 388 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, 389 RADEON_GEM_DOMAIN_GTT, 0, 390 NULL, &ring->ring_obj); 391 if (r) { 392 dev_err(rdev->dev, "(%d) ring create failed\n", r); 393 return r; 394 } 395 r = radeon_bo_reserve(ring->ring_obj, false); 396 if (unlikely(r != 0)) { 397 radeon_bo_unref(&ring->ring_obj); 398 return r; 399 } 400 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, 401 (u64 *)&ring->gpu_addr); 402 if (r) { 403 radeon_bo_unreserve(ring->ring_obj); 404 radeon_bo_unref(&ring->ring_obj); 405 dev_err(rdev->dev, "(%d) ring pin failed\n", r); 406 return r; 407 } 408 ring_ptr = &ring->ring; 409 r = radeon_bo_kmap(ring->ring_obj, 410 ring_ptr); 411 radeon_bo_unreserve(ring->ring_obj); 412 if (r) { 413 dev_err(rdev->dev, "(%d) ring map failed\n", r); 414 radeon_bo_unref(&ring->ring_obj); 415 return r; 416 } 417 } 418 ring->ptr_mask = (ring->ring_size / 4) - 1; 419 ring->ring_free_dw = ring->ring_size / 4; 420 if (rdev->wb.enabled) { 421 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); 422 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; 423 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; 424 } 425 #ifdef DUMBBELL_WIP 426 if (radeon_debugfs_ring_init(rdev, ring)) { 427 DRM_ERROR("Failed to register debugfs file for rings !\n"); 428 } 429 #endif /* DUMBBELL_WIP */ 430 radeon_ring_lockup_update(rdev, ring); 431 return 0; 432 } 433 434 /** 435 * radeon_ring_fini - tear down the driver ring struct. 436 * 437 * @rdev: radeon_device pointer 438 * @ring: radeon_ring structure holding ring information 439 * 440 * Tear down the driver information for the selected ring (all asics). 441 */ 442 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) 443 { 444 int r; 445 struct radeon_bo *ring_obj; 446 447 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE); 448 ring_obj = ring->ring_obj; 449 ring->ready = false; 450 ring->ring = NULL; 451 ring->ring_obj = NULL; 452 lockmgr(&rdev->ring_lock, LK_RELEASE); 453 454 if (ring_obj) { 455 r = radeon_bo_reserve(ring_obj, false); 456 if (likely(r == 0)) { 457 radeon_bo_kunmap(ring_obj); 458 radeon_bo_unpin(ring_obj); 459 radeon_bo_unreserve(ring_obj); 460 } 461 radeon_bo_unref(&ring_obj); 462 } 463 } 464 465 /* 466 * Debugfs info 467 */ 468 #if defined(CONFIG_DEBUG_FS) 469 470 static int radeon_debugfs_ring_info(struct seq_file *m, void *data) 471 { 472 struct drm_info_node *node = (struct drm_info_node *) m->private; 473 struct drm_device *dev = node->minor->dev; 474 struct radeon_device *rdev = dev->dev_private; 475 int ridx = *(int*)node->info_ent->data; 476 struct radeon_ring *ring = &rdev->ring[ridx]; 477 478 uint32_t rptr, wptr, rptr_next; 479 unsigned count, i, j; 480 481 radeon_ring_free_size(rdev, ring); 482 count = (ring->ring_size / 4) - ring->ring_free_dw; 483 484 wptr = radeon_ring_get_wptr(rdev, ring); 485 seq_printf(m, "wptr: 0x%08x [%5d]\n", 486 wptr, wptr); 487 488 rptr = radeon_ring_get_rptr(rdev, ring); 489 seq_printf(m, "rptr: 0x%08x [%5d]\n", 490 rptr, rptr); 491 492 if (ring->rptr_save_reg) { 493 rptr_next = RREG32(ring->rptr_save_reg); 494 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n", 495 ring->rptr_save_reg, rptr_next, rptr_next); 496 } else 497 rptr_next = ~0; 498 499 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", 500 ring->wptr, ring->wptr); 501 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", 502 ring->last_semaphore_signal_addr); 503 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", 504 ring->last_semaphore_wait_addr); 505 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 506 seq_printf(m, "%u dwords in ring\n", count); 507 508 if (!ring->ready) 509 return 0; 510 511 /* print 8 dw before current rptr as often it's the last executed 512 * packet that is the root issue 513 */ 514 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; 515 for (j = 0; j <= (count + 32); j++) { 516 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]); 517 if (rptr == i) 518 seq_puts(m, " *"); 519 if (rptr_next == i) 520 seq_puts(m, " #"); 521 seq_puts(m, "\n"); 522 i = (i + 1) & ring->ptr_mask; 523 } 524 return 0; 525 } 526 527 static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; 528 static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; 529 static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; 530 static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; 531 static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; 532 static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; 533 static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX; 534 static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX; 535 536 static struct drm_info_list radeon_debugfs_ring_info_list[] = { 537 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, 538 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, 539 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, 540 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, 541 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, 542 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, 543 {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index}, 544 {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index}, 545 }; 546 547 #endif 548 549 #ifdef DUMBBELL_WIP 550 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) 551 { 552 #if defined(CONFIG_DEBUG_FS) 553 unsigned i; 554 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { 555 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; 556 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; 557 unsigned r; 558 559 if (&rdev->ring[ridx] != ring) 560 continue; 561 562 r = radeon_debugfs_add_files(rdev, info, 1); 563 if (r) 564 return r; 565 } 566 #endif 567 return 0; 568 } 569 #endif /* DUMBBELL_WIP */ 570