1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 * 32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $ 33 */ 34 35 #include <drm/ttm/ttm_bo_api.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_placement.h> 38 #include <drm/ttm/ttm_module.h> 39 #include <drm/ttm/ttm_page_alloc.h> 40 #include <drm/drmP.h> 41 #include <uapi_drm/radeon_drm.h> 42 #include <linux/seq_file.h> 43 #include <linux/slab.h> 44 #include "radeon_reg.h" 45 #include "radeon.h" 46 47 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 48 49 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 50 51 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 52 { 53 struct radeon_mman *mman; 54 struct radeon_device *rdev; 55 56 mman = container_of(bdev, struct radeon_mman, bdev); 57 rdev = container_of(mman, struct radeon_device, mman); 58 return rdev; 59 } 60 61 62 /* 63 * Global memory. 64 */ 65 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 66 { 67 return ttm_mem_global_init(ref->object); 68 } 69 70 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 71 { 72 ttm_mem_global_release(ref->object); 73 } 74 75 static int radeon_ttm_global_init(struct radeon_device *rdev) 76 { 77 struct drm_global_reference *global_ref; 78 int r; 79 80 rdev->mman.mem_global_referenced = false; 81 global_ref = &rdev->mman.mem_global_ref; 82 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 83 global_ref->size = sizeof(struct ttm_mem_global); 84 global_ref->init = &radeon_ttm_mem_global_init; 85 global_ref->release = &radeon_ttm_mem_global_release; 86 r = drm_global_item_ref(global_ref); 87 if (r != 0) { 88 DRM_ERROR("Failed setting up TTM memory accounting " 89 "subsystem.\n"); 90 return r; 91 } 92 93 rdev->mman.bo_global_ref.mem_glob = 94 rdev->mman.mem_global_ref.object; 95 global_ref = &rdev->mman.bo_global_ref.ref; 96 global_ref->global_type = DRM_GLOBAL_TTM_BO; 97 global_ref->size = sizeof(struct ttm_bo_global); 98 global_ref->init = &ttm_bo_global_init; 99 global_ref->release = &ttm_bo_global_release; 100 r = drm_global_item_ref(global_ref); 101 if (r != 0) { 102 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 103 drm_global_item_unref(&rdev->mman.mem_global_ref); 104 return r; 105 } 106 107 rdev->mman.mem_global_referenced = true; 108 return 0; 109 } 110 111 static void radeon_ttm_global_fini(struct radeon_device *rdev) 112 { 113 if (rdev->mman.mem_global_referenced) { 114 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 115 drm_global_item_unref(&rdev->mman.mem_global_ref); 116 rdev->mman.mem_global_referenced = false; 117 } 118 } 119 120 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 121 { 122 return 0; 123 } 124 125 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 126 struct ttm_mem_type_manager *man) 127 { 128 struct radeon_device *rdev; 129 130 rdev = radeon_get_rdev(bdev); 131 132 switch (type) { 133 case TTM_PL_SYSTEM: 134 /* System memory */ 135 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 136 man->available_caching = TTM_PL_MASK_CACHING; 137 man->default_caching = TTM_PL_FLAG_CACHED; 138 break; 139 case TTM_PL_TT: 140 man->func = &ttm_bo_manager_func; 141 man->gpu_offset = rdev->mc.gtt_start; 142 man->available_caching = TTM_PL_MASK_CACHING; 143 man->default_caching = TTM_PL_FLAG_CACHED; 144 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 145 #if __OS_HAS_AGP 146 if (rdev->flags & RADEON_IS_AGP) { 147 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { 148 DRM_ERROR("AGP is not enabled for memory type %u\n", 149 (unsigned)type); 150 return -EINVAL; 151 } 152 if (!rdev->ddev->agp->cant_use_aperture) 153 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 154 man->available_caching = TTM_PL_FLAG_UNCACHED | 155 TTM_PL_FLAG_WC; 156 man->default_caching = TTM_PL_FLAG_WC; 157 } 158 #endif 159 break; 160 case TTM_PL_VRAM: 161 /* "On-card" video ram */ 162 man->func = &ttm_bo_manager_func; 163 man->gpu_offset = rdev->mc.vram_start; 164 man->flags = TTM_MEMTYPE_FLAG_FIXED | 165 TTM_MEMTYPE_FLAG_MAPPABLE; 166 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 167 man->default_caching = TTM_PL_FLAG_WC; 168 break; 169 default: 170 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 171 return -EINVAL; 172 } 173 return 0; 174 } 175 176 static void radeon_evict_flags(struct ttm_buffer_object *bo, 177 struct ttm_placement *placement) 178 { 179 struct radeon_bo *rbo; 180 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 181 182 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 183 placement->fpfn = 0; 184 placement->lpfn = 0; 185 placement->placement = &placements; 186 placement->busy_placement = &placements; 187 placement->num_placement = 1; 188 placement->num_busy_placement = 1; 189 return; 190 } 191 rbo = container_of(bo, struct radeon_bo, tbo); 192 switch (bo->mem.mem_type) { 193 case TTM_PL_VRAM: 194 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) 195 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 196 else 197 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 198 break; 199 case TTM_PL_TT: 200 default: 201 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 202 } 203 *placement = rbo->placement; 204 } 205 206 static int radeon_verify_access(struct ttm_buffer_object *bo) 207 { 208 return 0; 209 } 210 211 static void radeon_move_null(struct ttm_buffer_object *bo, 212 struct ttm_mem_reg *new_mem) 213 { 214 struct ttm_mem_reg *old_mem = &bo->mem; 215 216 BUG_ON(old_mem->mm_node != NULL); 217 *old_mem = *new_mem; 218 new_mem->mm_node = NULL; 219 } 220 221 static int radeon_move_blit(struct ttm_buffer_object *bo, 222 bool evict, bool no_wait_gpu, 223 struct ttm_mem_reg *new_mem, 224 struct ttm_mem_reg *old_mem) 225 { 226 struct radeon_device *rdev; 227 uint64_t old_start, new_start; 228 struct radeon_fence *fence; 229 int r, ridx; 230 231 rdev = radeon_get_rdev(bo->bdev); 232 ridx = radeon_copy_ring_index(rdev); 233 old_start = old_mem->start << PAGE_SHIFT; 234 new_start = new_mem->start << PAGE_SHIFT; 235 236 switch (old_mem->mem_type) { 237 case TTM_PL_VRAM: 238 old_start += rdev->mc.vram_start; 239 break; 240 case TTM_PL_TT: 241 old_start += rdev->mc.gtt_start; 242 break; 243 default: 244 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 245 return -EINVAL; 246 } 247 switch (new_mem->mem_type) { 248 case TTM_PL_VRAM: 249 new_start += rdev->mc.vram_start; 250 break; 251 case TTM_PL_TT: 252 new_start += rdev->mc.gtt_start; 253 break; 254 default: 255 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 256 return -EINVAL; 257 } 258 if (!rdev->ring[ridx].ready) { 259 DRM_ERROR("Trying to move memory with ring turned off.\n"); 260 return -EINVAL; 261 } 262 263 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 264 265 /* sync other rings */ 266 fence = bo->sync_obj; 267 r = radeon_copy(rdev, old_start, new_start, 268 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ 269 &fence); 270 /* FIXME: handle copy error */ 271 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, 272 evict, no_wait_gpu, new_mem); 273 radeon_fence_unref(&fence); 274 return r; 275 } 276 277 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 278 bool evict, bool interruptible, 279 bool no_wait_gpu, 280 struct ttm_mem_reg *new_mem) 281 { 282 struct radeon_device *rdev; 283 struct ttm_mem_reg *old_mem = &bo->mem; 284 struct ttm_mem_reg tmp_mem; 285 u32 placements; 286 struct ttm_placement placement; 287 int r; 288 289 rdev = radeon_get_rdev(bo->bdev); 290 tmp_mem = *new_mem; 291 tmp_mem.mm_node = NULL; 292 placement.fpfn = 0; 293 placement.lpfn = 0; 294 placement.num_placement = 1; 295 placement.placement = &placements; 296 placement.num_busy_placement = 1; 297 placement.busy_placement = &placements; 298 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 299 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 300 interruptible, no_wait_gpu); 301 if (unlikely(r)) { 302 return r; 303 } 304 305 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 306 if (unlikely(r)) { 307 goto out_cleanup; 308 } 309 310 r = ttm_tt_bind(bo->ttm, &tmp_mem); 311 if (unlikely(r)) { 312 goto out_cleanup; 313 } 314 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 315 if (unlikely(r)) { 316 goto out_cleanup; 317 } 318 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 319 out_cleanup: 320 ttm_bo_mem_put(bo, &tmp_mem); 321 return r; 322 } 323 324 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 325 bool evict, bool interruptible, 326 bool no_wait_gpu, 327 struct ttm_mem_reg *new_mem) 328 { 329 struct radeon_device *rdev; 330 struct ttm_mem_reg *old_mem = &bo->mem; 331 struct ttm_mem_reg tmp_mem; 332 struct ttm_placement placement; 333 u32 placements; 334 int r; 335 336 rdev = radeon_get_rdev(bo->bdev); 337 tmp_mem = *new_mem; 338 tmp_mem.mm_node = NULL; 339 placement.fpfn = 0; 340 placement.lpfn = 0; 341 placement.num_placement = 1; 342 placement.placement = &placements; 343 placement.num_busy_placement = 1; 344 placement.busy_placement = &placements; 345 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 346 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 347 interruptible, no_wait_gpu); 348 if (unlikely(r)) { 349 return r; 350 } 351 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 352 if (unlikely(r)) { 353 goto out_cleanup; 354 } 355 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 356 if (unlikely(r)) { 357 goto out_cleanup; 358 } 359 out_cleanup: 360 ttm_bo_mem_put(bo, &tmp_mem); 361 return r; 362 } 363 364 static int radeon_bo_move(struct ttm_buffer_object *bo, 365 bool evict, bool interruptible, 366 bool no_wait_gpu, 367 struct ttm_mem_reg *new_mem) 368 { 369 struct radeon_device *rdev; 370 struct ttm_mem_reg *old_mem = &bo->mem; 371 int r; 372 373 rdev = radeon_get_rdev(bo->bdev); 374 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 375 radeon_move_null(bo, new_mem); 376 return 0; 377 } 378 if ((old_mem->mem_type == TTM_PL_TT && 379 new_mem->mem_type == TTM_PL_SYSTEM) || 380 (old_mem->mem_type == TTM_PL_SYSTEM && 381 new_mem->mem_type == TTM_PL_TT)) { 382 /* bind is enough */ 383 radeon_move_null(bo, new_mem); 384 return 0; 385 } 386 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 387 rdev->asic->copy.copy == NULL) { 388 /* use memcpy */ 389 goto memcpy; 390 } 391 392 if (old_mem->mem_type == TTM_PL_VRAM && 393 new_mem->mem_type == TTM_PL_SYSTEM) { 394 r = radeon_move_vram_ram(bo, evict, interruptible, 395 no_wait_gpu, new_mem); 396 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 397 new_mem->mem_type == TTM_PL_VRAM) { 398 r = radeon_move_ram_vram(bo, evict, interruptible, 399 no_wait_gpu, new_mem); 400 } else { 401 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 402 } 403 404 if (r) { 405 memcpy: 406 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 407 } 408 return r; 409 } 410 411 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 412 { 413 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 414 struct radeon_device *rdev = radeon_get_rdev(bdev); 415 416 mem->bus.addr = NULL; 417 mem->bus.offset = 0; 418 mem->bus.size = mem->num_pages << PAGE_SHIFT; 419 mem->bus.base = 0; 420 mem->bus.is_iomem = false; 421 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 422 return -EINVAL; 423 switch (mem->mem_type) { 424 case TTM_PL_SYSTEM: 425 /* system memory */ 426 return 0; 427 case TTM_PL_TT: 428 #if __OS_HAS_AGP 429 if (rdev->flags & RADEON_IS_AGP) { 430 /* RADEON_IS_AGP is set only if AGP is active */ 431 mem->bus.offset = mem->start << PAGE_SHIFT; 432 mem->bus.base = rdev->mc.agp_base; 433 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 434 } 435 #endif 436 break; 437 case TTM_PL_VRAM: 438 mem->bus.offset = mem->start << PAGE_SHIFT; 439 /* check if it's visible */ 440 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 441 return -EINVAL; 442 mem->bus.base = rdev->mc.aper_base; 443 mem->bus.is_iomem = true; 444 #ifdef __alpha__ 445 /* 446 * Alpha: use bus.addr to hold the ioremap() return, 447 * so we can modify bus.base below. 448 */ 449 if (mem->placement & TTM_PL_FLAG_WC) 450 mem->bus.addr = 451 ioremap_wc(mem->bus.base + mem->bus.offset, 452 mem->bus.size); 453 else 454 mem->bus.addr = 455 ioremap_nocache(mem->bus.base + mem->bus.offset, 456 mem->bus.size); 457 458 /* 459 * Alpha: Use just the bus offset plus 460 * the hose/domain memory base for bus.base. 461 * It then can be used to build PTEs for VRAM 462 * access, as done in ttm_bo_vm_fault(). 463 */ 464 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 465 rdev->ddev->hose->dense_mem_base; 466 #endif 467 break; 468 default: 469 return -EINVAL; 470 } 471 return 0; 472 } 473 474 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 475 { 476 } 477 478 static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) 479 { 480 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); 481 } 482 483 static int radeon_sync_obj_flush(void *sync_obj) 484 { 485 return 0; 486 } 487 488 static void radeon_sync_obj_unref(void **sync_obj) 489 { 490 radeon_fence_unref((struct radeon_fence **)sync_obj); 491 } 492 493 static void *radeon_sync_obj_ref(void *sync_obj) 494 { 495 return radeon_fence_ref((struct radeon_fence *)sync_obj); 496 } 497 498 static bool radeon_sync_obj_signaled(void *sync_obj) 499 { 500 return radeon_fence_signaled((struct radeon_fence *)sync_obj); 501 } 502 503 /* 504 * TTM backend functions. 505 */ 506 struct radeon_ttm_tt { 507 struct ttm_dma_tt ttm; 508 struct radeon_device *rdev; 509 u64 offset; 510 }; 511 512 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 513 struct ttm_mem_reg *bo_mem) 514 { 515 struct radeon_ttm_tt *gtt = (void*)ttm; 516 int r; 517 518 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 519 if (!ttm->num_pages) { 520 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 521 ttm->num_pages, bo_mem, ttm); 522 } 523 r = radeon_gart_bind(gtt->rdev, gtt->offset, 524 ttm->num_pages, ttm->pages, gtt->ttm.dma_address); 525 if (r) { 526 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 527 ttm->num_pages, (unsigned)gtt->offset); 528 return r; 529 } 530 return 0; 531 } 532 533 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 534 { 535 struct radeon_ttm_tt *gtt = (void *)ttm; 536 537 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 538 return 0; 539 } 540 541 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 542 { 543 struct radeon_ttm_tt *gtt = (void *)ttm; 544 545 ttm_dma_tt_fini(>t->ttm); 546 kfree(gtt); 547 } 548 549 static struct ttm_backend_func radeon_backend_func = { 550 .bind = &radeon_ttm_backend_bind, 551 .unbind = &radeon_ttm_backend_unbind, 552 .destroy = &radeon_ttm_backend_destroy, 553 }; 554 555 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 556 unsigned long size, uint32_t page_flags, 557 vm_page_t dummy_read_page) 558 { 559 struct radeon_device *rdev; 560 struct radeon_ttm_tt *gtt; 561 562 rdev = radeon_get_rdev(bdev); 563 #if __OS_HAS_AGP 564 #ifdef DUMBBELL_WIP 565 if (rdev->flags & RADEON_IS_AGP) { 566 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev, 567 size, page_flags, dummy_read_page); 568 } 569 #endif /* DUMBBELL_WIP */ 570 #endif 571 572 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 573 if (gtt == NULL) { 574 return NULL; 575 } 576 gtt->ttm.ttm.func = &radeon_backend_func; 577 gtt->rdev = rdev; 578 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 579 kfree(gtt); 580 return NULL; 581 } 582 return >t->ttm.ttm; 583 } 584 585 static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 586 { 587 struct radeon_device *rdev; 588 struct radeon_ttm_tt *gtt = (void *)ttm; 589 unsigned i; 590 int r; 591 #ifdef DUMBBELL_WIP 592 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 593 #endif /* DUMBBELL_WIP */ 594 595 if (ttm->state != tt_unpopulated) 596 return 0; 597 598 #ifdef DUMBBELL_WIP 599 /* 600 * Maybe unneeded on FreeBSD. 601 * -- dumbbell@ 602 */ 603 if (slave && ttm->sg) { 604 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 605 gtt->ttm.dma_address, ttm->num_pages); 606 ttm->state = tt_unbound; 607 return 0; 608 } 609 #endif /* DUMBBELL_WIP */ 610 611 rdev = radeon_get_rdev(ttm->bdev); 612 #if __OS_HAS_AGP 613 #ifdef DUMBBELL_WIP 614 if (rdev->flags & RADEON_IS_AGP) { 615 return ttm_agp_tt_populate(ttm); 616 } 617 #endif /* DUMBBELL_WIP */ 618 #endif 619 620 #ifdef CONFIG_SWIOTLB 621 if (swiotlb_nr_tbl()) { 622 return ttm_dma_populate(>t->ttm, rdev->dev); 623 } 624 #endif 625 626 r = ttm_pool_populate(ttm); 627 if (r) { 628 return r; 629 } 630 631 for (i = 0; i < ttm->num_pages; i++) { 632 gtt->ttm.dma_address[i] = VM_PAGE_TO_PHYS(ttm->pages[i]); 633 #ifdef DUMBBELL_WIP 634 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 635 0, PAGE_SIZE, 636 PCI_DMA_BIDIRECTIONAL); 637 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { 638 while (--i) { 639 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 640 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 641 gtt->ttm.dma_address[i] = 0; 642 } 643 ttm_pool_unpopulate(ttm); 644 return -EFAULT; 645 } 646 #endif /* DUMBBELL_WIP */ 647 } 648 return 0; 649 } 650 651 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 652 { 653 struct radeon_device *rdev; 654 struct radeon_ttm_tt *gtt = (void *)ttm; 655 unsigned i; 656 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 657 658 if (slave) 659 return; 660 661 rdev = radeon_get_rdev(ttm->bdev); 662 #if __OS_HAS_AGP 663 #ifdef DUMBBELL_WIP 664 if (rdev->flags & RADEON_IS_AGP) { 665 ttm_agp_tt_unpopulate(ttm); 666 return; 667 } 668 #endif /* DUMBBELL_WIP */ 669 #endif 670 671 #ifdef CONFIG_SWIOTLB 672 if (swiotlb_nr_tbl()) { 673 ttm_dma_unpopulate(>t->ttm, rdev->dev); 674 return; 675 } 676 #endif 677 678 for (i = 0; i < ttm->num_pages; i++) { 679 if (gtt->ttm.dma_address[i]) { 680 gtt->ttm.dma_address[i] = 0; 681 #ifdef DUMBBELL_WIP 682 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 683 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 684 #endif /* DUMBBELL_WIP */ 685 } 686 } 687 688 ttm_pool_unpopulate(ttm); 689 } 690 691 static struct ttm_bo_driver radeon_bo_driver = { 692 .ttm_tt_create = &radeon_ttm_tt_create, 693 .ttm_tt_populate = &radeon_ttm_tt_populate, 694 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 695 .invalidate_caches = &radeon_invalidate_caches, 696 .init_mem_type = &radeon_init_mem_type, 697 .evict_flags = &radeon_evict_flags, 698 .move = &radeon_bo_move, 699 .verify_access = &radeon_verify_access, 700 .sync_obj_signaled = &radeon_sync_obj_signaled, 701 .sync_obj_wait = &radeon_sync_obj_wait, 702 .sync_obj_flush = &radeon_sync_obj_flush, 703 .sync_obj_unref = &radeon_sync_obj_unref, 704 .sync_obj_ref = &radeon_sync_obj_ref, 705 .move_notify = &radeon_bo_move_notify, 706 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 707 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 708 .io_mem_free = &radeon_ttm_io_mem_free, 709 }; 710 711 int radeon_ttm_init(struct radeon_device *rdev) 712 { 713 int r, r2; 714 715 r = radeon_ttm_global_init(rdev); 716 if (r) { 717 return r; 718 } 719 /* No others user of address space so set it to 0 */ 720 r = ttm_bo_device_init(&rdev->mman.bdev, 721 rdev->mman.bo_global_ref.ref.object, 722 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, 723 rdev->need_dma32); 724 if (r) { 725 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 726 return r; 727 } 728 rdev->mman.initialized = true; 729 rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev; 730 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 731 rdev->mc.real_vram_size >> PAGE_SHIFT); 732 if (r) { 733 DRM_ERROR("Failed initializing VRAM heap.\n"); 734 return r; 735 } 736 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 737 RADEON_GEM_DOMAIN_VRAM, 738 NULL, &rdev->stollen_vga_memory); 739 if (r) { 740 return r; 741 } 742 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 743 if (r) { 744 radeon_bo_unref(&rdev->stollen_vga_memory); 745 return r; 746 } 747 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 748 radeon_bo_unreserve(rdev->stollen_vga_memory); 749 if (r) { 750 radeon_bo_unref(&rdev->stollen_vga_memory); 751 return r; 752 } 753 DRM_INFO("radeon: %uM of VRAM memory ready\n", 754 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 755 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 756 rdev->mc.gtt_size >> PAGE_SHIFT); 757 if (r) { 758 DRM_ERROR("Failed initializing GTT heap.\n"); 759 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); 760 if (likely(r2 == 0)) { 761 radeon_bo_unpin(rdev->stollen_vga_memory); 762 radeon_bo_unreserve(rdev->stollen_vga_memory); 763 } 764 radeon_bo_unref(&rdev->stollen_vga_memory); 765 return r; 766 } 767 DRM_INFO("radeon: %uM of GTT memory ready.\n", 768 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 769 770 r = radeon_ttm_debugfs_init(rdev); 771 if (r) { 772 DRM_ERROR("Failed to init debugfs\n"); 773 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); 774 if (likely(r2 == 0)) { 775 radeon_bo_unpin(rdev->stollen_vga_memory); 776 radeon_bo_unreserve(rdev->stollen_vga_memory); 777 } 778 radeon_bo_unref(&rdev->stollen_vga_memory); 779 return r; 780 } 781 return 0; 782 } 783 784 void radeon_ttm_fini(struct radeon_device *rdev) 785 { 786 int r; 787 788 if (!rdev->mman.initialized) 789 return; 790 if (rdev->stollen_vga_memory) { 791 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 792 if (r == 0) { 793 radeon_bo_unpin(rdev->stollen_vga_memory); 794 radeon_bo_unreserve(rdev->stollen_vga_memory); 795 } 796 radeon_bo_unref(&rdev->stollen_vga_memory); 797 } 798 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 799 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 800 ttm_bo_device_release(&rdev->mman.bdev); 801 radeon_gart_fini(rdev); 802 radeon_ttm_global_fini(rdev); 803 rdev->mman.initialized = false; 804 DRM_INFO("radeon: ttm finalized\n"); 805 } 806 807 /* this should only be called at bootup or when userspace 808 * isn't running */ 809 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 810 { 811 struct ttm_mem_type_manager *man; 812 813 if (!rdev->mman.initialized) 814 return; 815 816 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 817 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 818 man->size = size >> PAGE_SHIFT; 819 } 820 821 #ifdef DUMBBELL_WIP 822 static struct vm_operations_struct radeon_ttm_vm_ops; 823 static const struct vm_operations_struct *ttm_vm_ops = NULL; 824 825 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 826 { 827 struct ttm_buffer_object *bo; 828 struct radeon_device *rdev; 829 int r; 830 831 bo = (struct ttm_buffer_object *)vma->vm_private_data; 832 if (bo == NULL) { 833 return VM_FAULT_NOPAGE; 834 } 835 rdev = radeon_get_rdev(bo->bdev); 836 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 837 r = ttm_vm_ops->fault(vma, vmf); 838 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 839 return r; 840 } 841 842 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 843 { 844 struct drm_file *file_priv; 845 struct radeon_device *rdev; 846 int r; 847 848 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { 849 return drm_mmap(filp, vma); 850 } 851 852 file_priv = filp->private_data; 853 rdev = file_priv->minor->dev->dev_private; 854 if (rdev == NULL) { 855 return -EINVAL; 856 } 857 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 858 if (unlikely(r != 0)) { 859 return r; 860 } 861 if (unlikely(ttm_vm_ops == NULL)) { 862 ttm_vm_ops = vma->vm_ops; 863 radeon_ttm_vm_ops = *ttm_vm_ops; 864 radeon_ttm_vm_ops.fault = &radeon_ttm_fault; 865 } 866 vma->vm_ops = &radeon_ttm_vm_ops; 867 return 0; 868 } 869 #endif /* DUMBBELL_WIP */ 870 871 872 #define RADEON_DEBUGFS_MEM_TYPES 2 873 874 #if defined(CONFIG_DEBUG_FS) 875 static int radeon_mm_dump_table(struct seq_file *m, void *data) 876 { 877 struct drm_info_node *node = (struct drm_info_node *)m->private; 878 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; 879 struct drm_device *dev = node->minor->dev; 880 struct radeon_device *rdev = dev->dev_private; 881 int ret; 882 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 883 884 spin_lock(&glob->lru_lock); 885 ret = drm_mm_dump_table(m, mm); 886 spin_unlock(&glob->lru_lock); 887 return ret; 888 } 889 #endif 890 891 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 892 { 893 #if defined(CONFIG_DEBUG_FS) 894 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; 895 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; 896 unsigned i; 897 898 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { 899 if (i == 0) 900 sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); 901 else 902 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); 903 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 904 radeon_mem_types_list[i].show = &radeon_mm_dump_table; 905 radeon_mem_types_list[i].driver_features = 0; 906 if (i == 0) 907 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; 908 else 909 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; 910 911 } 912 /* Add ttm page pool to debugfs */ 913 sprintf(radeon_mem_types_names[i], "ttm_page_pool"); 914 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 915 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; 916 radeon_mem_types_list[i].driver_features = 0; 917 radeon_mem_types_list[i++].data = NULL; 918 #ifdef CONFIG_SWIOTLB 919 if (swiotlb_nr_tbl()) { 920 sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); 921 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 922 radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; 923 radeon_mem_types_list[i].driver_features = 0; 924 radeon_mem_types_list[i++].data = NULL; 925 } 926 #endif 927 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i); 928 929 #endif 930 return 0; 931 } 932