1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 * 32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $ 33 */ 34 35 #include <drm/ttm/ttm_bo_api.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_placement.h> 38 #include <drm/ttm/ttm_module.h> 39 #include <drm/ttm/ttm_page_alloc.h> 40 #include <drm/drmP.h> 41 #include <drm/radeon_drm.h> 42 #include <linux/seq_file.h> 43 #include <linux/slab.h> 44 #include "radeon_reg.h" 45 #include "radeon.h" 46 47 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 48 49 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 50 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 51 52 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 53 { 54 struct radeon_mman *mman; 55 struct radeon_device *rdev; 56 57 mman = container_of(bdev, struct radeon_mman, bdev); 58 rdev = container_of(mman, struct radeon_device, mman); 59 return rdev; 60 } 61 62 63 /* 64 * Global memory. 65 */ 66 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 67 { 68 return ttm_mem_global_init(ref->object); 69 } 70 71 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 72 { 73 ttm_mem_global_release(ref->object); 74 } 75 76 static int radeon_ttm_global_init(struct radeon_device *rdev) 77 { 78 struct drm_global_reference *global_ref; 79 int r; 80 81 rdev->mman.mem_global_referenced = false; 82 global_ref = &rdev->mman.mem_global_ref; 83 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 84 global_ref->size = sizeof(struct ttm_mem_global); 85 global_ref->init = &radeon_ttm_mem_global_init; 86 global_ref->release = &radeon_ttm_mem_global_release; 87 r = drm_global_item_ref(global_ref); 88 if (r != 0) { 89 DRM_ERROR("Failed setting up TTM memory accounting " 90 "subsystem.\n"); 91 return r; 92 } 93 94 rdev->mman.bo_global_ref.mem_glob = 95 rdev->mman.mem_global_ref.object; 96 global_ref = &rdev->mman.bo_global_ref.ref; 97 global_ref->global_type = DRM_GLOBAL_TTM_BO; 98 global_ref->size = sizeof(struct ttm_bo_global); 99 global_ref->init = &ttm_bo_global_init; 100 global_ref->release = &ttm_bo_global_release; 101 r = drm_global_item_ref(global_ref); 102 if (r != 0) { 103 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 104 drm_global_item_unref(&rdev->mman.mem_global_ref); 105 return r; 106 } 107 108 rdev->mman.mem_global_referenced = true; 109 return 0; 110 } 111 112 static void radeon_ttm_global_fini(struct radeon_device *rdev) 113 { 114 if (rdev->mman.mem_global_referenced) { 115 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 116 drm_global_item_unref(&rdev->mman.mem_global_ref); 117 rdev->mman.mem_global_referenced = false; 118 } 119 } 120 121 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 122 { 123 return 0; 124 } 125 126 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 127 struct ttm_mem_type_manager *man) 128 { 129 struct radeon_device *rdev; 130 131 rdev = radeon_get_rdev(bdev); 132 133 switch (type) { 134 case TTM_PL_SYSTEM: 135 /* System memory */ 136 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 137 man->available_caching = TTM_PL_MASK_CACHING; 138 man->default_caching = TTM_PL_FLAG_CACHED; 139 break; 140 case TTM_PL_TT: 141 man->func = &ttm_bo_manager_func; 142 man->gpu_offset = rdev->mc.gtt_start; 143 man->available_caching = TTM_PL_MASK_CACHING; 144 man->default_caching = TTM_PL_FLAG_CACHED; 145 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 146 #if __OS_HAS_AGP 147 if (rdev->flags & RADEON_IS_AGP) { 148 if (!rdev->ddev->agp) { 149 DRM_ERROR("AGP is not enabled for memory type %u\n", 150 (unsigned)type); 151 return -EINVAL; 152 } 153 if (!rdev->ddev->agp->cant_use_aperture) 154 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 155 man->available_caching = TTM_PL_FLAG_UNCACHED | 156 TTM_PL_FLAG_WC; 157 man->default_caching = TTM_PL_FLAG_WC; 158 } 159 #endif 160 break; 161 case TTM_PL_VRAM: 162 /* "On-card" video ram */ 163 man->func = &ttm_bo_manager_func; 164 man->gpu_offset = rdev->mc.vram_start; 165 man->flags = TTM_MEMTYPE_FLAG_FIXED | 166 TTM_MEMTYPE_FLAG_MAPPABLE; 167 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 168 man->default_caching = TTM_PL_FLAG_WC; 169 break; 170 default: 171 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 172 return -EINVAL; 173 } 174 return 0; 175 } 176 177 static void radeon_evict_flags(struct ttm_buffer_object *bo, 178 struct ttm_placement *placement) 179 { 180 static struct ttm_place placements = { 181 .fpfn = 0, 182 .lpfn = 0, 183 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 184 }; 185 186 struct radeon_bo *rbo; 187 188 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 189 placement->placement = &placements; 190 placement->busy_placement = &placements; 191 placement->num_placement = 1; 192 placement->num_busy_placement = 1; 193 return; 194 } 195 rbo = container_of(bo, struct radeon_bo, tbo); 196 switch (bo->mem.mem_type) { 197 case TTM_PL_VRAM: 198 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) 199 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 200 else 201 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 202 break; 203 case TTM_PL_TT: 204 default: 205 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 206 } 207 *placement = rbo->placement; 208 } 209 210 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *fp) 211 { 212 #if 0 213 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 214 #endif 215 216 return 0; 217 218 #if 0 219 /* XXX needs radeon_gem_userptr_ioctl() and related infrastructure */ 220 if (radeon_ttm_tt_has_userptr(bo->ttm)) 221 return -EPERM; 222 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, 223 fp->private_data); 224 #endif 225 } 226 227 static void radeon_move_null(struct ttm_buffer_object *bo, 228 struct ttm_mem_reg *new_mem) 229 { 230 struct ttm_mem_reg *old_mem = &bo->mem; 231 232 BUG_ON(old_mem->mm_node != NULL); 233 *old_mem = *new_mem; 234 new_mem->mm_node = NULL; 235 } 236 237 static int radeon_move_blit(struct ttm_buffer_object *bo, 238 bool evict, bool no_wait_gpu, 239 struct ttm_mem_reg *new_mem, 240 struct ttm_mem_reg *old_mem) 241 { 242 struct radeon_device *rdev; 243 uint64_t old_start, new_start; 244 struct radeon_fence *fence; 245 unsigned num_pages; 246 int r, ridx; 247 248 rdev = radeon_get_rdev(bo->bdev); 249 ridx = radeon_copy_ring_index(rdev); 250 old_start = old_mem->start << PAGE_SHIFT; 251 new_start = new_mem->start << PAGE_SHIFT; 252 253 switch (old_mem->mem_type) { 254 case TTM_PL_VRAM: 255 old_start += rdev->mc.vram_start; 256 break; 257 case TTM_PL_TT: 258 old_start += rdev->mc.gtt_start; 259 break; 260 default: 261 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 262 return -EINVAL; 263 } 264 switch (new_mem->mem_type) { 265 case TTM_PL_VRAM: 266 new_start += rdev->mc.vram_start; 267 break; 268 case TTM_PL_TT: 269 new_start += rdev->mc.gtt_start; 270 break; 271 default: 272 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 273 return -EINVAL; 274 } 275 if (!rdev->ring[ridx].ready) { 276 DRM_ERROR("Trying to move memory with ring turned off.\n"); 277 return -EINVAL; 278 } 279 280 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 281 282 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 283 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv); 284 if (IS_ERR(fence)) 285 return PTR_ERR(fence); 286 287 r = ttm_bo_move_accel_cleanup(bo, &fence->base, 288 evict, no_wait_gpu, new_mem); 289 radeon_fence_unref(&fence); 290 return r; 291 } 292 293 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 294 bool evict, bool interruptible, 295 bool no_wait_gpu, 296 struct ttm_mem_reg *new_mem) 297 { 298 struct radeon_device *rdev; 299 struct ttm_mem_reg *old_mem = &bo->mem; 300 struct ttm_mem_reg tmp_mem; 301 struct ttm_place placements; 302 struct ttm_placement placement; 303 int r; 304 305 rdev = radeon_get_rdev(bo->bdev); 306 tmp_mem = *new_mem; 307 tmp_mem.mm_node = NULL; 308 placement.num_placement = 1; 309 placement.placement = &placements; 310 placement.num_busy_placement = 1; 311 placement.busy_placement = &placements; 312 placements.fpfn = 0; 313 placements.lpfn = 0; 314 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 315 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 316 interruptible, no_wait_gpu); 317 if (unlikely(r)) { 318 return r; 319 } 320 321 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 322 if (unlikely(r)) { 323 goto out_cleanup; 324 } 325 326 r = ttm_tt_bind(bo->ttm, &tmp_mem); 327 if (unlikely(r)) { 328 goto out_cleanup; 329 } 330 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 331 if (unlikely(r)) { 332 goto out_cleanup; 333 } 334 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 335 out_cleanup: 336 ttm_bo_mem_put(bo, &tmp_mem); 337 return r; 338 } 339 340 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 341 bool evict, bool interruptible, 342 bool no_wait_gpu, 343 struct ttm_mem_reg *new_mem) 344 { 345 struct radeon_device *rdev; 346 struct ttm_mem_reg *old_mem = &bo->mem; 347 struct ttm_mem_reg tmp_mem; 348 struct ttm_placement placement; 349 struct ttm_place placements; 350 int r; 351 352 rdev = radeon_get_rdev(bo->bdev); 353 tmp_mem = *new_mem; 354 tmp_mem.mm_node = NULL; 355 placement.num_placement = 1; 356 placement.placement = &placements; 357 placement.num_busy_placement = 1; 358 placement.busy_placement = &placements; 359 placements.fpfn = 0; 360 placements.lpfn = 0; 361 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 362 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 363 interruptible, no_wait_gpu); 364 if (unlikely(r)) { 365 return r; 366 } 367 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 368 if (unlikely(r)) { 369 goto out_cleanup; 370 } 371 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 372 if (unlikely(r)) { 373 goto out_cleanup; 374 } 375 out_cleanup: 376 ttm_bo_mem_put(bo, &tmp_mem); 377 return r; 378 } 379 380 static int radeon_bo_move(struct ttm_buffer_object *bo, 381 bool evict, bool interruptible, 382 bool no_wait_gpu, 383 struct ttm_mem_reg *new_mem) 384 { 385 struct radeon_device *rdev; 386 struct ttm_mem_reg *old_mem = &bo->mem; 387 int r; 388 389 rdev = radeon_get_rdev(bo->bdev); 390 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 391 radeon_move_null(bo, new_mem); 392 return 0; 393 } 394 if ((old_mem->mem_type == TTM_PL_TT && 395 new_mem->mem_type == TTM_PL_SYSTEM) || 396 (old_mem->mem_type == TTM_PL_SYSTEM && 397 new_mem->mem_type == TTM_PL_TT)) { 398 /* bind is enough */ 399 radeon_move_null(bo, new_mem); 400 return 0; 401 } 402 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 403 rdev->asic->copy.copy == NULL) { 404 /* use memcpy */ 405 goto memcpy; 406 } 407 408 if (old_mem->mem_type == TTM_PL_VRAM && 409 new_mem->mem_type == TTM_PL_SYSTEM) { 410 r = radeon_move_vram_ram(bo, evict, interruptible, 411 no_wait_gpu, new_mem); 412 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 413 new_mem->mem_type == TTM_PL_VRAM) { 414 r = radeon_move_ram_vram(bo, evict, interruptible, 415 no_wait_gpu, new_mem); 416 } else { 417 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 418 } 419 420 if (r) { 421 memcpy: 422 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 423 if (r) { 424 return r; 425 } 426 } 427 428 /* update statistics */ 429 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 430 return 0; 431 } 432 433 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 434 { 435 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 436 struct radeon_device *rdev = radeon_get_rdev(bdev); 437 438 mem->bus.addr = NULL; 439 mem->bus.offset = 0; 440 mem->bus.size = mem->num_pages << PAGE_SHIFT; 441 mem->bus.base = 0; 442 mem->bus.is_iomem = false; 443 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 444 return -EINVAL; 445 switch (mem->mem_type) { 446 case TTM_PL_SYSTEM: 447 /* system memory */ 448 return 0; 449 case TTM_PL_TT: 450 #if __OS_HAS_AGP 451 if (rdev->flags & RADEON_IS_AGP) { 452 /* RADEON_IS_AGP is set only if AGP is active */ 453 mem->bus.offset = mem->start << PAGE_SHIFT; 454 mem->bus.base = rdev->mc.agp_base; 455 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 456 } 457 #endif 458 break; 459 case TTM_PL_VRAM: 460 mem->bus.offset = mem->start << PAGE_SHIFT; 461 /* check if it's visible */ 462 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 463 return -EINVAL; 464 mem->bus.base = rdev->mc.aper_base; 465 mem->bus.is_iomem = true; 466 #ifdef __alpha__ 467 /* 468 * Alpha: use bus.addr to hold the ioremap() return, 469 * so we can modify bus.base below. 470 */ 471 if (mem->placement & TTM_PL_FLAG_WC) 472 mem->bus.addr = 473 ioremap_wc(mem->bus.base + mem->bus.offset, 474 mem->bus.size); 475 else 476 mem->bus.addr = 477 ioremap_nocache(mem->bus.base + mem->bus.offset, 478 mem->bus.size); 479 480 /* 481 * Alpha: Use just the bus offset plus 482 * the hose/domain memory base for bus.base. 483 * It then can be used to build PTEs for VRAM 484 * access, as done in ttm_bo_vm_fault(). 485 */ 486 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 487 rdev->ddev->hose->dense_mem_base; 488 #endif 489 break; 490 default: 491 return -EINVAL; 492 } 493 return 0; 494 } 495 496 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 497 { 498 } 499 500 /* 501 * TTM backend functions. 502 */ 503 struct radeon_ttm_tt { 504 struct ttm_dma_tt ttm; 505 struct radeon_device *rdev; 506 u64 offset; 507 }; 508 509 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 510 struct ttm_mem_reg *bo_mem) 511 { 512 struct radeon_ttm_tt *gtt = (void*)ttm; 513 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 514 RADEON_GART_PAGE_WRITE; 515 int r; 516 517 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 518 if (!ttm->num_pages) { 519 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 520 ttm->num_pages, bo_mem, ttm); 521 } 522 if (ttm->caching_state == tt_cached) 523 flags |= RADEON_GART_PAGE_SNOOP; 524 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, 525 ttm->pages, gtt->ttm.dma_address, flags); 526 if (r) { 527 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 528 ttm->num_pages, (unsigned)gtt->offset); 529 return r; 530 } 531 return 0; 532 } 533 534 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 535 { 536 struct radeon_ttm_tt *gtt = (void *)ttm; 537 538 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 539 return 0; 540 } 541 542 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 543 { 544 struct radeon_ttm_tt *gtt = (void *)ttm; 545 546 ttm_dma_tt_fini(>t->ttm); 547 kfree(gtt); 548 } 549 550 static struct ttm_backend_func radeon_backend_func = { 551 .bind = &radeon_ttm_backend_bind, 552 .unbind = &radeon_ttm_backend_unbind, 553 .destroy = &radeon_ttm_backend_destroy, 554 }; 555 556 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 557 unsigned long size, uint32_t page_flags, 558 struct page *dummy_read_page) 559 { 560 struct radeon_device *rdev; 561 struct radeon_ttm_tt *gtt; 562 563 rdev = radeon_get_rdev(bdev); 564 #if __OS_HAS_AGP 565 #ifdef DUMBBELL_WIP 566 if (rdev->flags & RADEON_IS_AGP) { 567 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev, 568 size, page_flags, dummy_read_page); 569 } 570 #endif /* DUMBBELL_WIP */ 571 #endif 572 573 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 574 if (gtt == NULL) { 575 return NULL; 576 } 577 gtt->ttm.ttm.func = &radeon_backend_func; 578 gtt->rdev = rdev; 579 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 580 kfree(gtt); 581 return NULL; 582 } 583 return >t->ttm.ttm; 584 } 585 586 static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 587 { 588 struct radeon_device *rdev; 589 struct radeon_ttm_tt *gtt = (void *)ttm; 590 unsigned i; 591 int r; 592 #ifdef DUMBBELL_WIP 593 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 594 #endif /* DUMBBELL_WIP */ 595 596 if (ttm->state != tt_unpopulated) 597 return 0; 598 599 #ifdef DUMBBELL_WIP 600 /* 601 * Maybe unneeded on FreeBSD. 602 * -- dumbbell@ 603 */ 604 if (slave && ttm->sg) { 605 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 606 gtt->ttm.dma_address, ttm->num_pages); 607 ttm->state = tt_unbound; 608 return 0; 609 } 610 #endif /* DUMBBELL_WIP */ 611 612 rdev = radeon_get_rdev(ttm->bdev); 613 #if __OS_HAS_AGP 614 #ifdef DUMBBELL_WIP 615 if (rdev->flags & RADEON_IS_AGP) { 616 return ttm_agp_tt_populate(ttm); 617 } 618 #endif /* DUMBBELL_WIP */ 619 #endif 620 621 #ifdef CONFIG_SWIOTLB 622 if (swiotlb_nr_tbl()) { 623 return ttm_dma_populate(>t->ttm, rdev->dev); 624 } 625 #endif 626 627 r = ttm_pool_populate(ttm); 628 if (r) { 629 return r; 630 } 631 632 for (i = 0; i < ttm->num_pages; i++) { 633 gtt->ttm.dma_address[i] = VM_PAGE_TO_PHYS((struct vm_page *)ttm->pages[i]); 634 #ifdef DUMBBELL_WIP 635 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 636 0, PAGE_SIZE, 637 PCI_DMA_BIDIRECTIONAL); 638 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { 639 while (--i) { 640 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 641 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 642 gtt->ttm.dma_address[i] = 0; 643 } 644 ttm_pool_unpopulate(ttm); 645 return -EFAULT; 646 } 647 #endif /* DUMBBELL_WIP */ 648 } 649 return 0; 650 } 651 652 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 653 { 654 struct radeon_device *rdev; 655 struct radeon_ttm_tt *gtt = (void *)ttm; 656 unsigned i; 657 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 658 659 if (slave) 660 return; 661 662 rdev = radeon_get_rdev(ttm->bdev); 663 #if __OS_HAS_AGP 664 #ifdef DUMBBELL_WIP 665 if (rdev->flags & RADEON_IS_AGP) { 666 ttm_agp_tt_unpopulate(ttm); 667 return; 668 } 669 #endif /* DUMBBELL_WIP */ 670 #endif 671 672 #ifdef CONFIG_SWIOTLB 673 if (swiotlb_nr_tbl()) { 674 ttm_dma_unpopulate(>t->ttm, rdev->dev); 675 return; 676 } 677 #endif 678 679 for (i = 0; i < ttm->num_pages; i++) { 680 if (gtt->ttm.dma_address[i]) { 681 gtt->ttm.dma_address[i] = 0; 682 #ifdef DUMBBELL_WIP 683 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 684 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 685 #endif /* DUMBBELL_WIP */ 686 } 687 } 688 689 ttm_pool_unpopulate(ttm); 690 } 691 692 static struct ttm_bo_driver radeon_bo_driver = { 693 .ttm_tt_create = &radeon_ttm_tt_create, 694 .ttm_tt_populate = &radeon_ttm_tt_populate, 695 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 696 .invalidate_caches = &radeon_invalidate_caches, 697 .init_mem_type = &radeon_init_mem_type, 698 .evict_flags = &radeon_evict_flags, 699 .move = &radeon_bo_move, 700 .verify_access = &radeon_verify_access, 701 .move_notify = &radeon_bo_move_notify, 702 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 703 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 704 .io_mem_free = &radeon_ttm_io_mem_free, 705 }; 706 707 int radeon_ttm_init(struct radeon_device *rdev) 708 { 709 int r, r2; 710 711 r = radeon_ttm_global_init(rdev); 712 if (r) { 713 return r; 714 } 715 /* No others user of address space so set it to 0 */ 716 r = ttm_bo_device_init(&rdev->mman.bdev, 717 rdev->mman.bo_global_ref.ref.object, 718 &radeon_bo_driver, 719 #ifdef __DragonFly__ 720 NULL, 721 #else 722 rdev->ddev->anon_inode->i_mapping, 723 #endif 724 DRM_FILE_PAGE_OFFSET, 725 rdev->need_dma32); 726 if (r) { 727 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 728 return r; 729 } 730 rdev->mman.initialized = true; 731 rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev; 732 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 733 rdev->mc.real_vram_size >> PAGE_SHIFT); 734 if (r) { 735 DRM_ERROR("Failed initializing VRAM heap.\n"); 736 return r; 737 } 738 /* Change the size here instead of the init above so only lpfn is affected */ 739 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 740 741 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 742 RADEON_GEM_DOMAIN_VRAM, 0, 743 NULL, &rdev->stollen_vga_memory); 744 if (r) { 745 return r; 746 } 747 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 748 if (r) { 749 radeon_bo_unref(&rdev->stollen_vga_memory); 750 return r; 751 } 752 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 753 radeon_bo_unreserve(rdev->stollen_vga_memory); 754 if (r) { 755 radeon_bo_unref(&rdev->stollen_vga_memory); 756 return r; 757 } 758 DRM_INFO("radeon: %uM of VRAM memory ready\n", 759 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 760 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 761 rdev->mc.gtt_size >> PAGE_SHIFT); 762 if (r) { 763 DRM_ERROR("Failed initializing GTT heap.\n"); 764 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); 765 if (likely(r2 == 0)) { 766 radeon_bo_unpin(rdev->stollen_vga_memory); 767 radeon_bo_unreserve(rdev->stollen_vga_memory); 768 } 769 radeon_bo_unref(&rdev->stollen_vga_memory); 770 return r; 771 } 772 DRM_INFO("radeon: %uM of GTT memory ready.\n", 773 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 774 775 r = radeon_ttm_debugfs_init(rdev); 776 if (r) { 777 DRM_ERROR("Failed to init debugfs\n"); 778 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); 779 if (likely(r2 == 0)) { 780 radeon_bo_unpin(rdev->stollen_vga_memory); 781 radeon_bo_unreserve(rdev->stollen_vga_memory); 782 } 783 radeon_bo_unref(&rdev->stollen_vga_memory); 784 return r; 785 } 786 return 0; 787 } 788 789 void radeon_ttm_fini(struct radeon_device *rdev) 790 { 791 int r; 792 793 if (!rdev->mman.initialized) 794 return; 795 radeon_ttm_debugfs_fini(rdev); 796 if (rdev->stollen_vga_memory) { 797 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 798 if (r == 0) { 799 radeon_bo_unpin(rdev->stollen_vga_memory); 800 radeon_bo_unreserve(rdev->stollen_vga_memory); 801 } 802 radeon_bo_unref(&rdev->stollen_vga_memory); 803 } 804 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 805 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 806 ttm_bo_device_release(&rdev->mman.bdev); 807 radeon_gart_fini(rdev); 808 radeon_ttm_global_fini(rdev); 809 rdev->mman.initialized = false; 810 DRM_INFO("radeon: ttm finalized\n"); 811 } 812 813 /* this should only be called at bootup or when userspace 814 * isn't running */ 815 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 816 { 817 struct ttm_mem_type_manager *man; 818 819 if (!rdev->mman.initialized) 820 return; 821 822 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 823 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 824 man->size = size >> PAGE_SHIFT; 825 } 826 827 #ifdef DUMBBELL_WIP 828 static struct vm_operations_struct radeon_ttm_vm_ops; 829 static const struct vm_operations_struct *ttm_vm_ops = NULL; 830 831 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 832 { 833 struct ttm_buffer_object *bo; 834 struct radeon_device *rdev; 835 int r; 836 837 bo = (struct ttm_buffer_object *)vma->vm_private_data; 838 if (bo == NULL) { 839 return VM_FAULT_NOPAGE; 840 } 841 rdev = radeon_get_rdev(bo->bdev); 842 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 843 r = ttm_vm_ops->fault(vma, vmf); 844 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 845 return r; 846 } 847 848 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 849 { 850 struct drm_file *file_priv; 851 struct radeon_device *rdev; 852 int r; 853 854 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { 855 return -EINVAL; 856 } 857 858 file_priv = filp->private_data; 859 rdev = file_priv->minor->dev->dev_private; 860 if (rdev == NULL) { 861 return -EINVAL; 862 } 863 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 864 if (unlikely(r != 0)) { 865 return r; 866 } 867 if (unlikely(ttm_vm_ops == NULL)) { 868 ttm_vm_ops = vma->vm_ops; 869 radeon_ttm_vm_ops = *ttm_vm_ops; 870 radeon_ttm_vm_ops.fault = &radeon_ttm_fault; 871 } 872 vma->vm_ops = &radeon_ttm_vm_ops; 873 return 0; 874 } 875 #endif /* DUMBBELL_WIP */ 876 877 #if defined(CONFIG_DEBUG_FS) 878 879 static int radeon_mm_dump_table(struct seq_file *m, void *data) 880 { 881 struct drm_info_node *node = (struct drm_info_node *)m->private; 882 unsigned ttm_pl = *(int *)node->info_ent->data; 883 struct drm_device *dev = node->minor->dev; 884 struct radeon_device *rdev = dev->dev_private; 885 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; 886 int ret; 887 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 888 889 spin_lock(&glob->lru_lock); 890 ret = drm_mm_dump_table(m, mm); 891 spin_unlock(&glob->lru_lock); 892 return ret; 893 } 894 895 static int ttm_pl_vram = TTM_PL_VRAM; 896 static int ttm_pl_tt = TTM_PL_TT; 897 898 static struct drm_info_list radeon_ttm_debugfs_list[] = { 899 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 900 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 901 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 902 #ifdef CONFIG_SWIOTLB 903 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 904 #endif 905 }; 906 907 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 908 { 909 struct radeon_device *rdev = inode->i_private; 910 i_size_write(inode, rdev->mc.mc_vram_size); 911 filep->private_data = inode->i_private; 912 return 0; 913 } 914 915 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 916 size_t size, loff_t *pos) 917 { 918 struct radeon_device *rdev = f->private_data; 919 ssize_t result = 0; 920 int r; 921 922 if (size & 0x3 || *pos & 0x3) 923 return -EINVAL; 924 925 while (size) { 926 unsigned long flags; 927 uint32_t value; 928 929 if (*pos >= rdev->mc.mc_vram_size) 930 return result; 931 932 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 933 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 934 if (rdev->family >= CHIP_CEDAR) 935 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 936 value = RREG32(RADEON_MM_DATA); 937 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 938 939 r = put_user(value, (uint32_t *)buf); 940 if (r) 941 return r; 942 943 result += 4; 944 buf += 4; 945 *pos += 4; 946 size -= 4; 947 } 948 949 return result; 950 } 951 952 static const struct file_operations radeon_ttm_vram_fops = { 953 .owner = THIS_MODULE, 954 .open = radeon_ttm_vram_open, 955 .read = radeon_ttm_vram_read, 956 .llseek = default_llseek 957 }; 958 959 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 960 { 961 struct radeon_device *rdev = inode->i_private; 962 i_size_write(inode, rdev->mc.gtt_size); 963 filep->private_data = inode->i_private; 964 return 0; 965 } 966 967 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 968 size_t size, loff_t *pos) 969 { 970 struct radeon_device *rdev = f->private_data; 971 ssize_t result = 0; 972 int r; 973 974 while (size) { 975 loff_t p = *pos / PAGE_SIZE; 976 unsigned off = *pos & ~LINUX_PAGE_MASK; 977 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 978 struct page *page; 979 void *ptr; 980 981 if (p >= rdev->gart.num_cpu_pages) 982 return result; 983 984 page = rdev->gart.pages[p]; 985 if (page) { 986 ptr = kmap(page); 987 ptr += off; 988 989 r = copy_to_user(buf, ptr, cur_size); 990 kunmap(rdev->gart.pages[p]); 991 } else 992 r = clear_user(buf, cur_size); 993 994 if (r) 995 return -EFAULT; 996 997 result += cur_size; 998 buf += cur_size; 999 *pos += cur_size; 1000 size -= cur_size; 1001 } 1002 1003 return result; 1004 } 1005 1006 static const struct file_operations radeon_ttm_gtt_fops = { 1007 .owner = THIS_MODULE, 1008 .open = radeon_ttm_gtt_open, 1009 .read = radeon_ttm_gtt_read, 1010 .llseek = default_llseek 1011 }; 1012 1013 #endif 1014 1015 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1016 { 1017 #if defined(CONFIG_DEBUG_FS) 1018 unsigned count; 1019 1020 struct drm_minor *minor = rdev->ddev->primary; 1021 struct dentry *ent, *root = minor->debugfs_root; 1022 1023 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, 1024 rdev, &radeon_ttm_vram_fops); 1025 if (IS_ERR(ent)) 1026 return PTR_ERR(ent); 1027 rdev->mman.vram = ent; 1028 1029 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, 1030 rdev, &radeon_ttm_gtt_fops); 1031 if (IS_ERR(ent)) 1032 return PTR_ERR(ent); 1033 rdev->mman.gtt = ent; 1034 1035 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1036 1037 #ifdef CONFIG_SWIOTLB 1038 if (!swiotlb_nr_tbl()) 1039 --count; 1040 #endif 1041 1042 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1043 #else 1044 1045 return 0; 1046 #endif 1047 } 1048 1049 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1050 { 1051 #if defined(CONFIG_DEBUG_FS) 1052 1053 debugfs_remove(rdev->mman.vram); 1054 rdev->mman.vram = NULL; 1055 1056 debugfs_remove(rdev->mman.gtt); 1057 rdev->mman.gtt = NULL; 1058 #endif 1059 } 1060