1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 * 32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $ 33 */ 34 35 #include <drm/ttm/ttm_bo_api.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_placement.h> 38 #include <drm/ttm/ttm_module.h> 39 #include <drm/ttm/ttm_page_alloc.h> 40 #include <drm/drmP.h> 41 #include <uapi_drm/radeon_drm.h> 42 #include <linux/seq_file.h> 43 #include <linux/slab.h> 44 #include "radeon_reg.h" 45 #include "radeon.h" 46 47 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 48 49 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 50 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 51 52 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 53 { 54 struct radeon_mman *mman; 55 struct radeon_device *rdev; 56 57 mman = container_of(bdev, struct radeon_mman, bdev); 58 rdev = container_of(mman, struct radeon_device, mman); 59 return rdev; 60 } 61 62 63 /* 64 * Global memory. 65 */ 66 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 67 { 68 return ttm_mem_global_init(ref->object); 69 } 70 71 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 72 { 73 ttm_mem_global_release(ref->object); 74 } 75 76 static int radeon_ttm_global_init(struct radeon_device *rdev) 77 { 78 struct drm_global_reference *global_ref; 79 int r; 80 81 rdev->mman.mem_global_referenced = false; 82 global_ref = &rdev->mman.mem_global_ref; 83 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 84 global_ref->size = sizeof(struct ttm_mem_global); 85 global_ref->init = &radeon_ttm_mem_global_init; 86 global_ref->release = &radeon_ttm_mem_global_release; 87 r = drm_global_item_ref(global_ref); 88 if (r != 0) { 89 DRM_ERROR("Failed setting up TTM memory accounting " 90 "subsystem.\n"); 91 return r; 92 } 93 94 rdev->mman.bo_global_ref.mem_glob = 95 rdev->mman.mem_global_ref.object; 96 global_ref = &rdev->mman.bo_global_ref.ref; 97 global_ref->global_type = DRM_GLOBAL_TTM_BO; 98 global_ref->size = sizeof(struct ttm_bo_global); 99 global_ref->init = &ttm_bo_global_init; 100 global_ref->release = &ttm_bo_global_release; 101 r = drm_global_item_ref(global_ref); 102 if (r != 0) { 103 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 104 drm_global_item_unref(&rdev->mman.mem_global_ref); 105 return r; 106 } 107 108 rdev->mman.mem_global_referenced = true; 109 return 0; 110 } 111 112 static void radeon_ttm_global_fini(struct radeon_device *rdev) 113 { 114 if (rdev->mman.mem_global_referenced) { 115 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 116 drm_global_item_unref(&rdev->mman.mem_global_ref); 117 rdev->mman.mem_global_referenced = false; 118 } 119 } 120 121 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 122 { 123 return 0; 124 } 125 126 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 127 struct ttm_mem_type_manager *man) 128 { 129 struct radeon_device *rdev; 130 131 rdev = radeon_get_rdev(bdev); 132 133 switch (type) { 134 case TTM_PL_SYSTEM: 135 /* System memory */ 136 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 137 man->available_caching = TTM_PL_MASK_CACHING; 138 man->default_caching = TTM_PL_FLAG_CACHED; 139 break; 140 case TTM_PL_TT: 141 man->func = &ttm_bo_manager_func; 142 man->gpu_offset = rdev->mc.gtt_start; 143 man->available_caching = TTM_PL_MASK_CACHING; 144 man->default_caching = TTM_PL_FLAG_CACHED; 145 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 146 #if __OS_HAS_AGP 147 if (rdev->flags & RADEON_IS_AGP) { 148 if (!rdev->ddev->agp) { 149 DRM_ERROR("AGP is not enabled for memory type %u\n", 150 (unsigned)type); 151 return -EINVAL; 152 } 153 if (!rdev->ddev->agp->cant_use_aperture) 154 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 155 man->available_caching = TTM_PL_FLAG_UNCACHED | 156 TTM_PL_FLAG_WC; 157 man->default_caching = TTM_PL_FLAG_WC; 158 } 159 #endif 160 break; 161 case TTM_PL_VRAM: 162 /* "On-card" video ram */ 163 man->func = &ttm_bo_manager_func; 164 man->gpu_offset = rdev->mc.vram_start; 165 man->flags = TTM_MEMTYPE_FLAG_FIXED | 166 TTM_MEMTYPE_FLAG_MAPPABLE; 167 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 168 man->default_caching = TTM_PL_FLAG_WC; 169 break; 170 default: 171 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 172 return -EINVAL; 173 } 174 return 0; 175 } 176 177 static void radeon_evict_flags(struct ttm_buffer_object *bo, 178 struct ttm_placement *placement) 179 { 180 static struct ttm_place placements = { 181 .fpfn = 0, 182 .lpfn = 0, 183 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 184 }; 185 186 struct radeon_bo *rbo; 187 188 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 189 placement->placement = &placements; 190 placement->busy_placement = &placements; 191 placement->num_placement = 1; 192 placement->num_busy_placement = 1; 193 return; 194 } 195 rbo = container_of(bo, struct radeon_bo, tbo); 196 switch (bo->mem.mem_type) { 197 case TTM_PL_VRAM: 198 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) 199 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 200 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && 201 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { 202 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 203 int i; 204 205 /* Try evicting to the CPU inaccessible part of VRAM 206 * first, but only set GTT as busy placement, so this 207 * BO will be evicted to GTT rather than causing other 208 * BOs to be evicted from VRAM 209 */ 210 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | 211 RADEON_GEM_DOMAIN_GTT); 212 rbo->placement.num_busy_placement = 0; 213 for (i = 0; i < rbo->placement.num_placement; i++) { 214 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { 215 if (rbo->placements[0].fpfn < fpfn) 216 rbo->placements[0].fpfn = fpfn; 217 } else { 218 rbo->placement.busy_placement = 219 &rbo->placements[i]; 220 rbo->placement.num_busy_placement = 1; 221 } 222 } 223 } else 224 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 225 break; 226 case TTM_PL_TT: 227 default: 228 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 229 } 230 *placement = rbo->placement; 231 } 232 233 static int radeon_verify_access(struct ttm_buffer_object *bo) 234 { 235 return 0; 236 } 237 238 static void radeon_move_null(struct ttm_buffer_object *bo, 239 struct ttm_mem_reg *new_mem) 240 { 241 struct ttm_mem_reg *old_mem = &bo->mem; 242 243 BUG_ON(old_mem->mm_node != NULL); 244 *old_mem = *new_mem; 245 new_mem->mm_node = NULL; 246 } 247 248 static int radeon_move_blit(struct ttm_buffer_object *bo, 249 bool evict, bool no_wait_gpu, 250 struct ttm_mem_reg *new_mem, 251 struct ttm_mem_reg *old_mem) 252 { 253 struct radeon_device *rdev; 254 uint64_t old_start, new_start; 255 struct radeon_fence *fence; 256 int r, ridx; 257 258 rdev = radeon_get_rdev(bo->bdev); 259 ridx = radeon_copy_ring_index(rdev); 260 old_start = (u64)old_mem->start << PAGE_SHIFT; 261 new_start = (u64)new_mem->start << PAGE_SHIFT; 262 263 switch (old_mem->mem_type) { 264 case TTM_PL_VRAM: 265 old_start += rdev->mc.vram_start; 266 break; 267 case TTM_PL_TT: 268 old_start += rdev->mc.gtt_start; 269 break; 270 default: 271 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 272 return -EINVAL; 273 } 274 switch (new_mem->mem_type) { 275 case TTM_PL_VRAM: 276 new_start += rdev->mc.vram_start; 277 break; 278 case TTM_PL_TT: 279 new_start += rdev->mc.gtt_start; 280 break; 281 default: 282 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 283 return -EINVAL; 284 } 285 if (!rdev->ring[ridx].ready) { 286 DRM_ERROR("Trying to move memory with ring turned off.\n"); 287 return -EINVAL; 288 } 289 290 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 291 292 /* sync other rings */ 293 fence = bo->sync_obj; 294 r = radeon_copy(rdev, old_start, new_start, 295 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ 296 &fence); 297 /* FIXME: handle copy error */ 298 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, 299 evict, no_wait_gpu, new_mem); 300 radeon_fence_unref(&fence); 301 return r; 302 } 303 304 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 305 bool evict, bool interruptible, 306 bool no_wait_gpu, 307 struct ttm_mem_reg *new_mem) 308 { 309 struct radeon_device *rdev; 310 struct ttm_mem_reg *old_mem = &bo->mem; 311 struct ttm_mem_reg tmp_mem; 312 struct ttm_place placements; 313 struct ttm_placement placement; 314 int r; 315 316 rdev = radeon_get_rdev(bo->bdev); 317 tmp_mem = *new_mem; 318 tmp_mem.mm_node = NULL; 319 placement.num_placement = 1; 320 placement.placement = &placements; 321 placement.num_busy_placement = 1; 322 placement.busy_placement = &placements; 323 placements.fpfn = 0; 324 placements.lpfn = 0; 325 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 326 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 327 interruptible, no_wait_gpu); 328 if (unlikely(r)) { 329 return r; 330 } 331 332 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 333 if (unlikely(r)) { 334 goto out_cleanup; 335 } 336 337 r = ttm_tt_bind(bo->ttm, &tmp_mem); 338 if (unlikely(r)) { 339 goto out_cleanup; 340 } 341 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 342 if (unlikely(r)) { 343 goto out_cleanup; 344 } 345 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 346 out_cleanup: 347 ttm_bo_mem_put(bo, &tmp_mem); 348 return r; 349 } 350 351 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 352 bool evict, bool interruptible, 353 bool no_wait_gpu, 354 struct ttm_mem_reg *new_mem) 355 { 356 struct radeon_device *rdev; 357 struct ttm_mem_reg *old_mem = &bo->mem; 358 struct ttm_mem_reg tmp_mem; 359 struct ttm_placement placement; 360 struct ttm_place placements; 361 int r; 362 363 rdev = radeon_get_rdev(bo->bdev); 364 tmp_mem = *new_mem; 365 tmp_mem.mm_node = NULL; 366 placement.num_placement = 1; 367 placement.placement = &placements; 368 placement.num_busy_placement = 1; 369 placement.busy_placement = &placements; 370 placements.fpfn = 0; 371 placements.lpfn = 0; 372 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 373 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 374 interruptible, no_wait_gpu); 375 if (unlikely(r)) { 376 return r; 377 } 378 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 379 if (unlikely(r)) { 380 goto out_cleanup; 381 } 382 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 383 if (unlikely(r)) { 384 goto out_cleanup; 385 } 386 out_cleanup: 387 ttm_bo_mem_put(bo, &tmp_mem); 388 return r; 389 } 390 391 static int radeon_bo_move(struct ttm_buffer_object *bo, 392 bool evict, bool interruptible, 393 bool no_wait_gpu, 394 struct ttm_mem_reg *new_mem) 395 { 396 struct radeon_device *rdev; 397 struct radeon_bo *rbo; 398 struct ttm_mem_reg *old_mem = &bo->mem; 399 int r; 400 401 /* Can't move a pinned BO */ 402 rbo = container_of(bo, struct radeon_bo, tbo); 403 if (WARN_ON_ONCE(rbo->pin_count > 0)) 404 return -EINVAL; 405 406 rdev = radeon_get_rdev(bo->bdev); 407 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 408 radeon_move_null(bo, new_mem); 409 return 0; 410 } 411 if ((old_mem->mem_type == TTM_PL_TT && 412 new_mem->mem_type == TTM_PL_SYSTEM) || 413 (old_mem->mem_type == TTM_PL_SYSTEM && 414 new_mem->mem_type == TTM_PL_TT)) { 415 /* bind is enough */ 416 radeon_move_null(bo, new_mem); 417 return 0; 418 } 419 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 420 rdev->asic->copy.copy == NULL) { 421 /* use memcpy */ 422 goto memcpy; 423 } 424 425 if (old_mem->mem_type == TTM_PL_VRAM && 426 new_mem->mem_type == TTM_PL_SYSTEM) { 427 r = radeon_move_vram_ram(bo, evict, interruptible, 428 no_wait_gpu, new_mem); 429 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 430 new_mem->mem_type == TTM_PL_VRAM) { 431 r = radeon_move_ram_vram(bo, evict, interruptible, 432 no_wait_gpu, new_mem); 433 } else { 434 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 435 } 436 437 if (r) { 438 memcpy: 439 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 440 if (r) { 441 return r; 442 } 443 } 444 445 /* update statistics */ 446 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 447 return 0; 448 } 449 450 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 451 { 452 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 453 struct radeon_device *rdev = radeon_get_rdev(bdev); 454 455 mem->bus.addr = NULL; 456 mem->bus.offset = 0; 457 mem->bus.size = mem->num_pages << PAGE_SHIFT; 458 mem->bus.base = 0; 459 mem->bus.is_iomem = false; 460 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 461 return -EINVAL; 462 switch (mem->mem_type) { 463 case TTM_PL_SYSTEM: 464 /* system memory */ 465 return 0; 466 case TTM_PL_TT: 467 #if __OS_HAS_AGP 468 if (rdev->flags & RADEON_IS_AGP) { 469 /* RADEON_IS_AGP is set only if AGP is active */ 470 mem->bus.offset = mem->start << PAGE_SHIFT; 471 mem->bus.base = rdev->mc.agp_base; 472 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 473 } 474 #endif 475 break; 476 case TTM_PL_VRAM: 477 mem->bus.offset = mem->start << PAGE_SHIFT; 478 /* check if it's visible */ 479 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 480 return -EINVAL; 481 mem->bus.base = rdev->mc.aper_base; 482 mem->bus.is_iomem = true; 483 #ifdef __alpha__ 484 /* 485 * Alpha: use bus.addr to hold the ioremap() return, 486 * so we can modify bus.base below. 487 */ 488 if (mem->placement & TTM_PL_FLAG_WC) 489 mem->bus.addr = 490 ioremap_wc(mem->bus.base + mem->bus.offset, 491 mem->bus.size); 492 else 493 mem->bus.addr = 494 ioremap_nocache(mem->bus.base + mem->bus.offset, 495 mem->bus.size); 496 497 /* 498 * Alpha: Use just the bus offset plus 499 * the hose/domain memory base for bus.base. 500 * It then can be used to build PTEs for VRAM 501 * access, as done in ttm_bo_vm_fault(). 502 */ 503 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 504 rdev->ddev->hose->dense_mem_base; 505 #endif 506 break; 507 default: 508 return -EINVAL; 509 } 510 return 0; 511 } 512 513 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 514 { 515 } 516 517 static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) 518 { 519 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); 520 } 521 522 static int radeon_sync_obj_flush(void *sync_obj) 523 { 524 return 0; 525 } 526 527 static void radeon_sync_obj_unref(void **sync_obj) 528 { 529 radeon_fence_unref((struct radeon_fence **)sync_obj); 530 } 531 532 static void *radeon_sync_obj_ref(void *sync_obj) 533 { 534 return radeon_fence_ref((struct radeon_fence *)sync_obj); 535 } 536 537 static bool radeon_sync_obj_signaled(void *sync_obj) 538 { 539 return radeon_fence_signaled((struct radeon_fence *)sync_obj); 540 } 541 542 /* 543 * TTM backend functions. 544 */ 545 struct radeon_ttm_tt { 546 struct ttm_dma_tt ttm; 547 struct radeon_device *rdev; 548 u64 offset; 549 }; 550 551 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 552 struct ttm_mem_reg *bo_mem) 553 { 554 struct radeon_ttm_tt *gtt = (void*)ttm; 555 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 556 RADEON_GART_PAGE_WRITE; 557 int r; 558 559 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 560 if (!ttm->num_pages) { 561 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 562 ttm->num_pages, bo_mem, ttm); 563 } 564 if (ttm->caching_state == tt_cached) 565 flags |= RADEON_GART_PAGE_SNOOP; 566 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, 567 ttm->pages, gtt->ttm.dma_address, flags); 568 if (r) { 569 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 570 ttm->num_pages, (unsigned)gtt->offset); 571 return r; 572 } 573 return 0; 574 } 575 576 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 577 { 578 struct radeon_ttm_tt *gtt = (void *)ttm; 579 580 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 581 return 0; 582 } 583 584 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 585 { 586 struct radeon_ttm_tt *gtt = (void *)ttm; 587 588 ttm_dma_tt_fini(>t->ttm); 589 kfree(gtt); 590 } 591 592 static struct ttm_backend_func radeon_backend_func = { 593 .bind = &radeon_ttm_backend_bind, 594 .unbind = &radeon_ttm_backend_unbind, 595 .destroy = &radeon_ttm_backend_destroy, 596 }; 597 598 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 599 unsigned long size, uint32_t page_flags, 600 vm_page_t dummy_read_page) 601 { 602 struct radeon_device *rdev; 603 struct radeon_ttm_tt *gtt; 604 605 rdev = radeon_get_rdev(bdev); 606 #if __OS_HAS_AGP 607 #ifdef DUMBBELL_WIP 608 if (rdev->flags & RADEON_IS_AGP) { 609 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev, 610 size, page_flags, dummy_read_page); 611 } 612 #endif /* DUMBBELL_WIP */ 613 #endif 614 615 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 616 if (gtt == NULL) { 617 return NULL; 618 } 619 gtt->ttm.ttm.func = &radeon_backend_func; 620 gtt->rdev = rdev; 621 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 622 kfree(gtt); 623 return NULL; 624 } 625 return >t->ttm.ttm; 626 } 627 628 static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 629 { 630 struct radeon_device *rdev; 631 struct radeon_ttm_tt *gtt = (void *)ttm; 632 unsigned i; 633 int r; 634 #ifdef DUMBBELL_WIP 635 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 636 #endif /* DUMBBELL_WIP */ 637 638 if (ttm->state != tt_unpopulated) 639 return 0; 640 641 #ifdef DUMBBELL_WIP 642 /* 643 * Maybe unneeded on FreeBSD. 644 * -- dumbbell@ 645 */ 646 if (slave && ttm->sg) { 647 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 648 gtt->ttm.dma_address, ttm->num_pages); 649 ttm->state = tt_unbound; 650 return 0; 651 } 652 #endif /* DUMBBELL_WIP */ 653 654 rdev = radeon_get_rdev(ttm->bdev); 655 #if __OS_HAS_AGP 656 #ifdef DUMBBELL_WIP 657 if (rdev->flags & RADEON_IS_AGP) { 658 return ttm_agp_tt_populate(ttm); 659 } 660 #endif /* DUMBBELL_WIP */ 661 #endif 662 663 #ifdef CONFIG_SWIOTLB 664 if (swiotlb_nr_tbl()) { 665 return ttm_dma_populate(>t->ttm, rdev->dev); 666 } 667 #endif 668 669 r = ttm_pool_populate(ttm); 670 if (r) { 671 return r; 672 } 673 674 for (i = 0; i < ttm->num_pages; i++) { 675 gtt->ttm.dma_address[i] = VM_PAGE_TO_PHYS(ttm->pages[i]); 676 #ifdef DUMBBELL_WIP 677 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 678 0, PAGE_SIZE, 679 PCI_DMA_BIDIRECTIONAL); 680 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { 681 while (i--) { 682 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 683 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 684 gtt->ttm.dma_address[i] = 0; 685 } 686 ttm_pool_unpopulate(ttm); 687 return -EFAULT; 688 } 689 #endif /* DUMBBELL_WIP */ 690 } 691 return 0; 692 } 693 694 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 695 { 696 struct radeon_device *rdev; 697 struct radeon_ttm_tt *gtt = (void *)ttm; 698 unsigned i; 699 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 700 701 if (slave) 702 return; 703 704 rdev = radeon_get_rdev(ttm->bdev); 705 #if __OS_HAS_AGP 706 #ifdef DUMBBELL_WIP 707 if (rdev->flags & RADEON_IS_AGP) { 708 ttm_agp_tt_unpopulate(ttm); 709 return; 710 } 711 #endif /* DUMBBELL_WIP */ 712 #endif 713 714 #ifdef CONFIG_SWIOTLB 715 if (swiotlb_nr_tbl()) { 716 ttm_dma_unpopulate(>t->ttm, rdev->dev); 717 return; 718 } 719 #endif 720 721 for (i = 0; i < ttm->num_pages; i++) { 722 if (gtt->ttm.dma_address[i]) { 723 gtt->ttm.dma_address[i] = 0; 724 #ifdef DUMBBELL_WIP 725 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 726 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 727 #endif /* DUMBBELL_WIP */ 728 } 729 } 730 731 ttm_pool_unpopulate(ttm); 732 } 733 734 static struct ttm_bo_driver radeon_bo_driver = { 735 .ttm_tt_create = &radeon_ttm_tt_create, 736 .ttm_tt_populate = &radeon_ttm_tt_populate, 737 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 738 .invalidate_caches = &radeon_invalidate_caches, 739 .init_mem_type = &radeon_init_mem_type, 740 .evict_flags = &radeon_evict_flags, 741 .move = &radeon_bo_move, 742 .verify_access = &radeon_verify_access, 743 .sync_obj_signaled = &radeon_sync_obj_signaled, 744 .sync_obj_wait = &radeon_sync_obj_wait, 745 .sync_obj_flush = &radeon_sync_obj_flush, 746 .sync_obj_unref = &radeon_sync_obj_unref, 747 .sync_obj_ref = &radeon_sync_obj_ref, 748 .move_notify = &radeon_bo_move_notify, 749 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 750 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 751 .io_mem_free = &radeon_ttm_io_mem_free, 752 }; 753 754 int radeon_ttm_init(struct radeon_device *rdev) 755 { 756 int r; 757 758 r = radeon_ttm_global_init(rdev); 759 if (r) { 760 return r; 761 } 762 /* No others user of address space so set it to 0 */ 763 r = ttm_bo_device_init(&rdev->mman.bdev, 764 rdev->mman.bo_global_ref.ref.object, 765 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, 766 rdev->need_dma32); 767 if (r) { 768 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 769 return r; 770 } 771 rdev->mman.initialized = true; 772 rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev; 773 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 774 rdev->mc.real_vram_size >> PAGE_SHIFT); 775 if (r) { 776 DRM_ERROR("Failed initializing VRAM heap.\n"); 777 return r; 778 } 779 /* Change the size here instead of the init above so only lpfn is affected */ 780 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 781 782 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 783 RADEON_GEM_DOMAIN_VRAM, 0, 784 NULL, &rdev->stollen_vga_memory); 785 if (r) { 786 return r; 787 } 788 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 789 if (r) 790 return r; 791 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 792 radeon_bo_unreserve(rdev->stollen_vga_memory); 793 if (r) { 794 radeon_bo_unref(&rdev->stollen_vga_memory); 795 return r; 796 } 797 DRM_INFO("radeon: %uM of VRAM memory ready\n", 798 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 799 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 800 rdev->mc.gtt_size >> PAGE_SHIFT); 801 if (r) { 802 DRM_ERROR("Failed initializing GTT heap.\n"); 803 return r; 804 } 805 DRM_INFO("radeon: %uM of GTT memory ready.\n", 806 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 807 808 r = radeon_ttm_debugfs_init(rdev); 809 if (r) { 810 DRM_ERROR("Failed to init debugfs\n"); 811 return r; 812 } 813 return 0; 814 } 815 816 void radeon_ttm_fini(struct radeon_device *rdev) 817 { 818 int r; 819 820 if (!rdev->mman.initialized) 821 return; 822 radeon_ttm_debugfs_fini(rdev); 823 if (rdev->stollen_vga_memory) { 824 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 825 if (r == 0) { 826 radeon_bo_unpin(rdev->stollen_vga_memory); 827 radeon_bo_unreserve(rdev->stollen_vga_memory); 828 } 829 radeon_bo_unref(&rdev->stollen_vga_memory); 830 } 831 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 832 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 833 ttm_bo_device_release(&rdev->mman.bdev); 834 radeon_gart_fini(rdev); 835 radeon_ttm_global_fini(rdev); 836 rdev->mman.initialized = false; 837 DRM_INFO("radeon: ttm finalized\n"); 838 } 839 840 /* this should only be called at bootup or when userspace 841 * isn't running */ 842 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 843 { 844 struct ttm_mem_type_manager *man; 845 846 if (!rdev->mman.initialized) 847 return; 848 849 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 850 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 851 man->size = size >> PAGE_SHIFT; 852 } 853 854 #ifdef DUMBBELL_WIP 855 static struct vm_operations_struct radeon_ttm_vm_ops; 856 static const struct vm_operations_struct *ttm_vm_ops = NULL; 857 858 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 859 { 860 struct ttm_buffer_object *bo; 861 struct radeon_device *rdev; 862 int r; 863 864 bo = (struct ttm_buffer_object *)vma->vm_private_data; 865 if (bo == NULL) { 866 return VM_FAULT_NOPAGE; 867 } 868 rdev = radeon_get_rdev(bo->bdev); 869 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 870 r = ttm_vm_ops->fault(vma, vmf); 871 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 872 return r; 873 } 874 875 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 876 { 877 struct drm_file *file_priv; 878 struct radeon_device *rdev; 879 int r; 880 881 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { 882 return -EINVAL; 883 } 884 885 file_priv = filp->private_data; 886 rdev = file_priv->minor->dev->dev_private; 887 if (rdev == NULL) { 888 return -EINVAL; 889 } 890 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 891 if (unlikely(r != 0)) { 892 return r; 893 } 894 if (unlikely(ttm_vm_ops == NULL)) { 895 ttm_vm_ops = vma->vm_ops; 896 radeon_ttm_vm_ops = *ttm_vm_ops; 897 radeon_ttm_vm_ops.fault = &radeon_ttm_fault; 898 } 899 vma->vm_ops = &radeon_ttm_vm_ops; 900 return 0; 901 } 902 #endif /* DUMBBELL_WIP */ 903 904 #if defined(CONFIG_DEBUG_FS) 905 906 static int radeon_mm_dump_table(struct seq_file *m, void *data) 907 { 908 struct drm_info_node *node = (struct drm_info_node *)m->private; 909 unsigned ttm_pl = *(int *)node->info_ent->data; 910 struct drm_device *dev = node->minor->dev; 911 struct radeon_device *rdev = dev->dev_private; 912 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; 913 int ret; 914 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 915 916 spin_lock(&glob->lru_lock); 917 ret = drm_mm_dump_table(m, mm); 918 spin_unlock(&glob->lru_lock); 919 return ret; 920 } 921 922 static int ttm_pl_vram = TTM_PL_VRAM; 923 static int ttm_pl_tt = TTM_PL_TT; 924 925 static struct drm_info_list radeon_ttm_debugfs_list[] = { 926 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 927 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 928 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 929 #ifdef CONFIG_SWIOTLB 930 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 931 #endif 932 }; 933 934 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 935 { 936 struct radeon_device *rdev = inode->i_private; 937 i_size_write(inode, rdev->mc.mc_vram_size); 938 filep->private_data = inode->i_private; 939 return 0; 940 } 941 942 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 943 size_t size, loff_t *pos) 944 { 945 struct radeon_device *rdev = f->private_data; 946 ssize_t result = 0; 947 int r; 948 949 if (size & 0x3 || *pos & 0x3) 950 return -EINVAL; 951 952 while (size) { 953 unsigned long flags; 954 uint32_t value; 955 956 if (*pos >= rdev->mc.mc_vram_size) 957 return result; 958 959 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 960 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 961 if (rdev->family >= CHIP_CEDAR) 962 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 963 value = RREG32(RADEON_MM_DATA); 964 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 965 966 r = put_user(value, (uint32_t *)buf); 967 if (r) 968 return r; 969 970 result += 4; 971 buf += 4; 972 *pos += 4; 973 size -= 4; 974 } 975 976 return result; 977 } 978 979 static const struct file_operations radeon_ttm_vram_fops = { 980 .owner = THIS_MODULE, 981 .open = radeon_ttm_vram_open, 982 .read = radeon_ttm_vram_read, 983 .llseek = default_llseek 984 }; 985 986 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 987 { 988 struct radeon_device *rdev = inode->i_private; 989 i_size_write(inode, rdev->mc.gtt_size); 990 filep->private_data = inode->i_private; 991 return 0; 992 } 993 994 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 995 size_t size, loff_t *pos) 996 { 997 struct radeon_device *rdev = f->private_data; 998 ssize_t result = 0; 999 int r; 1000 1001 while (size) { 1002 loff_t p = *pos / PAGE_SIZE; 1003 unsigned off = *pos & ~PAGE_MASK; 1004 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1005 struct page *page; 1006 void *ptr; 1007 1008 if (p >= rdev->gart.num_cpu_pages) 1009 return result; 1010 1011 page = rdev->gart.pages[p]; 1012 if (page) { 1013 ptr = kmap(page); 1014 ptr += off; 1015 1016 r = copy_to_user(buf, ptr, cur_size); 1017 kunmap(rdev->gart.pages[p]); 1018 } else 1019 r = clear_user(buf, cur_size); 1020 1021 if (r) 1022 return -EFAULT; 1023 1024 result += cur_size; 1025 buf += cur_size; 1026 *pos += cur_size; 1027 size -= cur_size; 1028 } 1029 1030 return result; 1031 } 1032 1033 static const struct file_operations radeon_ttm_gtt_fops = { 1034 .owner = THIS_MODULE, 1035 .open = radeon_ttm_gtt_open, 1036 .read = radeon_ttm_gtt_read, 1037 .llseek = default_llseek 1038 }; 1039 1040 #endif 1041 1042 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1043 { 1044 #if defined(CONFIG_DEBUG_FS) 1045 unsigned count; 1046 1047 struct drm_minor *minor = rdev->ddev->primary; 1048 struct dentry *ent, *root = minor->debugfs_root; 1049 1050 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, 1051 rdev, &radeon_ttm_vram_fops); 1052 if (IS_ERR(ent)) 1053 return PTR_ERR(ent); 1054 rdev->mman.vram = ent; 1055 1056 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, 1057 rdev, &radeon_ttm_gtt_fops); 1058 if (IS_ERR(ent)) 1059 return PTR_ERR(ent); 1060 rdev->mman.gtt = ent; 1061 1062 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1063 1064 #ifdef CONFIG_SWIOTLB 1065 if (!swiotlb_nr_tbl()) 1066 --count; 1067 #endif 1068 1069 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1070 #else 1071 1072 return 0; 1073 #endif 1074 } 1075 1076 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1077 { 1078 #if defined(CONFIG_DEBUG_FS) 1079 1080 debugfs_remove(rdev->mman.vram); 1081 rdev->mman.vram = NULL; 1082 1083 debugfs_remove(rdev->mman.gtt); 1084 rdev->mman.gtt = NULL; 1085 #endif 1086 } 1087