1c6f73aabSFrançois Tigeot /* 2c6f73aabSFrançois Tigeot * Copyright 2008 Advanced Micro Devices, Inc. 3c6f73aabSFrançois Tigeot * Copyright 2008 Red Hat Inc. 4c6f73aabSFrançois Tigeot * Copyright 2009 Jerome Glisse. 5c6f73aabSFrançois Tigeot * 6c6f73aabSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 7c6f73aabSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 8c6f73aabSFrançois Tigeot * to deal in the Software without restriction, including without limitation 9c6f73aabSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10c6f73aabSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 11c6f73aabSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 12c6f73aabSFrançois Tigeot * 13c6f73aabSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 14c6f73aabSFrançois Tigeot * all copies or substantial portions of the Software. 15c6f73aabSFrançois Tigeot * 16c6f73aabSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17c6f73aabSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18c6f73aabSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19c6f73aabSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20c6f73aabSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21c6f73aabSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22c6f73aabSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 23c6f73aabSFrançois Tigeot * 24c6f73aabSFrançois Tigeot * Authors: Dave Airlie 25c6f73aabSFrançois Tigeot * Alex Deucher 26c6f73aabSFrançois Tigeot * Jerome Glisse 27c6f73aabSFrançois Tigeot */ 28c6f73aabSFrançois Tigeot #include <drm/drmP.h> 2983b4b9b9SFrançois Tigeot #include <drm/radeon_drm.h> 30c6f73aabSFrançois Tigeot #include "radeon.h" 31c6f73aabSFrançois Tigeot #include "radeon_trace.h" 32c6f73aabSFrançois Tigeot 33c6f73aabSFrançois Tigeot /* 34c6f73aabSFrançois Tigeot * GPUVM 35c6f73aabSFrançois Tigeot * GPUVM is similar to the legacy gart on older asics, however 36c6f73aabSFrançois Tigeot * rather than there being a single global gart table 37c6f73aabSFrançois Tigeot * for the entire GPU, there are multiple VM page tables active 38c6f73aabSFrançois Tigeot * at any given time. The VM page tables can contain a mix 39c6f73aabSFrançois Tigeot * vram pages and system memory pages and system memory pages 40c6f73aabSFrançois Tigeot * can be mapped as snooped (cached system pages) or unsnooped 41c6f73aabSFrançois Tigeot * (uncached system pages). 42c6f73aabSFrançois Tigeot * Each VM has an ID associated with it and there is a page table 43c6f73aabSFrançois Tigeot * associated with each VMID. When execting a command buffer, 44c6f73aabSFrançois Tigeot * the kernel tells the the ring what VMID to use for that command 45c6f73aabSFrançois Tigeot * buffer. VMIDs are allocated dynamically as commands are submitted. 46c6f73aabSFrançois Tigeot * The userspace drivers maintain their own address space and the kernel 47c6f73aabSFrançois Tigeot * sets up their pages tables accordingly when they submit their 48c6f73aabSFrançois Tigeot * command buffers and a VMID is assigned. 49c6f73aabSFrançois Tigeot * Cayman/Trinity support up to 8 active VMs at any given time; 50c6f73aabSFrançois Tigeot * SI supports 16. 51c6f73aabSFrançois Tigeot */ 52c6f73aabSFrançois Tigeot 53c6f73aabSFrançois Tigeot /** 54c6f73aabSFrançois Tigeot * radeon_vm_num_pde - return the number of page directory entries 55c6f73aabSFrançois Tigeot * 56c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 57c6f73aabSFrançois Tigeot * 58c6f73aabSFrançois Tigeot * Calculate the number of page directory entries (cayman+). 59c6f73aabSFrançois Tigeot */ 60c6f73aabSFrançois Tigeot static unsigned radeon_vm_num_pdes(struct radeon_device *rdev) 61c6f73aabSFrançois Tigeot { 62c6f73aabSFrançois Tigeot return rdev->vm_manager.max_pfn >> radeon_vm_block_size; 63c6f73aabSFrançois Tigeot } 64c6f73aabSFrançois Tigeot 65c6f73aabSFrançois Tigeot /** 66c6f73aabSFrançois Tigeot * radeon_vm_directory_size - returns the size of the page directory in bytes 67c6f73aabSFrançois Tigeot * 68c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 69c6f73aabSFrançois Tigeot * 70c6f73aabSFrançois Tigeot * Calculate the size of the page directory in bytes (cayman+). 71c6f73aabSFrançois Tigeot */ 72c6f73aabSFrançois Tigeot static unsigned radeon_vm_directory_size(struct radeon_device *rdev) 73c6f73aabSFrançois Tigeot { 74c6f73aabSFrançois Tigeot return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8); 75c6f73aabSFrançois Tigeot } 76c6f73aabSFrançois Tigeot 77c6f73aabSFrançois Tigeot /** 78c6f73aabSFrançois Tigeot * radeon_vm_manager_init - init the vm manager 79c6f73aabSFrançois Tigeot * 80c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 81c6f73aabSFrançois Tigeot * 82c6f73aabSFrançois Tigeot * Init the vm manager (cayman+). 83c6f73aabSFrançois Tigeot * Returns 0 for success, error for failure. 84c6f73aabSFrançois Tigeot */ 85c6f73aabSFrançois Tigeot int radeon_vm_manager_init(struct radeon_device *rdev) 86c6f73aabSFrançois Tigeot { 87c6f73aabSFrançois Tigeot int r; 88c6f73aabSFrançois Tigeot 89c6f73aabSFrançois Tigeot if (!rdev->vm_manager.enabled) { 90c6f73aabSFrançois Tigeot r = radeon_asic_vm_init(rdev); 91c6f73aabSFrançois Tigeot if (r) 92c6f73aabSFrançois Tigeot return r; 93c6f73aabSFrançois Tigeot 94c6f73aabSFrançois Tigeot rdev->vm_manager.enabled = true; 95c6f73aabSFrançois Tigeot } 96c6f73aabSFrançois Tigeot return 0; 97c6f73aabSFrançois Tigeot } 98c6f73aabSFrançois Tigeot 99c6f73aabSFrançois Tigeot /** 100c6f73aabSFrançois Tigeot * radeon_vm_manager_fini - tear down the vm manager 101c6f73aabSFrançois Tigeot * 102c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 103c6f73aabSFrançois Tigeot * 104c6f73aabSFrançois Tigeot * Tear down the VM manager (cayman+). 105c6f73aabSFrançois Tigeot */ 106c6f73aabSFrançois Tigeot void radeon_vm_manager_fini(struct radeon_device *rdev) 107c6f73aabSFrançois Tigeot { 108c6f73aabSFrançois Tigeot int i; 109c6f73aabSFrançois Tigeot 110c6f73aabSFrançois Tigeot if (!rdev->vm_manager.enabled) 111c6f73aabSFrançois Tigeot return; 112c6f73aabSFrançois Tigeot 113c6f73aabSFrançois Tigeot for (i = 0; i < RADEON_NUM_VM; ++i) 114c6f73aabSFrançois Tigeot radeon_fence_unref(&rdev->vm_manager.active[i]); 115c6f73aabSFrançois Tigeot radeon_asic_vm_fini(rdev); 116c6f73aabSFrançois Tigeot rdev->vm_manager.enabled = false; 117c6f73aabSFrançois Tigeot } 118c6f73aabSFrançois Tigeot 119c6f73aabSFrançois Tigeot /** 120c6f73aabSFrançois Tigeot * radeon_vm_get_bos - add the vm BOs to a validation list 121c6f73aabSFrançois Tigeot * 122c6f73aabSFrançois Tigeot * @vm: vm providing the BOs 123c6f73aabSFrançois Tigeot * @head: head of validation list 124c6f73aabSFrançois Tigeot * 125c6f73aabSFrançois Tigeot * Add the page directory to the list of BOs to 126c6f73aabSFrançois Tigeot * validate for command submission (cayman+). 127c6f73aabSFrançois Tigeot */ 1287dcf36dcSFrançois Tigeot struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 129c6f73aabSFrançois Tigeot struct radeon_vm *vm, 130c6f73aabSFrançois Tigeot struct list_head *head) 131c6f73aabSFrançois Tigeot { 1327dcf36dcSFrançois Tigeot struct radeon_bo_list *list; 133c6f73aabSFrançois Tigeot unsigned i, idx; 134c6f73aabSFrançois Tigeot 135591d5043SFrançois Tigeot list = drm_malloc_ab(vm->max_pde_used + 2, 1367dcf36dcSFrançois Tigeot sizeof(struct radeon_bo_list)); 137c6f73aabSFrançois Tigeot if (!list) 138c6f73aabSFrançois Tigeot return NULL; 139c6f73aabSFrançois Tigeot 140c6f73aabSFrançois Tigeot /* add the vm page table to the list */ 141c6f73aabSFrançois Tigeot list[0].robj = vm->page_directory; 142c6f73aabSFrançois Tigeot list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM; 143c6f73aabSFrançois Tigeot list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM; 144c6f73aabSFrançois Tigeot list[0].tv.bo = &vm->page_directory->tbo; 1457dcf36dcSFrançois Tigeot list[0].tv.shared = true; 146c6f73aabSFrançois Tigeot list[0].tiling_flags = 0; 147c6f73aabSFrançois Tigeot list_add(&list[0].tv.head, head); 148c6f73aabSFrançois Tigeot 149c6f73aabSFrançois Tigeot for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { 150c6f73aabSFrançois Tigeot if (!vm->page_tables[i].bo) 151c6f73aabSFrançois Tigeot continue; 152c6f73aabSFrançois Tigeot 153c6f73aabSFrançois Tigeot list[idx].robj = vm->page_tables[i].bo; 154c6f73aabSFrançois Tigeot list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM; 155c6f73aabSFrançois Tigeot list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM; 156c6f73aabSFrançois Tigeot list[idx].tv.bo = &list[idx].robj->tbo; 1577dcf36dcSFrançois Tigeot list[idx].tv.shared = true; 158c6f73aabSFrançois Tigeot list[idx].tiling_flags = 0; 159c6f73aabSFrançois Tigeot list_add(&list[idx++].tv.head, head); 160c6f73aabSFrançois Tigeot } 161c6f73aabSFrançois Tigeot 162c6f73aabSFrançois Tigeot return list; 163c6f73aabSFrançois Tigeot } 164c6f73aabSFrançois Tigeot 165c6f73aabSFrançois Tigeot /** 166c6f73aabSFrançois Tigeot * radeon_vm_grab_id - allocate the next free VMID 167c6f73aabSFrançois Tigeot * 168c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 169c6f73aabSFrançois Tigeot * @vm: vm to allocate id for 170c6f73aabSFrançois Tigeot * @ring: ring we want to submit job to 171c6f73aabSFrançois Tigeot * 172c6f73aabSFrançois Tigeot * Allocate an id for the vm (cayman+). 173c6f73aabSFrançois Tigeot * Returns the fence we need to sync to (if any). 174c6f73aabSFrançois Tigeot * 175c6f73aabSFrançois Tigeot * Global and local mutex must be locked! 176c6f73aabSFrançois Tigeot */ 177c6f73aabSFrançois Tigeot struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 178c6f73aabSFrançois Tigeot struct radeon_vm *vm, int ring) 179c6f73aabSFrançois Tigeot { 180c6f73aabSFrançois Tigeot struct radeon_fence *best[RADEON_NUM_RINGS] = {}; 1817dcf36dcSFrançois Tigeot struct radeon_vm_id *vm_id = &vm->ids[ring]; 1827dcf36dcSFrançois Tigeot 183c6f73aabSFrançois Tigeot unsigned choices[2] = {}; 184c6f73aabSFrançois Tigeot unsigned i; 185c6f73aabSFrançois Tigeot 186c6f73aabSFrançois Tigeot /* check if the id is still valid */ 1877dcf36dcSFrançois Tigeot if (vm_id->id && vm_id->last_id_use && 1887dcf36dcSFrançois Tigeot vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) 189c6f73aabSFrançois Tigeot return NULL; 190c6f73aabSFrançois Tigeot 191c6f73aabSFrançois Tigeot /* we definately need to flush */ 1927dcf36dcSFrançois Tigeot vm_id->pd_gpu_addr = ~0ll; 193c6f73aabSFrançois Tigeot 194c6f73aabSFrançois Tigeot /* skip over VMID 0, since it is the system VM */ 195c6f73aabSFrançois Tigeot for (i = 1; i < rdev->vm_manager.nvm; ++i) { 196c6f73aabSFrançois Tigeot struct radeon_fence *fence = rdev->vm_manager.active[i]; 197c6f73aabSFrançois Tigeot 198c6f73aabSFrançois Tigeot if (fence == NULL) { 199c6f73aabSFrançois Tigeot /* found a free one */ 2007dcf36dcSFrançois Tigeot vm_id->id = i; 2017dcf36dcSFrançois Tigeot trace_radeon_vm_grab_id(i, ring); 202c6f73aabSFrançois Tigeot return NULL; 203c6f73aabSFrançois Tigeot } 204c6f73aabSFrançois Tigeot 205c6f73aabSFrançois Tigeot if (radeon_fence_is_earlier(fence, best[fence->ring])) { 206c6f73aabSFrançois Tigeot best[fence->ring] = fence; 207c6f73aabSFrançois Tigeot choices[fence->ring == ring ? 0 : 1] = i; 208c6f73aabSFrançois Tigeot } 209c6f73aabSFrançois Tigeot } 210c6f73aabSFrançois Tigeot 211c6f73aabSFrançois Tigeot for (i = 0; i < 2; ++i) { 212c6f73aabSFrançois Tigeot if (choices[i]) { 2137dcf36dcSFrançois Tigeot vm_id->id = choices[i]; 2147dcf36dcSFrançois Tigeot trace_radeon_vm_grab_id(choices[i], ring); 215c6f73aabSFrançois Tigeot return rdev->vm_manager.active[choices[i]]; 216c6f73aabSFrançois Tigeot } 217c6f73aabSFrançois Tigeot } 218c6f73aabSFrançois Tigeot 219c6f73aabSFrançois Tigeot /* should never happen */ 220c6f73aabSFrançois Tigeot BUG(); 221c6f73aabSFrançois Tigeot return NULL; 222c6f73aabSFrançois Tigeot } 223c6f73aabSFrançois Tigeot 224c6f73aabSFrançois Tigeot /** 225c6f73aabSFrançois Tigeot * radeon_vm_flush - hardware flush the vm 226c6f73aabSFrançois Tigeot * 227c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 228c6f73aabSFrançois Tigeot * @vm: vm we want to flush 229c6f73aabSFrançois Tigeot * @ring: ring to use for flush 2307dcf36dcSFrançois Tigeot * @updates: last vm update that is waited for 231c6f73aabSFrançois Tigeot * 232c6f73aabSFrançois Tigeot * Flush the vm (cayman+). 233c6f73aabSFrançois Tigeot * 234c6f73aabSFrançois Tigeot * Global and local mutex must be locked! 235c6f73aabSFrançois Tigeot */ 236c6f73aabSFrançois Tigeot void radeon_vm_flush(struct radeon_device *rdev, 237c6f73aabSFrançois Tigeot struct radeon_vm *vm, 2387dcf36dcSFrançois Tigeot int ring, struct radeon_fence *updates) 239c6f73aabSFrançois Tigeot { 240c6f73aabSFrançois Tigeot uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory); 2417dcf36dcSFrançois Tigeot struct radeon_vm_id *vm_id = &vm->ids[ring]; 242c6f73aabSFrançois Tigeot 2437dcf36dcSFrançois Tigeot if (pd_addr != vm_id->pd_gpu_addr || !vm_id->flushed_updates || 2447dcf36dcSFrançois Tigeot radeon_fence_is_earlier(vm_id->flushed_updates, updates)) { 2457dcf36dcSFrançois Tigeot 2467dcf36dcSFrançois Tigeot trace_radeon_vm_flush(pd_addr, ring, vm->ids[ring].id); 2477dcf36dcSFrançois Tigeot radeon_fence_unref(&vm_id->flushed_updates); 2487dcf36dcSFrançois Tigeot vm_id->flushed_updates = radeon_fence_ref(updates); 2497dcf36dcSFrançois Tigeot vm_id->pd_gpu_addr = pd_addr; 2507dcf36dcSFrançois Tigeot radeon_ring_vm_flush(rdev, &rdev->ring[ring], 2517dcf36dcSFrançois Tigeot vm_id->id, vm_id->pd_gpu_addr); 2527dcf36dcSFrançois Tigeot 253c6f73aabSFrançois Tigeot } 254c6f73aabSFrançois Tigeot } 255c6f73aabSFrançois Tigeot 256c6f73aabSFrançois Tigeot /** 257c6f73aabSFrançois Tigeot * radeon_vm_fence - remember fence for vm 258c6f73aabSFrançois Tigeot * 259c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 260c6f73aabSFrançois Tigeot * @vm: vm we want to fence 261c6f73aabSFrançois Tigeot * @fence: fence to remember 262c6f73aabSFrançois Tigeot * 263c6f73aabSFrançois Tigeot * Fence the vm (cayman+). 264c6f73aabSFrançois Tigeot * Set the fence used to protect page table and id. 265c6f73aabSFrançois Tigeot * 266c6f73aabSFrançois Tigeot * Global and local mutex must be locked! 267c6f73aabSFrançois Tigeot */ 268c6f73aabSFrançois Tigeot void radeon_vm_fence(struct radeon_device *rdev, 269c6f73aabSFrançois Tigeot struct radeon_vm *vm, 270c6f73aabSFrançois Tigeot struct radeon_fence *fence) 271c6f73aabSFrançois Tigeot { 2727dcf36dcSFrançois Tigeot unsigned vm_id = vm->ids[fence->ring].id; 273c6f73aabSFrançois Tigeot 2747dcf36dcSFrançois Tigeot radeon_fence_unref(&rdev->vm_manager.active[vm_id]); 2757dcf36dcSFrançois Tigeot rdev->vm_manager.active[vm_id] = radeon_fence_ref(fence); 276c6f73aabSFrançois Tigeot 2777dcf36dcSFrançois Tigeot radeon_fence_unref(&vm->ids[fence->ring].last_id_use); 2787dcf36dcSFrançois Tigeot vm->ids[fence->ring].last_id_use = radeon_fence_ref(fence); 279c6f73aabSFrançois Tigeot } 280c6f73aabSFrançois Tigeot 281c6f73aabSFrançois Tigeot /** 282c6f73aabSFrançois Tigeot * radeon_vm_bo_find - find the bo_va for a specific vm & bo 283c6f73aabSFrançois Tigeot * 284c6f73aabSFrançois Tigeot * @vm: requested vm 285c6f73aabSFrançois Tigeot * @bo: requested buffer object 286c6f73aabSFrançois Tigeot * 287c6f73aabSFrançois Tigeot * Find @bo inside the requested vm (cayman+). 288c6f73aabSFrançois Tigeot * Search inside the @bos vm list for the requested vm 289c6f73aabSFrançois Tigeot * Returns the found bo_va or NULL if none is found 290c6f73aabSFrançois Tigeot * 291c6f73aabSFrançois Tigeot * Object has to be reserved! 292c6f73aabSFrançois Tigeot */ 293c6f73aabSFrançois Tigeot struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 294c6f73aabSFrançois Tigeot struct radeon_bo *bo) 295c6f73aabSFrançois Tigeot { 296c6f73aabSFrançois Tigeot struct radeon_bo_va *bo_va; 297c6f73aabSFrançois Tigeot 298c6f73aabSFrançois Tigeot list_for_each_entry(bo_va, &bo->va, bo_list) { 299c6f73aabSFrançois Tigeot if (bo_va->vm == vm) { 300c6f73aabSFrançois Tigeot return bo_va; 301c6f73aabSFrançois Tigeot } 302c6f73aabSFrançois Tigeot } 303c6f73aabSFrançois Tigeot return NULL; 304c6f73aabSFrançois Tigeot } 305c6f73aabSFrançois Tigeot 306c6f73aabSFrançois Tigeot /** 307c6f73aabSFrançois Tigeot * radeon_vm_bo_add - add a bo to a specific vm 308c6f73aabSFrançois Tigeot * 309c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 310c6f73aabSFrançois Tigeot * @vm: requested vm 311c6f73aabSFrançois Tigeot * @bo: radeon buffer object 312c6f73aabSFrançois Tigeot * 313c6f73aabSFrançois Tigeot * Add @bo into the requested vm (cayman+). 314c6f73aabSFrançois Tigeot * Add @bo to the list of bos associated with the vm 315c6f73aabSFrançois Tigeot * Returns newly added bo_va or NULL for failure 316c6f73aabSFrançois Tigeot * 317c6f73aabSFrançois Tigeot * Object has to be reserved! 318c6f73aabSFrançois Tigeot */ 319c6f73aabSFrançois Tigeot struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 320c6f73aabSFrançois Tigeot struct radeon_vm *vm, 321c6f73aabSFrançois Tigeot struct radeon_bo *bo) 322c6f73aabSFrançois Tigeot { 323c6f73aabSFrançois Tigeot struct radeon_bo_va *bo_va; 324c6f73aabSFrançois Tigeot 325c6f73aabSFrançois Tigeot bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); 326c6f73aabSFrançois Tigeot if (bo_va == NULL) { 327c6f73aabSFrançois Tigeot return NULL; 328c6f73aabSFrançois Tigeot } 329c6f73aabSFrançois Tigeot bo_va->vm = vm; 330c6f73aabSFrançois Tigeot bo_va->bo = bo; 3311cfef1a5SFrançois Tigeot bo_va->it.start = 0; 3321cfef1a5SFrançois Tigeot bo_va->it.last = 0; 333c6f73aabSFrançois Tigeot bo_va->flags = 0; 334c6f73aabSFrançois Tigeot bo_va->ref_count = 1; 335c6f73aabSFrançois Tigeot INIT_LIST_HEAD(&bo_va->bo_list); 336c6f73aabSFrançois Tigeot INIT_LIST_HEAD(&bo_va->vm_status); 337c6f73aabSFrançois Tigeot 3387dcf36dcSFrançois Tigeot mutex_lock(&vm->mutex); 339c6f73aabSFrançois Tigeot list_add_tail(&bo_va->bo_list, &bo->va); 3407dcf36dcSFrançois Tigeot mutex_unlock(&vm->mutex); 341c6f73aabSFrançois Tigeot 342c6f73aabSFrançois Tigeot return bo_va; 343c6f73aabSFrançois Tigeot } 344c6f73aabSFrançois Tigeot 345c6f73aabSFrançois Tigeot /** 346c6f73aabSFrançois Tigeot * radeon_vm_set_pages - helper to call the right asic function 347c6f73aabSFrançois Tigeot * 348c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 349c6f73aabSFrançois Tigeot * @ib: indirect buffer to fill with commands 350c6f73aabSFrançois Tigeot * @pe: addr of the page entry 351c6f73aabSFrançois Tigeot * @addr: dst addr to write into pe 352c6f73aabSFrançois Tigeot * @count: number of page entries to update 353c6f73aabSFrançois Tigeot * @incr: increase next addr by incr bytes 354c6f73aabSFrançois Tigeot * @flags: hw access flags 355c6f73aabSFrançois Tigeot * 356c6f73aabSFrançois Tigeot * Traces the parameters and calls the right asic functions 357c6f73aabSFrançois Tigeot * to setup the page table using the DMA. 358c6f73aabSFrançois Tigeot */ 359c6f73aabSFrançois Tigeot static void radeon_vm_set_pages(struct radeon_device *rdev, 360c6f73aabSFrançois Tigeot struct radeon_ib *ib, 361c6f73aabSFrançois Tigeot uint64_t pe, 362c6f73aabSFrançois Tigeot uint64_t addr, unsigned count, 363c6f73aabSFrançois Tigeot uint32_t incr, uint32_t flags) 364c6f73aabSFrançois Tigeot { 365c6f73aabSFrançois Tigeot trace_radeon_vm_set_page(pe, addr, count, incr, flags); 366c6f73aabSFrançois Tigeot 367c6f73aabSFrançois Tigeot if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) { 368c6f73aabSFrançois Tigeot uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8; 369c6f73aabSFrançois Tigeot radeon_asic_vm_copy_pages(rdev, ib, pe, src, count); 370c6f73aabSFrançois Tigeot 371c6f73aabSFrançois Tigeot } else if ((flags & R600_PTE_SYSTEM) || (count < 3)) { 372c6f73aabSFrançois Tigeot radeon_asic_vm_write_pages(rdev, ib, pe, addr, 373c6f73aabSFrançois Tigeot count, incr, flags); 374c6f73aabSFrançois Tigeot 375c6f73aabSFrançois Tigeot } else { 376c6f73aabSFrançois Tigeot radeon_asic_vm_set_pages(rdev, ib, pe, addr, 377c6f73aabSFrançois Tigeot count, incr, flags); 378c6f73aabSFrançois Tigeot } 379c6f73aabSFrançois Tigeot } 380c6f73aabSFrançois Tigeot 381c6f73aabSFrançois Tigeot /** 382c6f73aabSFrançois Tigeot * radeon_vm_clear_bo - initially clear the page dir/table 383c6f73aabSFrançois Tigeot * 384c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 385c6f73aabSFrançois Tigeot * @bo: bo to clear 386c6f73aabSFrançois Tigeot */ 387c6f73aabSFrançois Tigeot static int radeon_vm_clear_bo(struct radeon_device *rdev, 388c6f73aabSFrançois Tigeot struct radeon_bo *bo) 389c6f73aabSFrançois Tigeot { 390c6f73aabSFrançois Tigeot struct radeon_ib ib; 391c6f73aabSFrançois Tigeot unsigned entries; 392c6f73aabSFrançois Tigeot uint64_t addr; 393c6f73aabSFrançois Tigeot int r; 394c6f73aabSFrançois Tigeot 3957dcf36dcSFrançois Tigeot r = radeon_bo_reserve(bo, false); 396c6f73aabSFrançois Tigeot if (r) 397c6f73aabSFrançois Tigeot return r; 398c6f73aabSFrançois Tigeot 399c6f73aabSFrançois Tigeot r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 400c6f73aabSFrançois Tigeot if (r) 4017dcf36dcSFrançois Tigeot goto error_unreserve; 402c6f73aabSFrançois Tigeot 403c6f73aabSFrançois Tigeot addr = radeon_bo_gpu_offset(bo); 404c6f73aabSFrançois Tigeot entries = radeon_bo_size(bo) / 8; 405c6f73aabSFrançois Tigeot 406c6f73aabSFrançois Tigeot r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256); 407c6f73aabSFrançois Tigeot if (r) 4087dcf36dcSFrançois Tigeot goto error_unreserve; 409c6f73aabSFrançois Tigeot 410c6f73aabSFrançois Tigeot ib.length_dw = 0; 411c6f73aabSFrançois Tigeot 412c6f73aabSFrançois Tigeot radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0); 413c6f73aabSFrançois Tigeot radeon_asic_vm_pad_ib(rdev, &ib); 414c6f73aabSFrançois Tigeot WARN_ON(ib.length_dw > 64); 415c6f73aabSFrançois Tigeot 416c6f73aabSFrançois Tigeot r = radeon_ib_schedule(rdev, &ib, NULL, false); 417c6f73aabSFrançois Tigeot if (r) 4187dcf36dcSFrançois Tigeot goto error_free; 419c6f73aabSFrançois Tigeot 4207dcf36dcSFrançois Tigeot ib.fence->is_vm_update = true; 4217dcf36dcSFrançois Tigeot radeon_bo_fence(bo, ib.fence, false); 4227dcf36dcSFrançois Tigeot 4237dcf36dcSFrançois Tigeot error_free: 424c6f73aabSFrançois Tigeot radeon_ib_free(rdev, &ib); 425c6f73aabSFrançois Tigeot 4267dcf36dcSFrançois Tigeot error_unreserve: 4277dcf36dcSFrançois Tigeot radeon_bo_unreserve(bo); 428c6f73aabSFrançois Tigeot return r; 429c6f73aabSFrançois Tigeot } 430c6f73aabSFrançois Tigeot 431c6f73aabSFrançois Tigeot /** 432c6f73aabSFrançois Tigeot * radeon_vm_bo_set_addr - set bos virtual address inside a vm 433c6f73aabSFrançois Tigeot * 434c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 435c6f73aabSFrançois Tigeot * @bo_va: bo_va to store the address 436c6f73aabSFrançois Tigeot * @soffset: requested offset of the buffer in the VM address space 437c6f73aabSFrançois Tigeot * @flags: attributes of pages (read/write/valid/etc.) 438c6f73aabSFrançois Tigeot * 439c6f73aabSFrançois Tigeot * Set offset of @bo_va (cayman+). 440c6f73aabSFrançois Tigeot * Validate and set the offset requested within the vm address space. 441c6f73aabSFrançois Tigeot * Returns 0 for success, error for failure. 442c6f73aabSFrançois Tigeot * 4437dcf36dcSFrançois Tigeot * Object has to be reserved and gets unreserved by this function! 444c6f73aabSFrançois Tigeot */ 445c6f73aabSFrançois Tigeot int radeon_vm_bo_set_addr(struct radeon_device *rdev, 446c6f73aabSFrançois Tigeot struct radeon_bo_va *bo_va, 447c6f73aabSFrançois Tigeot uint64_t soffset, 448c6f73aabSFrançois Tigeot uint32_t flags) 449c6f73aabSFrançois Tigeot { 450c6f73aabSFrançois Tigeot uint64_t size = radeon_bo_size(bo_va->bo); 451c6f73aabSFrançois Tigeot struct radeon_vm *vm = bo_va->vm; 452c6f73aabSFrançois Tigeot unsigned last_pfn, pt_idx; 4531cfef1a5SFrançois Tigeot uint64_t eoffset; 454c6f73aabSFrançois Tigeot int r; 455c6f73aabSFrançois Tigeot 456c6f73aabSFrançois Tigeot if (soffset) { 457c6f73aabSFrançois Tigeot /* make sure object fit at this offset */ 458c59a5c48SFrançois Tigeot eoffset = soffset + size - 1; 459c6f73aabSFrançois Tigeot if (soffset >= eoffset) { 460c59a5c48SFrançois Tigeot r = -EINVAL; 461c59a5c48SFrançois Tigeot goto error_unreserve; 462c6f73aabSFrançois Tigeot } 463c6f73aabSFrançois Tigeot 464c6f73aabSFrançois Tigeot last_pfn = eoffset / RADEON_GPU_PAGE_SIZE; 465c59a5c48SFrançois Tigeot if (last_pfn >= rdev->vm_manager.max_pfn) { 466c59a5c48SFrançois Tigeot dev_err(rdev->dev, "va above limit (0x%08X >= 0x%08X)\n", 467c6f73aabSFrançois Tigeot last_pfn, rdev->vm_manager.max_pfn); 468c59a5c48SFrançois Tigeot r = -EINVAL; 469c59a5c48SFrançois Tigeot goto error_unreserve; 470c6f73aabSFrançois Tigeot } 471c6f73aabSFrançois Tigeot 472c6f73aabSFrançois Tigeot } else { 473c6f73aabSFrançois Tigeot eoffset = last_pfn = 0; 474c6f73aabSFrançois Tigeot } 475c6f73aabSFrançois Tigeot 4761cfef1a5SFrançois Tigeot mutex_lock(&vm->mutex); 4771cfef1a5SFrançois Tigeot soffset /= RADEON_GPU_PAGE_SIZE; 4781cfef1a5SFrançois Tigeot eoffset /= RADEON_GPU_PAGE_SIZE; 4791cfef1a5SFrançois Tigeot if (soffset || eoffset) { 4801cfef1a5SFrançois Tigeot struct interval_tree_node *it; 481c59a5c48SFrançois Tigeot it = interval_tree_iter_first(&vm->va, soffset, eoffset); 482c59a5c48SFrançois Tigeot if (it && it != &bo_va->it) { 4831cfef1a5SFrançois Tigeot struct radeon_bo_va *tmp; 4841cfef1a5SFrançois Tigeot tmp = container_of(it, struct radeon_bo_va, it); 4851cfef1a5SFrançois Tigeot /* bo and tmp overlap, invalid offset */ 4861cfef1a5SFrançois Tigeot dev_err(rdev->dev, "bo %p va 0x%010lx conflict with " 4871cfef1a5SFrançois Tigeot "(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo, 4881cfef1a5SFrançois Tigeot soffset, tmp->bo, tmp->it.start, tmp->it.last); 4891cfef1a5SFrançois Tigeot mutex_unlock(&vm->mutex); 490c59a5c48SFrançois Tigeot r = -EINVAL; 491c59a5c48SFrançois Tigeot goto error_unreserve; 4921cfef1a5SFrançois Tigeot } 493c59a5c48SFrançois Tigeot } 494c59a5c48SFrançois Tigeot 495c59a5c48SFrançois Tigeot if (bo_va->it.start || bo_va->it.last) { 496c59a5c48SFrançois Tigeot /* add a clone of the bo_va to clear the old address */ 497c59a5c48SFrançois Tigeot struct radeon_bo_va *tmp; 498c59a5c48SFrançois Tigeot tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); 499c59a5c48SFrançois Tigeot if (!tmp) { 500c59a5c48SFrançois Tigeot mutex_unlock(&vm->mutex); 501c59a5c48SFrançois Tigeot r = -ENOMEM; 502c59a5c48SFrançois Tigeot goto error_unreserve; 503c59a5c48SFrançois Tigeot } 504c59a5c48SFrançois Tigeot tmp->it.start = bo_va->it.start; 505c59a5c48SFrançois Tigeot tmp->it.last = bo_va->it.last; 506c59a5c48SFrançois Tigeot tmp->vm = vm; 507c59a5c48SFrançois Tigeot tmp->bo = radeon_bo_ref(bo_va->bo); 508c59a5c48SFrançois Tigeot 509c59a5c48SFrançois Tigeot interval_tree_remove(&bo_va->it, &vm->va); 510*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 511c59a5c48SFrançois Tigeot bo_va->it.start = 0; 512c59a5c48SFrançois Tigeot bo_va->it.last = 0; 513c59a5c48SFrançois Tigeot list_del_init(&bo_va->vm_status); 514c59a5c48SFrançois Tigeot list_add(&tmp->vm_status, &vm->freed); 515*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 516c59a5c48SFrançois Tigeot } 517c59a5c48SFrançois Tigeot 518c59a5c48SFrançois Tigeot if (soffset || eoffset) { 519*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 5201cfef1a5SFrançois Tigeot bo_va->it.start = soffset; 521c59a5c48SFrançois Tigeot bo_va->it.last = eoffset; 522c59a5c48SFrançois Tigeot list_add(&bo_va->vm_status, &vm->cleared); 523*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 5241cfef1a5SFrançois Tigeot interval_tree_insert(&bo_va->it, &vm->va); 5251cfef1a5SFrançois Tigeot } 5261cfef1a5SFrançois Tigeot 527c6f73aabSFrançois Tigeot bo_va->flags = flags; 528c6f73aabSFrançois Tigeot 5291cfef1a5SFrançois Tigeot soffset >>= radeon_vm_block_size; 5301cfef1a5SFrançois Tigeot eoffset >>= radeon_vm_block_size; 531c6f73aabSFrançois Tigeot 532c6f73aabSFrançois Tigeot BUG_ON(eoffset >= radeon_vm_num_pdes(rdev)); 533c6f73aabSFrançois Tigeot 534c6f73aabSFrançois Tigeot if (eoffset > vm->max_pde_used) 535c6f73aabSFrançois Tigeot vm->max_pde_used = eoffset; 536c6f73aabSFrançois Tigeot 537c6f73aabSFrançois Tigeot radeon_bo_unreserve(bo_va->bo); 538c6f73aabSFrançois Tigeot 539c6f73aabSFrançois Tigeot /* walk over the address space and allocate the page tables */ 540c6f73aabSFrançois Tigeot for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) { 541c6f73aabSFrançois Tigeot struct radeon_bo *pt; 542c6f73aabSFrançois Tigeot 543c6f73aabSFrançois Tigeot if (vm->page_tables[pt_idx].bo) 544c6f73aabSFrançois Tigeot continue; 545c6f73aabSFrançois Tigeot 546c6f73aabSFrançois Tigeot /* drop mutex to allocate and clear page table */ 5471cfef1a5SFrançois Tigeot mutex_unlock(&vm->mutex); 548c6f73aabSFrançois Tigeot 549c6f73aabSFrançois Tigeot r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8, 550c6f73aabSFrançois Tigeot RADEON_GPU_PAGE_SIZE, true, 5517dcf36dcSFrançois Tigeot RADEON_GEM_DOMAIN_VRAM, 0, 5527dcf36dcSFrançois Tigeot NULL, NULL, &pt); 553c6f73aabSFrançois Tigeot if (r) 554c6f73aabSFrançois Tigeot return r; 555c6f73aabSFrançois Tigeot 556c6f73aabSFrançois Tigeot r = radeon_vm_clear_bo(rdev, pt); 557c6f73aabSFrançois Tigeot if (r) { 558c6f73aabSFrançois Tigeot radeon_bo_unref(&pt); 559c6f73aabSFrançois Tigeot return r; 560c6f73aabSFrançois Tigeot } 561c6f73aabSFrançois Tigeot 562c6f73aabSFrançois Tigeot /* aquire mutex again */ 5631cfef1a5SFrançois Tigeot mutex_lock(&vm->mutex); 564c6f73aabSFrançois Tigeot if (vm->page_tables[pt_idx].bo) { 565c6f73aabSFrançois Tigeot /* someone else allocated the pt in the meantime */ 5661cfef1a5SFrançois Tigeot mutex_unlock(&vm->mutex); 567c6f73aabSFrançois Tigeot radeon_bo_unref(&pt); 5681cfef1a5SFrançois Tigeot mutex_lock(&vm->mutex); 569c6f73aabSFrançois Tigeot continue; 570c6f73aabSFrançois Tigeot } 571c6f73aabSFrançois Tigeot 572c6f73aabSFrançois Tigeot vm->page_tables[pt_idx].addr = 0; 573c6f73aabSFrançois Tigeot vm->page_tables[pt_idx].bo = pt; 574c6f73aabSFrançois Tigeot } 575c6f73aabSFrançois Tigeot 5761cfef1a5SFrançois Tigeot mutex_unlock(&vm->mutex); 5777dcf36dcSFrançois Tigeot return 0; 578c59a5c48SFrançois Tigeot 579c59a5c48SFrançois Tigeot error_unreserve: 580c59a5c48SFrançois Tigeot radeon_bo_unreserve(bo_va->bo); 581c59a5c48SFrançois Tigeot return r; 582c6f73aabSFrançois Tigeot } 583c6f73aabSFrançois Tigeot 584c6f73aabSFrançois Tigeot /** 585c6f73aabSFrançois Tigeot * radeon_vm_map_gart - get the physical address of a gart page 586c6f73aabSFrançois Tigeot * 587c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 588c6f73aabSFrançois Tigeot * @addr: the unmapped addr 589c6f73aabSFrançois Tigeot * 590c6f73aabSFrançois Tigeot * Look up the physical address of the page that the pte resolves 591c6f73aabSFrançois Tigeot * to (cayman+). 592c6f73aabSFrançois Tigeot * Returns the physical address of the page. 593c6f73aabSFrançois Tigeot */ 594c6f73aabSFrançois Tigeot uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr) 595c6f73aabSFrançois Tigeot { 596c6f73aabSFrançois Tigeot uint64_t result; 597c6f73aabSFrançois Tigeot 598c6f73aabSFrançois Tigeot /* page table offset */ 5997dcf36dcSFrançois Tigeot result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT]; 6007dcf36dcSFrançois Tigeot result &= ~RADEON_GPU_PAGE_MASK; 601c6f73aabSFrançois Tigeot 602c6f73aabSFrançois Tigeot return result; 603c6f73aabSFrançois Tigeot } 604c6f73aabSFrançois Tigeot 605c6f73aabSFrançois Tigeot /** 606c6f73aabSFrançois Tigeot * radeon_vm_page_flags - translate page flags to what the hw uses 607c6f73aabSFrançois Tigeot * 608c6f73aabSFrançois Tigeot * @flags: flags comming from userspace 609c6f73aabSFrançois Tigeot * 610c6f73aabSFrançois Tigeot * Translate the flags the userspace ABI uses to hw flags. 611c6f73aabSFrançois Tigeot */ 612c6f73aabSFrançois Tigeot static uint32_t radeon_vm_page_flags(uint32_t flags) 613c6f73aabSFrançois Tigeot { 614c6f73aabSFrançois Tigeot uint32_t hw_flags = 0; 615d78d3a22SFrançois Tigeot 616c6f73aabSFrançois Tigeot hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0; 617c6f73aabSFrançois Tigeot hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; 618c6f73aabSFrançois Tigeot hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; 619c6f73aabSFrançois Tigeot if (flags & RADEON_VM_PAGE_SYSTEM) { 620c6f73aabSFrançois Tigeot hw_flags |= R600_PTE_SYSTEM; 621c6f73aabSFrançois Tigeot hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; 622c6f73aabSFrançois Tigeot } 623c6f73aabSFrançois Tigeot return hw_flags; 624c6f73aabSFrançois Tigeot } 625c6f73aabSFrançois Tigeot 626c6f73aabSFrançois Tigeot /** 627c6f73aabSFrançois Tigeot * radeon_vm_update_pdes - make sure that page directory is valid 628c6f73aabSFrançois Tigeot * 629c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 630c6f73aabSFrançois Tigeot * @vm: requested vm 631c6f73aabSFrançois Tigeot * @start: start of GPU address range 632c6f73aabSFrançois Tigeot * @end: end of GPU address range 633c6f73aabSFrançois Tigeot * 634c6f73aabSFrançois Tigeot * Allocates new page tables if necessary 635c6f73aabSFrançois Tigeot * and updates the page directory (cayman+). 636c6f73aabSFrançois Tigeot * Returns 0 for success, error for failure. 637c6f73aabSFrançois Tigeot * 638c6f73aabSFrançois Tigeot * Global and local mutex must be locked! 639c6f73aabSFrançois Tigeot */ 640c6f73aabSFrançois Tigeot int radeon_vm_update_page_directory(struct radeon_device *rdev, 641c6f73aabSFrançois Tigeot struct radeon_vm *vm) 642c6f73aabSFrançois Tigeot { 643c6f73aabSFrançois Tigeot struct radeon_bo *pd = vm->page_directory; 644c6f73aabSFrançois Tigeot uint64_t pd_addr = radeon_bo_gpu_offset(pd); 645c6f73aabSFrançois Tigeot uint32_t incr = RADEON_VM_PTE_COUNT * 8; 646c6f73aabSFrançois Tigeot uint64_t last_pde = ~0, last_pt = ~0; 647c6f73aabSFrançois Tigeot unsigned count = 0, pt_idx, ndw; 648c6f73aabSFrançois Tigeot struct radeon_ib ib; 649c6f73aabSFrançois Tigeot int r; 650c6f73aabSFrançois Tigeot 651c6f73aabSFrançois Tigeot /* padding, etc. */ 652c6f73aabSFrançois Tigeot ndw = 64; 653c6f73aabSFrançois Tigeot 654c6f73aabSFrançois Tigeot /* assume the worst case */ 655c6f73aabSFrançois Tigeot ndw += vm->max_pde_used * 6; 656c6f73aabSFrançois Tigeot 657c6f73aabSFrançois Tigeot /* update too big for an IB */ 658c6f73aabSFrançois Tigeot if (ndw > 0xfffff) 659c6f73aabSFrançois Tigeot return -ENOMEM; 660c6f73aabSFrançois Tigeot 661c6f73aabSFrançois Tigeot r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4); 662c6f73aabSFrançois Tigeot if (r) 663c6f73aabSFrançois Tigeot return r; 664c6f73aabSFrançois Tigeot ib.length_dw = 0; 665c6f73aabSFrançois Tigeot 666c6f73aabSFrançois Tigeot /* walk over the address space and update the page directory */ 667c6f73aabSFrançois Tigeot for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { 668c6f73aabSFrançois Tigeot struct radeon_bo *bo = vm->page_tables[pt_idx].bo; 669c6f73aabSFrançois Tigeot uint64_t pde, pt; 670c6f73aabSFrançois Tigeot 671c6f73aabSFrançois Tigeot if (bo == NULL) 672c6f73aabSFrançois Tigeot continue; 673c6f73aabSFrançois Tigeot 674c6f73aabSFrançois Tigeot pt = radeon_bo_gpu_offset(bo); 675c6f73aabSFrançois Tigeot if (vm->page_tables[pt_idx].addr == pt) 676c6f73aabSFrançois Tigeot continue; 677c6f73aabSFrançois Tigeot vm->page_tables[pt_idx].addr = pt; 678c6f73aabSFrançois Tigeot 679c6f73aabSFrançois Tigeot pde = pd_addr + pt_idx * 8; 680c6f73aabSFrançois Tigeot if (((last_pde + 8 * count) != pde) || 681c6f73aabSFrançois Tigeot ((last_pt + incr * count) != pt)) { 682c6f73aabSFrançois Tigeot 683c6f73aabSFrançois Tigeot if (count) { 684c6f73aabSFrançois Tigeot radeon_vm_set_pages(rdev, &ib, last_pde, 685c6f73aabSFrançois Tigeot last_pt, count, incr, 686c6f73aabSFrançois Tigeot R600_PTE_VALID); 687c6f73aabSFrançois Tigeot } 688c6f73aabSFrançois Tigeot 689c6f73aabSFrançois Tigeot count = 1; 690c6f73aabSFrançois Tigeot last_pde = pde; 691c6f73aabSFrançois Tigeot last_pt = pt; 692c6f73aabSFrançois Tigeot } else { 693c6f73aabSFrançois Tigeot ++count; 694c6f73aabSFrançois Tigeot } 695c6f73aabSFrançois Tigeot } 696c6f73aabSFrançois Tigeot 697c6f73aabSFrançois Tigeot if (count) 698c6f73aabSFrançois Tigeot radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count, 699c6f73aabSFrançois Tigeot incr, R600_PTE_VALID); 700c6f73aabSFrançois Tigeot 701c6f73aabSFrançois Tigeot if (ib.length_dw != 0) { 702c6f73aabSFrançois Tigeot radeon_asic_vm_pad_ib(rdev, &ib); 7031cfef1a5SFrançois Tigeot 7047dcf36dcSFrançois Tigeot radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true); 705c6f73aabSFrançois Tigeot WARN_ON(ib.length_dw > ndw); 706c6f73aabSFrançois Tigeot r = radeon_ib_schedule(rdev, &ib, NULL, false); 707c6f73aabSFrançois Tigeot if (r) { 708c6f73aabSFrançois Tigeot radeon_ib_free(rdev, &ib); 709c6f73aabSFrançois Tigeot return r; 710c6f73aabSFrançois Tigeot } 7117dcf36dcSFrançois Tigeot ib.fence->is_vm_update = true; 7127dcf36dcSFrançois Tigeot radeon_bo_fence(pd, ib.fence, false); 713c6f73aabSFrançois Tigeot } 714c6f73aabSFrançois Tigeot radeon_ib_free(rdev, &ib); 715c6f73aabSFrançois Tigeot 716c6f73aabSFrançois Tigeot return 0; 717c6f73aabSFrançois Tigeot } 718c6f73aabSFrançois Tigeot 719c6f73aabSFrançois Tigeot /** 720c6f73aabSFrançois Tigeot * radeon_vm_frag_ptes - add fragment information to PTEs 721c6f73aabSFrançois Tigeot * 722c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 723c6f73aabSFrançois Tigeot * @ib: IB for the update 724c6f73aabSFrançois Tigeot * @pe_start: first PTE to handle 725c6f73aabSFrançois Tigeot * @pe_end: last PTE to handle 726c6f73aabSFrançois Tigeot * @addr: addr those PTEs should point to 727c6f73aabSFrançois Tigeot * @flags: hw mapping flags 728c6f73aabSFrançois Tigeot * 729c6f73aabSFrançois Tigeot * Global and local mutex must be locked! 730c6f73aabSFrançois Tigeot */ 731c6f73aabSFrançois Tigeot static void radeon_vm_frag_ptes(struct radeon_device *rdev, 732c6f73aabSFrançois Tigeot struct radeon_ib *ib, 733c6f73aabSFrançois Tigeot uint64_t pe_start, uint64_t pe_end, 734c6f73aabSFrançois Tigeot uint64_t addr, uint32_t flags) 735c6f73aabSFrançois Tigeot { 736c6f73aabSFrançois Tigeot /** 737c6f73aabSFrançois Tigeot * The MC L1 TLB supports variable sized pages, based on a fragment 738c6f73aabSFrançois Tigeot * field in the PTE. When this field is set to a non-zero value, page 739c6f73aabSFrançois Tigeot * granularity is increased from 4KB to (1 << (12 + frag)). The PTE 740c6f73aabSFrançois Tigeot * flags are considered valid for all PTEs within the fragment range 741c6f73aabSFrançois Tigeot * and corresponding mappings are assumed to be physically contiguous. 742c6f73aabSFrançois Tigeot * 743c6f73aabSFrançois Tigeot * The L1 TLB can store a single PTE for the whole fragment, 744c6f73aabSFrançois Tigeot * significantly increasing the space available for translation 745c6f73aabSFrançois Tigeot * caching. This leads to large improvements in throughput when the 746c6f73aabSFrançois Tigeot * TLB is under pressure. 747c6f73aabSFrançois Tigeot * 748c6f73aabSFrançois Tigeot * The L2 TLB distributes small and large fragments into two 749c6f73aabSFrançois Tigeot * asymmetric partitions. The large fragment cache is significantly 750c6f73aabSFrançois Tigeot * larger. Thus, we try to use large fragments wherever possible. 751c6f73aabSFrançois Tigeot * Userspace can support this by aligning virtual base address and 752c6f73aabSFrançois Tigeot * allocation size to the fragment size. 753c6f73aabSFrançois Tigeot */ 754c6f73aabSFrançois Tigeot 755c6f73aabSFrançois Tigeot /* NI is optimized for 256KB fragments, SI and newer for 64KB */ 7567dcf36dcSFrançois Tigeot uint64_t frag_flags = ((rdev->family == CHIP_CAYMAN) || 7577dcf36dcSFrançois Tigeot (rdev->family == CHIP_ARUBA)) ? 758c6f73aabSFrançois Tigeot R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB; 7597dcf36dcSFrançois Tigeot uint64_t frag_align = ((rdev->family == CHIP_CAYMAN) || 7607dcf36dcSFrançois Tigeot (rdev->family == CHIP_ARUBA)) ? 0x200 : 0x80; 761c6f73aabSFrançois Tigeot 762c6f73aabSFrançois Tigeot uint64_t frag_start = ALIGN(pe_start, frag_align); 763c6f73aabSFrançois Tigeot uint64_t frag_end = pe_end & ~(frag_align - 1); 764c6f73aabSFrançois Tigeot 765c6f73aabSFrançois Tigeot unsigned count; 766c6f73aabSFrançois Tigeot 767c6f73aabSFrançois Tigeot /* system pages are non continuously */ 768c6f73aabSFrançois Tigeot if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) || 769c6f73aabSFrançois Tigeot (frag_start >= frag_end)) { 770c6f73aabSFrançois Tigeot 771c6f73aabSFrançois Tigeot count = (pe_end - pe_start) / 8; 772c6f73aabSFrançois Tigeot radeon_vm_set_pages(rdev, ib, pe_start, addr, count, 773c6f73aabSFrançois Tigeot RADEON_GPU_PAGE_SIZE, flags); 774c6f73aabSFrançois Tigeot return; 775c6f73aabSFrançois Tigeot } 776c6f73aabSFrançois Tigeot 777c6f73aabSFrançois Tigeot /* handle the 4K area at the beginning */ 778c6f73aabSFrançois Tigeot if (pe_start != frag_start) { 779c6f73aabSFrançois Tigeot count = (frag_start - pe_start) / 8; 780c6f73aabSFrançois Tigeot radeon_vm_set_pages(rdev, ib, pe_start, addr, count, 781c6f73aabSFrançois Tigeot RADEON_GPU_PAGE_SIZE, flags); 782c6f73aabSFrançois Tigeot addr += RADEON_GPU_PAGE_SIZE * count; 783c6f73aabSFrançois Tigeot } 784c6f73aabSFrançois Tigeot 785c6f73aabSFrançois Tigeot /* handle the area in the middle */ 786c6f73aabSFrançois Tigeot count = (frag_end - frag_start) / 8; 787c6f73aabSFrançois Tigeot radeon_vm_set_pages(rdev, ib, frag_start, addr, count, 788c6f73aabSFrançois Tigeot RADEON_GPU_PAGE_SIZE, flags | frag_flags); 789c6f73aabSFrançois Tigeot 790c6f73aabSFrançois Tigeot /* handle the 4K area at the end */ 791c6f73aabSFrançois Tigeot if (frag_end != pe_end) { 792c6f73aabSFrançois Tigeot addr += RADEON_GPU_PAGE_SIZE * count; 793c6f73aabSFrançois Tigeot count = (pe_end - frag_end) / 8; 794c6f73aabSFrançois Tigeot radeon_vm_set_pages(rdev, ib, frag_end, addr, count, 795c6f73aabSFrançois Tigeot RADEON_GPU_PAGE_SIZE, flags); 796c6f73aabSFrançois Tigeot } 797c6f73aabSFrançois Tigeot } 798c6f73aabSFrançois Tigeot 799c6f73aabSFrançois Tigeot /** 800c6f73aabSFrançois Tigeot * radeon_vm_update_ptes - make sure that page tables are valid 801c6f73aabSFrançois Tigeot * 802c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 803c6f73aabSFrançois Tigeot * @vm: requested vm 804c6f73aabSFrançois Tigeot * @start: start of GPU address range 805c6f73aabSFrançois Tigeot * @end: end of GPU address range 806c6f73aabSFrançois Tigeot * @dst: destination address to map to 807c6f73aabSFrançois Tigeot * @flags: mapping flags 808c6f73aabSFrançois Tigeot * 809c6f73aabSFrançois Tigeot * Update the page tables in the range @start - @end (cayman+). 810c6f73aabSFrançois Tigeot * 811c6f73aabSFrançois Tigeot * Global and local mutex must be locked! 812c6f73aabSFrançois Tigeot */ 8137dcf36dcSFrançois Tigeot static int radeon_vm_update_ptes(struct radeon_device *rdev, 814c6f73aabSFrançois Tigeot struct radeon_vm *vm, 815c6f73aabSFrançois Tigeot struct radeon_ib *ib, 816c6f73aabSFrançois Tigeot uint64_t start, uint64_t end, 817c6f73aabSFrançois Tigeot uint64_t dst, uint32_t flags) 818c6f73aabSFrançois Tigeot { 819c6f73aabSFrançois Tigeot uint64_t mask = RADEON_VM_PTE_COUNT - 1; 820c6f73aabSFrançois Tigeot uint64_t last_pte = ~0, last_dst = ~0; 821c6f73aabSFrançois Tigeot unsigned count = 0; 822c6f73aabSFrançois Tigeot uint64_t addr; 823c6f73aabSFrançois Tigeot 824c6f73aabSFrançois Tigeot /* walk over the address space and update the page tables */ 825c6f73aabSFrançois Tigeot for (addr = start; addr < end; ) { 826c6f73aabSFrançois Tigeot uint64_t pt_idx = addr >> radeon_vm_block_size; 827c6f73aabSFrançois Tigeot struct radeon_bo *pt = vm->page_tables[pt_idx].bo; 828c6f73aabSFrançois Tigeot unsigned nptes; 829c6f73aabSFrançois Tigeot uint64_t pte; 8307dcf36dcSFrançois Tigeot int r; 831c6f73aabSFrançois Tigeot 8327dcf36dcSFrançois Tigeot radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true); 8337dcf36dcSFrançois Tigeot r = reservation_object_reserve_shared(pt->tbo.resv); 8347dcf36dcSFrançois Tigeot if (r) 8357dcf36dcSFrançois Tigeot return r; 836c6f73aabSFrançois Tigeot 837c6f73aabSFrançois Tigeot if ((addr & ~mask) == (end & ~mask)) 838c6f73aabSFrançois Tigeot nptes = end - addr; 839c6f73aabSFrançois Tigeot else 840c6f73aabSFrançois Tigeot nptes = RADEON_VM_PTE_COUNT - (addr & mask); 841c6f73aabSFrançois Tigeot 842c6f73aabSFrançois Tigeot pte = radeon_bo_gpu_offset(pt); 843c6f73aabSFrançois Tigeot pte += (addr & mask) * 8; 844c6f73aabSFrançois Tigeot 845c6f73aabSFrançois Tigeot if ((last_pte + 8 * count) != pte) { 846c6f73aabSFrançois Tigeot 847c6f73aabSFrançois Tigeot if (count) { 848c6f73aabSFrançois Tigeot radeon_vm_frag_ptes(rdev, ib, last_pte, 849c6f73aabSFrançois Tigeot last_pte + 8 * count, 850c6f73aabSFrançois Tigeot last_dst, flags); 851c6f73aabSFrançois Tigeot } 852c6f73aabSFrançois Tigeot 853c6f73aabSFrançois Tigeot count = nptes; 854c6f73aabSFrançois Tigeot last_pte = pte; 855c6f73aabSFrançois Tigeot last_dst = dst; 856c6f73aabSFrançois Tigeot } else { 857c6f73aabSFrançois Tigeot count += nptes; 858c6f73aabSFrançois Tigeot } 859c6f73aabSFrançois Tigeot 860c6f73aabSFrançois Tigeot addr += nptes; 861c6f73aabSFrançois Tigeot dst += nptes * RADEON_GPU_PAGE_SIZE; 862c6f73aabSFrançois Tigeot } 863c6f73aabSFrançois Tigeot 864c6f73aabSFrançois Tigeot if (count) { 865c6f73aabSFrançois Tigeot radeon_vm_frag_ptes(rdev, ib, last_pte, 866c6f73aabSFrançois Tigeot last_pte + 8 * count, 867c6f73aabSFrançois Tigeot last_dst, flags); 868c6f73aabSFrançois Tigeot } 8697dcf36dcSFrançois Tigeot 8707dcf36dcSFrançois Tigeot return 0; 8717dcf36dcSFrançois Tigeot } 8727dcf36dcSFrançois Tigeot 8737dcf36dcSFrançois Tigeot /** 8747dcf36dcSFrançois Tigeot * radeon_vm_fence_pts - fence page tables after an update 8757dcf36dcSFrançois Tigeot * 8767dcf36dcSFrançois Tigeot * @vm: requested vm 8777dcf36dcSFrançois Tigeot * @start: start of GPU address range 8787dcf36dcSFrançois Tigeot * @end: end of GPU address range 8797dcf36dcSFrançois Tigeot * @fence: fence to use 8807dcf36dcSFrançois Tigeot * 8817dcf36dcSFrançois Tigeot * Fence the page tables in the range @start - @end (cayman+). 8827dcf36dcSFrançois Tigeot * 8837dcf36dcSFrançois Tigeot * Global and local mutex must be locked! 8847dcf36dcSFrançois Tigeot */ 8857dcf36dcSFrançois Tigeot static void radeon_vm_fence_pts(struct radeon_vm *vm, 8867dcf36dcSFrançois Tigeot uint64_t start, uint64_t end, 8877dcf36dcSFrançois Tigeot struct radeon_fence *fence) 8887dcf36dcSFrançois Tigeot { 8897dcf36dcSFrançois Tigeot unsigned i; 8907dcf36dcSFrançois Tigeot 8917dcf36dcSFrançois Tigeot start >>= radeon_vm_block_size; 892c59a5c48SFrançois Tigeot end = (end - 1) >> radeon_vm_block_size; 8937dcf36dcSFrançois Tigeot 8947dcf36dcSFrançois Tigeot for (i = start; i <= end; ++i) 8957dcf36dcSFrançois Tigeot radeon_bo_fence(vm->page_tables[i].bo, fence, true); 896c6f73aabSFrançois Tigeot } 897c6f73aabSFrançois Tigeot 898c6f73aabSFrançois Tigeot /** 899c6f73aabSFrançois Tigeot * radeon_vm_bo_update - map a bo into the vm page table 900c6f73aabSFrançois Tigeot * 901c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 902c6f73aabSFrançois Tigeot * @vm: requested vm 903c6f73aabSFrançois Tigeot * @bo: radeon buffer object 904c6f73aabSFrançois Tigeot * @mem: ttm mem 905c6f73aabSFrançois Tigeot * 906c6f73aabSFrançois Tigeot * Fill in the page table entries for @bo (cayman+). 907c6f73aabSFrançois Tigeot * Returns 0 for success, -EINVAL for failure. 908c6f73aabSFrançois Tigeot * 909c6f73aabSFrançois Tigeot * Object have to be reserved and mutex must be locked! 910c6f73aabSFrançois Tigeot */ 911c6f73aabSFrançois Tigeot int radeon_vm_bo_update(struct radeon_device *rdev, 912c6f73aabSFrançois Tigeot struct radeon_bo_va *bo_va, 913c6f73aabSFrançois Tigeot struct ttm_mem_reg *mem) 914c6f73aabSFrançois Tigeot { 915c6f73aabSFrançois Tigeot struct radeon_vm *vm = bo_va->vm; 916c6f73aabSFrançois Tigeot struct radeon_ib ib; 9177dcf36dcSFrançois Tigeot unsigned nptes, ncmds, ndw; 918c6f73aabSFrançois Tigeot uint64_t addr; 9197dcf36dcSFrançois Tigeot uint32_t flags; 920c6f73aabSFrançois Tigeot int r; 921c6f73aabSFrançois Tigeot 9221cfef1a5SFrançois Tigeot if (!bo_va->it.start) { 923c6f73aabSFrançois Tigeot dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n", 924c6f73aabSFrançois Tigeot bo_va->bo, vm); 925c6f73aabSFrançois Tigeot return -EINVAL; 926c6f73aabSFrançois Tigeot } 927c6f73aabSFrançois Tigeot 928*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 929c59a5c48SFrançois Tigeot if (mem) { 930c59a5c48SFrançois Tigeot if (list_empty(&bo_va->vm_status)) { 931*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 932c59a5c48SFrançois Tigeot return 0; 933c59a5c48SFrançois Tigeot } 934c6f73aabSFrançois Tigeot list_del_init(&bo_va->vm_status); 935c59a5c48SFrançois Tigeot } else { 936c59a5c48SFrançois Tigeot list_del(&bo_va->vm_status); 937c59a5c48SFrançois Tigeot list_add(&bo_va->vm_status, &vm->cleared); 938c59a5c48SFrançois Tigeot } 939*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 940c6f73aabSFrançois Tigeot 941c6f73aabSFrançois Tigeot bo_va->flags &= ~RADEON_VM_PAGE_VALID; 942c6f73aabSFrançois Tigeot bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM; 943c6f73aabSFrançois Tigeot bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED; 9447dcf36dcSFrançois Tigeot if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm)) 9457dcf36dcSFrançois Tigeot bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE; 9467dcf36dcSFrançois Tigeot 947c6f73aabSFrançois Tigeot if (mem) { 948c6f73aabSFrançois Tigeot addr = mem->start << PAGE_SHIFT; 949c6f73aabSFrançois Tigeot if (mem->mem_type != TTM_PL_SYSTEM) { 950c6f73aabSFrançois Tigeot bo_va->flags |= RADEON_VM_PAGE_VALID; 951c6f73aabSFrançois Tigeot } 952c6f73aabSFrançois Tigeot if (mem->mem_type == TTM_PL_TT) { 953c6f73aabSFrançois Tigeot bo_va->flags |= RADEON_VM_PAGE_SYSTEM; 954c6f73aabSFrançois Tigeot if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC))) 955c6f73aabSFrançois Tigeot bo_va->flags |= RADEON_VM_PAGE_SNOOPED; 956c6f73aabSFrançois Tigeot 957c6f73aabSFrançois Tigeot } else { 958c6f73aabSFrançois Tigeot addr += rdev->vm_manager.vram_base_offset; 959c6f73aabSFrançois Tigeot } 960c6f73aabSFrançois Tigeot } else { 961c6f73aabSFrançois Tigeot addr = 0; 962c6f73aabSFrançois Tigeot } 963c6f73aabSFrançois Tigeot 964c6f73aabSFrançois Tigeot trace_radeon_vm_bo_update(bo_va); 965c6f73aabSFrançois Tigeot 9661cfef1a5SFrançois Tigeot nptes = bo_va->it.last - bo_va->it.start + 1; 967c6f73aabSFrançois Tigeot 9687dcf36dcSFrançois Tigeot /* reserve space for one command every (1 << BLOCK_SIZE) entries 9697dcf36dcSFrançois Tigeot or 2k dwords (whatever is smaller) */ 9707dcf36dcSFrançois Tigeot ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1; 9717dcf36dcSFrançois Tigeot 972c6f73aabSFrançois Tigeot /* padding, etc. */ 973c6f73aabSFrançois Tigeot ndw = 64; 974c6f73aabSFrançois Tigeot 9757dcf36dcSFrançois Tigeot flags = radeon_vm_page_flags(bo_va->flags); 9767dcf36dcSFrançois Tigeot if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) { 9777dcf36dcSFrançois Tigeot /* only copy commands needed */ 9787dcf36dcSFrançois Tigeot ndw += ncmds * 7; 979c6f73aabSFrançois Tigeot 9807dcf36dcSFrançois Tigeot } else if (flags & R600_PTE_SYSTEM) { 9817dcf36dcSFrançois Tigeot /* header for write data commands */ 9827dcf36dcSFrançois Tigeot ndw += ncmds * 4; 9837dcf36dcSFrançois Tigeot 9847dcf36dcSFrançois Tigeot /* body of write data command */ 985c6f73aabSFrançois Tigeot ndw += nptes * 2; 986c6f73aabSFrançois Tigeot 9877dcf36dcSFrançois Tigeot } else { 9887dcf36dcSFrançois Tigeot /* set page commands needed */ 9897dcf36dcSFrançois Tigeot ndw += ncmds * 10; 9907dcf36dcSFrançois Tigeot 9917dcf36dcSFrançois Tigeot /* two extra commands for begin/end of fragment */ 9927dcf36dcSFrançois Tigeot ndw += 2 * 10; 9937dcf36dcSFrançois Tigeot } 9947dcf36dcSFrançois Tigeot 995c6f73aabSFrançois Tigeot /* update too big for an IB */ 996c6f73aabSFrançois Tigeot if (ndw > 0xfffff) 997c6f73aabSFrançois Tigeot return -ENOMEM; 998c6f73aabSFrançois Tigeot 999c6f73aabSFrançois Tigeot r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4); 1000c6f73aabSFrançois Tigeot if (r) 1001c6f73aabSFrançois Tigeot return r; 1002c6f73aabSFrançois Tigeot ib.length_dw = 0; 1003c6f73aabSFrançois Tigeot 10047dcf36dcSFrançois Tigeot if (!(bo_va->flags & RADEON_VM_PAGE_VALID)) { 10057dcf36dcSFrançois Tigeot unsigned i; 10067dcf36dcSFrançois Tigeot 10077dcf36dcSFrançois Tigeot for (i = 0; i < RADEON_NUM_RINGS; ++i) 10087dcf36dcSFrançois Tigeot radeon_sync_fence(&ib.sync, vm->ids[i].last_id_use); 10097dcf36dcSFrançois Tigeot } 10107dcf36dcSFrançois Tigeot 10117dcf36dcSFrançois Tigeot r = radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start, 10121cfef1a5SFrançois Tigeot bo_va->it.last + 1, addr, 10131cfef1a5SFrançois Tigeot radeon_vm_page_flags(bo_va->flags)); 10147dcf36dcSFrançois Tigeot if (r) { 10157dcf36dcSFrançois Tigeot radeon_ib_free(rdev, &ib); 10167dcf36dcSFrançois Tigeot return r; 10177dcf36dcSFrançois Tigeot } 1018c6f73aabSFrançois Tigeot 10197dcf36dcSFrançois Tigeot radeon_asic_vm_pad_ib(rdev, &ib); 10207dcf36dcSFrançois Tigeot WARN_ON(ib.length_dw > ndw); 10217dcf36dcSFrançois Tigeot 1022c6f73aabSFrançois Tigeot r = radeon_ib_schedule(rdev, &ib, NULL, false); 1023c6f73aabSFrançois Tigeot if (r) { 1024c6f73aabSFrançois Tigeot radeon_ib_free(rdev, &ib); 1025c6f73aabSFrançois Tigeot return r; 1026c6f73aabSFrançois Tigeot } 10277dcf36dcSFrançois Tigeot ib.fence->is_vm_update = true; 10287dcf36dcSFrançois Tigeot radeon_vm_fence_pts(vm, bo_va->it.start, bo_va->it.last + 1, ib.fence); 10297dcf36dcSFrançois Tigeot radeon_fence_unref(&bo_va->last_pt_update); 10307dcf36dcSFrançois Tigeot bo_va->last_pt_update = radeon_fence_ref(ib.fence); 1031c6f73aabSFrançois Tigeot radeon_ib_free(rdev, &ib); 1032c6f73aabSFrançois Tigeot 1033c6f73aabSFrançois Tigeot return 0; 1034c6f73aabSFrançois Tigeot } 1035c6f73aabSFrançois Tigeot 1036c6f73aabSFrançois Tigeot /** 1037c6f73aabSFrançois Tigeot * radeon_vm_clear_freed - clear freed BOs in the PT 1038c6f73aabSFrançois Tigeot * 1039c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 1040c6f73aabSFrançois Tigeot * @vm: requested vm 1041c6f73aabSFrançois Tigeot * 1042c6f73aabSFrançois Tigeot * Make sure all freed BOs are cleared in the PT. 1043c6f73aabSFrançois Tigeot * Returns 0 for success. 1044c6f73aabSFrançois Tigeot * 1045c6f73aabSFrançois Tigeot * PTs have to be reserved and mutex must be locked! 1046c6f73aabSFrançois Tigeot */ 1047c6f73aabSFrançois Tigeot int radeon_vm_clear_freed(struct radeon_device *rdev, 1048c6f73aabSFrançois Tigeot struct radeon_vm *vm) 1049c6f73aabSFrançois Tigeot { 10507dcf36dcSFrançois Tigeot struct radeon_bo_va *bo_va; 1051c59a5c48SFrançois Tigeot int r = 0; 1052c6f73aabSFrançois Tigeot 1053*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 10547dcf36dcSFrançois Tigeot while (!list_empty(&vm->freed)) { 10557dcf36dcSFrançois Tigeot bo_va = list_first_entry(&vm->freed, 10567dcf36dcSFrançois Tigeot struct radeon_bo_va, vm_status); 1057*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 10587dcf36dcSFrançois Tigeot 1059c6f73aabSFrançois Tigeot r = radeon_vm_bo_update(rdev, bo_va, NULL); 10607dcf36dcSFrançois Tigeot radeon_bo_unref(&bo_va->bo); 10617dcf36dcSFrançois Tigeot radeon_fence_unref(&bo_va->last_pt_update); 1062*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 1063c59a5c48SFrançois Tigeot list_del(&bo_va->vm_status); 1064c6f73aabSFrançois Tigeot kfree(bo_va); 1065c6f73aabSFrançois Tigeot if (r) 1066c59a5c48SFrançois Tigeot break; 10677dcf36dcSFrançois Tigeot 1068c6f73aabSFrançois Tigeot } 1069*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 1070c59a5c48SFrançois Tigeot return r; 1071c6f73aabSFrançois Tigeot 1072c6f73aabSFrançois Tigeot } 1073c6f73aabSFrançois Tigeot 1074c6f73aabSFrançois Tigeot /** 1075c6f73aabSFrançois Tigeot * radeon_vm_clear_invalids - clear invalidated BOs in the PT 1076c6f73aabSFrançois Tigeot * 1077c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 1078c6f73aabSFrançois Tigeot * @vm: requested vm 1079c6f73aabSFrançois Tigeot * 1080c6f73aabSFrançois Tigeot * Make sure all invalidated BOs are cleared in the PT. 1081c6f73aabSFrançois Tigeot * Returns 0 for success. 1082c6f73aabSFrançois Tigeot * 1083c6f73aabSFrançois Tigeot * PTs have to be reserved and mutex must be locked! 1084c6f73aabSFrançois Tigeot */ 1085c6f73aabSFrançois Tigeot int radeon_vm_clear_invalids(struct radeon_device *rdev, 1086c6f73aabSFrançois Tigeot struct radeon_vm *vm) 1087c6f73aabSFrançois Tigeot { 10887dcf36dcSFrançois Tigeot struct radeon_bo_va *bo_va; 1089c6f73aabSFrançois Tigeot int r; 1090c6f73aabSFrançois Tigeot 1091*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 10927dcf36dcSFrançois Tigeot while (!list_empty(&vm->invalidated)) { 10937dcf36dcSFrançois Tigeot bo_va = list_first_entry(&vm->invalidated, 10947dcf36dcSFrançois Tigeot struct radeon_bo_va, vm_status); 1095*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 10967dcf36dcSFrançois Tigeot 1097c6f73aabSFrançois Tigeot r = radeon_vm_bo_update(rdev, bo_va, NULL); 1098c6f73aabSFrançois Tigeot if (r) 1099c6f73aabSFrançois Tigeot return r; 11007dcf36dcSFrançois Tigeot 1101*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 1102c6f73aabSFrançois Tigeot } 1103*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 11047dcf36dcSFrançois Tigeot 1105c6f73aabSFrançois Tigeot return 0; 1106c6f73aabSFrançois Tigeot } 1107c6f73aabSFrançois Tigeot 1108c6f73aabSFrançois Tigeot /** 1109c6f73aabSFrançois Tigeot * radeon_vm_bo_rmv - remove a bo to a specific vm 1110c6f73aabSFrançois Tigeot * 1111c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 1112c6f73aabSFrançois Tigeot * @bo_va: requested bo_va 1113c6f73aabSFrançois Tigeot * 1114c6f73aabSFrançois Tigeot * Remove @bo_va->bo from the requested vm (cayman+). 1115c6f73aabSFrançois Tigeot * 1116c6f73aabSFrançois Tigeot * Object have to be reserved! 1117c6f73aabSFrançois Tigeot */ 1118c6f73aabSFrançois Tigeot void radeon_vm_bo_rmv(struct radeon_device *rdev, 1119c6f73aabSFrançois Tigeot struct radeon_bo_va *bo_va) 1120c6f73aabSFrançois Tigeot { 1121c6f73aabSFrançois Tigeot struct radeon_vm *vm = bo_va->vm; 1122c6f73aabSFrançois Tigeot 1123c6f73aabSFrançois Tigeot list_del(&bo_va->bo_list); 1124c6f73aabSFrançois Tigeot 11251cfef1a5SFrançois Tigeot mutex_lock(&vm->mutex); 112680670160SMatthew Dillon if (bo_va->it.start || bo_va->it.last) 11271cfef1a5SFrançois Tigeot interval_tree_remove(&bo_va->it, &vm->va); 11287dcf36dcSFrançois Tigeot 1129*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_EXCLUSIVE); 11307dcf36dcSFrançois Tigeot list_del(&bo_va->vm_status); 1131c59a5c48SFrançois Tigeot if (bo_va->it.start || bo_va->it.last) { 1132c59a5c48SFrançois Tigeot bo_va->bo = radeon_bo_ref(bo_va->bo); 1133c6f73aabSFrançois Tigeot list_add(&bo_va->vm_status, &vm->freed); 1134c6f73aabSFrançois Tigeot } else { 11357dcf36dcSFrançois Tigeot radeon_fence_unref(&bo_va->last_pt_update); 1136c6f73aabSFrançois Tigeot kfree(bo_va); 1137c6f73aabSFrançois Tigeot } 1138*ec5b6af4SFrançois Tigeot lockmgr(&vm->status_lock, LK_RELEASE); 1139c6f73aabSFrançois Tigeot 11401cfef1a5SFrançois Tigeot mutex_unlock(&vm->mutex); 1141c6f73aabSFrançois Tigeot } 1142c6f73aabSFrançois Tigeot 1143c6f73aabSFrançois Tigeot /** 1144c6f73aabSFrançois Tigeot * radeon_vm_bo_invalidate - mark the bo as invalid 1145c6f73aabSFrançois Tigeot * 1146c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 1147c6f73aabSFrançois Tigeot * @vm: requested vm 1148c6f73aabSFrançois Tigeot * @bo: radeon buffer object 1149c6f73aabSFrançois Tigeot * 1150c6f73aabSFrançois Tigeot * Mark @bo as invalid (cayman+). 1151c6f73aabSFrançois Tigeot */ 1152c6f73aabSFrançois Tigeot void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1153c6f73aabSFrançois Tigeot struct radeon_bo *bo) 1154c6f73aabSFrançois Tigeot { 1155c6f73aabSFrançois Tigeot struct radeon_bo_va *bo_va; 1156c6f73aabSFrançois Tigeot 1157c6f73aabSFrançois Tigeot list_for_each_entry(bo_va, &bo->va, bo_list) { 1158*ec5b6af4SFrançois Tigeot lockmgr(&bo_va->vm->status_lock, LK_EXCLUSIVE); 1159c59a5c48SFrançois Tigeot if (list_empty(&bo_va->vm_status) && 1160c59a5c48SFrançois Tigeot (bo_va->it.start || bo_va->it.last)) 1161c6f73aabSFrançois Tigeot list_add(&bo_va->vm_status, &bo_va->vm->invalidated); 1162*ec5b6af4SFrançois Tigeot lockmgr(&bo_va->vm->status_lock, LK_RELEASE); 1163c6f73aabSFrançois Tigeot } 1164c6f73aabSFrançois Tigeot } 1165c6f73aabSFrançois Tigeot 1166c6f73aabSFrançois Tigeot /** 1167c6f73aabSFrançois Tigeot * radeon_vm_init - initialize a vm instance 1168c6f73aabSFrançois Tigeot * 1169c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 1170c6f73aabSFrançois Tigeot * @vm: requested vm 1171c6f73aabSFrançois Tigeot * 1172c6f73aabSFrançois Tigeot * Init @vm fields (cayman+). 1173c6f73aabSFrançois Tigeot */ 1174c6f73aabSFrançois Tigeot int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm) 1175c6f73aabSFrançois Tigeot { 1176c6f73aabSFrançois Tigeot const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE, 1177c6f73aabSFrançois Tigeot RADEON_VM_PTE_COUNT * 8); 1178c6f73aabSFrançois Tigeot unsigned pd_size, pd_entries, pts_size; 11797dcf36dcSFrançois Tigeot int i, r; 1180c6f73aabSFrançois Tigeot 1181c6f73aabSFrançois Tigeot vm->ib_bo_va = NULL; 11827dcf36dcSFrançois Tigeot for (i = 0; i < RADEON_NUM_RINGS; ++i) { 11837dcf36dcSFrançois Tigeot vm->ids[i].id = 0; 11847dcf36dcSFrançois Tigeot vm->ids[i].flushed_updates = NULL; 11857dcf36dcSFrançois Tigeot vm->ids[i].last_id_use = NULL; 11867dcf36dcSFrançois Tigeot } 1187c6f73aabSFrançois Tigeot lockinit(&vm->mutex, "rvmmtx", 0, LK_CANRECURSE); 11881cfef1a5SFrançois Tigeot vm->va = LINUX_RB_ROOT; 1189*ec5b6af4SFrançois Tigeot lockinit(&vm->status_lock, "rdnvsl", 0, LK_EXCLUSIVE); 1190c6f73aabSFrançois Tigeot INIT_LIST_HEAD(&vm->invalidated); 1191c6f73aabSFrançois Tigeot INIT_LIST_HEAD(&vm->freed); 1192c59a5c48SFrançois Tigeot INIT_LIST_HEAD(&vm->cleared); 1193c6f73aabSFrançois Tigeot 1194c6f73aabSFrançois Tigeot pd_size = radeon_vm_directory_size(rdev); 1195c6f73aabSFrançois Tigeot pd_entries = radeon_vm_num_pdes(rdev); 1196c6f73aabSFrançois Tigeot 1197c6f73aabSFrançois Tigeot /* allocate page table array */ 1198c6f73aabSFrançois Tigeot pts_size = pd_entries * sizeof(struct radeon_vm_pt); 1199c6f73aabSFrançois Tigeot vm->page_tables = kzalloc(pts_size, GFP_KERNEL); 1200c6f73aabSFrançois Tigeot if (vm->page_tables == NULL) { 1201c6f73aabSFrançois Tigeot DRM_ERROR("Cannot allocate memory for page table array\n"); 1202c6f73aabSFrançois Tigeot return -ENOMEM; 1203c6f73aabSFrançois Tigeot } 1204c6f73aabSFrançois Tigeot 1205c6f73aabSFrançois Tigeot r = radeon_bo_create(rdev, pd_size, align, true, 1206c6f73aabSFrançois Tigeot RADEON_GEM_DOMAIN_VRAM, 0, NULL, 12077dcf36dcSFrançois Tigeot NULL, &vm->page_directory); 1208c6f73aabSFrançois Tigeot if (r) 1209c6f73aabSFrançois Tigeot return r; 1210c6f73aabSFrançois Tigeot 1211c6f73aabSFrançois Tigeot r = radeon_vm_clear_bo(rdev, vm->page_directory); 1212c6f73aabSFrançois Tigeot if (r) { 1213c6f73aabSFrançois Tigeot radeon_bo_unref(&vm->page_directory); 1214c6f73aabSFrançois Tigeot vm->page_directory = NULL; 1215c6f73aabSFrançois Tigeot return r; 1216c6f73aabSFrançois Tigeot } 1217c6f73aabSFrançois Tigeot 1218c6f73aabSFrançois Tigeot return 0; 1219c6f73aabSFrançois Tigeot } 1220c6f73aabSFrançois Tigeot 1221c6f73aabSFrançois Tigeot /** 1222c6f73aabSFrançois Tigeot * radeon_vm_fini - tear down a vm instance 1223c6f73aabSFrançois Tigeot * 1224c6f73aabSFrançois Tigeot * @rdev: radeon_device pointer 1225c6f73aabSFrançois Tigeot * @vm: requested vm 1226c6f73aabSFrançois Tigeot * 1227c6f73aabSFrançois Tigeot * Tear down @vm (cayman+). 1228c6f73aabSFrançois Tigeot * Unbind the VM and remove all bos from the vm bo list 1229c6f73aabSFrançois Tigeot */ 1230c6f73aabSFrançois Tigeot void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm) 1231c6f73aabSFrançois Tigeot { 1232c6f73aabSFrançois Tigeot struct radeon_bo_va *bo_va, *tmp; 1233c6f73aabSFrançois Tigeot int i, r; 1234c6f73aabSFrançois Tigeot 12351cfef1a5SFrançois Tigeot if (!RB_EMPTY_ROOT(&vm->va)) { 1236c6f73aabSFrançois Tigeot dev_err(rdev->dev, "still active bo inside vm\n"); 1237c6f73aabSFrançois Tigeot } 12381cfef1a5SFrançois Tigeot #ifndef __DragonFly__ 12391cfef1a5SFrançois Tigeot rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) { 12401cfef1a5SFrançois Tigeot #else 12411cfef1a5SFrançois Tigeot /* 12421cfef1a5SFrançois Tigeot * DFly interval tree mock-up does not use RB trees, the RB iterator 12431cfef1a5SFrançois Tigeot * may not be used. 12441cfef1a5SFrançois Tigeot * 12451cfef1a5SFrançois Tigeot * rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) 12461cfef1a5SFrançois Tigeot * 12471cfef1a5SFrançois Tigeot * This code is removing all entries so it is fairly easy to replace. 12481cfef1a5SFrançois Tigeot */ 12491cfef1a5SFrançois Tigeot while (vm->va.rb_node) { 12501cfef1a5SFrançois Tigeot bo_va = container_of((void *)vm->va.rb_node, struct radeon_bo_va, it); 12511cfef1a5SFrançois Tigeot #endif 1252c6f73aabSFrançois Tigeot r = radeon_bo_reserve(bo_va->bo, false); 1253c6f73aabSFrançois Tigeot if (!r) { 125480670160SMatthew Dillon interval_tree_remove(&bo_va->it, &vm->va); 1255c6f73aabSFrançois Tigeot list_del_init(&bo_va->bo_list); 1256c6f73aabSFrançois Tigeot radeon_bo_unreserve(bo_va->bo); 12577dcf36dcSFrançois Tigeot radeon_fence_unref(&bo_va->last_pt_update); 1258c6f73aabSFrançois Tigeot kfree(bo_va); 1259c6f73aabSFrançois Tigeot } 1260c6f73aabSFrançois Tigeot } 12617dcf36dcSFrançois Tigeot list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) { 12627dcf36dcSFrançois Tigeot radeon_bo_unref(&bo_va->bo); 12637dcf36dcSFrançois Tigeot radeon_fence_unref(&bo_va->last_pt_update); 1264c6f73aabSFrançois Tigeot kfree(bo_va); 12657dcf36dcSFrançois Tigeot } 1266c6f73aabSFrançois Tigeot 1267c6f73aabSFrançois Tigeot for (i = 0; i < radeon_vm_num_pdes(rdev); i++) 1268c6f73aabSFrançois Tigeot radeon_bo_unref(&vm->page_tables[i].bo); 1269c6f73aabSFrançois Tigeot kfree(vm->page_tables); 1270c6f73aabSFrançois Tigeot 1271c6f73aabSFrançois Tigeot radeon_bo_unref(&vm->page_directory); 1272c6f73aabSFrançois Tigeot 12737dcf36dcSFrançois Tigeot for (i = 0; i < RADEON_NUM_RINGS; ++i) { 12747dcf36dcSFrançois Tigeot radeon_fence_unref(&vm->ids[i].flushed_updates); 12757dcf36dcSFrançois Tigeot radeon_fence_unref(&vm->ids[i].last_id_use); 12767dcf36dcSFrançois Tigeot } 1277c6f73aabSFrançois Tigeot 12787dcf36dcSFrançois Tigeot mutex_destroy(&vm->mutex); 1279c6f73aabSFrançois Tigeot } 1280