1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "rs400d.h" 32 33 /* This files gather functions specifics to : rs400,rs480 */ 34 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 35 36 void rs400_gart_adjust_size(struct radeon_device *rdev) 37 { 38 /* Check gart size */ 39 switch (rdev->mc.gtt_size/(1024*1024)) { 40 case 32: 41 case 64: 42 case 128: 43 case 256: 44 case 512: 45 case 1024: 46 case 2048: 47 break; 48 default: 49 DRM_ERROR("Unable to use IGP GART size %uM\n", 50 (unsigned)(rdev->mc.gtt_size >> 20)); 51 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 52 DRM_ERROR("Forcing to 32M GART size\n"); 53 rdev->mc.gtt_size = 32 * 1024 * 1024; 54 return; 55 } 56 } 57 58 void rs400_gart_tlb_flush(struct radeon_device *rdev) 59 { 60 uint32_t tmp; 61 unsigned int timeout = rdev->usec_timeout; 62 63 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 64 do { 65 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 66 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 67 break; 68 DRM_UDELAY(1); 69 timeout--; 70 } while (timeout > 0); 71 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 72 } 73 74 int rs400_gart_init(struct radeon_device *rdev) 75 { 76 int r; 77 78 if (rdev->gart.ptr) { 79 WARN(1, "RS400 GART already initialized\n"); 80 return 0; 81 } 82 /* Check gart size */ 83 switch(rdev->mc.gtt_size / (1024 * 1024)) { 84 case 32: 85 case 64: 86 case 128: 87 case 256: 88 case 512: 89 case 1024: 90 case 2048: 91 break; 92 default: 93 return -EINVAL; 94 } 95 /* Initialize common gart structure */ 96 r = radeon_gart_init(rdev); 97 if (r) 98 return r; 99 if (rs400_debugfs_pcie_gart_info_init(rdev)) 100 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 102 return radeon_gart_table_ram_alloc(rdev); 103 } 104 105 int rs400_gart_enable(struct radeon_device *rdev) 106 { 107 uint32_t size_reg; 108 uint32_t tmp; 109 110 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 111 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 112 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 113 /* Check gart size */ 114 switch(rdev->mc.gtt_size / (1024 * 1024)) { 115 case 32: 116 size_reg = RS480_VA_SIZE_32MB; 117 break; 118 case 64: 119 size_reg = RS480_VA_SIZE_64MB; 120 break; 121 case 128: 122 size_reg = RS480_VA_SIZE_128MB; 123 break; 124 case 256: 125 size_reg = RS480_VA_SIZE_256MB; 126 break; 127 case 512: 128 size_reg = RS480_VA_SIZE_512MB; 129 break; 130 case 1024: 131 size_reg = RS480_VA_SIZE_1GB; 132 break; 133 case 2048: 134 size_reg = RS480_VA_SIZE_2GB; 135 break; 136 default: 137 return -EINVAL; 138 } 139 /* It should be fine to program it to max value */ 140 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 141 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 142 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 143 } else { 144 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 145 WREG32(RS480_AGP_BASE_2, 0); 146 } 147 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 148 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 149 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 150 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 151 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 152 WREG32(RADEON_BUS_CNTL, tmp); 153 } else { 154 WREG32(RADEON_MC_AGP_LOCATION, tmp); 155 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 156 WREG32(RADEON_BUS_CNTL, tmp); 157 } 158 /* Table should be in 32bits address space so ignore bits above. */ 159 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 160 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 161 162 WREG32_MC(RS480_GART_BASE, tmp); 163 /* TODO: more tweaking here */ 164 WREG32_MC(RS480_GART_FEATURE_ID, 165 (RS480_TLB_ENABLE | 166 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 167 /* Disable snooping */ 168 WREG32_MC(RS480_AGP_MODE_CNTL, 169 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 170 /* Disable AGP mode */ 171 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 172 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 173 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 174 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 175 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; 176 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 177 } else { 178 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 179 tmp |= RS480_GART_INDEX_REG_EN; 180 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 181 } 182 /* Enable gart */ 183 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 184 rs400_gart_tlb_flush(rdev); 185 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 186 (unsigned)(rdev->mc.gtt_size >> 20), 187 (unsigned long long)rdev->gart.table_addr); 188 rdev->gart.ready = true; 189 return 0; 190 } 191 192 void rs400_gart_disable(struct radeon_device *rdev) 193 { 194 uint32_t tmp; 195 196 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 197 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 198 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 199 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 200 } 201 202 void rs400_gart_fini(struct radeon_device *rdev) 203 { 204 radeon_gart_fini(rdev); 205 rs400_gart_disable(rdev); 206 radeon_gart_table_ram_free(rdev); 207 } 208 209 #define RS400_PTE_UNSNOOPED (1 << 0) 210 #define RS400_PTE_WRITEABLE (1 << 2) 211 #define RS400_PTE_READABLE (1 << 3) 212 213 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 214 uint64_t addr, uint32_t flags) 215 { 216 uint32_t entry; 217 u32 *gtt = rdev->gart.ptr; 218 219 entry = (lower_32_bits(addr) & 0xfffff000) | 220 ((upper_32_bits(addr) & 0xff) << 4); 221 if (flags & RADEON_GART_PAGE_READ) 222 entry |= RS400_PTE_READABLE; 223 if (flags & RADEON_GART_PAGE_WRITE) 224 entry |= RS400_PTE_WRITEABLE; 225 if (!(flags & RADEON_GART_PAGE_SNOOP)) 226 entry |= RS400_PTE_UNSNOOPED; 227 entry = cpu_to_le32(entry); 228 gtt[i] = entry; 229 } 230 231 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 232 { 233 unsigned i; 234 uint32_t tmp; 235 236 for (i = 0; i < rdev->usec_timeout; i++) { 237 /* read MC_STATUS */ 238 tmp = RREG32(RADEON_MC_STATUS); 239 if (tmp & RADEON_MC_IDLE) { 240 return 0; 241 } 242 DRM_UDELAY(1); 243 } 244 return -1; 245 } 246 247 static void rs400_gpu_init(struct radeon_device *rdev) 248 { 249 /* FIXME: is this correct ? */ 250 r420_pipes_init(rdev); 251 if (rs400_mc_wait_for_idle(rdev)) { 252 printk(KERN_WARNING "rs400: Failed to wait MC idle while " 253 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 254 } 255 } 256 257 static void rs400_mc_init(struct radeon_device *rdev) 258 { 259 u64 base; 260 261 rs400_gart_adjust_size(rdev); 262 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 263 /* DDR for all card after R300 & IGP */ 264 rdev->mc.vram_is_ddr = true; 265 rdev->mc.vram_width = 128; 266 r100_vram_init_sizes(rdev); 267 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 268 radeon_vram_location(rdev, &rdev->mc, base); 269 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 270 radeon_gtt_location(rdev, &rdev->mc); 271 radeon_update_bandwidth_info(rdev); 272 } 273 274 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 275 { 276 uint32_t r; 277 278 spin_lock(&rdev->mc_idx_lock); 279 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 280 r = RREG32(RS480_NB_MC_DATA); 281 WREG32(RS480_NB_MC_INDEX, 0xff); 282 spin_unlock(&rdev->mc_idx_lock); 283 return r; 284 } 285 286 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 287 { 288 spin_lock(&rdev->mc_idx_lock); 289 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 290 WREG32(RS480_NB_MC_DATA, (v)); 291 WREG32(RS480_NB_MC_INDEX, 0xff); 292 spin_unlock(&rdev->mc_idx_lock); 293 } 294 295 #if defined(CONFIG_DEBUG_FS) 296 static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 297 { 298 struct drm_info_node *node = (struct drm_info_node *) m->private; 299 struct drm_device *dev = node->minor->dev; 300 struct radeon_device *rdev = dev->dev_private; 301 uint32_t tmp; 302 303 tmp = RREG32(RADEON_HOST_PATH_CNTL); 304 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 305 tmp = RREG32(RADEON_BUS_CNTL); 306 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 307 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 308 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 309 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 310 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 311 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 312 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 313 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 314 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 315 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 316 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 317 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 318 tmp = RREG32(RS690_HDP_FB_LOCATION); 319 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 320 } else { 321 tmp = RREG32(RADEON_AGP_BASE); 322 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 323 tmp = RREG32(RS480_AGP_BASE_2); 324 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 325 tmp = RREG32(RADEON_MC_AGP_LOCATION); 326 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 327 } 328 tmp = RREG32_MC(RS480_GART_BASE); 329 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 330 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 331 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 332 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 333 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 334 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 335 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 336 tmp = RREG32_MC(0x5F); 337 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 338 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 339 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 340 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 341 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 342 tmp = RREG32_MC(0x3B); 343 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 344 tmp = RREG32_MC(0x3C); 345 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 346 tmp = RREG32_MC(0x30); 347 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 348 tmp = RREG32_MC(0x31); 349 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 350 tmp = RREG32_MC(0x32); 351 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 352 tmp = RREG32_MC(0x33); 353 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 354 tmp = RREG32_MC(0x34); 355 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 356 tmp = RREG32_MC(0x35); 357 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 358 tmp = RREG32_MC(0x36); 359 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 360 tmp = RREG32_MC(0x37); 361 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 362 return 0; 363 } 364 365 static struct drm_info_list rs400_gart_info_list[] = { 366 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 367 }; 368 #endif 369 370 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 371 { 372 #if defined(CONFIG_DEBUG_FS) 373 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 374 #else 375 return 0; 376 #endif 377 } 378 379 static void rs400_mc_program(struct radeon_device *rdev) 380 { 381 struct r100_mc_save save; 382 383 /* Stops all mc clients */ 384 r100_mc_stop(rdev, &save); 385 386 /* Wait for mc idle */ 387 if (rs400_mc_wait_for_idle(rdev)) 388 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 389 WREG32(R_000148_MC_FB_LOCATION, 390 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 391 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 392 393 r100_mc_resume(rdev, &save); 394 } 395 396 static int rs400_startup(struct radeon_device *rdev) 397 { 398 int r; 399 400 r100_set_common_regs(rdev); 401 402 rs400_mc_program(rdev); 403 /* Resume clock */ 404 r300_clock_startup(rdev); 405 /* Initialize GPU configuration (# pipes, ...) */ 406 rs400_gpu_init(rdev); 407 r100_enable_bm(rdev); 408 /* Initialize GART (initialize after TTM so we can allocate 409 * memory through TTM but finalize after TTM) */ 410 r = rs400_gart_enable(rdev); 411 if (r) 412 return r; 413 414 /* allocate wb buffer */ 415 r = radeon_wb_init(rdev); 416 if (r) 417 return r; 418 419 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 420 if (r) { 421 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 422 return r; 423 } 424 425 /* Enable IRQ */ 426 if (!rdev->irq.installed) { 427 r = radeon_irq_kms_init(rdev); 428 if (r) 429 return r; 430 } 431 432 r100_irq_set(rdev); 433 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 434 /* 1M ring buffer */ 435 r = r100_cp_init(rdev, 1024 * 1024); 436 if (r) { 437 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 438 return r; 439 } 440 441 r = radeon_ib_pool_init(rdev); 442 if (r) { 443 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 444 return r; 445 } 446 447 return 0; 448 } 449 450 int rs400_resume(struct radeon_device *rdev) 451 { 452 int r; 453 454 /* Make sur GART are not working */ 455 rs400_gart_disable(rdev); 456 /* Resume clock before doing reset */ 457 r300_clock_startup(rdev); 458 /* setup MC before calling post tables */ 459 rs400_mc_program(rdev); 460 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 461 if (radeon_asic_reset(rdev)) { 462 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 463 RREG32(R_000E40_RBBM_STATUS), 464 RREG32(R_0007C0_CP_STAT)); 465 } 466 /* post */ 467 radeon_combios_asic_init(rdev->ddev); 468 /* Resume clock after posting */ 469 r300_clock_startup(rdev); 470 /* Initialize surface registers */ 471 radeon_surface_init(rdev); 472 473 rdev->accel_working = true; 474 r = rs400_startup(rdev); 475 if (r) { 476 rdev->accel_working = false; 477 } 478 return r; 479 } 480 481 int rs400_suspend(struct radeon_device *rdev) 482 { 483 radeon_pm_suspend(rdev); 484 r100_cp_disable(rdev); 485 radeon_wb_disable(rdev); 486 r100_irq_disable(rdev); 487 rs400_gart_disable(rdev); 488 return 0; 489 } 490 491 void rs400_fini(struct radeon_device *rdev) 492 { 493 radeon_pm_fini(rdev); 494 r100_cp_fini(rdev); 495 radeon_wb_fini(rdev); 496 radeon_ib_pool_fini(rdev); 497 radeon_gem_fini(rdev); 498 rs400_gart_fini(rdev); 499 radeon_irq_kms_fini(rdev); 500 radeon_fence_driver_fini(rdev); 501 radeon_bo_fini(rdev); 502 radeon_atombios_fini(rdev); 503 kfree(rdev->bios); 504 rdev->bios = NULL; 505 } 506 507 int rs400_init(struct radeon_device *rdev) 508 { 509 int r; 510 511 /* Disable VGA */ 512 r100_vga_render_disable(rdev); 513 /* Initialize scratch registers */ 514 radeon_scratch_init(rdev); 515 /* Initialize surface registers */ 516 radeon_surface_init(rdev); 517 /* TODO: disable VGA need to use VGA request */ 518 /* restore some register to sane defaults */ 519 r100_restore_sanity(rdev); 520 /* BIOS*/ 521 if (!radeon_get_bios(rdev)) { 522 if (ASIC_IS_AVIVO(rdev)) 523 return -EINVAL; 524 } 525 if (rdev->is_atom_bios) { 526 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 527 return -EINVAL; 528 } else { 529 r = radeon_combios_init(rdev); 530 if (r) 531 return r; 532 } 533 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 534 if (radeon_asic_reset(rdev)) { 535 dev_warn(rdev->dev, 536 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 537 RREG32(R_000E40_RBBM_STATUS), 538 RREG32(R_0007C0_CP_STAT)); 539 } 540 /* check if cards are posted or not */ 541 if (radeon_boot_test_post_card(rdev) == false) 542 return -EINVAL; 543 544 /* Initialize clocks */ 545 radeon_get_clock_info(rdev->ddev); 546 /* initialize memory controller */ 547 rs400_mc_init(rdev); 548 /* Fence driver */ 549 r = radeon_fence_driver_init(rdev); 550 if (r) 551 return r; 552 /* Memory manager */ 553 r = radeon_bo_init(rdev); 554 if (r) 555 return r; 556 r = rs400_gart_init(rdev); 557 if (r) 558 return r; 559 r300_set_reg_safe(rdev); 560 561 /* Initialize power management */ 562 radeon_pm_init(rdev); 563 564 rdev->accel_working = true; 565 r = rs400_startup(rdev); 566 if (r) { 567 /* Somethings want wront with the accel init stop accel */ 568 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 569 r100_cp_fini(rdev); 570 radeon_wb_fini(rdev); 571 radeon_ib_pool_fini(rdev); 572 rs400_gart_fini(rdev); 573 radeon_irq_kms_fini(rdev); 574 rdev->accel_working = false; 575 } 576 return 0; 577 } 578