1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "rs400d.h" 32 33 /* This files gather functions specifics to : rs400,rs480 */ 34 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 35 36 void rs400_gart_adjust_size(struct radeon_device *rdev) 37 { 38 /* Check gart size */ 39 switch (rdev->mc.gtt_size/(1024*1024)) { 40 case 32: 41 case 64: 42 case 128: 43 case 256: 44 case 512: 45 case 1024: 46 case 2048: 47 break; 48 default: 49 DRM_ERROR("Unable to use IGP GART size %uM\n", 50 (unsigned)(rdev->mc.gtt_size >> 20)); 51 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 52 DRM_ERROR("Forcing to 32M GART size\n"); 53 rdev->mc.gtt_size = 32 * 1024 * 1024; 54 return; 55 } 56 } 57 58 void rs400_gart_tlb_flush(struct radeon_device *rdev) 59 { 60 uint32_t tmp; 61 unsigned int timeout = rdev->usec_timeout; 62 63 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 64 do { 65 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 66 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 67 break; 68 DRM_UDELAY(1); 69 timeout--; 70 } while (timeout > 0); 71 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 72 } 73 74 int rs400_gart_init(struct radeon_device *rdev) 75 { 76 int r; 77 78 if (rdev->gart.ptr) { 79 WARN(1, "RS400 GART already initialized\n"); 80 return 0; 81 } 82 /* Check gart size */ 83 switch(rdev->mc.gtt_size / (1024 * 1024)) { 84 case 32: 85 case 64: 86 case 128: 87 case 256: 88 case 512: 89 case 1024: 90 case 2048: 91 break; 92 default: 93 return -EINVAL; 94 } 95 /* Initialize common gart structure */ 96 r = radeon_gart_init(rdev); 97 if (r) 98 return r; 99 if (rs400_debugfs_pcie_gart_info_init(rdev)) 100 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 102 return radeon_gart_table_ram_alloc(rdev); 103 } 104 105 int rs400_gart_enable(struct radeon_device *rdev) 106 { 107 uint32_t size_reg; 108 uint32_t tmp; 109 110 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 111 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 112 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 113 /* Check gart size */ 114 switch(rdev->mc.gtt_size / (1024 * 1024)) { 115 case 32: 116 size_reg = RS480_VA_SIZE_32MB; 117 break; 118 case 64: 119 size_reg = RS480_VA_SIZE_64MB; 120 break; 121 case 128: 122 size_reg = RS480_VA_SIZE_128MB; 123 break; 124 case 256: 125 size_reg = RS480_VA_SIZE_256MB; 126 break; 127 case 512: 128 size_reg = RS480_VA_SIZE_512MB; 129 break; 130 case 1024: 131 size_reg = RS480_VA_SIZE_1GB; 132 break; 133 case 2048: 134 size_reg = RS480_VA_SIZE_2GB; 135 break; 136 default: 137 return -EINVAL; 138 } 139 /* It should be fine to program it to max value */ 140 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 141 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 142 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 143 } else { 144 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 145 WREG32(RS480_AGP_BASE_2, 0); 146 } 147 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 148 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 149 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 150 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 151 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 152 WREG32(RADEON_BUS_CNTL, tmp); 153 } else { 154 WREG32(RADEON_MC_AGP_LOCATION, tmp); 155 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 156 WREG32(RADEON_BUS_CNTL, tmp); 157 } 158 /* Table should be in 32bits address space so ignore bits above. */ 159 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 160 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 161 162 WREG32_MC(RS480_GART_BASE, tmp); 163 /* TODO: more tweaking here */ 164 WREG32_MC(RS480_GART_FEATURE_ID, 165 (RS480_TLB_ENABLE | 166 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 167 /* Disable snooping */ 168 WREG32_MC(RS480_AGP_MODE_CNTL, 169 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 170 /* Disable AGP mode */ 171 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 172 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 173 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 174 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 175 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; 176 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 177 } else { 178 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 179 tmp |= RS480_GART_INDEX_REG_EN; 180 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 181 } 182 /* Enable gart */ 183 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 184 rs400_gart_tlb_flush(rdev); 185 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 186 (unsigned)(rdev->mc.gtt_size >> 20), 187 (unsigned long long)rdev->gart.table_addr); 188 rdev->gart.ready = true; 189 return 0; 190 } 191 192 void rs400_gart_disable(struct radeon_device *rdev) 193 { 194 uint32_t tmp; 195 196 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 197 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 198 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 199 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 200 } 201 202 void rs400_gart_fini(struct radeon_device *rdev) 203 { 204 radeon_gart_fini(rdev); 205 rs400_gart_disable(rdev); 206 radeon_gart_table_ram_free(rdev); 207 } 208 209 #define RS400_PTE_UNSNOOPED (1 << 0) 210 #define RS400_PTE_WRITEABLE (1 << 2) 211 #define RS400_PTE_READABLE (1 << 3) 212 213 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags) 214 { 215 uint32_t entry; 216 217 entry = (lower_32_bits(addr) & 0xfffff000) | 218 ((upper_32_bits(addr) & 0xff) << 4); 219 if (flags & RADEON_GART_PAGE_READ) 220 entry |= RS400_PTE_READABLE; 221 if (flags & RADEON_GART_PAGE_WRITE) 222 entry |= RS400_PTE_WRITEABLE; 223 if (!(flags & RADEON_GART_PAGE_SNOOP)) 224 entry |= RS400_PTE_UNSNOOPED; 225 return entry; 226 } 227 228 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 229 uint64_t entry) 230 { 231 u32 *gtt = rdev->gart.ptr; 232 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 233 } 234 235 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 236 { 237 unsigned i; 238 uint32_t tmp; 239 240 for (i = 0; i < rdev->usec_timeout; i++) { 241 /* read MC_STATUS */ 242 tmp = RREG32(RADEON_MC_STATUS); 243 if (tmp & RADEON_MC_IDLE) { 244 return 0; 245 } 246 DRM_UDELAY(1); 247 } 248 return -1; 249 } 250 251 static void rs400_gpu_init(struct radeon_device *rdev) 252 { 253 /* FIXME: is this correct ? */ 254 r420_pipes_init(rdev); 255 if (rs400_mc_wait_for_idle(rdev)) { 256 printk(KERN_WARNING "rs400: Failed to wait MC idle while " 257 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 258 } 259 } 260 261 static void rs400_mc_init(struct radeon_device *rdev) 262 { 263 u64 base; 264 265 rs400_gart_adjust_size(rdev); 266 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 267 /* DDR for all card after R300 & IGP */ 268 rdev->mc.vram_is_ddr = true; 269 rdev->mc.vram_width = 128; 270 r100_vram_init_sizes(rdev); 271 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 272 radeon_vram_location(rdev, &rdev->mc, base); 273 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 274 radeon_gtt_location(rdev, &rdev->mc); 275 radeon_update_bandwidth_info(rdev); 276 } 277 278 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 279 { 280 unsigned long flags; 281 uint32_t r; 282 283 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 284 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 285 r = RREG32(RS480_NB_MC_DATA); 286 WREG32(RS480_NB_MC_INDEX, 0xff); 287 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 288 return r; 289 } 290 291 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 292 { 293 unsigned long flags; 294 295 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 296 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 297 WREG32(RS480_NB_MC_DATA, (v)); 298 WREG32(RS480_NB_MC_INDEX, 0xff); 299 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 300 } 301 302 #if defined(CONFIG_DEBUG_FS) 303 static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 304 { 305 struct drm_info_node *node = (struct drm_info_node *) m->private; 306 struct drm_device *dev = node->minor->dev; 307 struct radeon_device *rdev = dev->dev_private; 308 uint32_t tmp; 309 310 tmp = RREG32(RADEON_HOST_PATH_CNTL); 311 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 312 tmp = RREG32(RADEON_BUS_CNTL); 313 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 314 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 315 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 316 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 317 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 318 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 319 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 320 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 321 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 322 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 323 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 324 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 325 tmp = RREG32(RS690_HDP_FB_LOCATION); 326 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 327 } else { 328 tmp = RREG32(RADEON_AGP_BASE); 329 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 330 tmp = RREG32(RS480_AGP_BASE_2); 331 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 332 tmp = RREG32(RADEON_MC_AGP_LOCATION); 333 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 334 } 335 tmp = RREG32_MC(RS480_GART_BASE); 336 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 337 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 338 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 339 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 340 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 341 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 342 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 343 tmp = RREG32_MC(0x5F); 344 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 345 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 346 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 347 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 348 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 349 tmp = RREG32_MC(0x3B); 350 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 351 tmp = RREG32_MC(0x3C); 352 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 353 tmp = RREG32_MC(0x30); 354 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 355 tmp = RREG32_MC(0x31); 356 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 357 tmp = RREG32_MC(0x32); 358 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 359 tmp = RREG32_MC(0x33); 360 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 361 tmp = RREG32_MC(0x34); 362 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 363 tmp = RREG32_MC(0x35); 364 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 365 tmp = RREG32_MC(0x36); 366 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 367 tmp = RREG32_MC(0x37); 368 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 369 return 0; 370 } 371 372 static struct drm_info_list rs400_gart_info_list[] = { 373 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 374 }; 375 #endif 376 377 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 378 { 379 #if defined(CONFIG_DEBUG_FS) 380 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 381 #else 382 return 0; 383 #endif 384 } 385 386 static void rs400_mc_program(struct radeon_device *rdev) 387 { 388 struct r100_mc_save save; 389 390 /* Stops all mc clients */ 391 r100_mc_stop(rdev, &save); 392 393 /* Wait for mc idle */ 394 if (rs400_mc_wait_for_idle(rdev)) 395 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 396 WREG32(R_000148_MC_FB_LOCATION, 397 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 398 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 399 400 r100_mc_resume(rdev, &save); 401 } 402 403 static int rs400_startup(struct radeon_device *rdev) 404 { 405 int r; 406 407 r100_set_common_regs(rdev); 408 409 rs400_mc_program(rdev); 410 /* Resume clock */ 411 r300_clock_startup(rdev); 412 /* Initialize GPU configuration (# pipes, ...) */ 413 rs400_gpu_init(rdev); 414 r100_enable_bm(rdev); 415 /* Initialize GART (initialize after TTM so we can allocate 416 * memory through TTM but finalize after TTM) */ 417 r = rs400_gart_enable(rdev); 418 if (r) 419 return r; 420 421 /* allocate wb buffer */ 422 r = radeon_wb_init(rdev); 423 if (r) 424 return r; 425 426 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 427 if (r) { 428 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 429 return r; 430 } 431 432 /* Enable IRQ */ 433 if (!rdev->irq.installed) { 434 r = radeon_irq_kms_init(rdev); 435 if (r) 436 return r; 437 } 438 439 r100_irq_set(rdev); 440 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 441 /* 1M ring buffer */ 442 r = r100_cp_init(rdev, 1024 * 1024); 443 if (r) { 444 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 445 return r; 446 } 447 448 r = radeon_ib_pool_init(rdev); 449 if (r) { 450 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 451 return r; 452 } 453 454 return 0; 455 } 456 457 int rs400_resume(struct radeon_device *rdev) 458 { 459 int r; 460 461 /* Make sur GART are not working */ 462 rs400_gart_disable(rdev); 463 /* Resume clock before doing reset */ 464 r300_clock_startup(rdev); 465 /* setup MC before calling post tables */ 466 rs400_mc_program(rdev); 467 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 468 if (radeon_asic_reset(rdev)) { 469 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 470 RREG32(R_000E40_RBBM_STATUS), 471 RREG32(R_0007C0_CP_STAT)); 472 } 473 /* post */ 474 radeon_combios_asic_init(rdev->ddev); 475 /* Resume clock after posting */ 476 r300_clock_startup(rdev); 477 /* Initialize surface registers */ 478 radeon_surface_init(rdev); 479 480 rdev->accel_working = true; 481 r = rs400_startup(rdev); 482 if (r) { 483 rdev->accel_working = false; 484 } 485 return r; 486 } 487 488 int rs400_suspend(struct radeon_device *rdev) 489 { 490 radeon_pm_suspend(rdev); 491 r100_cp_disable(rdev); 492 radeon_wb_disable(rdev); 493 r100_irq_disable(rdev); 494 rs400_gart_disable(rdev); 495 return 0; 496 } 497 498 void rs400_fini(struct radeon_device *rdev) 499 { 500 radeon_pm_fini(rdev); 501 r100_cp_fini(rdev); 502 radeon_wb_fini(rdev); 503 radeon_ib_pool_fini(rdev); 504 radeon_gem_fini(rdev); 505 rs400_gart_fini(rdev); 506 radeon_irq_kms_fini(rdev); 507 radeon_fence_driver_fini(rdev); 508 radeon_bo_fini(rdev); 509 radeon_atombios_fini(rdev); 510 kfree(rdev->bios); 511 rdev->bios = NULL; 512 } 513 514 int rs400_init(struct radeon_device *rdev) 515 { 516 int r; 517 518 /* Disable VGA */ 519 r100_vga_render_disable(rdev); 520 /* Initialize scratch registers */ 521 radeon_scratch_init(rdev); 522 /* Initialize surface registers */ 523 radeon_surface_init(rdev); 524 /* TODO: disable VGA need to use VGA request */ 525 /* restore some register to sane defaults */ 526 r100_restore_sanity(rdev); 527 /* BIOS*/ 528 if (!radeon_get_bios(rdev)) { 529 if (ASIC_IS_AVIVO(rdev)) 530 return -EINVAL; 531 } 532 if (rdev->is_atom_bios) { 533 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 534 return -EINVAL; 535 } else { 536 r = radeon_combios_init(rdev); 537 if (r) 538 return r; 539 } 540 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 541 if (radeon_asic_reset(rdev)) { 542 dev_warn(rdev->dev, 543 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 544 RREG32(R_000E40_RBBM_STATUS), 545 RREG32(R_0007C0_CP_STAT)); 546 } 547 /* check if cards are posted or not */ 548 if (radeon_boot_test_post_card(rdev) == false) 549 return -EINVAL; 550 551 /* Initialize clocks */ 552 radeon_get_clock_info(rdev->ddev); 553 /* initialize memory controller */ 554 rs400_mc_init(rdev); 555 /* Fence driver */ 556 r = radeon_fence_driver_init(rdev); 557 if (r) 558 return r; 559 /* Memory manager */ 560 r = radeon_bo_init(rdev); 561 if (r) 562 return r; 563 r = rs400_gart_init(rdev); 564 if (r) 565 return r; 566 r300_set_reg_safe(rdev); 567 568 /* Initialize power management */ 569 radeon_pm_init(rdev); 570 571 rdev->accel_working = true; 572 r = rs400_startup(rdev); 573 if (r) { 574 /* Somethings want wront with the accel init stop accel */ 575 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 576 r100_cp_fini(rdev); 577 radeon_wb_fini(rdev); 578 radeon_ib_pool_fini(rdev); 579 rs400_gart_fini(rdev); 580 radeon_irq_kms_fini(rdev); 581 rdev->accel_working = false; 582 } 583 return 0; 584 } 585