1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/rs400.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 #include <drm/drmP.h> 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "rs400d.h" 34 35 /* This files gather functions specifics to : rs400,rs480 */ 36 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 37 38 void rs400_gart_adjust_size(struct radeon_device *rdev) 39 { 40 /* Check gart size */ 41 switch (rdev->mc.gtt_size/(1024*1024)) { 42 case 32: 43 case 64: 44 case 128: 45 case 256: 46 case 512: 47 case 1024: 48 case 2048: 49 break; 50 default: 51 DRM_ERROR("Unable to use IGP GART size %uM\n", 52 (unsigned)(rdev->mc.gtt_size >> 20)); 53 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 54 DRM_ERROR("Forcing to 32M GART size\n"); 55 rdev->mc.gtt_size = 32 * 1024 * 1024; 56 return; 57 } 58 } 59 60 void rs400_gart_tlb_flush(struct radeon_device *rdev) 61 { 62 uint32_t tmp; 63 unsigned int timeout = rdev->usec_timeout; 64 65 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 66 do { 67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 68 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 69 break; 70 DRM_UDELAY(1); 71 timeout--; 72 } while (timeout > 0); 73 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 74 } 75 76 int rs400_gart_init(struct radeon_device *rdev) 77 { 78 int r; 79 80 if (rdev->gart.ptr) { 81 WARN(1, "RS400 GART already initialized\n"); 82 return 0; 83 } 84 /* Check gart size */ 85 switch(rdev->mc.gtt_size / (1024 * 1024)) { 86 case 32: 87 case 64: 88 case 128: 89 case 256: 90 case 512: 91 case 1024: 92 case 2048: 93 break; 94 default: 95 return -EINVAL; 96 } 97 /* Initialize common gart structure */ 98 r = radeon_gart_init(rdev); 99 if (r) 100 return r; 101 if (rs400_debugfs_pcie_gart_info_init(rdev)) 102 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 104 return radeon_gart_table_ram_alloc(rdev); 105 } 106 107 int rs400_gart_enable(struct radeon_device *rdev) 108 { 109 uint32_t size_reg; 110 uint32_t tmp; 111 112 radeon_gart_restore(rdev); 113 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 114 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 115 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 116 /* Check gart size */ 117 switch(rdev->mc.gtt_size / (1024 * 1024)) { 118 case 32: 119 size_reg = RS480_VA_SIZE_32MB; 120 break; 121 case 64: 122 size_reg = RS480_VA_SIZE_64MB; 123 break; 124 case 128: 125 size_reg = RS480_VA_SIZE_128MB; 126 break; 127 case 256: 128 size_reg = RS480_VA_SIZE_256MB; 129 break; 130 case 512: 131 size_reg = RS480_VA_SIZE_512MB; 132 break; 133 case 1024: 134 size_reg = RS480_VA_SIZE_1GB; 135 break; 136 case 2048: 137 size_reg = RS480_VA_SIZE_2GB; 138 break; 139 default: 140 return -EINVAL; 141 } 142 /* It should be fine to program it to max value */ 143 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 144 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 145 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 146 } else { 147 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 148 WREG32(RS480_AGP_BASE_2, 0); 149 } 150 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 151 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 152 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 153 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 154 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 155 WREG32(RADEON_BUS_CNTL, tmp); 156 } else { 157 WREG32(RADEON_MC_AGP_LOCATION, tmp); 158 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 159 WREG32(RADEON_BUS_CNTL, tmp); 160 } 161 /* Table should be in 32bits address space so ignore bits above. */ 162 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 163 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 164 165 WREG32_MC(RS480_GART_BASE, tmp); 166 /* TODO: more tweaking here */ 167 WREG32_MC(RS480_GART_FEATURE_ID, 168 (RS480_TLB_ENABLE | 169 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 170 /* Disable snooping */ 171 WREG32_MC(RS480_AGP_MODE_CNTL, 172 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 173 /* Disable AGP mode */ 174 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 175 tmp = RREG32_MC(RS690_MC_NB_CNTL); 176 tmp &= ~(RS690_HIDE_MMCFG_BAR | 177 RS690_AGPMODE30 | 178 RS690_AGP30ENHANCED); 179 WREG32_MC(RS690_MC_NB_CNTL, tmp); 180 WREG32_MC(RS480_MC_MISC_CNTL, 181 (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); 182 } else { 183 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 184 } 185 /* Enable gart */ 186 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 187 rs400_gart_tlb_flush(rdev); 188 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 189 (unsigned)(rdev->mc.gtt_size >> 20), 190 (unsigned long long)rdev->gart.table_addr); 191 rdev->gart.ready = true; 192 return 0; 193 } 194 195 void rs400_gart_disable(struct radeon_device *rdev) 196 { 197 uint32_t tmp; 198 199 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 200 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 201 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 202 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 203 } 204 205 void rs400_gart_fini(struct radeon_device *rdev) 206 { 207 radeon_gart_fini(rdev); 208 rs400_gart_disable(rdev); 209 radeon_gart_table_ram_free(rdev); 210 } 211 212 #define RS400_PTE_WRITEABLE (1 << 2) 213 #define RS400_PTE_READABLE (1 << 3) 214 215 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 216 { 217 uint32_t entry; 218 u32 *gtt = rdev->gart.ptr; 219 220 if (i < 0 || i > rdev->gart.num_gpu_pages) { 221 return -EINVAL; 222 } 223 224 entry = (lower_32_bits(addr) & 0xfffff000) | 225 ((upper_32_bits(addr) & 0xff) << 4) | 226 RS400_PTE_WRITEABLE | RS400_PTE_READABLE; 227 entry = cpu_to_le32(entry); 228 gtt[i] = entry; 229 return 0; 230 } 231 232 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 233 { 234 unsigned i; 235 uint32_t tmp; 236 237 for (i = 0; i < rdev->usec_timeout; i++) { 238 /* read MC_STATUS */ 239 tmp = RREG32(RADEON_MC_STATUS); 240 if (tmp & RADEON_MC_IDLE) { 241 return 0; 242 } 243 DRM_UDELAY(1); 244 } 245 return -1; 246 } 247 248 static void rs400_gpu_init(struct radeon_device *rdev) 249 { 250 /* FIXME: is this correct ? */ 251 r420_pipes_init(rdev); 252 if (rs400_mc_wait_for_idle(rdev)) { 253 printk(KERN_WARNING "rs400: Failed to wait MC idle while " 254 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 255 } 256 } 257 258 static void rs400_mc_init(struct radeon_device *rdev) 259 { 260 u64 base; 261 262 rs400_gart_adjust_size(rdev); 263 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 264 /* DDR for all card after R300 & IGP */ 265 rdev->mc.vram_is_ddr = true; 266 rdev->mc.vram_width = 128; 267 r100_vram_init_sizes(rdev); 268 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 269 radeon_vram_location(rdev, &rdev->mc, base); 270 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 271 radeon_gtt_location(rdev, &rdev->mc); 272 radeon_update_bandwidth_info(rdev); 273 } 274 275 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 276 { 277 uint32_t r; 278 279 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 280 r = RREG32(RS480_NB_MC_DATA); 281 WREG32(RS480_NB_MC_INDEX, 0xff); 282 return r; 283 } 284 285 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 286 { 287 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 288 WREG32(RS480_NB_MC_DATA, (v)); 289 WREG32(RS480_NB_MC_INDEX, 0xff); 290 } 291 292 #if defined(CONFIG_DEBUG_FS) 293 static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 294 { 295 struct drm_info_node *node = (struct drm_info_node *) m->private; 296 struct drm_device *dev = node->minor->dev; 297 struct radeon_device *rdev = dev->dev_private; 298 uint32_t tmp; 299 300 tmp = RREG32(RADEON_HOST_PATH_CNTL); 301 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 302 tmp = RREG32(RADEON_BUS_CNTL); 303 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 304 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 305 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 306 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 307 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 308 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 309 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 310 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 311 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 312 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 313 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 314 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 315 tmp = RREG32(RS690_HDP_FB_LOCATION); 316 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 317 } else { 318 tmp = RREG32(RADEON_AGP_BASE); 319 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 320 tmp = RREG32(RS480_AGP_BASE_2); 321 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 322 tmp = RREG32(RADEON_MC_AGP_LOCATION); 323 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 324 } 325 tmp = RREG32_MC(RS480_GART_BASE); 326 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 327 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 328 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 329 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 330 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 331 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 332 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 333 tmp = RREG32_MC(0x5F); 334 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 335 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 336 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 337 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 338 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 339 tmp = RREG32_MC(0x3B); 340 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 341 tmp = RREG32_MC(0x3C); 342 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 343 tmp = RREG32_MC(0x30); 344 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 345 tmp = RREG32_MC(0x31); 346 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 347 tmp = RREG32_MC(0x32); 348 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 349 tmp = RREG32_MC(0x33); 350 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 351 tmp = RREG32_MC(0x34); 352 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 353 tmp = RREG32_MC(0x35); 354 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 355 tmp = RREG32_MC(0x36); 356 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 357 tmp = RREG32_MC(0x37); 358 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 359 return 0; 360 } 361 362 static struct drm_info_list rs400_gart_info_list[] = { 363 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 364 }; 365 #endif 366 367 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 368 { 369 #if defined(CONFIG_DEBUG_FS) 370 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 371 #else 372 return 0; 373 #endif 374 } 375 376 static void rs400_mc_program(struct radeon_device *rdev) 377 { 378 struct r100_mc_save save; 379 380 /* Stops all mc clients */ 381 r100_mc_stop(rdev, &save); 382 383 /* Wait for mc idle */ 384 if (rs400_mc_wait_for_idle(rdev)) 385 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 386 WREG32(R_000148_MC_FB_LOCATION, 387 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 388 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 389 390 r100_mc_resume(rdev, &save); 391 } 392 393 static int rs400_startup(struct radeon_device *rdev) 394 { 395 int r; 396 397 r100_set_common_regs(rdev); 398 399 rs400_mc_program(rdev); 400 /* Resume clock */ 401 r300_clock_startup(rdev); 402 /* Initialize GPU configuration (# pipes, ...) */ 403 rs400_gpu_init(rdev); 404 r100_enable_bm(rdev); 405 /* Initialize GART (initialize after TTM so we can allocate 406 * memory through TTM but finalize after TTM) */ 407 r = rs400_gart_enable(rdev); 408 if (r) 409 return r; 410 411 /* allocate wb buffer */ 412 r = radeon_wb_init(rdev); 413 if (r) 414 return r; 415 416 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 417 if (r) { 418 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 419 return r; 420 } 421 422 /* Enable IRQ */ 423 if (!rdev->irq.installed) { 424 r = radeon_irq_kms_init(rdev); 425 if (r) 426 return r; 427 } 428 429 r100_irq_set(rdev); 430 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 431 /* 1M ring buffer */ 432 r = r100_cp_init(rdev, 1024 * 1024); 433 if (r) { 434 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 435 return r; 436 } 437 438 r = radeon_ib_pool_init(rdev); 439 if (r) { 440 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 441 return r; 442 } 443 444 return 0; 445 } 446 447 int rs400_resume(struct radeon_device *rdev) 448 { 449 int r; 450 451 /* Make sur GART are not working */ 452 rs400_gart_disable(rdev); 453 /* Resume clock before doing reset */ 454 r300_clock_startup(rdev); 455 /* setup MC before calling post tables */ 456 rs400_mc_program(rdev); 457 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 458 if (radeon_asic_reset(rdev)) { 459 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 460 RREG32(R_000E40_RBBM_STATUS), 461 RREG32(R_0007C0_CP_STAT)); 462 } 463 /* post */ 464 radeon_combios_asic_init(rdev->ddev); 465 /* Resume clock after posting */ 466 r300_clock_startup(rdev); 467 /* Initialize surface registers */ 468 radeon_surface_init(rdev); 469 470 rdev->accel_working = true; 471 r = rs400_startup(rdev); 472 if (r) { 473 rdev->accel_working = false; 474 } 475 return r; 476 } 477 478 int rs400_suspend(struct radeon_device *rdev) 479 { 480 r100_cp_disable(rdev); 481 radeon_wb_disable(rdev); 482 r100_irq_disable(rdev); 483 rs400_gart_disable(rdev); 484 return 0; 485 } 486 487 void rs400_fini(struct radeon_device *rdev) 488 { 489 r100_cp_fini(rdev); 490 radeon_wb_fini(rdev); 491 radeon_ib_pool_fini(rdev); 492 radeon_gem_fini(rdev); 493 rs400_gart_fini(rdev); 494 radeon_irq_kms_fini(rdev); 495 radeon_fence_driver_fini(rdev); 496 radeon_bo_fini(rdev); 497 radeon_atombios_fini(rdev); 498 kfree(rdev->bios); 499 rdev->bios = NULL; 500 } 501 502 int rs400_init(struct radeon_device *rdev) 503 { 504 int r; 505 506 /* Disable VGA */ 507 r100_vga_render_disable(rdev); 508 /* Initialize scratch registers */ 509 radeon_scratch_init(rdev); 510 /* Initialize surface registers */ 511 radeon_surface_init(rdev); 512 /* TODO: disable VGA need to use VGA request */ 513 /* restore some register to sane defaults */ 514 r100_restore_sanity(rdev); 515 /* BIOS*/ 516 if (!radeon_get_bios(rdev)) { 517 if (ASIC_IS_AVIVO(rdev)) 518 return -EINVAL; 519 } 520 if (rdev->is_atom_bios) { 521 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 522 return -EINVAL; 523 } else { 524 r = radeon_combios_init(rdev); 525 if (r) 526 return r; 527 } 528 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 529 if (radeon_asic_reset(rdev)) { 530 dev_warn(rdev->dev, 531 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 532 RREG32(R_000E40_RBBM_STATUS), 533 RREG32(R_0007C0_CP_STAT)); 534 } 535 /* check if cards are posted or not */ 536 if (radeon_boot_test_post_card(rdev) == false) 537 return -EINVAL; 538 539 /* Initialize clocks */ 540 radeon_get_clock_info(rdev->ddev); 541 /* initialize memory controller */ 542 rs400_mc_init(rdev); 543 /* Fence driver */ 544 r = radeon_fence_driver_init(rdev); 545 if (r) 546 return r; 547 /* Memory manager */ 548 r = radeon_bo_init(rdev); 549 if (r) 550 return r; 551 r = rs400_gart_init(rdev); 552 if (r) 553 return r; 554 r300_set_reg_safe(rdev); 555 556 rdev->accel_working = true; 557 r = rs400_startup(rdev); 558 if (r) { 559 /* Somethings want wront with the accel init stop accel */ 560 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 561 r100_cp_fini(rdev); 562 radeon_wb_fini(rdev); 563 radeon_ib_pool_fini(rdev); 564 rs400_gart_fini(rdev); 565 radeon_irq_kms_fini(rdev); 566 rdev->accel_working = false; 567 } 568 return 0; 569 } 570