1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 /* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 */ 38 #include <drm/drmP.h> 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "atom.h" 42 #include "rs600d.h" 43 44 #include "rs600_reg_safe.h" 45 46 static void rs600_gpu_init(struct radeon_device *rdev); 47 48 static const u32 crtc_offsets[2] = 49 { 50 0, 51 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 52 }; 53 54 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) 55 { 56 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 57 return true; 58 else 59 return false; 60 } 61 62 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) 63 { 64 u32 pos1, pos2; 65 66 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 67 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 68 69 if (pos1 != pos2) 70 return true; 71 else 72 return false; 73 } 74 75 /** 76 * avivo_wait_for_vblank - vblank wait asic callback. 77 * 78 * @rdev: radeon_device pointer 79 * @crtc: crtc to wait for vblank on 80 * 81 * Wait for vblank on the requested crtc (r5xx-r7xx). 82 */ 83 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 84 { 85 unsigned i = 0; 86 87 if (crtc >= rdev->num_crtc) 88 return; 89 90 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) 91 return; 92 93 /* depending on when we hit vblank, we may be close to active; if so, 94 * wait for another frame. 95 */ 96 while (avivo_is_in_vblank(rdev, crtc)) { 97 if (i++ % 100 == 0) { 98 if (!avivo_is_counter_moving(rdev, crtc)) 99 break; 100 } 101 } 102 103 while (!avivo_is_in_vblank(rdev, crtc)) { 104 if (i++ % 100 == 0) { 105 if (!avivo_is_counter_moving(rdev, crtc)) 106 break; 107 } 108 } 109 } 110 111 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 112 { 113 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 114 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 115 int i; 116 117 /* Lock the graphics update lock */ 118 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 119 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 120 121 /* update the scanout addresses */ 122 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 123 (u32)crtc_base); 124 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 125 (u32)crtc_base); 126 127 /* Wait for update_pending to go high. */ 128 for (i = 0; i < rdev->usec_timeout; i++) { 129 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 130 break; 131 udelay(1); 132 } 133 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 134 135 /* Unlock the lock, so double-buffering can take place inside vblank */ 136 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 137 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 138 } 139 140 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id) 141 { 142 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 143 144 /* Return current update_pending status: */ 145 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & 146 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); 147 } 148 149 void avivo_program_fmt(struct drm_encoder *encoder) 150 { 151 struct drm_device *dev = encoder->dev; 152 struct radeon_device *rdev = dev->dev_private; 153 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 154 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 155 int bpc = 0; 156 u32 tmp = 0; 157 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 158 159 if (connector) { 160 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 161 bpc = radeon_get_monitor_bpc(connector); 162 dither = radeon_connector->dither; 163 } 164 165 /* LVDS FMT is set up by atom */ 166 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 167 return; 168 169 if (bpc == 0) 170 return; 171 172 switch (bpc) { 173 case 6: 174 if (dither == RADEON_FMT_DITHER_ENABLE) 175 /* XXX sort out optimal dither settings */ 176 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 177 else 178 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; 179 break; 180 case 8: 181 if (dither == RADEON_FMT_DITHER_ENABLE) 182 /* XXX sort out optimal dither settings */ 183 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | 184 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); 185 else 186 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | 187 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); 188 break; 189 case 10: 190 default: 191 /* not needed */ 192 break; 193 } 194 195 switch (radeon_encoder->encoder_id) { 196 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 197 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); 198 break; 199 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 200 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); 201 break; 202 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 203 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); 204 break; 205 case ENCODER_OBJECT_ID_INTERNAL_DDI: 206 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); 207 break; 208 default: 209 break; 210 } 211 } 212 213 void rs600_pm_misc(struct radeon_device *rdev) 214 { 215 int requested_index = rdev->pm.requested_power_state_index; 216 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 217 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 218 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 219 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 220 221 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 222 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 223 tmp = RREG32(voltage->gpio.reg); 224 if (voltage->active_high) 225 tmp |= voltage->gpio.mask; 226 else 227 tmp &= ~(voltage->gpio.mask); 228 WREG32(voltage->gpio.reg, tmp); 229 if (voltage->delay) 230 udelay(voltage->delay); 231 } else { 232 tmp = RREG32(voltage->gpio.reg); 233 if (voltage->active_high) 234 tmp &= ~voltage->gpio.mask; 235 else 236 tmp |= voltage->gpio.mask; 237 WREG32(voltage->gpio.reg, tmp); 238 if (voltage->delay) 239 udelay(voltage->delay); 240 } 241 } else if (voltage->type == VOLTAGE_VDDC) 242 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 243 244 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 245 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 246 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 247 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 248 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 249 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 250 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 251 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 252 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 253 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 254 } 255 } else { 256 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 257 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 258 } 259 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 260 261 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 262 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 263 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 264 if (voltage->delay) { 265 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 266 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 267 } else 268 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 269 } else 270 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 271 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 272 273 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 274 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 275 hdp_dyn_cntl &= ~HDP_FORCEON; 276 else 277 hdp_dyn_cntl |= HDP_FORCEON; 278 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 279 #if 0 280 /* mc_host_dyn seems to cause hangs from time to time */ 281 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 282 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 283 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 284 else 285 mc_host_dyn_cntl |= MC_HOST_FORCEON; 286 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 287 #endif 288 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 289 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 290 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 291 else 292 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 293 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 294 295 /* set pcie lanes */ 296 if ((rdev->flags & RADEON_IS_PCIE) && 297 !(rdev->flags & RADEON_IS_IGP) && 298 rdev->asic->pm.set_pcie_lanes && 299 (ps->pcie_lanes != 300 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 301 radeon_set_pcie_lanes(rdev, 302 ps->pcie_lanes); 303 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 304 } 305 } 306 307 void rs600_pm_prepare(struct radeon_device *rdev) 308 { 309 struct drm_device *ddev = rdev->ddev; 310 struct drm_crtc *crtc; 311 struct radeon_crtc *radeon_crtc; 312 u32 tmp; 313 314 /* disable any active CRTCs */ 315 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 316 radeon_crtc = to_radeon_crtc(crtc); 317 if (radeon_crtc->enabled) { 318 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 319 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 320 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 321 } 322 } 323 } 324 325 void rs600_pm_finish(struct radeon_device *rdev) 326 { 327 struct drm_device *ddev = rdev->ddev; 328 struct drm_crtc *crtc; 329 struct radeon_crtc *radeon_crtc; 330 u32 tmp; 331 332 /* enable any active CRTCs */ 333 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 334 radeon_crtc = to_radeon_crtc(crtc); 335 if (radeon_crtc->enabled) { 336 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 337 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 338 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 339 } 340 } 341 } 342 343 /* hpd for digital panel detect/disconnect */ 344 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 345 { 346 u32 tmp; 347 bool connected = false; 348 349 switch (hpd) { 350 case RADEON_HPD_1: 351 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 352 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 353 connected = true; 354 break; 355 case RADEON_HPD_2: 356 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 357 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 358 connected = true; 359 break; 360 default: 361 break; 362 } 363 return connected; 364 } 365 366 void rs600_hpd_set_polarity(struct radeon_device *rdev, 367 enum radeon_hpd_id hpd) 368 { 369 u32 tmp; 370 bool connected = rs600_hpd_sense(rdev, hpd); 371 372 switch (hpd) { 373 case RADEON_HPD_1: 374 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 375 if (connected) 376 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 377 else 378 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 379 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 380 break; 381 case RADEON_HPD_2: 382 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 383 if (connected) 384 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 385 else 386 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 387 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 388 break; 389 default: 390 break; 391 } 392 } 393 394 void rs600_hpd_init(struct radeon_device *rdev) 395 { 396 struct drm_device *dev = rdev->ddev; 397 struct drm_connector *connector; 398 unsigned enable = 0; 399 400 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 401 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 402 switch (radeon_connector->hpd.hpd) { 403 case RADEON_HPD_1: 404 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 405 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 406 break; 407 case RADEON_HPD_2: 408 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 409 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 410 break; 411 default: 412 break; 413 } 414 enable |= 1 << radeon_connector->hpd.hpd; 415 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 416 } 417 radeon_irq_kms_enable_hpd(rdev, enable); 418 } 419 420 void rs600_hpd_fini(struct radeon_device *rdev) 421 { 422 struct drm_device *dev = rdev->ddev; 423 struct drm_connector *connector; 424 unsigned disable = 0; 425 426 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 427 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 428 switch (radeon_connector->hpd.hpd) { 429 case RADEON_HPD_1: 430 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 431 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 432 break; 433 case RADEON_HPD_2: 434 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 435 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 436 break; 437 default: 438 break; 439 } 440 disable |= 1 << radeon_connector->hpd.hpd; 441 } 442 radeon_irq_kms_disable_hpd(rdev, disable); 443 } 444 445 int rs600_asic_reset(struct radeon_device *rdev) 446 { 447 struct rv515_mc_save save; 448 u32 status, tmp; 449 int ret = 0; 450 451 status = RREG32(R_000E40_RBBM_STATUS); 452 if (!G_000E40_GUI_ACTIVE(status)) { 453 return 0; 454 } 455 /* Stops all mc clients */ 456 rv515_mc_stop(rdev, &save); 457 status = RREG32(R_000E40_RBBM_STATUS); 458 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 459 /* stop CP */ 460 WREG32(RADEON_CP_CSQ_CNTL, 0); 461 tmp = RREG32(RADEON_CP_RB_CNTL); 462 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 463 WREG32(RADEON_CP_RB_RPTR_WR, 0); 464 WREG32(RADEON_CP_RB_WPTR, 0); 465 WREG32(RADEON_CP_RB_CNTL, tmp); 466 pci_save_state(device_get_parent(rdev->dev->bsddev)); 467 /* disable bus mastering */ 468 pci_disable_busmaster(rdev->dev->bsddev); 469 mdelay(1); 470 /* reset GA+VAP */ 471 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 472 S_0000F0_SOFT_RESET_GA(1)); 473 RREG32(R_0000F0_RBBM_SOFT_RESET); 474 mdelay(500); 475 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 476 mdelay(1); 477 status = RREG32(R_000E40_RBBM_STATUS); 478 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 479 /* reset CP */ 480 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 481 RREG32(R_0000F0_RBBM_SOFT_RESET); 482 mdelay(500); 483 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 484 mdelay(1); 485 status = RREG32(R_000E40_RBBM_STATUS); 486 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 487 /* reset MC */ 488 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 489 RREG32(R_0000F0_RBBM_SOFT_RESET); 490 mdelay(500); 491 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 492 mdelay(1); 493 status = RREG32(R_000E40_RBBM_STATUS); 494 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 495 /* restore PCI & busmastering */ 496 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 497 /* Check if GPU is idle */ 498 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 499 dev_err(rdev->dev, "failed to reset GPU\n"); 500 ret = -1; 501 } else 502 dev_info(rdev->dev, "GPU reset succeed\n"); 503 rv515_mc_resume(rdev, &save); 504 return ret; 505 } 506 507 /* 508 * GART. 509 */ 510 void rs600_gart_tlb_flush(struct radeon_device *rdev) 511 { 512 uint32_t tmp; 513 514 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 515 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 516 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 517 518 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 519 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 520 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 521 522 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 523 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 524 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 525 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 526 } 527 528 static int rs600_gart_init(struct radeon_device *rdev) 529 { 530 int r; 531 532 if (rdev->gart.robj) { 533 WARN(1, "RS600 GART already initialized\n"); 534 return 0; 535 } 536 /* Initialize common gart structure */ 537 r = radeon_gart_init(rdev); 538 if (r) { 539 return r; 540 } 541 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 542 return radeon_gart_table_vram_alloc(rdev); 543 } 544 545 static int rs600_gart_enable(struct radeon_device *rdev) 546 { 547 u32 tmp; 548 int r, i; 549 550 if (rdev->gart.robj == NULL) { 551 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 552 return -EINVAL; 553 } 554 r = radeon_gart_table_vram_pin(rdev); 555 if (r) 556 return r; 557 /* Enable bus master */ 558 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 559 WREG32(RADEON_BUS_CNTL, tmp); 560 /* FIXME: setup default page */ 561 WREG32_MC(R_000100_MC_PT0_CNTL, 562 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 563 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 564 565 for (i = 0; i < 19; i++) { 566 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 567 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 568 S_00016C_SYSTEM_ACCESS_MODE_MASK( 569 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 570 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 571 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 572 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 573 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 574 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 575 } 576 /* enable first context */ 577 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 578 S_000102_ENABLE_PAGE_TABLE(1) | 579 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 580 581 /* disable all other contexts */ 582 for (i = 1; i < 8; i++) 583 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 584 585 /* setup the page table */ 586 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 587 rdev->gart.table_addr); 588 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 589 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 590 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 591 592 /* System context maps to VRAM space */ 593 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 594 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 595 596 /* enable page tables */ 597 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 598 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 599 tmp = RREG32_MC(R_000009_MC_CNTL1); 600 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 601 rs600_gart_tlb_flush(rdev); 602 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 603 (unsigned)(rdev->mc.gtt_size >> 20), 604 (unsigned long long)rdev->gart.table_addr); 605 rdev->gart.ready = true; 606 return 0; 607 } 608 609 static void rs600_gart_disable(struct radeon_device *rdev) 610 { 611 u32 tmp; 612 613 /* FIXME: disable out of gart access */ 614 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 615 tmp = RREG32_MC(R_000009_MC_CNTL1); 616 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 617 radeon_gart_table_vram_unpin(rdev); 618 } 619 620 static void rs600_gart_fini(struct radeon_device *rdev) 621 { 622 radeon_gart_fini(rdev); 623 rs600_gart_disable(rdev); 624 radeon_gart_table_vram_free(rdev); 625 } 626 627 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) 628 { 629 addr = addr & 0xFFFFFFFFFFFFF000ULL; 630 addr |= R600_PTE_SYSTEM; 631 if (flags & RADEON_GART_PAGE_VALID) 632 addr |= R600_PTE_VALID; 633 if (flags & RADEON_GART_PAGE_READ) 634 addr |= R600_PTE_READABLE; 635 if (flags & RADEON_GART_PAGE_WRITE) 636 addr |= R600_PTE_WRITEABLE; 637 if (flags & RADEON_GART_PAGE_SNOOP) 638 addr |= R600_PTE_SNOOPED; 639 return addr; 640 } 641 642 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 643 uint64_t entry) 644 { 645 void __iomem *ptr = (void *)rdev->gart.ptr; 646 writeq(entry, (uint8_t *)ptr + (i * 8)); 647 } 648 649 int rs600_irq_set(struct radeon_device *rdev) 650 { 651 uint32_t tmp = 0; 652 uint32_t mode_int = 0; 653 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 654 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 655 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 656 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 657 u32 hdmi0; 658 if (ASIC_IS_DCE2(rdev)) 659 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 660 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 661 else 662 hdmi0 = 0; 663 664 if (!rdev->irq.installed) { 665 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 666 WREG32(R_000040_GEN_INT_CNTL, 0); 667 return -EINVAL; 668 } 669 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 670 tmp |= S_000040_SW_INT_EN(1); 671 } 672 if (rdev->irq.crtc_vblank_int[0] || 673 atomic_read(&rdev->irq.pflip[0])) { 674 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 675 } 676 if (rdev->irq.crtc_vblank_int[1] || 677 atomic_read(&rdev->irq.pflip[1])) { 678 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 679 } 680 if (rdev->irq.hpd[0]) { 681 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 682 } 683 if (rdev->irq.hpd[1]) { 684 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 685 } 686 if (rdev->irq.afmt[0]) { 687 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 688 } 689 WREG32(R_000040_GEN_INT_CNTL, tmp); 690 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 691 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 692 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 693 if (ASIC_IS_DCE2(rdev)) 694 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 695 696 /* posting read */ 697 RREG32(R_000040_GEN_INT_CNTL); 698 699 return 0; 700 } 701 702 static inline u32 rs600_irq_ack(struct radeon_device *rdev) 703 { 704 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 705 uint32_t irq_mask = S_000044_SW_INT(1); 706 u32 tmp; 707 708 if (G_000044_DISPLAY_INT_STAT(irqs)) { 709 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 710 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 711 WREG32(R_006534_D1MODE_VBLANK_STATUS, 712 S_006534_D1MODE_VBLANK_ACK(1)); 713 } 714 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 715 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 716 S_006D34_D2MODE_VBLANK_ACK(1)); 717 } 718 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 719 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 720 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 721 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 722 } 723 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 724 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 725 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 726 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 727 } 728 } else { 729 rdev->irq.stat_regs.r500.disp_int = 0; 730 } 731 732 if (ASIC_IS_DCE2(rdev)) { 733 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 734 S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 735 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 736 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 737 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 738 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 739 } 740 } else 741 rdev->irq.stat_regs.r500.hdmi0_status = 0; 742 743 if (irqs) { 744 WREG32(R_000044_GEN_INT_STATUS, irqs); 745 } 746 return irqs & irq_mask; 747 } 748 749 void rs600_irq_disable(struct radeon_device *rdev) 750 { 751 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 752 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 753 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 754 WREG32(R_000040_GEN_INT_CNTL, 0); 755 WREG32(R_006540_DxMODE_INT_MASK, 0); 756 /* Wait and acknowledge irq */ 757 mdelay(1); 758 rs600_irq_ack(rdev); 759 } 760 761 irqreturn_t rs600_irq_process(struct radeon_device *rdev) 762 { 763 u32 status, msi_rearm; 764 bool queue_hotplug = false; 765 bool queue_hdmi = false; 766 767 status = rs600_irq_ack(rdev); 768 if (!status && 769 !rdev->irq.stat_regs.r500.disp_int && 770 !rdev->irq.stat_regs.r500.hdmi0_status) { 771 return IRQ_NONE; 772 } 773 while (status || 774 rdev->irq.stat_regs.r500.disp_int || 775 rdev->irq.stat_regs.r500.hdmi0_status) { 776 /* SW interrupt */ 777 if (G_000044_SW_INT(status)) { 778 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 779 } 780 /* Vertical blank interrupts */ 781 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 782 if (rdev->irq.crtc_vblank_int[0]) { 783 drm_handle_vblank(rdev->ddev, 0); 784 rdev->pm.vblank_sync = true; 785 wake_up(&rdev->irq.vblank_queue); 786 } 787 if (atomic_read(&rdev->irq.pflip[0])) 788 radeon_crtc_handle_vblank(rdev, 0); 789 } 790 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 791 if (rdev->irq.crtc_vblank_int[1]) { 792 drm_handle_vblank(rdev->ddev, 1); 793 rdev->pm.vblank_sync = true; 794 wake_up(&rdev->irq.vblank_queue); 795 } 796 if (atomic_read(&rdev->irq.pflip[1])) 797 radeon_crtc_handle_vblank(rdev, 1); 798 } 799 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 800 queue_hotplug = true; 801 DRM_DEBUG("HPD1\n"); 802 } 803 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 804 queue_hotplug = true; 805 DRM_DEBUG("HPD2\n"); 806 } 807 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 808 queue_hdmi = true; 809 DRM_DEBUG("HDMI0\n"); 810 } 811 status = rs600_irq_ack(rdev); 812 } 813 if (queue_hotplug) 814 schedule_work(&rdev->hotplug_work); 815 if (queue_hdmi) 816 schedule_work(&rdev->audio_work); 817 if (rdev->msi_enabled) { 818 switch (rdev->family) { 819 case CHIP_RS600: 820 case CHIP_RS690: 821 case CHIP_RS740: 822 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 823 WREG32(RADEON_BUS_CNTL, msi_rearm); 824 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 825 break; 826 default: 827 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 828 break; 829 } 830 } 831 return IRQ_HANDLED; 832 } 833 834 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 835 { 836 if (crtc == 0) 837 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 838 else 839 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 840 } 841 842 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 843 { 844 unsigned i; 845 846 for (i = 0; i < rdev->usec_timeout; i++) { 847 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 848 return 0; 849 udelay(1); 850 } 851 return -1; 852 } 853 854 static void rs600_gpu_init(struct radeon_device *rdev) 855 { 856 r420_pipes_init(rdev); 857 /* Wait for mc idle */ 858 if (rs600_mc_wait_for_idle(rdev)) 859 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 860 } 861 862 static void rs600_mc_init(struct radeon_device *rdev) 863 { 864 u64 base; 865 866 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 867 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 868 rdev->mc.vram_is_ddr = true; 869 rdev->mc.vram_width = 128; 870 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 871 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 872 rdev->mc.visible_vram_size = rdev->mc.aper_size; 873 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 874 base = RREG32_MC(R_000004_MC_FB_LOCATION); 875 base = G_000004_MC_FB_START(base) << 16; 876 radeon_vram_location(rdev, &rdev->mc, base); 877 rdev->mc.gtt_base_align = 0; 878 radeon_gtt_location(rdev, &rdev->mc); 879 radeon_update_bandwidth_info(rdev); 880 } 881 882 void rs600_bandwidth_update(struct radeon_device *rdev) 883 { 884 struct drm_display_mode *mode0 = NULL; 885 struct drm_display_mode *mode1 = NULL; 886 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 887 /* FIXME: implement full support */ 888 889 if (!rdev->mode_info.mode_config_initialized) 890 return; 891 892 radeon_update_display_priority(rdev); 893 894 if (rdev->mode_info.crtcs[0]->base.enabled) 895 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 896 if (rdev->mode_info.crtcs[1]->base.enabled) 897 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 898 899 rs690_line_buffer_adjust(rdev, mode0, mode1); 900 901 if (rdev->disp_priority == 2) { 902 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 903 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 904 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 905 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 906 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 907 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 908 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 909 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 910 } 911 } 912 913 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 914 { 915 u32 r; 916 917 spin_lock(&rdev->mc_idx_lock); 918 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 919 S_000070_MC_IND_CITF_ARB0(1)); 920 r = RREG32(R_000074_MC_IND_DATA); 921 spin_unlock(&rdev->mc_idx_lock); 922 return r; 923 } 924 925 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 926 { 927 spin_lock(&rdev->mc_idx_lock); 928 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 929 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 930 WREG32(R_000074_MC_IND_DATA, v); 931 spin_unlock(&rdev->mc_idx_lock); 932 } 933 934 static void rs600_debugfs(struct radeon_device *rdev) 935 { 936 if (r100_debugfs_rbbm_init(rdev)) 937 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 938 } 939 940 void rs600_set_safe_registers(struct radeon_device *rdev) 941 { 942 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 943 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 944 } 945 946 static void rs600_mc_program(struct radeon_device *rdev) 947 { 948 struct rv515_mc_save save; 949 950 /* Stops all mc clients */ 951 rv515_mc_stop(rdev, &save); 952 953 /* Wait for mc idle */ 954 if (rs600_mc_wait_for_idle(rdev)) 955 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 956 957 /* FIXME: What does AGP means for such chipset ? */ 958 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 959 WREG32_MC(R_000006_AGP_BASE, 0); 960 WREG32_MC(R_000007_AGP_BASE_2, 0); 961 /* Program MC */ 962 WREG32_MC(R_000004_MC_FB_LOCATION, 963 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 964 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 965 WREG32(R_000134_HDP_FB_LOCATION, 966 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 967 968 rv515_mc_resume(rdev, &save); 969 } 970 971 static int rs600_startup(struct radeon_device *rdev) 972 { 973 int r; 974 975 rs600_mc_program(rdev); 976 /* Resume clock */ 977 rv515_clock_startup(rdev); 978 /* Initialize GPU configuration (# pipes, ...) */ 979 rs600_gpu_init(rdev); 980 /* Initialize GART (initialize after TTM so we can allocate 981 * memory through TTM but finalize after TTM) */ 982 r = rs600_gart_enable(rdev); 983 if (r) 984 return r; 985 986 /* allocate wb buffer */ 987 r = radeon_wb_init(rdev); 988 if (r) 989 return r; 990 991 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 992 if (r) { 993 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 994 return r; 995 } 996 997 /* Enable IRQ */ 998 if (!rdev->irq.installed) { 999 r = radeon_irq_kms_init(rdev); 1000 if (r) 1001 return r; 1002 } 1003 1004 rs600_irq_set(rdev); 1005 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1006 /* 1M ring buffer */ 1007 r = r100_cp_init(rdev, 1024 * 1024); 1008 if (r) { 1009 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1010 return r; 1011 } 1012 1013 r = radeon_ib_pool_init(rdev); 1014 if (r) { 1015 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1016 return r; 1017 } 1018 1019 r = r600_audio_init(rdev); 1020 if (r) { 1021 dev_err(rdev->dev, "failed initializing audio\n"); 1022 return r; 1023 } 1024 1025 return 0; 1026 } 1027 1028 int rs600_resume(struct radeon_device *rdev) 1029 { 1030 int r; 1031 1032 /* Make sur GART are not working */ 1033 rs600_gart_disable(rdev); 1034 /* Resume clock before doing reset */ 1035 rv515_clock_startup(rdev); 1036 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1037 if (radeon_asic_reset(rdev)) { 1038 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1039 RREG32(R_000E40_RBBM_STATUS), 1040 RREG32(R_0007C0_CP_STAT)); 1041 } 1042 /* post */ 1043 atom_asic_init(rdev->mode_info.atom_context); 1044 /* Resume clock after posting */ 1045 rv515_clock_startup(rdev); 1046 /* Initialize surface registers */ 1047 radeon_surface_init(rdev); 1048 1049 rdev->accel_working = true; 1050 r = rs600_startup(rdev); 1051 if (r) { 1052 rdev->accel_working = false; 1053 } 1054 return r; 1055 } 1056 1057 int rs600_suspend(struct radeon_device *rdev) 1058 { 1059 radeon_pm_suspend(rdev); 1060 r600_audio_fini(rdev); 1061 r100_cp_disable(rdev); 1062 radeon_wb_disable(rdev); 1063 rs600_irq_disable(rdev); 1064 rs600_gart_disable(rdev); 1065 return 0; 1066 } 1067 1068 void rs600_fini(struct radeon_device *rdev) 1069 { 1070 radeon_pm_fini(rdev); 1071 r600_audio_fini(rdev); 1072 r100_cp_fini(rdev); 1073 radeon_wb_fini(rdev); 1074 radeon_ib_pool_fini(rdev); 1075 radeon_gem_fini(rdev); 1076 rs600_gart_fini(rdev); 1077 radeon_irq_kms_fini(rdev); 1078 radeon_fence_driver_fini(rdev); 1079 radeon_bo_fini(rdev); 1080 radeon_atombios_fini(rdev); 1081 kfree(rdev->bios); 1082 rdev->bios = NULL; 1083 } 1084 1085 int rs600_init(struct radeon_device *rdev) 1086 { 1087 int r; 1088 1089 /* Disable VGA */ 1090 rv515_vga_render_disable(rdev); 1091 /* Initialize scratch registers */ 1092 radeon_scratch_init(rdev); 1093 /* Initialize surface registers */ 1094 radeon_surface_init(rdev); 1095 /* restore some register to sane defaults */ 1096 r100_restore_sanity(rdev); 1097 /* BIOS */ 1098 if (!radeon_get_bios(rdev)) { 1099 if (ASIC_IS_AVIVO(rdev)) 1100 return -EINVAL; 1101 } 1102 if (rdev->is_atom_bios) { 1103 r = radeon_atombios_init(rdev); 1104 if (r) 1105 return r; 1106 } else { 1107 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 1108 return -EINVAL; 1109 } 1110 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1111 if (radeon_asic_reset(rdev)) { 1112 dev_warn(rdev->dev, 1113 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1114 RREG32(R_000E40_RBBM_STATUS), 1115 RREG32(R_0007C0_CP_STAT)); 1116 } 1117 /* check if cards are posted or not */ 1118 if (radeon_boot_test_post_card(rdev) == false) 1119 return -EINVAL; 1120 1121 /* Initialize clocks */ 1122 radeon_get_clock_info(rdev->ddev); 1123 /* initialize memory controller */ 1124 rs600_mc_init(rdev); 1125 rs600_debugfs(rdev); 1126 /* Fence driver */ 1127 r = radeon_fence_driver_init(rdev); 1128 if (r) 1129 return r; 1130 /* Memory manager */ 1131 r = radeon_bo_init(rdev); 1132 if (r) 1133 return r; 1134 r = rs600_gart_init(rdev); 1135 if (r) 1136 return r; 1137 rs600_set_safe_registers(rdev); 1138 1139 /* Initialize power management */ 1140 radeon_pm_init(rdev); 1141 1142 rdev->accel_working = true; 1143 r = rs600_startup(rdev); 1144 if (r) { 1145 /* Somethings want wront with the accel init stop accel */ 1146 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1147 r100_cp_fini(rdev); 1148 radeon_wb_fini(rdev); 1149 radeon_ib_pool_fini(rdev); 1150 rs600_gart_fini(rdev); 1151 radeon_irq_kms_fini(rdev); 1152 rdev->accel_working = false; 1153 } 1154 return 0; 1155 } 1156