1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 /* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 * 38 * $FreeBSD: head/sys/dev/drm2/radeon/rs600.c 255573 2013-09-14 17:24:41Z dumbbell $ 39 */ 40 41 #include <drm/drmP.h> 42 #include "radeon.h" 43 #include "radeon_asic.h" 44 #include "atom.h" 45 #include "rs600d.h" 46 47 #include "rs600_reg_safe.h" 48 49 static void rs600_gpu_init(struct radeon_device *rdev); 50 51 static const u32 crtc_offsets[2] = 52 { 53 0, 54 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 55 }; 56 57 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 58 { 59 int i; 60 61 if (crtc >= rdev->num_crtc) 62 return; 63 64 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { 65 for (i = 0; i < rdev->usec_timeout; i++) { 66 if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) 67 break; 68 DRM_UDELAY(1); 69 } 70 for (i = 0; i < rdev->usec_timeout; i++) { 71 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 72 break; 73 DRM_UDELAY(1); 74 } 75 } 76 } 77 78 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc) 79 { 80 /* enable the pflip int */ 81 radeon_irq_kms_pflip_irq_get(rdev, crtc); 82 } 83 84 void rs600_post_page_flip(struct radeon_device *rdev, int crtc) 85 { 86 /* disable the pflip int */ 87 radeon_irq_kms_pflip_irq_put(rdev, crtc); 88 } 89 90 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 91 { 92 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 93 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 94 int i; 95 96 /* Lock the graphics update lock */ 97 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 98 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 99 100 /* update the scanout addresses */ 101 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 102 (u32)crtc_base); 103 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 104 (u32)crtc_base); 105 106 /* Wait for update_pending to go high. */ 107 for (i = 0; i < rdev->usec_timeout; i++) { 108 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 109 break; 110 DRM_UDELAY(1); 111 } 112 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 113 114 /* Unlock the lock, so double-buffering can take place inside vblank */ 115 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 116 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 117 118 /* Return current update_pending status: */ 119 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 120 } 121 122 void rs600_pm_misc(struct radeon_device *rdev) 123 { 124 int requested_index = rdev->pm.requested_power_state_index; 125 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 126 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 127 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 128 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 129 130 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 131 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 132 tmp = RREG32(voltage->gpio.reg); 133 if (voltage->active_high) 134 tmp |= voltage->gpio.mask; 135 else 136 tmp &= ~(voltage->gpio.mask); 137 WREG32(voltage->gpio.reg, tmp); 138 if (voltage->delay) 139 DRM_UDELAY(voltage->delay); 140 } else { 141 tmp = RREG32(voltage->gpio.reg); 142 if (voltage->active_high) 143 tmp &= ~voltage->gpio.mask; 144 else 145 tmp |= voltage->gpio.mask; 146 WREG32(voltage->gpio.reg, tmp); 147 if (voltage->delay) 148 DRM_UDELAY(voltage->delay); 149 } 150 } else if (voltage->type == VOLTAGE_VDDC) 151 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 152 153 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 154 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 155 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 156 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 157 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 158 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 159 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 160 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 161 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 162 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 163 } 164 } else { 165 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 166 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 167 } 168 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 169 170 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 171 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 172 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 173 if (voltage->delay) { 174 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 175 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 176 } else 177 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 178 } else 179 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 180 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 181 182 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 183 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 184 hdp_dyn_cntl &= ~HDP_FORCEON; 185 else 186 hdp_dyn_cntl |= HDP_FORCEON; 187 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 188 #if 0 189 /* mc_host_dyn seems to cause hangs from time to time */ 190 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 191 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 192 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 193 else 194 mc_host_dyn_cntl |= MC_HOST_FORCEON; 195 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 196 #endif 197 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 198 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 199 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 200 else 201 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 202 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 203 204 /* set pcie lanes */ 205 if ((rdev->flags & RADEON_IS_PCIE) && 206 !(rdev->flags & RADEON_IS_IGP) && 207 rdev->asic->pm.set_pcie_lanes && 208 (ps->pcie_lanes != 209 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 210 radeon_set_pcie_lanes(rdev, 211 ps->pcie_lanes); 212 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 213 } 214 } 215 216 void rs600_pm_prepare(struct radeon_device *rdev) 217 { 218 struct drm_device *ddev = rdev->ddev; 219 struct drm_crtc *crtc; 220 struct radeon_crtc *radeon_crtc; 221 u32 tmp; 222 223 /* disable any active CRTCs */ 224 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 225 radeon_crtc = to_radeon_crtc(crtc); 226 if (radeon_crtc->enabled) { 227 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 228 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 229 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 230 } 231 } 232 } 233 234 void rs600_pm_finish(struct radeon_device *rdev) 235 { 236 struct drm_device *ddev = rdev->ddev; 237 struct drm_crtc *crtc; 238 struct radeon_crtc *radeon_crtc; 239 u32 tmp; 240 241 /* enable any active CRTCs */ 242 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 243 radeon_crtc = to_radeon_crtc(crtc); 244 if (radeon_crtc->enabled) { 245 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 246 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 247 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 248 } 249 } 250 } 251 252 /* hpd for digital panel detect/disconnect */ 253 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 254 { 255 u32 tmp; 256 bool connected = false; 257 258 switch (hpd) { 259 case RADEON_HPD_1: 260 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 261 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 262 connected = true; 263 break; 264 case RADEON_HPD_2: 265 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 266 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 267 connected = true; 268 break; 269 default: 270 break; 271 } 272 return connected; 273 } 274 275 void rs600_hpd_set_polarity(struct radeon_device *rdev, 276 enum radeon_hpd_id hpd) 277 { 278 u32 tmp; 279 bool connected = rs600_hpd_sense(rdev, hpd); 280 281 switch (hpd) { 282 case RADEON_HPD_1: 283 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 284 if (connected) 285 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 286 else 287 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 288 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 289 break; 290 case RADEON_HPD_2: 291 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 292 if (connected) 293 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 294 else 295 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 296 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 297 break; 298 default: 299 break; 300 } 301 } 302 303 void rs600_hpd_init(struct radeon_device *rdev) 304 { 305 struct drm_device *dev = rdev->ddev; 306 struct drm_connector *connector; 307 unsigned enable = 0; 308 309 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 310 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 311 switch (radeon_connector->hpd.hpd) { 312 case RADEON_HPD_1: 313 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 314 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 315 break; 316 case RADEON_HPD_2: 317 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 318 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 319 break; 320 default: 321 break; 322 } 323 enable |= 1 << radeon_connector->hpd.hpd; 324 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 325 } 326 radeon_irq_kms_enable_hpd(rdev, enable); 327 } 328 329 void rs600_hpd_fini(struct radeon_device *rdev) 330 { 331 struct drm_device *dev = rdev->ddev; 332 struct drm_connector *connector; 333 unsigned disable = 0; 334 335 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 336 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 337 switch (radeon_connector->hpd.hpd) { 338 case RADEON_HPD_1: 339 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 340 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 341 break; 342 case RADEON_HPD_2: 343 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 344 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 345 break; 346 default: 347 break; 348 } 349 disable |= 1 << radeon_connector->hpd.hpd; 350 } 351 radeon_irq_kms_disable_hpd(rdev, disable); 352 } 353 354 int rs600_asic_reset(struct radeon_device *rdev) 355 { 356 struct rv515_mc_save save; 357 u32 status, tmp; 358 int ret = 0; 359 360 status = RREG32(R_000E40_RBBM_STATUS); 361 if (!G_000E40_GUI_ACTIVE(status)) { 362 return 0; 363 } 364 /* Stops all mc clients */ 365 rv515_mc_stop(rdev, &save); 366 status = RREG32(R_000E40_RBBM_STATUS); 367 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 368 /* stop CP */ 369 WREG32(RADEON_CP_CSQ_CNTL, 0); 370 tmp = RREG32(RADEON_CP_RB_CNTL); 371 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 372 WREG32(RADEON_CP_RB_RPTR_WR, 0); 373 WREG32(RADEON_CP_RB_WPTR, 0); 374 WREG32(RADEON_CP_RB_CNTL, tmp); 375 pci_save_state(device_get_parent(rdev->dev)); 376 /* disable bus mastering */ 377 pci_disable_busmaster(rdev->dev); 378 DRM_MDELAY(1); 379 /* reset GA+VAP */ 380 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 381 S_0000F0_SOFT_RESET_GA(1)); 382 RREG32(R_0000F0_RBBM_SOFT_RESET); 383 DRM_MDELAY(500); 384 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 385 DRM_MDELAY(1); 386 status = RREG32(R_000E40_RBBM_STATUS); 387 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 388 /* reset CP */ 389 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 390 RREG32(R_0000F0_RBBM_SOFT_RESET); 391 DRM_MDELAY(500); 392 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 393 DRM_MDELAY(1); 394 status = RREG32(R_000E40_RBBM_STATUS); 395 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 396 /* reset MC */ 397 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 398 RREG32(R_0000F0_RBBM_SOFT_RESET); 399 DRM_MDELAY(500); 400 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 401 DRM_MDELAY(1); 402 status = RREG32(R_000E40_RBBM_STATUS); 403 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 404 /* restore PCI & busmastering */ 405 pci_restore_state(device_get_parent(rdev->dev)); 406 /* Check if GPU is idle */ 407 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 408 dev_err(rdev->dev, "failed to reset GPU\n"); 409 ret = -1; 410 } else 411 dev_info(rdev->dev, "GPU reset succeed\n"); 412 rv515_mc_resume(rdev, &save); 413 return ret; 414 } 415 416 /* 417 * GART. 418 */ 419 void rs600_gart_tlb_flush(struct radeon_device *rdev) 420 { 421 uint32_t tmp; 422 423 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 424 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 425 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 426 427 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 428 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 429 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 430 431 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 432 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 433 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 434 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 435 } 436 437 static int rs600_gart_init(struct radeon_device *rdev) 438 { 439 int r; 440 441 if (rdev->gart.robj) { 442 DRM_ERROR("RS600 GART already initialized\n"); 443 return 0; 444 } 445 /* Initialize common gart structure */ 446 r = radeon_gart_init(rdev); 447 if (r) { 448 return r; 449 } 450 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 451 return radeon_gart_table_vram_alloc(rdev); 452 } 453 454 static int rs600_gart_enable(struct radeon_device *rdev) 455 { 456 u32 tmp; 457 int r, i; 458 459 if (rdev->gart.robj == NULL) { 460 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 461 return -EINVAL; 462 } 463 r = radeon_gart_table_vram_pin(rdev); 464 if (r) 465 return r; 466 radeon_gart_restore(rdev); 467 /* Enable bus master */ 468 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 469 WREG32(RADEON_BUS_CNTL, tmp); 470 /* FIXME: setup default page */ 471 WREG32_MC(R_000100_MC_PT0_CNTL, 472 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 473 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 474 475 for (i = 0; i < 19; i++) { 476 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 477 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 478 S_00016C_SYSTEM_ACCESS_MODE_MASK( 479 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 480 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 481 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 482 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 483 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 484 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 485 } 486 /* enable first context */ 487 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 488 S_000102_ENABLE_PAGE_TABLE(1) | 489 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 490 491 /* disable all other contexts */ 492 for (i = 1; i < 8; i++) 493 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 494 495 /* setup the page table */ 496 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 497 rdev->gart.table_addr); 498 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 499 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 500 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 501 502 /* System context maps to VRAM space */ 503 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 504 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 505 506 /* enable page tables */ 507 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 508 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 509 tmp = RREG32_MC(R_000009_MC_CNTL1); 510 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 511 rs600_gart_tlb_flush(rdev); 512 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 513 (unsigned)(rdev->mc.gtt_size >> 20), 514 (unsigned long long)rdev->gart.table_addr); 515 rdev->gart.ready = true; 516 return 0; 517 } 518 519 static void rs600_gart_disable(struct radeon_device *rdev) 520 { 521 u32 tmp; 522 523 /* FIXME: disable out of gart access */ 524 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 525 tmp = RREG32_MC(R_000009_MC_CNTL1); 526 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 527 radeon_gart_table_vram_unpin(rdev); 528 } 529 530 static void rs600_gart_fini(struct radeon_device *rdev) 531 { 532 radeon_gart_fini(rdev); 533 rs600_gart_disable(rdev); 534 radeon_gart_table_vram_free(rdev); 535 } 536 537 #define R600_PTE_VALID (1 << 0) 538 #define R600_PTE_SYSTEM (1 << 1) 539 #define R600_PTE_SNOOPED (1 << 2) 540 #define R600_PTE_READABLE (1 << 5) 541 #define R600_PTE_WRITEABLE (1 << 6) 542 543 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 544 { 545 uint64_t *ptr = rdev->gart.ptr; 546 547 if (i < 0 || i > rdev->gart.num_gpu_pages) { 548 return -EINVAL; 549 } 550 addr = addr & 0xFFFFFFFFFFFFF000ULL; 551 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 552 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 553 ptr[i] = addr; 554 return 0; 555 } 556 557 int rs600_irq_set(struct radeon_device *rdev) 558 { 559 uint32_t tmp = 0; 560 uint32_t mode_int = 0; 561 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 562 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 563 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 564 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 565 u32 hdmi0; 566 if (ASIC_IS_DCE2(rdev)) 567 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 568 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 569 else 570 hdmi0 = 0; 571 572 if (!rdev->irq.installed) { 573 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 574 WREG32(R_000040_GEN_INT_CNTL, 0); 575 return -EINVAL; 576 } 577 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 578 tmp |= S_000040_SW_INT_EN(1); 579 } 580 if (rdev->irq.crtc_vblank_int[0] || 581 atomic_read(&rdev->irq.pflip[0])) { 582 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 583 } 584 if (rdev->irq.crtc_vblank_int[1] || 585 atomic_read(&rdev->irq.pflip[1])) { 586 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 587 } 588 if (rdev->irq.hpd[0]) { 589 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 590 } 591 if (rdev->irq.hpd[1]) { 592 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 593 } 594 if (rdev->irq.afmt[0]) { 595 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 596 } 597 WREG32(R_000040_GEN_INT_CNTL, tmp); 598 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 599 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 600 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 601 if (ASIC_IS_DCE2(rdev)) 602 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 603 return 0; 604 } 605 606 static inline u32 rs600_irq_ack(struct radeon_device *rdev) 607 { 608 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 609 uint32_t irq_mask = S_000044_SW_INT(1); 610 u32 tmp; 611 612 if (G_000044_DISPLAY_INT_STAT(irqs)) { 613 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 614 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 615 WREG32(R_006534_D1MODE_VBLANK_STATUS, 616 S_006534_D1MODE_VBLANK_ACK(1)); 617 } 618 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 619 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 620 S_006D34_D2MODE_VBLANK_ACK(1)); 621 } 622 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 623 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 624 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 625 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 626 } 627 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 628 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 629 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 630 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 631 } 632 } else { 633 rdev->irq.stat_regs.r500.disp_int = 0; 634 } 635 636 if (ASIC_IS_DCE2(rdev)) { 637 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 638 S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 639 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 640 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 641 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 642 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 643 } 644 } else 645 rdev->irq.stat_regs.r500.hdmi0_status = 0; 646 647 if (irqs) { 648 WREG32(R_000044_GEN_INT_STATUS, irqs); 649 } 650 return irqs & irq_mask; 651 } 652 653 void rs600_irq_disable(struct radeon_device *rdev) 654 { 655 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 656 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 657 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 658 WREG32(R_000040_GEN_INT_CNTL, 0); 659 WREG32(R_006540_DxMODE_INT_MASK, 0); 660 /* Wait and acknowledge irq */ 661 DRM_MDELAY(1); 662 rs600_irq_ack(rdev); 663 } 664 665 irqreturn_t rs600_irq_process(struct radeon_device *rdev) 666 { 667 u32 status, msi_rearm; 668 bool queue_hotplug = false; 669 bool queue_hdmi = false; 670 671 status = rs600_irq_ack(rdev); 672 if (!status && 673 !rdev->irq.stat_regs.r500.disp_int && 674 !rdev->irq.stat_regs.r500.hdmi0_status) { 675 return IRQ_NONE; 676 } 677 while (status || 678 rdev->irq.stat_regs.r500.disp_int || 679 rdev->irq.stat_regs.r500.hdmi0_status) { 680 /* SW interrupt */ 681 if (G_000044_SW_INT(status)) { 682 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 683 } 684 /* Vertical blank interrupts */ 685 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 686 if (rdev->irq.crtc_vblank_int[0]) { 687 drm_handle_vblank(rdev->ddev, 0); 688 rdev->pm.vblank_sync = true; 689 DRM_WAKEUP(&rdev->irq.vblank_queue); 690 } 691 if (atomic_read(&rdev->irq.pflip[0])) 692 radeon_crtc_handle_flip(rdev, 0); 693 } 694 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 695 if (rdev->irq.crtc_vblank_int[1]) { 696 drm_handle_vblank(rdev->ddev, 1); 697 rdev->pm.vblank_sync = true; 698 DRM_WAKEUP(&rdev->irq.vblank_queue); 699 } 700 if (atomic_read(&rdev->irq.pflip[1])) 701 radeon_crtc_handle_flip(rdev, 1); 702 } 703 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 704 queue_hotplug = true; 705 DRM_DEBUG("HPD1\n"); 706 } 707 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 708 queue_hotplug = true; 709 DRM_DEBUG("HPD2\n"); 710 } 711 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 712 queue_hdmi = true; 713 DRM_DEBUG("HDMI0\n"); 714 } 715 status = rs600_irq_ack(rdev); 716 } 717 if (queue_hotplug) 718 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 719 if (queue_hdmi) 720 taskqueue_enqueue(rdev->tq, &rdev->audio_work); 721 if (rdev->msi_enabled) { 722 switch (rdev->family) { 723 case CHIP_RS600: 724 case CHIP_RS690: 725 case CHIP_RS740: 726 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 727 WREG32(RADEON_BUS_CNTL, msi_rearm); 728 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 729 break; 730 default: 731 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 732 break; 733 } 734 } 735 return IRQ_HANDLED; 736 } 737 738 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 739 { 740 if (crtc == 0) 741 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 742 else 743 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 744 } 745 746 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 747 { 748 unsigned i; 749 750 for (i = 0; i < rdev->usec_timeout; i++) { 751 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 752 return 0; 753 DRM_UDELAY(1); 754 } 755 return -1; 756 } 757 758 static void rs600_gpu_init(struct radeon_device *rdev) 759 { 760 r420_pipes_init(rdev); 761 /* Wait for mc idle */ 762 if (rs600_mc_wait_for_idle(rdev)) 763 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 764 } 765 766 static void rs600_mc_init(struct radeon_device *rdev) 767 { 768 u64 base; 769 770 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 771 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 772 rdev->mc.vram_is_ddr = true; 773 rdev->mc.vram_width = 128; 774 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 775 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 776 rdev->mc.visible_vram_size = rdev->mc.aper_size; 777 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 778 base = RREG32_MC(R_000004_MC_FB_LOCATION); 779 base = G_000004_MC_FB_START(base) << 16; 780 radeon_vram_location(rdev, &rdev->mc, base); 781 rdev->mc.gtt_base_align = 0; 782 radeon_gtt_location(rdev, &rdev->mc); 783 radeon_update_bandwidth_info(rdev); 784 } 785 786 void rs600_bandwidth_update(struct radeon_device *rdev) 787 { 788 struct drm_display_mode *mode0 = NULL; 789 struct drm_display_mode *mode1 = NULL; 790 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 791 /* FIXME: implement full support */ 792 793 radeon_update_display_priority(rdev); 794 795 if (rdev->mode_info.crtcs[0]->base.enabled) 796 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 797 if (rdev->mode_info.crtcs[1]->base.enabled) 798 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 799 800 rs690_line_buffer_adjust(rdev, mode0, mode1); 801 802 if (rdev->disp_priority == 2) { 803 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 804 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 805 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 806 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 807 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 808 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 809 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 810 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 811 } 812 } 813 814 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 815 { 816 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 817 S_000070_MC_IND_CITF_ARB0(1)); 818 return RREG32(R_000074_MC_IND_DATA); 819 } 820 821 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 822 { 823 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 824 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 825 WREG32(R_000074_MC_IND_DATA, v); 826 } 827 828 static void rs600_debugfs(struct radeon_device *rdev) 829 { 830 if (r100_debugfs_rbbm_init(rdev)) 831 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 832 } 833 834 void rs600_set_safe_registers(struct radeon_device *rdev) 835 { 836 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 837 rdev->config.r300.reg_safe_bm_size = DRM_ARRAY_SIZE(rs600_reg_safe_bm); 838 } 839 840 static void rs600_mc_program(struct radeon_device *rdev) 841 { 842 struct rv515_mc_save save; 843 844 /* Stops all mc clients */ 845 rv515_mc_stop(rdev, &save); 846 847 /* Wait for mc idle */ 848 if (rs600_mc_wait_for_idle(rdev)) 849 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 850 851 /* FIXME: What does AGP means for such chipset ? */ 852 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 853 WREG32_MC(R_000006_AGP_BASE, 0); 854 WREG32_MC(R_000007_AGP_BASE_2, 0); 855 /* Program MC */ 856 WREG32_MC(R_000004_MC_FB_LOCATION, 857 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 858 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 859 WREG32(R_000134_HDP_FB_LOCATION, 860 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 861 862 rv515_mc_resume(rdev, &save); 863 } 864 865 static int rs600_startup(struct radeon_device *rdev) 866 { 867 int r; 868 869 rs600_mc_program(rdev); 870 /* Resume clock */ 871 rv515_clock_startup(rdev); 872 /* Initialize GPU configuration (# pipes, ...) */ 873 rs600_gpu_init(rdev); 874 /* Initialize GART (initialize after TTM so we can allocate 875 * memory through TTM but finalize after TTM) */ 876 r = rs600_gart_enable(rdev); 877 if (r) 878 return r; 879 880 /* allocate wb buffer */ 881 r = radeon_wb_init(rdev); 882 if (r) 883 return r; 884 885 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 886 if (r) { 887 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 888 return r; 889 } 890 891 /* Enable IRQ */ 892 rs600_irq_set(rdev); 893 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 894 /* 1M ring buffer */ 895 r = r100_cp_init(rdev, 1024 * 1024); 896 if (r) { 897 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 898 return r; 899 } 900 901 r = radeon_ib_pool_init(rdev); 902 if (r) { 903 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 904 return r; 905 } 906 907 r = r600_audio_init(rdev); 908 if (r) { 909 dev_err(rdev->dev, "failed initializing audio\n"); 910 return r; 911 } 912 913 return 0; 914 } 915 916 int rs600_resume(struct radeon_device *rdev) 917 { 918 int r; 919 920 /* Make sur GART are not working */ 921 rs600_gart_disable(rdev); 922 /* Resume clock before doing reset */ 923 rv515_clock_startup(rdev); 924 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 925 if (radeon_asic_reset(rdev)) { 926 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 927 RREG32(R_000E40_RBBM_STATUS), 928 RREG32(R_0007C0_CP_STAT)); 929 } 930 /* post */ 931 atom_asic_init(rdev->mode_info.atom_context); 932 /* Resume clock after posting */ 933 rv515_clock_startup(rdev); 934 /* Initialize surface registers */ 935 radeon_surface_init(rdev); 936 937 rdev->accel_working = true; 938 r = rs600_startup(rdev); 939 if (r) { 940 rdev->accel_working = false; 941 } 942 return r; 943 } 944 945 int rs600_suspend(struct radeon_device *rdev) 946 { 947 r600_audio_fini(rdev); 948 r100_cp_disable(rdev); 949 radeon_wb_disable(rdev); 950 rs600_irq_disable(rdev); 951 rs600_gart_disable(rdev); 952 return 0; 953 } 954 955 void rs600_fini(struct radeon_device *rdev) 956 { 957 r600_audio_fini(rdev); 958 r100_cp_fini(rdev); 959 radeon_wb_fini(rdev); 960 radeon_ib_pool_fini(rdev); 961 radeon_gem_fini(rdev); 962 rs600_gart_fini(rdev); 963 radeon_irq_kms_fini(rdev); 964 radeon_fence_driver_fini(rdev); 965 radeon_bo_fini(rdev); 966 radeon_atombios_fini(rdev); 967 drm_free(rdev->bios, M_DRM); 968 rdev->bios = NULL; 969 } 970 971 int rs600_init(struct radeon_device *rdev) 972 { 973 int r; 974 975 /* Disable VGA */ 976 rv515_vga_render_disable(rdev); 977 /* Initialize scratch registers */ 978 radeon_scratch_init(rdev); 979 /* Initialize surface registers */ 980 radeon_surface_init(rdev); 981 /* restore some register to sane defaults */ 982 r100_restore_sanity(rdev); 983 /* BIOS */ 984 if (!radeon_get_bios(rdev)) { 985 if (ASIC_IS_AVIVO(rdev)) 986 return -EINVAL; 987 } 988 if (rdev->is_atom_bios) { 989 r = radeon_atombios_init(rdev); 990 if (r) 991 return r; 992 } else { 993 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 994 return -EINVAL; 995 } 996 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 997 if (radeon_asic_reset(rdev)) { 998 dev_warn(rdev->dev, 999 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1000 RREG32(R_000E40_RBBM_STATUS), 1001 RREG32(R_0007C0_CP_STAT)); 1002 } 1003 /* check if cards are posted or not */ 1004 if (radeon_boot_test_post_card(rdev) == false) 1005 return -EINVAL; 1006 1007 /* Initialize clocks */ 1008 radeon_get_clock_info(rdev->ddev); 1009 /* initialize memory controller */ 1010 rs600_mc_init(rdev); 1011 rs600_debugfs(rdev); 1012 /* Fence driver */ 1013 r = radeon_fence_driver_init(rdev); 1014 if (r) 1015 return r; 1016 r = radeon_irq_kms_init(rdev); 1017 if (r) 1018 return r; 1019 /* Memory manager */ 1020 r = radeon_bo_init(rdev); 1021 if (r) 1022 return r; 1023 r = rs600_gart_init(rdev); 1024 if (r) 1025 return r; 1026 rs600_set_safe_registers(rdev); 1027 1028 rdev->accel_working = true; 1029 r = rs600_startup(rdev); 1030 if (r) { 1031 /* Somethings want wront with the accel init stop accel */ 1032 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1033 r100_cp_fini(rdev); 1034 radeon_wb_fini(rdev); 1035 radeon_ib_pool_fini(rdev); 1036 rs600_gart_fini(rdev); 1037 radeon_irq_kms_fini(rdev); 1038 rdev->accel_working = false; 1039 } 1040 return 0; 1041 } 1042