1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/rs690.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 #include "rs690d.h" 36 37 int rs690_mc_wait_for_idle(struct radeon_device *rdev) 38 { 39 unsigned i; 40 uint32_t tmp; 41 42 for (i = 0; i < rdev->usec_timeout; i++) { 43 /* read MC_STATUS */ 44 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 45 if (G_000090_MC_SYSTEM_IDLE(tmp)) 46 return 0; 47 udelay(1); 48 } 49 return -1; 50 } 51 52 static void rs690_gpu_init(struct radeon_device *rdev) 53 { 54 /* FIXME: is this correct ? */ 55 r420_pipes_init(rdev); 56 if (rs690_mc_wait_for_idle(rdev)) { 57 printk(KERN_WARNING "Failed to wait MC idle while " 58 "programming pipes. Bad things might happen.\n"); 59 } 60 } 61 62 union igp_info { 63 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 64 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 65 }; 66 67 void rs690_pm_info(struct radeon_device *rdev) 68 { 69 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 70 union igp_info *info; 71 uint16_t data_offset; 72 uint8_t frev, crev; 73 fixed20_12 tmp; 74 75 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 76 &frev, &crev, &data_offset)) { 77 info = (union igp_info *)((uintptr_t)rdev->mode_info.atom_context->bios + data_offset); 78 79 /* Get various system informations from bios */ 80 switch (crev) { 81 case 1: 82 tmp.full = dfixed_const(100); 83 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 84 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 85 if (le16_to_cpu(info->info.usK8MemoryClock)) 86 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 87 else if (rdev->clock.default_mclk) { 88 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 89 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 90 } else 91 rdev->pm.igp_system_mclk.full = dfixed_const(400); 92 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 93 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 94 break; 95 case 2: 96 tmp.full = dfixed_const(100); 97 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 98 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 99 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 100 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 101 else if (rdev->clock.default_mclk) 102 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 103 else 104 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 105 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 106 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 107 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 108 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 109 break; 110 default: 111 /* We assume the slower possible clock ie worst case */ 112 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 113 rdev->pm.igp_system_mclk.full = dfixed_const(200); 114 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 115 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 116 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 117 break; 118 } 119 } else { 120 /* We assume the slower possible clock ie worst case */ 121 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 122 rdev->pm.igp_system_mclk.full = dfixed_const(200); 123 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 124 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 125 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 126 } 127 /* Compute various bandwidth */ 128 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 129 tmp.full = dfixed_const(4); 130 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 131 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 132 * = ht_clk * ht_width / 5 133 */ 134 tmp.full = dfixed_const(5); 135 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 136 rdev->pm.igp_ht_link_width); 137 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 138 if (tmp.full < rdev->pm.max_bandwidth.full) { 139 /* HT link is a limiting factor */ 140 rdev->pm.max_bandwidth.full = tmp.full; 141 } 142 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 143 * = (sideport_clk * 14) / 10 144 */ 145 tmp.full = dfixed_const(14); 146 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 147 tmp.full = dfixed_const(10); 148 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 149 } 150 151 static void rs690_mc_init(struct radeon_device *rdev) 152 { 153 u64 base; 154 uint32_t h_addr, l_addr; 155 unsigned long long k8_addr; 156 157 rs400_gart_adjust_size(rdev); 158 rdev->mc.vram_is_ddr = true; 159 rdev->mc.vram_width = 128; 160 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 161 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 162 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 163 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 164 rdev->mc.visible_vram_size = rdev->mc.aper_size; 165 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 166 base = G_000100_MC_FB_START(base) << 16; 167 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 168 169 /* Use K8 direct mapping for fast fb access. */ 170 rdev->fastfb_working = false; 171 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL)); 172 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION); 173 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 174 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 175 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 176 #endif 177 { 178 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 179 * memory is present. 180 */ 181 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 182 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 183 (unsigned long long)rdev->mc.aper_base, k8_addr); 184 rdev->mc.aper_base = (resource_size_t)k8_addr; 185 rdev->fastfb_working = true; 186 } 187 } 188 189 rs690_pm_info(rdev); 190 radeon_vram_location(rdev, &rdev->mc, base); 191 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 192 radeon_gtt_location(rdev, &rdev->mc); 193 radeon_update_bandwidth_info(rdev); 194 } 195 196 void rs690_line_buffer_adjust(struct radeon_device *rdev, 197 struct drm_display_mode *mode1, 198 struct drm_display_mode *mode2) 199 { 200 u32 tmp; 201 202 /* 203 * Line Buffer Setup 204 * There is a single line buffer shared by both display controllers. 205 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 206 * the display controllers. The paritioning can either be done 207 * manually or via one of four preset allocations specified in bits 1:0: 208 * 0 - line buffer is divided in half and shared between crtc 209 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 210 * 2 - D1 gets the whole buffer 211 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 212 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 213 * allocation mode. In manual allocation mode, D1 always starts at 0, 214 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 215 */ 216 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 217 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 218 /* auto */ 219 if (mode1 && mode2) { 220 if (mode1->hdisplay > mode2->hdisplay) { 221 if (mode1->hdisplay > 2560) 222 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 223 else 224 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 225 } else if (mode2->hdisplay > mode1->hdisplay) { 226 if (mode2->hdisplay > 2560) 227 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 228 else 229 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 230 } else 231 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 232 } else if (mode1) { 233 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 234 } else if (mode2) { 235 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 236 } 237 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 238 } 239 240 struct rs690_watermark { 241 u32 lb_request_fifo_depth; 242 fixed20_12 num_line_pair; 243 fixed20_12 estimated_width; 244 fixed20_12 worst_case_latency; 245 fixed20_12 consumption_rate; 246 fixed20_12 active_time; 247 fixed20_12 dbpp; 248 fixed20_12 priority_mark_max; 249 fixed20_12 priority_mark; 250 fixed20_12 sclk; 251 }; 252 253 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 254 struct radeon_crtc *crtc, 255 struct rs690_watermark *wm, 256 bool low) 257 { 258 struct drm_display_mode *mode = &crtc->base.mode; 259 fixed20_12 a, b, c; 260 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 261 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 262 fixed20_12 sclk, core_bandwidth, max_bandwidth; 263 u32 selected_sclk; 264 265 if (!crtc->base.enabled) { 266 /* FIXME: wouldn't it better to set priority mark to maximum */ 267 wm->lb_request_fifo_depth = 4; 268 return; 269 } 270 271 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) && 272 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 273 selected_sclk = radeon_dpm_get_sclk(rdev, low); 274 else 275 selected_sclk = rdev->pm.current_sclk; 276 277 /* sclk in Mhz */ 278 a.full = dfixed_const(100); 279 sclk.full = dfixed_const(selected_sclk); 280 sclk.full = dfixed_div(sclk, a); 281 282 /* core_bandwidth = sclk(Mhz) * 16 */ 283 a.full = dfixed_const(16); 284 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 285 286 if (crtc->vsc.full > dfixed_const(2)) 287 wm->num_line_pair.full = dfixed_const(2); 288 else 289 wm->num_line_pair.full = dfixed_const(1); 290 291 b.full = dfixed_const(mode->crtc_hdisplay); 292 c.full = dfixed_const(256); 293 a.full = dfixed_div(b, c); 294 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 295 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 296 if (a.full < dfixed_const(4)) { 297 wm->lb_request_fifo_depth = 4; 298 } else { 299 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 300 } 301 302 /* Determine consumption rate 303 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 304 * vtaps = number of vertical taps, 305 * vsc = vertical scaling ratio, defined as source/destination 306 * hsc = horizontal scaling ration, defined as source/destination 307 */ 308 a.full = dfixed_const(mode->clock); 309 b.full = dfixed_const(1000); 310 a.full = dfixed_div(a, b); 311 pclk.full = dfixed_div(b, a); 312 if (crtc->rmx_type != RMX_OFF) { 313 b.full = dfixed_const(2); 314 if (crtc->vsc.full > b.full) 315 b.full = crtc->vsc.full; 316 b.full = dfixed_mul(b, crtc->hsc); 317 c.full = dfixed_const(2); 318 b.full = dfixed_div(b, c); 319 consumption_time.full = dfixed_div(pclk, b); 320 } else { 321 consumption_time.full = pclk.full; 322 } 323 a.full = dfixed_const(1); 324 wm->consumption_rate.full = dfixed_div(a, consumption_time); 325 326 327 /* Determine line time 328 * LineTime = total time for one line of displayhtotal 329 * LineTime = total number of horizontal pixels 330 * pclk = pixel clock period(ns) 331 */ 332 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 333 line_time.full = dfixed_mul(a, pclk); 334 335 /* Determine active time 336 * ActiveTime = time of active region of display within one line, 337 * hactive = total number of horizontal active pixels 338 * htotal = total number of horizontal pixels 339 */ 340 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 341 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 342 wm->active_time.full = dfixed_mul(line_time, b); 343 wm->active_time.full = dfixed_div(wm->active_time, a); 344 345 /* Maximun bandwidth is the minimun bandwidth of all component */ 346 max_bandwidth = core_bandwidth; 347 if (rdev->mc.igp_sideport_enabled) { 348 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 349 rdev->pm.sideport_bandwidth.full) 350 max_bandwidth = rdev->pm.sideport_bandwidth; 351 #ifdef DUMBBELL_WIP 352 read_delay_latency.full = dfixed_const(370 * 800 * 1000); 353 #endif /* DUMBBELL_WIP */ 354 read_delay_latency.full = UINT_MAX; 355 read_delay_latency.full = dfixed_div(read_delay_latency, 356 rdev->pm.igp_sideport_mclk); 357 } else { 358 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && 359 rdev->pm.k8_bandwidth.full) 360 max_bandwidth = rdev->pm.k8_bandwidth; 361 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full && 362 rdev->pm.ht_bandwidth.full) 363 max_bandwidth = rdev->pm.ht_bandwidth; 364 read_delay_latency.full = dfixed_const(5000); 365 } 366 367 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 368 a.full = dfixed_const(16); 369 sclk.full = dfixed_mul(max_bandwidth, a); 370 a.full = dfixed_const(1000); 371 sclk.full = dfixed_div(a, sclk); 372 /* Determine chunk time 373 * ChunkTime = the time it takes the DCP to send one chunk of data 374 * to the LB which consists of pipeline delay and inter chunk gap 375 * sclk = system clock(ns) 376 */ 377 a.full = dfixed_const(256 * 13); 378 chunk_time.full = dfixed_mul(sclk, a); 379 a.full = dfixed_const(10); 380 chunk_time.full = dfixed_div(chunk_time, a); 381 382 /* Determine the worst case latency 383 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 384 * WorstCaseLatency = worst case time from urgent to when the MC starts 385 * to return data 386 * READ_DELAY_IDLE_MAX = constant of 1us 387 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 388 * which consists of pipeline delay and inter chunk gap 389 */ 390 if (dfixed_trunc(wm->num_line_pair) > 1) { 391 a.full = dfixed_const(3); 392 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 393 wm->worst_case_latency.full += read_delay_latency.full; 394 } else { 395 a.full = dfixed_const(2); 396 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 397 wm->worst_case_latency.full += read_delay_latency.full; 398 } 399 400 /* Determine the tolerable latency 401 * TolerableLatency = Any given request has only 1 line time 402 * for the data to be returned 403 * LBRequestFifoDepth = Number of chunk requests the LB can 404 * put into the request FIFO for a display 405 * LineTime = total time for one line of display 406 * ChunkTime = the time it takes the DCP to send one chunk 407 * of data to the LB which consists of 408 * pipeline delay and inter chunk gap 409 */ 410 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 411 tolerable_latency.full = line_time.full; 412 } else { 413 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 414 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 415 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 416 tolerable_latency.full = line_time.full - tolerable_latency.full; 417 } 418 /* We assume worst case 32bits (4 bytes) */ 419 wm->dbpp.full = dfixed_const(4 * 8); 420 421 /* Determine the maximum priority mark 422 * width = viewport width in pixels 423 */ 424 a.full = dfixed_const(16); 425 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 426 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 427 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 428 429 /* Determine estimated width */ 430 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 431 estimated_width.full = dfixed_div(estimated_width, consumption_time); 432 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 433 wm->priority_mark.full = dfixed_const(10); 434 } else { 435 a.full = dfixed_const(16); 436 wm->priority_mark.full = dfixed_div(estimated_width, a); 437 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 438 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 439 } 440 } 441 442 static void rs690_compute_mode_priority(struct radeon_device *rdev, 443 struct rs690_watermark *wm0, 444 struct rs690_watermark *wm1, 445 struct drm_display_mode *mode0, 446 struct drm_display_mode *mode1, 447 u32 *d1mode_priority_a_cnt, 448 u32 *d2mode_priority_a_cnt) 449 { 450 fixed20_12 priority_mark02, priority_mark12, fill_rate; 451 fixed20_12 a, b; 452 453 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 454 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 455 456 if (mode0 && mode1) { 457 if (dfixed_trunc(wm0->dbpp) > 64) 458 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 459 else 460 a.full = wm0->num_line_pair.full; 461 if (dfixed_trunc(wm1->dbpp) > 64) 462 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 463 else 464 b.full = wm1->num_line_pair.full; 465 a.full += b.full; 466 fill_rate.full = dfixed_div(wm0->sclk, a); 467 if (wm0->consumption_rate.full > fill_rate.full) { 468 b.full = wm0->consumption_rate.full - fill_rate.full; 469 b.full = dfixed_mul(b, wm0->active_time); 470 a.full = dfixed_mul(wm0->worst_case_latency, 471 wm0->consumption_rate); 472 a.full = a.full + b.full; 473 b.full = dfixed_const(16 * 1000); 474 priority_mark02.full = dfixed_div(a, b); 475 } else { 476 a.full = dfixed_mul(wm0->worst_case_latency, 477 wm0->consumption_rate); 478 b.full = dfixed_const(16 * 1000); 479 priority_mark02.full = dfixed_div(a, b); 480 } 481 if (wm1->consumption_rate.full > fill_rate.full) { 482 b.full = wm1->consumption_rate.full - fill_rate.full; 483 b.full = dfixed_mul(b, wm1->active_time); 484 a.full = dfixed_mul(wm1->worst_case_latency, 485 wm1->consumption_rate); 486 a.full = a.full + b.full; 487 b.full = dfixed_const(16 * 1000); 488 priority_mark12.full = dfixed_div(a, b); 489 } else { 490 a.full = dfixed_mul(wm1->worst_case_latency, 491 wm1->consumption_rate); 492 b.full = dfixed_const(16 * 1000); 493 priority_mark12.full = dfixed_div(a, b); 494 } 495 if (wm0->priority_mark.full > priority_mark02.full) 496 priority_mark02.full = wm0->priority_mark.full; 497 if (dfixed_trunc(priority_mark02) < 0) 498 priority_mark02.full = 0; 499 if (wm0->priority_mark_max.full > priority_mark02.full) 500 priority_mark02.full = wm0->priority_mark_max.full; 501 if (wm1->priority_mark.full > priority_mark12.full) 502 priority_mark12.full = wm1->priority_mark.full; 503 if (dfixed_trunc(priority_mark12) < 0) 504 priority_mark12.full = 0; 505 if (wm1->priority_mark_max.full > priority_mark12.full) 506 priority_mark12.full = wm1->priority_mark_max.full; 507 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 508 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 509 if (rdev->disp_priority == 2) { 510 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 511 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 512 } 513 } else if (mode0) { 514 if (dfixed_trunc(wm0->dbpp) > 64) 515 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 516 else 517 a.full = wm0->num_line_pair.full; 518 fill_rate.full = dfixed_div(wm0->sclk, a); 519 if (wm0->consumption_rate.full > fill_rate.full) { 520 b.full = wm0->consumption_rate.full - fill_rate.full; 521 b.full = dfixed_mul(b, wm0->active_time); 522 a.full = dfixed_mul(wm0->worst_case_latency, 523 wm0->consumption_rate); 524 a.full = a.full + b.full; 525 b.full = dfixed_const(16 * 1000); 526 priority_mark02.full = dfixed_div(a, b); 527 } else { 528 a.full = dfixed_mul(wm0->worst_case_latency, 529 wm0->consumption_rate); 530 b.full = dfixed_const(16 * 1000); 531 priority_mark02.full = dfixed_div(a, b); 532 } 533 if (wm0->priority_mark.full > priority_mark02.full) 534 priority_mark02.full = wm0->priority_mark.full; 535 if (dfixed_trunc(priority_mark02) < 0) 536 priority_mark02.full = 0; 537 if (wm0->priority_mark_max.full > priority_mark02.full) 538 priority_mark02.full = wm0->priority_mark_max.full; 539 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 540 if (rdev->disp_priority == 2) 541 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 542 } else if (mode1) { 543 if (dfixed_trunc(wm1->dbpp) > 64) 544 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 545 else 546 a.full = wm1->num_line_pair.full; 547 fill_rate.full = dfixed_div(wm1->sclk, a); 548 if (wm1->consumption_rate.full > fill_rate.full) { 549 b.full = wm1->consumption_rate.full - fill_rate.full; 550 b.full = dfixed_mul(b, wm1->active_time); 551 a.full = dfixed_mul(wm1->worst_case_latency, 552 wm1->consumption_rate); 553 a.full = a.full + b.full; 554 b.full = dfixed_const(16 * 1000); 555 priority_mark12.full = dfixed_div(a, b); 556 } else { 557 a.full = dfixed_mul(wm1->worst_case_latency, 558 wm1->consumption_rate); 559 b.full = dfixed_const(16 * 1000); 560 priority_mark12.full = dfixed_div(a, b); 561 } 562 if (wm1->priority_mark.full > priority_mark12.full) 563 priority_mark12.full = wm1->priority_mark.full; 564 if (dfixed_trunc(priority_mark12) < 0) 565 priority_mark12.full = 0; 566 if (wm1->priority_mark_max.full > priority_mark12.full) 567 priority_mark12.full = wm1->priority_mark_max.full; 568 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 569 if (rdev->disp_priority == 2) 570 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 571 } 572 } 573 574 void rs690_bandwidth_update(struct radeon_device *rdev) 575 { 576 struct drm_display_mode *mode0 = NULL; 577 struct drm_display_mode *mode1 = NULL; 578 struct rs690_watermark wm0_high, wm0_low; 579 struct rs690_watermark wm1_high, wm1_low; 580 u32 tmp; 581 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 582 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 583 584 radeon_update_display_priority(rdev); 585 586 if (rdev->mode_info.crtcs[0]->base.enabled) 587 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 588 if (rdev->mode_info.crtcs[1]->base.enabled) 589 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 590 /* 591 * Set display0/1 priority up in the memory controller for 592 * modes if the user specifies HIGH for displaypriority 593 * option. 594 */ 595 if ((rdev->disp_priority == 2) && 596 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 597 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 598 tmp &= C_000104_MC_DISP0R_INIT_LAT; 599 tmp &= C_000104_MC_DISP1R_INIT_LAT; 600 if (mode0) 601 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 602 if (mode1) 603 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 604 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 605 } 606 rs690_line_buffer_adjust(rdev, mode0, mode1); 607 608 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 609 WREG32(R_006C9C_DCP_CONTROL, 0); 610 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 611 WREG32(R_006C9C_DCP_CONTROL, 2); 612 613 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 614 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 615 616 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); 617 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); 618 619 tmp = (wm0_high.lb_request_fifo_depth - 1); 620 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16; 621 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 622 623 rs690_compute_mode_priority(rdev, 624 &wm0_high, &wm1_high, 625 mode0, mode1, 626 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 627 rs690_compute_mode_priority(rdev, 628 &wm0_low, &wm1_low, 629 mode0, mode1, 630 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 631 632 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 633 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 634 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 635 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 636 } 637 638 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 639 { 640 uint32_t r; 641 642 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 643 r = RREG32(R_00007C_MC_DATA); 644 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 645 return r; 646 } 647 648 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 649 { 650 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 651 S_000078_MC_IND_WR_EN(1)); 652 WREG32(R_00007C_MC_DATA, v); 653 WREG32(R_000078_MC_INDEX, 0x7F); 654 } 655 656 static void rs690_mc_program(struct radeon_device *rdev) 657 { 658 struct rv515_mc_save save; 659 660 /* Stops all mc clients */ 661 rv515_mc_stop(rdev, &save); 662 663 /* Wait for mc idle */ 664 if (rs690_mc_wait_for_idle(rdev)) 665 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 666 /* Program MC, should be a 32bits limited address space */ 667 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 668 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 669 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 670 WREG32(R_000134_HDP_FB_LOCATION, 671 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 672 673 rv515_mc_resume(rdev, &save); 674 } 675 676 static int rs690_startup(struct radeon_device *rdev) 677 { 678 int r; 679 680 rs690_mc_program(rdev); 681 /* Resume clock */ 682 rv515_clock_startup(rdev); 683 /* Initialize GPU configuration (# pipes, ...) */ 684 rs690_gpu_init(rdev); 685 /* Initialize GART (initialize after TTM so we can allocate 686 * memory through TTM but finalize after TTM) */ 687 r = rs400_gart_enable(rdev); 688 if (r) 689 return r; 690 691 /* allocate wb buffer */ 692 r = radeon_wb_init(rdev); 693 if (r) 694 return r; 695 696 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 697 if (r) { 698 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 699 return r; 700 } 701 702 /* Enable IRQ */ 703 if (!rdev->irq.installed) { 704 r = radeon_irq_kms_init(rdev); 705 if (r) 706 return r; 707 } 708 709 rs600_irq_set(rdev); 710 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 711 /* 1M ring buffer */ 712 r = r100_cp_init(rdev, 1024 * 1024); 713 if (r) { 714 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 715 return r; 716 } 717 718 r = radeon_ib_pool_init(rdev); 719 if (r) { 720 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 721 return r; 722 } 723 724 r = r600_audio_init(rdev); 725 if (r) { 726 dev_err(rdev->dev, "failed initializing audio\n"); 727 return r; 728 } 729 730 return 0; 731 } 732 733 int rs690_resume(struct radeon_device *rdev) 734 { 735 int r; 736 737 /* Make sur GART are not working */ 738 rs400_gart_disable(rdev); 739 /* Resume clock before doing reset */ 740 rv515_clock_startup(rdev); 741 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 742 if (radeon_asic_reset(rdev)) { 743 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 744 RREG32(R_000E40_RBBM_STATUS), 745 RREG32(R_0007C0_CP_STAT)); 746 } 747 /* post */ 748 atom_asic_init(rdev->mode_info.atom_context); 749 /* Resume clock after posting */ 750 rv515_clock_startup(rdev); 751 /* Initialize surface registers */ 752 radeon_surface_init(rdev); 753 754 rdev->accel_working = true; 755 r = rs690_startup(rdev); 756 if (r) { 757 rdev->accel_working = false; 758 } 759 return r; 760 } 761 762 int rs690_suspend(struct radeon_device *rdev) 763 { 764 r600_audio_fini(rdev); 765 r100_cp_disable(rdev); 766 radeon_wb_disable(rdev); 767 rs600_irq_disable(rdev); 768 rs400_gart_disable(rdev); 769 return 0; 770 } 771 772 void rs690_fini(struct radeon_device *rdev) 773 { 774 r600_audio_fini(rdev); 775 r100_cp_fini(rdev); 776 radeon_wb_fini(rdev); 777 radeon_ib_pool_fini(rdev); 778 radeon_gem_fini(rdev); 779 rs400_gart_fini(rdev); 780 radeon_irq_kms_fini(rdev); 781 radeon_fence_driver_fini(rdev); 782 radeon_bo_fini(rdev); 783 radeon_atombios_fini(rdev); 784 kfree(rdev->bios); 785 rdev->bios = NULL; 786 } 787 788 int rs690_init(struct radeon_device *rdev) 789 { 790 int r; 791 792 /* Disable VGA */ 793 rv515_vga_render_disable(rdev); 794 /* Initialize scratch registers */ 795 radeon_scratch_init(rdev); 796 /* Initialize surface registers */ 797 radeon_surface_init(rdev); 798 /* restore some register to sane defaults */ 799 r100_restore_sanity(rdev); 800 /* TODO: disable VGA need to use VGA request */ 801 /* BIOS*/ 802 if (!radeon_get_bios(rdev)) { 803 if (ASIC_IS_AVIVO(rdev)) 804 return -EINVAL; 805 } 806 if (rdev->is_atom_bios) { 807 r = radeon_atombios_init(rdev); 808 if (r) 809 return r; 810 } else { 811 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 812 return -EINVAL; 813 } 814 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 815 if (radeon_asic_reset(rdev)) { 816 dev_warn(rdev->dev, 817 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 818 RREG32(R_000E40_RBBM_STATUS), 819 RREG32(R_0007C0_CP_STAT)); 820 } 821 /* check if cards are posted or not */ 822 if (radeon_boot_test_post_card(rdev) == false) 823 return -EINVAL; 824 825 /* Initialize clocks */ 826 radeon_get_clock_info(rdev->ddev); 827 /* initialize memory controller */ 828 rs690_mc_init(rdev); 829 rv515_debugfs(rdev); 830 /* Fence driver */ 831 r = radeon_fence_driver_init(rdev); 832 if (r) 833 return r; 834 /* Memory manager */ 835 r = radeon_bo_init(rdev); 836 if (r) 837 return r; 838 r = rs400_gart_init(rdev); 839 if (r) 840 return r; 841 rs600_set_safe_registers(rdev); 842 843 rdev->accel_working = true; 844 r = rs690_startup(rdev); 845 if (r) { 846 /* Somethings want wront with the accel init stop accel */ 847 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 848 r100_cp_fini(rdev); 849 radeon_wb_fini(rdev); 850 radeon_ib_pool_fini(rdev); 851 rs400_gart_fini(rdev); 852 radeon_irq_kms_fini(rdev); 853 rdev->accel_working = false; 854 } 855 return 0; 856 } 857