1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include "rs780d.h" 29 #include "r600_dpm.h" 30 #include "rs780_dpm.h" 31 #include "atom.h" 32 #include <linux/seq_file.h> 33 34 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps) 35 { 36 struct igp_ps *ps = rps->ps_priv; 37 38 return ps; 39 } 40 41 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev) 42 { 43 struct igp_power_info *pi = rdev->pm.dpm.priv; 44 45 return pi; 46 } 47 48 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev) 49 { 50 struct igp_power_info *pi = rs780_get_pi(rdev); 51 struct radeon_mode_info *minfo = &rdev->mode_info; 52 struct drm_crtc *crtc; 53 struct radeon_crtc *radeon_crtc; 54 int i; 55 56 /* defaults */ 57 pi->crtc_id = 0; 58 pi->refresh_rate = 60; 59 60 for (i = 0; i < rdev->num_crtc; i++) { 61 crtc = (struct drm_crtc *)minfo->crtcs[i]; 62 if (crtc && crtc->enabled) { 63 radeon_crtc = to_radeon_crtc(crtc); 64 pi->crtc_id = radeon_crtc->crtc_id; 65 if (crtc->mode.htotal && crtc->mode.vtotal) 66 pi->refresh_rate = 67 (crtc->mode.clock * 1000) / 68 (crtc->mode.htotal * crtc->mode.vtotal); 69 break; 70 } 71 } 72 } 73 74 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable); 75 76 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev, 77 struct radeon_ps *boot_ps) 78 { 79 struct atom_clock_dividers dividers; 80 struct igp_ps *default_state = rs780_get_ps(boot_ps); 81 int i, ret; 82 83 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 84 default_state->sclk_low, false, ÷rs); 85 if (ret) 86 return ret; 87 88 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); 89 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); 90 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); 91 92 if (dividers.enable_post_div) 93 r600_engine_clock_entry_enable_post_divider(rdev, 0, true); 94 else 95 r600_engine_clock_entry_enable_post_divider(rdev, 0, false); 96 97 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT); 98 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false); 99 100 r600_engine_clock_entry_enable(rdev, 0, true); 101 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++) 102 r600_engine_clock_entry_enable(rdev, i, false); 103 104 r600_enable_mclk_control(rdev, false); 105 r600_voltage_control_enable_pins(rdev, 0); 106 107 return 0; 108 } 109 110 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev, 111 struct radeon_ps *boot_ps) 112 { 113 int ret = 0; 114 int i; 115 116 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT); 117 118 r600_set_at(rdev, 0, 0, 0, 0); 119 120 r600_set_git(rdev, R600_GICST_DFLT); 121 122 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 123 r600_set_tc(rdev, i, 0, 0); 124 125 r600_select_td(rdev, R600_TD_DFLT); 126 r600_set_vrc(rdev, 0); 127 128 r600_set_tpu(rdev, R600_TPU_DFLT); 129 r600_set_tpc(rdev, R600_TPC_DFLT); 130 131 r600_set_sstu(rdev, R600_SSTU_DFLT); 132 r600_set_sst(rdev, R600_SST_DFLT); 133 134 r600_set_fctu(rdev, R600_FCTU_DFLT); 135 r600_set_fct(rdev, R600_FCT_DFLT); 136 137 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT); 138 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT); 139 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT); 140 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT); 141 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT); 142 143 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT); 144 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT); 145 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT); 146 147 ret = rs780_initialize_dpm_power_state(rdev, boot_ps); 148 149 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0); 150 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 151 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0); 152 153 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); 154 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 155 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0); 156 157 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); 158 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 159 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0); 160 161 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH); 162 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH); 163 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH); 164 165 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false); 166 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); 167 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); 168 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); 169 170 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW); 171 172 r600_set_vrc(rdev, RS780_CGFTV_DFLT); 173 174 return ret; 175 } 176 177 static void rs780_start_dpm(struct radeon_device *rdev) 178 { 179 r600_enable_sclk_control(rdev, false); 180 r600_enable_mclk_control(rdev, false); 181 182 r600_dynamicpm_enable(rdev, true); 183 184 radeon_wait_for_vblank(rdev, 0); 185 radeon_wait_for_vblank(rdev, 1); 186 187 r600_enable_spll_bypass(rdev, true); 188 r600_wait_for_spll_change(rdev); 189 r600_enable_spll_bypass(rdev, false); 190 r600_wait_for_spll_change(rdev); 191 192 r600_enable_spll_bypass(rdev, true); 193 r600_wait_for_spll_change(rdev); 194 r600_enable_spll_bypass(rdev, false); 195 r600_wait_for_spll_change(rdev); 196 197 r600_enable_sclk_control(rdev, true); 198 } 199 200 201 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev) 202 { 203 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, 204 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN); 205 206 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, 207 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT), 208 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK); 209 } 210 211 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev) 212 { 213 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 214 215 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), 216 ~STARTING_FEEDBACK_DIV_MASK); 217 218 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), 219 ~FORCED_FEEDBACK_DIV_MASK); 220 221 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); 222 } 223 224 static void rs780_voltage_scaling_init(struct radeon_device *rdev) 225 { 226 struct igp_power_info *pi = rs780_get_pi(rdev); 227 struct drm_device *dev = rdev->ddev; 228 u32 fv_throt_pwm_fb_div_range[3]; 229 u32 fv_throt_pwm_range[4]; 230 231 if (dev->pci_device == 0x9614) { 232 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT; 233 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT; 234 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT; 235 } else if ((dev->pci_device == 0x9714) || 236 (dev->pci_device == 0x9715)) { 237 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT; 238 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT; 239 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT; 240 } else { 241 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT; 242 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT; 243 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT; 244 } 245 246 if (pi->pwm_voltage_control) { 247 fv_throt_pwm_range[0] = pi->min_voltage; 248 fv_throt_pwm_range[1] = pi->min_voltage; 249 fv_throt_pwm_range[2] = pi->max_voltage; 250 fv_throt_pwm_range[3] = pi->max_voltage; 251 } else { 252 fv_throt_pwm_range[0] = pi->invert_pwm_required ? 253 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT; 254 fv_throt_pwm_range[1] = pi->invert_pwm_required ? 255 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT; 256 fv_throt_pwm_range[2] = pi->invert_pwm_required ? 257 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT; 258 fv_throt_pwm_range[3] = pi->invert_pwm_required ? 259 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT; 260 } 261 262 WREG32_P(FVTHROT_PWM_CTRL_REG0, 263 STARTING_PWM_HIGHTIME(pi->max_voltage), 264 ~STARTING_PWM_HIGHTIME_MASK); 265 266 WREG32_P(FVTHROT_PWM_CTRL_REG0, 267 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period), 268 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK); 269 270 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, 271 ~FORCE_STARTING_PWM_HIGHTIME); 272 273 if (pi->invert_pwm_required) 274 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); 275 else 276 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM); 277 278 rs780_voltage_scaling_enable(rdev, true); 279 280 WREG32(FVTHROT_PWM_CTRL_REG1, 281 (MIN_PWM_HIGHTIME(pi->min_voltage) | 282 MAX_PWM_HIGHTIME(pi->max_voltage))); 283 284 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT); 285 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT); 286 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT); 287 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT); 288 289 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 290 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]), 291 ~RANGE0_PWM_FEEDBACK_DIV_MASK); 292 293 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2, 294 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) | 295 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2]))); 296 297 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3, 298 (RANGE0_PWM(fv_throt_pwm_range[1]) | 299 RANGE1_PWM(fv_throt_pwm_range[2]))); 300 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4, 301 (RANGE2_PWM(fv_throt_pwm_range[1]) | 302 RANGE3_PWM(fv_throt_pwm_range[2]))); 303 } 304 305 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable) 306 { 307 if (enable) 308 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE, 309 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE)); 310 else 311 WREG32_P(FVTHROT_CNTRL_REG, 0, 312 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE)); 313 } 314 315 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable) 316 { 317 if (enable) 318 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO); 319 else 320 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO); 321 } 322 323 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev) 324 { 325 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT); 326 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT); 327 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT); 328 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT); 329 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT); 330 331 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT); 332 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT); 333 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT); 334 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT); 335 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT); 336 } 337 338 static void rs780_set_engine_clock_sc(struct radeon_device *rdev) 339 { 340 WREG32_P(FVTHROT_FBDIV_REG2, 341 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT), 342 ~FB_DIV_TIMER_VAL_MASK); 343 344 WREG32_P(FVTHROT_CNTRL_REG, 345 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf), 346 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK)); 347 } 348 349 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev) 350 { 351 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE)); 352 } 353 354 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev) 355 { 356 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT); 357 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT); 358 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT); 359 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT); 360 361 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK); 362 } 363 364 static void rs780_program_at(struct radeon_device *rdev) 365 { 366 struct igp_power_info *pi = rs780_get_pi(rdev); 367 368 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate); 369 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate); 370 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate); 371 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate); 372 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate); 373 } 374 375 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev) 376 { 377 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000); 378 } 379 380 static void rs780_force_voltage_to_high(struct radeon_device *rdev) 381 { 382 struct igp_power_info *pi = rs780_get_pi(rdev); 383 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); 384 385 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) && 386 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH)) 387 return; 388 389 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 390 391 udelay(1); 392 393 WREG32_P(FVTHROT_PWM_CTRL_REG0, 394 STARTING_PWM_HIGHTIME(pi->max_voltage), 395 ~STARTING_PWM_HIGHTIME_MASK); 396 397 WREG32_P(FVTHROT_PWM_CTRL_REG0, 398 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME); 399 400 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0, 401 ~RANGE_PWM_FEEDBACK_DIV_EN); 402 403 udelay(1); 404 405 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 406 } 407 408 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev, 409 struct radeon_ps *new_ps, 410 struct radeon_ps *old_ps) 411 { 412 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers; 413 struct igp_ps *new_state = rs780_get_ps(new_ps); 414 struct igp_ps *old_state = rs780_get_ps(old_ps); 415 int ret; 416 417 if ((new_state->sclk_high == old_state->sclk_high) && 418 (new_state->sclk_low == old_state->sclk_low)) 419 return 0; 420 421 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 422 new_state->sclk_low, false, &min_dividers); 423 if (ret) 424 return ret; 425 426 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 427 new_state->sclk_high, false, &max_dividers); 428 if (ret) 429 return ret; 430 431 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 432 old_state->sclk_high, false, ¤t_max_dividers); 433 if (ret) 434 return ret; 435 436 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 437 438 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(max_dividers.fb_div), 439 ~FORCED_FEEDBACK_DIV_MASK); 440 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(max_dividers.fb_div), 441 ~STARTING_FEEDBACK_DIV_MASK); 442 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); 443 444 udelay(100); 445 446 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 447 448 if (max_dividers.fb_div > min_dividers.fb_div) { 449 WREG32_P(FVTHROT_FBDIV_REG0, 450 MIN_FEEDBACK_DIV(min_dividers.fb_div) | 451 MAX_FEEDBACK_DIV(max_dividers.fb_div), 452 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK)); 453 454 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV); 455 } 456 457 return 0; 458 } 459 460 static void rs780_set_engine_clock_spc(struct radeon_device *rdev, 461 struct radeon_ps *new_ps, 462 struct radeon_ps *old_ps) 463 { 464 struct igp_ps *new_state = rs780_get_ps(new_ps); 465 struct igp_ps *old_state = rs780_get_ps(old_ps); 466 struct igp_power_info *pi = rs780_get_pi(rdev); 467 468 if ((new_state->sclk_high == old_state->sclk_high) && 469 (new_state->sclk_low == old_state->sclk_low)) 470 return; 471 472 if (pi->crtc_id == 0) 473 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL); 474 else 475 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL); 476 477 } 478 479 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev, 480 struct radeon_ps *new_ps, 481 struct radeon_ps *old_ps) 482 { 483 struct igp_ps *new_state = rs780_get_ps(new_ps); 484 struct igp_ps *old_state = rs780_get_ps(old_ps); 485 486 if ((new_state->sclk_high == old_state->sclk_high) && 487 (new_state->sclk_low == old_state->sclk_low)) 488 return; 489 490 rs780_clk_scaling_enable(rdev, true); 491 } 492 493 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev, 494 enum rs780_vddc_level vddc) 495 { 496 struct igp_power_info *pi = rs780_get_pi(rdev); 497 498 if (vddc == RS780_VDDC_LEVEL_HIGH) 499 return pi->max_voltage; 500 else if (vddc == RS780_VDDC_LEVEL_LOW) 501 return pi->min_voltage; 502 else 503 return pi->max_voltage; 504 } 505 506 static void rs780_enable_voltage_scaling(struct radeon_device *rdev, 507 struct radeon_ps *new_ps) 508 { 509 struct igp_ps *new_state = rs780_get_ps(new_ps); 510 struct igp_power_info *pi = rs780_get_pi(rdev); 511 enum rs780_vddc_level vddc_high, vddc_low; 512 513 udelay(100); 514 515 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) && 516 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH)) 517 return; 518 519 vddc_high = rs780_get_voltage_for_vddc_level(rdev, 520 new_state->max_voltage); 521 vddc_low = rs780_get_voltage_for_vddc_level(rdev, 522 new_state->min_voltage); 523 524 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 525 526 udelay(1); 527 if (vddc_high > vddc_low) { 528 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 529 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN); 530 531 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME); 532 } else if (vddc_high == vddc_low) { 533 if (pi->max_voltage != vddc_high) { 534 WREG32_P(FVTHROT_PWM_CTRL_REG0, 535 STARTING_PWM_HIGHTIME(vddc_high), 536 ~STARTING_PWM_HIGHTIME_MASK); 537 538 WREG32_P(FVTHROT_PWM_CTRL_REG0, 539 FORCE_STARTING_PWM_HIGHTIME, 540 ~FORCE_STARTING_PWM_HIGHTIME); 541 } 542 } 543 544 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 545 } 546 547 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 548 struct radeon_ps *new_ps, 549 struct radeon_ps *old_ps) 550 { 551 struct igp_ps *new_state = rs780_get_ps(new_ps); 552 struct igp_ps *current_state = rs780_get_ps(old_ps); 553 554 if ((new_ps->vclk == old_ps->vclk) && 555 (new_ps->dclk == old_ps->dclk)) 556 return; 557 558 if (new_state->sclk_high >= current_state->sclk_high) 559 return; 560 561 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 562 } 563 564 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 565 struct radeon_ps *new_ps, 566 struct radeon_ps *old_ps) 567 { 568 struct igp_ps *new_state = rs780_get_ps(new_ps); 569 struct igp_ps *current_state = rs780_get_ps(old_ps); 570 571 if ((new_ps->vclk == old_ps->vclk) && 572 (new_ps->dclk == old_ps->dclk)) 573 return; 574 575 if (new_state->sclk_high < current_state->sclk_high) 576 return; 577 578 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 579 } 580 581 int rs780_dpm_enable(struct radeon_device *rdev) 582 { 583 struct igp_power_info *pi = rs780_get_pi(rdev); 584 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 585 int ret; 586 587 rs780_get_pm_mode_parameters(rdev); 588 rs780_disable_vbios_powersaving(rdev); 589 590 if (r600_dynamicpm_enabled(rdev)) 591 return -EINVAL; 592 ret = rs780_initialize_dpm_parameters(rdev, boot_ps); 593 if (ret) 594 return ret; 595 rs780_start_dpm(rdev); 596 597 rs780_preset_ranges_slow_clk_fbdiv_en(rdev); 598 rs780_preset_starting_fbdiv(rdev); 599 if (pi->voltage_control) 600 rs780_voltage_scaling_init(rdev); 601 rs780_clk_scaling_enable(rdev, true); 602 rs780_set_engine_clock_sc(rdev); 603 rs780_set_engine_clock_wfc(rdev); 604 rs780_program_at(rdev); 605 rs780_set_engine_clock_tdc(rdev); 606 rs780_set_engine_clock_ssc(rdev); 607 608 if (pi->gfx_clock_gating) 609 r600_gfx_clockgating_enable(rdev, true); 610 611 if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) { 612 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 613 if (ret) 614 return ret; 615 rdev->irq.dpm_thermal = true; 616 radeon_irq_set(rdev); 617 } 618 619 return 0; 620 } 621 622 void rs780_dpm_disable(struct radeon_device *rdev) 623 { 624 struct igp_power_info *pi = rs780_get_pi(rdev); 625 626 r600_dynamicpm_enable(rdev, false); 627 628 rs780_clk_scaling_enable(rdev, false); 629 rs780_voltage_scaling_enable(rdev, false); 630 631 if (pi->gfx_clock_gating) 632 r600_gfx_clockgating_enable(rdev, false); 633 634 if (rdev->irq.installed && 635 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) { 636 rdev->irq.dpm_thermal = false; 637 radeon_irq_set(rdev); 638 } 639 } 640 641 int rs780_dpm_set_power_state(struct radeon_device *rdev) 642 { 643 struct igp_power_info *pi = rs780_get_pi(rdev); 644 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 645 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; 646 int ret; 647 648 rs780_get_pm_mode_parameters(rdev); 649 650 rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 651 652 if (pi->voltage_control) { 653 rs780_force_voltage_to_high(rdev); 654 mdelay(5); 655 } 656 657 ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps); 658 if (ret) 659 return ret; 660 rs780_set_engine_clock_spc(rdev, new_ps, old_ps); 661 662 rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps); 663 664 if (pi->voltage_control) 665 rs780_enable_voltage_scaling(rdev, new_ps); 666 667 rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 668 669 return 0; 670 } 671 672 void rs780_dpm_setup_asic(struct radeon_device *rdev) 673 { 674 675 } 676 677 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev) 678 { 679 rs780_get_pm_mode_parameters(rdev); 680 rs780_program_at(rdev); 681 } 682 683 union igp_info { 684 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 685 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 686 }; 687 688 union power_info { 689 struct _ATOM_POWERPLAY_INFO info; 690 struct _ATOM_POWERPLAY_INFO_V2 info_2; 691 struct _ATOM_POWERPLAY_INFO_V3 info_3; 692 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 693 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 694 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 695 }; 696 697 union pplib_clock_info { 698 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 699 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 700 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 701 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 702 }; 703 704 union pplib_power_state { 705 struct _ATOM_PPLIB_STATE v1; 706 struct _ATOM_PPLIB_STATE_V2 v2; 707 }; 708 709 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev, 710 struct radeon_ps *rps, 711 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 712 u8 table_rev) 713 { 714 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 715 rps->class = le16_to_cpu(non_clock_info->usClassification); 716 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 717 718 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 719 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 720 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 721 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 722 rps->vclk = RS780_DEFAULT_VCLK_FREQ; 723 rps->dclk = RS780_DEFAULT_DCLK_FREQ; 724 } else { 725 rps->vclk = 0; 726 rps->dclk = 0; 727 } 728 729 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 730 rdev->pm.dpm.boot_ps = rps; 731 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 732 rdev->pm.dpm.uvd_ps = rps; 733 } 734 735 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev, 736 struct radeon_ps *rps, 737 union pplib_clock_info *clock_info) 738 { 739 struct igp_ps *ps = rs780_get_ps(rps); 740 u32 sclk; 741 742 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 743 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 744 ps->sclk_low = sclk; 745 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow); 746 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16; 747 ps->sclk_high = sclk; 748 switch (le16_to_cpu(clock_info->rs780.usVDDC)) { 749 case ATOM_PPLIB_RS780_VOLTAGE_NONE: 750 default: 751 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN; 752 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN; 753 break; 754 case ATOM_PPLIB_RS780_VOLTAGE_LOW: 755 ps->min_voltage = RS780_VDDC_LEVEL_LOW; 756 ps->max_voltage = RS780_VDDC_LEVEL_LOW; 757 break; 758 case ATOM_PPLIB_RS780_VOLTAGE_HIGH: 759 ps->min_voltage = RS780_VDDC_LEVEL_HIGH; 760 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 761 break; 762 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE: 763 ps->min_voltage = RS780_VDDC_LEVEL_LOW; 764 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 765 break; 766 } 767 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags); 768 769 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 770 ps->sclk_low = rdev->clock.default_sclk; 771 ps->sclk_high = rdev->clock.default_sclk; 772 ps->min_voltage = RS780_VDDC_LEVEL_HIGH; 773 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 774 } 775 } 776 777 static int rs780_parse_power_table(struct radeon_device *rdev) 778 { 779 struct radeon_mode_info *mode_info = &rdev->mode_info; 780 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 781 union pplib_power_state *power_state; 782 int i; 783 union pplib_clock_info *clock_info; 784 union power_info *power_info; 785 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 786 u16 data_offset; 787 u8 frev, crev; 788 struct igp_ps *ps; 789 790 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 791 &frev, &crev, &data_offset)) 792 return -EINVAL; 793 power_info = (union power_info *)((uint8_t*)mode_info->atom_context->bios + data_offset); 794 795 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 796 power_info->pplib.ucNumStates, GFP_KERNEL); 797 if (!rdev->pm.dpm.ps) 798 return -ENOMEM; 799 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 800 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 801 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 802 803 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 804 power_state = (union pplib_power_state *) 805 ((uint8_t*)mode_info->atom_context->bios + data_offset + 806 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 807 i * power_info->pplib.ucStateEntrySize); 808 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 809 ((uint8_t*)mode_info->atom_context->bios + data_offset + 810 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 811 (power_state->v1.ucNonClockStateIndex * 812 power_info->pplib.ucNonClockSize)); 813 if (power_info->pplib.ucStateEntrySize - 1) { 814 clock_info = (union pplib_clock_info *) 815 ((uint8_t*)mode_info->atom_context->bios + data_offset + 816 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 817 (power_state->v1.ucClockStateIndices[0] * 818 power_info->pplib.ucClockInfoSize)); 819 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL); 820 if (ps == NULL) { 821 kfree(rdev->pm.dpm.ps); 822 return -ENOMEM; 823 } 824 rdev->pm.dpm.ps[i].ps_priv = ps; 825 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 826 non_clock_info, 827 power_info->pplib.ucNonClockSize); 828 rs780_parse_pplib_clock_info(rdev, 829 &rdev->pm.dpm.ps[i], 830 clock_info); 831 } 832 } 833 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; 834 return 0; 835 } 836 837 int rs780_dpm_init(struct radeon_device *rdev) 838 { 839 struct igp_power_info *pi; 840 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 841 union igp_info *info; 842 u16 data_offset; 843 u8 frev, crev; 844 int ret; 845 846 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL); 847 if (pi == NULL) 848 return -ENOMEM; 849 rdev->pm.dpm.priv = pi; 850 851 ret = rs780_parse_power_table(rdev); 852 if (ret) 853 return ret; 854 855 pi->voltage_control = false; 856 pi->gfx_clock_gating = true; 857 858 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 859 &frev, &crev, &data_offset)) { 860 info = (union igp_info *)((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 861 862 /* Get various system informations from bios */ 863 switch (crev) { 864 case 1: 865 pi->num_of_cycles_in_period = 866 info->info.ucNumberOfCyclesInPeriod; 867 pi->num_of_cycles_in_period |= 868 info->info.ucNumberOfCyclesInPeriodHi << 8; 869 pi->invert_pwm_required = 870 (pi->num_of_cycles_in_period & 0x8000) ? true : false; 871 pi->boot_voltage = info->info.ucStartingPWM_HighTime; 872 pi->max_voltage = info->info.ucMaxNBVoltage; 873 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8; 874 pi->min_voltage = info->info.ucMinNBVoltage; 875 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8; 876 pi->inter_voltage_low = 877 le16_to_cpu(info->info.usInterNBVoltageLow); 878 pi->inter_voltage_high = 879 le16_to_cpu(info->info.usInterNBVoltageHigh); 880 pi->voltage_control = true; 881 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100; 882 break; 883 case 2: 884 pi->num_of_cycles_in_period = 885 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod); 886 pi->invert_pwm_required = 887 (pi->num_of_cycles_in_period & 0x8000) ? true : false; 888 pi->boot_voltage = 889 le16_to_cpu(info->info_2.usBootUpNBVoltage); 890 pi->max_voltage = 891 le16_to_cpu(info->info_2.usMaxNBVoltage); 892 pi->min_voltage = 893 le16_to_cpu(info->info_2.usMinNBVoltage); 894 pi->system_config = 895 le32_to_cpu(info->info_2.ulSystemConfig); 896 pi->pwm_voltage_control = 897 (pi->system_config & 0x4) ? true : false; 898 pi->voltage_control = true; 899 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock); 900 break; 901 default: 902 DRM_ERROR("No integrated system info for your GPU\n"); 903 return -EINVAL; 904 } 905 if (pi->min_voltage > pi->max_voltage) 906 pi->voltage_control = false; 907 if (pi->pwm_voltage_control) { 908 if ((pi->num_of_cycles_in_period == 0) || 909 (pi->max_voltage == 0) || 910 (pi->min_voltage == 0)) 911 pi->voltage_control = false; 912 } else { 913 if ((pi->num_of_cycles_in_period == 0) || 914 (pi->max_voltage == 0)) 915 pi->voltage_control = false; 916 } 917 918 return 0; 919 } 920 radeon_dpm_fini(rdev); 921 return -EINVAL; 922 } 923 924 void rs780_dpm_print_power_state(struct radeon_device *rdev, 925 struct radeon_ps *rps) 926 { 927 struct igp_ps *ps = rs780_get_ps(rps); 928 929 r600_dpm_print_class_info(rps->class, rps->class2); 930 r600_dpm_print_cap_info(rps->caps); 931 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 932 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n", 933 ps->sclk_low, ps->min_voltage); 934 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n", 935 ps->sclk_high, ps->max_voltage); 936 r600_dpm_print_ps_status(rdev, rps); 937 } 938 939 void rs780_dpm_fini(struct radeon_device *rdev) 940 { 941 int i; 942 943 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 944 kfree(rdev->pm.dpm.ps[i].ps_priv); 945 } 946 kfree(rdev->pm.dpm.ps); 947 kfree(rdev->pm.dpm.priv); 948 } 949 950 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low) 951 { 952 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps); 953 954 if (low) 955 return requested_state->sclk_low; 956 else 957 return requested_state->sclk_high; 958 } 959 960 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low) 961 { 962 struct igp_power_info *pi = rs780_get_pi(rdev); 963 964 return pi->bootup_uma_clk; 965 } 966 967 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 968 struct seq_file *m) 969 { 970 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 971 struct igp_ps *ps = rs780_get_ps(rps); 972 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; 973 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 974 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; 975 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + 976 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1; 977 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / 978 (post_div * ref_div); 979 980 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 981 982 /* guess based on the current sclk */ 983 if (sclk < (ps->sclk_low + 500)) 984 seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n", 985 ps->sclk_low, ps->min_voltage); 986 else 987 seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n", 988 ps->sclk_high, ps->max_voltage); 989 } 990