1926deccbSFrançois Tigeot /*
2926deccbSFrançois Tigeot * Copyright 2008 Advanced Micro Devices, Inc.
3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc.
4926deccbSFrançois Tigeot * Copyright 2009 Jerome Glisse.
5926deccbSFrançois Tigeot *
6926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a
7926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"),
8926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation
9926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the
11926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions:
12926deccbSFrançois Tigeot *
13926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in
14926deccbSFrançois Tigeot * all copies or substantial portions of the Software.
15926deccbSFrançois Tigeot *
16926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE.
23926deccbSFrançois Tigeot *
24926deccbSFrançois Tigeot * Authors: Dave Airlie
25926deccbSFrançois Tigeot * Alex Deucher
26926deccbSFrançois Tigeot * Jerome Glisse
27926deccbSFrançois Tigeot */
28*a85cb24fSFrançois Tigeot #include <linux/seq_file.h>
29*a85cb24fSFrançois Tigeot #include <linux/slab.h>
30926deccbSFrançois Tigeot #include <drm/drmP.h>
31926deccbSFrançois Tigeot #include "rv515d.h"
32926deccbSFrançois Tigeot #include "radeon.h"
33926deccbSFrançois Tigeot #include "radeon_asic.h"
34926deccbSFrançois Tigeot #include "atom.h"
35926deccbSFrançois Tigeot #include "rv515_reg_safe.h"
36926deccbSFrançois Tigeot
37926deccbSFrançois Tigeot /* This files gather functions specifics to: rv515 */
38926deccbSFrançois Tigeot static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39926deccbSFrançois Tigeot static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40926deccbSFrançois Tigeot static void rv515_gpu_init(struct radeon_device *rdev);
41926deccbSFrançois Tigeot
42926deccbSFrançois Tigeot static const u32 crtc_offsets[2] =
43926deccbSFrançois Tigeot {
44926deccbSFrançois Tigeot 0,
45926deccbSFrançois Tigeot AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
46926deccbSFrançois Tigeot };
47926deccbSFrançois Tigeot
rv515_debugfs(struct radeon_device * rdev)48926deccbSFrançois Tigeot void rv515_debugfs(struct radeon_device *rdev)
49926deccbSFrançois Tigeot {
50926deccbSFrançois Tigeot if (r100_debugfs_rbbm_init(rdev)) {
51926deccbSFrançois Tigeot DRM_ERROR("Failed to register debugfs file for RBBM !\n");
52926deccbSFrançois Tigeot }
53926deccbSFrançois Tigeot if (rv515_debugfs_pipes_info_init(rdev)) {
54926deccbSFrançois Tigeot DRM_ERROR("Failed to register debugfs file for pipes !\n");
55926deccbSFrançois Tigeot }
56926deccbSFrançois Tigeot if (rv515_debugfs_ga_info_init(rdev)) {
57926deccbSFrançois Tigeot DRM_ERROR("Failed to register debugfs file for pipes !\n");
58926deccbSFrançois Tigeot }
59926deccbSFrançois Tigeot }
60926deccbSFrançois Tigeot
rv515_ring_start(struct radeon_device * rdev,struct radeon_ring * ring)61926deccbSFrançois Tigeot void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
62926deccbSFrançois Tigeot {
63926deccbSFrançois Tigeot int r;
64926deccbSFrançois Tigeot
65926deccbSFrançois Tigeot r = radeon_ring_lock(rdev, ring, 64);
66926deccbSFrançois Tigeot if (r) {
67926deccbSFrançois Tigeot return;
68926deccbSFrançois Tigeot }
69926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
70926deccbSFrançois Tigeot radeon_ring_write(ring,
71926deccbSFrançois Tigeot ISYNC_ANY2D_IDLE3D |
72926deccbSFrançois Tigeot ISYNC_ANY3D_IDLE2D |
73926deccbSFrançois Tigeot ISYNC_WAIT_IDLEGUI |
74926deccbSFrançois Tigeot ISYNC_CPSCRATCH_IDLEGUI);
75926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
76926deccbSFrançois Tigeot radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
77926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
78926deccbSFrançois Tigeot radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
79926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
80926deccbSFrançois Tigeot radeon_ring_write(ring, 0);
81926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
82926deccbSFrançois Tigeot radeon_ring_write(ring, 0);
83926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
84926deccbSFrançois Tigeot radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
85926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
86926deccbSFrançois Tigeot radeon_ring_write(ring, 0);
87926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
88926deccbSFrançois Tigeot radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
89926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
90926deccbSFrançois Tigeot radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
91926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
92926deccbSFrançois Tigeot radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
93926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
94926deccbSFrançois Tigeot radeon_ring_write(ring, 0);
95926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
96926deccbSFrançois Tigeot radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
97926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
98926deccbSFrançois Tigeot radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
99926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
100926deccbSFrançois Tigeot radeon_ring_write(ring,
101926deccbSFrançois Tigeot ((6 << MS_X0_SHIFT) |
102926deccbSFrançois Tigeot (6 << MS_Y0_SHIFT) |
103926deccbSFrançois Tigeot (6 << MS_X1_SHIFT) |
104926deccbSFrançois Tigeot (6 << MS_Y1_SHIFT) |
105926deccbSFrançois Tigeot (6 << MS_X2_SHIFT) |
106926deccbSFrançois Tigeot (6 << MS_Y2_SHIFT) |
107926deccbSFrançois Tigeot (6 << MSBD0_Y_SHIFT) |
108926deccbSFrançois Tigeot (6 << MSBD0_X_SHIFT)));
109926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
110926deccbSFrançois Tigeot radeon_ring_write(ring,
111926deccbSFrançois Tigeot ((6 << MS_X3_SHIFT) |
112926deccbSFrançois Tigeot (6 << MS_Y3_SHIFT) |
113926deccbSFrançois Tigeot (6 << MS_X4_SHIFT) |
114926deccbSFrançois Tigeot (6 << MS_Y4_SHIFT) |
115926deccbSFrançois Tigeot (6 << MS_X5_SHIFT) |
116926deccbSFrançois Tigeot (6 << MS_Y5_SHIFT) |
117926deccbSFrançois Tigeot (6 << MSBD1_SHIFT)));
118926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
119926deccbSFrançois Tigeot radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
120926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
121926deccbSFrançois Tigeot radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
122926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
123926deccbSFrançois Tigeot radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
124926deccbSFrançois Tigeot radeon_ring_write(ring, PACKET0(0x20C8, 0));
125926deccbSFrançois Tigeot radeon_ring_write(ring, 0);
126c6f73aabSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring, false);
127926deccbSFrançois Tigeot }
128926deccbSFrançois Tigeot
rv515_mc_wait_for_idle(struct radeon_device * rdev)129926deccbSFrançois Tigeot int rv515_mc_wait_for_idle(struct radeon_device *rdev)
130926deccbSFrançois Tigeot {
131926deccbSFrançois Tigeot unsigned i;
132926deccbSFrançois Tigeot uint32_t tmp;
133926deccbSFrançois Tigeot
134926deccbSFrançois Tigeot for (i = 0; i < rdev->usec_timeout; i++) {
135926deccbSFrançois Tigeot /* read MC_STATUS */
136926deccbSFrançois Tigeot tmp = RREG32_MC(MC_STATUS);
137926deccbSFrançois Tigeot if (tmp & MC_STATUS_IDLE) {
138926deccbSFrançois Tigeot return 0;
139926deccbSFrançois Tigeot }
140926deccbSFrançois Tigeot DRM_UDELAY(1);
141926deccbSFrançois Tigeot }
142926deccbSFrançois Tigeot return -1;
143926deccbSFrançois Tigeot }
144926deccbSFrançois Tigeot
rv515_vga_render_disable(struct radeon_device * rdev)145926deccbSFrançois Tigeot void rv515_vga_render_disable(struct radeon_device *rdev)
146926deccbSFrançois Tigeot {
147926deccbSFrançois Tigeot WREG32(R_000300_VGA_RENDER_CONTROL,
148926deccbSFrançois Tigeot RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
149926deccbSFrançois Tigeot }
150926deccbSFrançois Tigeot
rv515_gpu_init(struct radeon_device * rdev)151926deccbSFrançois Tigeot static void rv515_gpu_init(struct radeon_device *rdev)
152926deccbSFrançois Tigeot {
153926deccbSFrançois Tigeot unsigned pipe_select_current, gb_pipe_select, tmp;
154926deccbSFrançois Tigeot
155926deccbSFrançois Tigeot if (r100_gui_wait_for_idle(rdev)) {
156*a85cb24fSFrançois Tigeot pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
157926deccbSFrançois Tigeot }
158926deccbSFrançois Tigeot rv515_vga_render_disable(rdev);
159926deccbSFrançois Tigeot r420_pipes_init(rdev);
160926deccbSFrançois Tigeot gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
161926deccbSFrançois Tigeot tmp = RREG32(R300_DST_PIPE_CONFIG);
162926deccbSFrançois Tigeot pipe_select_current = (tmp >> 2) & 3;
163926deccbSFrançois Tigeot tmp = (1 << pipe_select_current) |
164926deccbSFrançois Tigeot (((gb_pipe_select >> 8) & 0xF) << 4);
165926deccbSFrançois Tigeot WREG32_PLL(0x000D, tmp);
166926deccbSFrançois Tigeot if (r100_gui_wait_for_idle(rdev)) {
167*a85cb24fSFrançois Tigeot pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
168926deccbSFrançois Tigeot }
169926deccbSFrançois Tigeot if (rv515_mc_wait_for_idle(rdev)) {
170*a85cb24fSFrançois Tigeot pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
171926deccbSFrançois Tigeot }
172926deccbSFrançois Tigeot }
173926deccbSFrançois Tigeot
rv515_vram_get_type(struct radeon_device * rdev)174926deccbSFrançois Tigeot static void rv515_vram_get_type(struct radeon_device *rdev)
175926deccbSFrançois Tigeot {
176926deccbSFrançois Tigeot uint32_t tmp;
177926deccbSFrançois Tigeot
178926deccbSFrançois Tigeot rdev->mc.vram_width = 128;
179926deccbSFrançois Tigeot rdev->mc.vram_is_ddr = true;
180926deccbSFrançois Tigeot tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
181926deccbSFrançois Tigeot switch (tmp) {
182926deccbSFrançois Tigeot case 0:
183926deccbSFrançois Tigeot rdev->mc.vram_width = 64;
184926deccbSFrançois Tigeot break;
185926deccbSFrançois Tigeot case 1:
186926deccbSFrançois Tigeot rdev->mc.vram_width = 128;
187926deccbSFrançois Tigeot break;
188926deccbSFrançois Tigeot default:
189926deccbSFrançois Tigeot rdev->mc.vram_width = 128;
190926deccbSFrançois Tigeot break;
191926deccbSFrançois Tigeot }
192926deccbSFrançois Tigeot }
193926deccbSFrançois Tigeot
rv515_mc_init(struct radeon_device * rdev)194926deccbSFrançois Tigeot static void rv515_mc_init(struct radeon_device *rdev)
195926deccbSFrançois Tigeot {
196926deccbSFrançois Tigeot
197926deccbSFrançois Tigeot rv515_vram_get_type(rdev);
198926deccbSFrançois Tigeot r100_vram_init_sizes(rdev);
199926deccbSFrançois Tigeot radeon_vram_location(rdev, &rdev->mc, 0);
200926deccbSFrançois Tigeot rdev->mc.gtt_base_align = 0;
201926deccbSFrançois Tigeot if (!(rdev->flags & RADEON_IS_AGP))
202926deccbSFrançois Tigeot radeon_gtt_location(rdev, &rdev->mc);
203926deccbSFrançois Tigeot radeon_update_bandwidth_info(rdev);
204926deccbSFrançois Tigeot }
205926deccbSFrançois Tigeot
rv515_mc_rreg(struct radeon_device * rdev,uint32_t reg)206926deccbSFrançois Tigeot uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
207926deccbSFrançois Tigeot {
208*a85cb24fSFrançois Tigeot unsigned long flags;
209926deccbSFrançois Tigeot uint32_t r;
210926deccbSFrançois Tigeot
211*a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->mc_idx_lock, flags);
212926deccbSFrançois Tigeot WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
213926deccbSFrançois Tigeot r = RREG32(MC_IND_DATA);
214926deccbSFrançois Tigeot WREG32(MC_IND_INDEX, 0);
215*a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
216c6f73aabSFrançois Tigeot
217926deccbSFrançois Tigeot return r;
218926deccbSFrançois Tigeot }
219926deccbSFrançois Tigeot
rv515_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)220926deccbSFrançois Tigeot void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
221926deccbSFrançois Tigeot {
222*a85cb24fSFrançois Tigeot unsigned long flags;
223*a85cb24fSFrançois Tigeot
224*a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->mc_idx_lock, flags);
225926deccbSFrançois Tigeot WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
226926deccbSFrançois Tigeot WREG32(MC_IND_DATA, (v));
227926deccbSFrançois Tigeot WREG32(MC_IND_INDEX, 0);
228*a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
229926deccbSFrançois Tigeot }
230926deccbSFrançois Tigeot
231926deccbSFrançois Tigeot #if defined(CONFIG_DEBUG_FS)
rv515_debugfs_pipes_info(struct seq_file * m,void * data)232926deccbSFrançois Tigeot static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
233926deccbSFrançois Tigeot {
234926deccbSFrançois Tigeot struct drm_info_node *node = (struct drm_info_node *) m->private;
235926deccbSFrançois Tigeot struct drm_device *dev = node->minor->dev;
236926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
237926deccbSFrançois Tigeot uint32_t tmp;
238926deccbSFrançois Tigeot
239926deccbSFrançois Tigeot tmp = RREG32(GB_PIPE_SELECT);
240926deccbSFrançois Tigeot seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
241926deccbSFrançois Tigeot tmp = RREG32(SU_REG_DEST);
242926deccbSFrançois Tigeot seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
243926deccbSFrançois Tigeot tmp = RREG32(GB_TILE_CONFIG);
244926deccbSFrançois Tigeot seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
245926deccbSFrançois Tigeot tmp = RREG32(DST_PIPE_CONFIG);
246926deccbSFrançois Tigeot seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
247926deccbSFrançois Tigeot return 0;
248926deccbSFrançois Tigeot }
249926deccbSFrançois Tigeot
rv515_debugfs_ga_info(struct seq_file * m,void * data)250926deccbSFrançois Tigeot static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
251926deccbSFrançois Tigeot {
252926deccbSFrançois Tigeot struct drm_info_node *node = (struct drm_info_node *) m->private;
253926deccbSFrançois Tigeot struct drm_device *dev = node->minor->dev;
254926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
255926deccbSFrançois Tigeot uint32_t tmp;
256926deccbSFrançois Tigeot
257926deccbSFrançois Tigeot tmp = RREG32(0x2140);
258926deccbSFrançois Tigeot seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
259926deccbSFrançois Tigeot radeon_asic_reset(rdev);
260926deccbSFrançois Tigeot tmp = RREG32(0x425C);
261926deccbSFrançois Tigeot seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
262926deccbSFrançois Tigeot return 0;
263926deccbSFrançois Tigeot }
264926deccbSFrançois Tigeot
265926deccbSFrançois Tigeot static struct drm_info_list rv515_pipes_info_list[] = {
266926deccbSFrançois Tigeot {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
267926deccbSFrançois Tigeot };
268926deccbSFrançois Tigeot
269926deccbSFrançois Tigeot static struct drm_info_list rv515_ga_info_list[] = {
270926deccbSFrançois Tigeot {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
271926deccbSFrançois Tigeot };
272926deccbSFrançois Tigeot #endif
273926deccbSFrançois Tigeot
rv515_debugfs_pipes_info_init(struct radeon_device * rdev)274926deccbSFrançois Tigeot static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
275926deccbSFrançois Tigeot {
276926deccbSFrançois Tigeot #if defined(CONFIG_DEBUG_FS)
277926deccbSFrançois Tigeot return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
278926deccbSFrançois Tigeot #else
279926deccbSFrançois Tigeot return 0;
280926deccbSFrançois Tigeot #endif
281926deccbSFrançois Tigeot }
282926deccbSFrançois Tigeot
rv515_debugfs_ga_info_init(struct radeon_device * rdev)283926deccbSFrançois Tigeot static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
284926deccbSFrançois Tigeot {
285926deccbSFrançois Tigeot #if defined(CONFIG_DEBUG_FS)
286926deccbSFrançois Tigeot return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
287926deccbSFrançois Tigeot #else
288926deccbSFrançois Tigeot return 0;
289926deccbSFrançois Tigeot #endif
290926deccbSFrançois Tigeot }
291926deccbSFrançois Tigeot
rv515_mc_stop(struct radeon_device * rdev,struct rv515_mc_save * save)292926deccbSFrançois Tigeot void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
293926deccbSFrançois Tigeot {
294926deccbSFrançois Tigeot u32 crtc_enabled, tmp, frame_count, blackout;
295926deccbSFrançois Tigeot int i, j;
296926deccbSFrançois Tigeot
297926deccbSFrançois Tigeot save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
298926deccbSFrançois Tigeot save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
299926deccbSFrançois Tigeot
300926deccbSFrançois Tigeot /* disable VGA render */
301926deccbSFrançois Tigeot WREG32(R_000300_VGA_RENDER_CONTROL, 0);
302926deccbSFrançois Tigeot /* blank the display controllers */
303926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) {
304926deccbSFrançois Tigeot crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
305926deccbSFrançois Tigeot if (crtc_enabled) {
306926deccbSFrançois Tigeot save->crtc_enabled[i] = true;
307926deccbSFrançois Tigeot tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
308926deccbSFrançois Tigeot if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
309926deccbSFrançois Tigeot radeon_wait_for_vblank(rdev, i);
310f43cf1b1SMichael Neumann WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
311926deccbSFrançois Tigeot tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
312926deccbSFrançois Tigeot WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
313f43cf1b1SMichael Neumann WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
314926deccbSFrançois Tigeot }
315926deccbSFrançois Tigeot /* wait for the next frame */
316926deccbSFrançois Tigeot frame_count = radeon_get_vblank_counter(rdev, i);
317926deccbSFrançois Tigeot for (j = 0; j < rdev->usec_timeout; j++) {
318926deccbSFrançois Tigeot if (radeon_get_vblank_counter(rdev, i) != frame_count)
319926deccbSFrançois Tigeot break;
320c4ef309bSzrj udelay(1);
321926deccbSFrançois Tigeot }
322f43cf1b1SMichael Neumann
323f43cf1b1SMichael Neumann /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
324f43cf1b1SMichael Neumann WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
325f43cf1b1SMichael Neumann tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
326f43cf1b1SMichael Neumann tmp &= ~AVIVO_CRTC_EN;
327f43cf1b1SMichael Neumann WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
328f43cf1b1SMichael Neumann WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
329f43cf1b1SMichael Neumann save->crtc_enabled[i] = false;
330f43cf1b1SMichael Neumann /* ***** */
331926deccbSFrançois Tigeot } else {
332926deccbSFrançois Tigeot save->crtc_enabled[i] = false;
333926deccbSFrançois Tigeot }
334926deccbSFrançois Tigeot }
335926deccbSFrançois Tigeot
336926deccbSFrançois Tigeot radeon_mc_wait_for_idle(rdev);
337926deccbSFrançois Tigeot
338926deccbSFrançois Tigeot if (rdev->family >= CHIP_R600) {
339926deccbSFrançois Tigeot if (rdev->family >= CHIP_RV770)
340926deccbSFrançois Tigeot blackout = RREG32(R700_MC_CITF_CNTL);
341926deccbSFrançois Tigeot else
342926deccbSFrançois Tigeot blackout = RREG32(R600_CITF_CNTL);
343926deccbSFrançois Tigeot if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
344926deccbSFrançois Tigeot /* Block CPU access */
345926deccbSFrançois Tigeot WREG32(R600_BIF_FB_EN, 0);
346926deccbSFrançois Tigeot /* blackout the MC */
347926deccbSFrançois Tigeot blackout |= R600_BLACKOUT_MASK;
348926deccbSFrançois Tigeot if (rdev->family >= CHIP_RV770)
349926deccbSFrançois Tigeot WREG32(R700_MC_CITF_CNTL, blackout);
350926deccbSFrançois Tigeot else
351926deccbSFrançois Tigeot WREG32(R600_CITF_CNTL, blackout);
352926deccbSFrançois Tigeot }
353926deccbSFrançois Tigeot }
354926deccbSFrançois Tigeot /* wait for the MC to settle */
355c4ef309bSzrj udelay(100);
356f43cf1b1SMichael Neumann
357f43cf1b1SMichael Neumann /* lock double buffered regs */
358f43cf1b1SMichael Neumann for (i = 0; i < rdev->num_crtc; i++) {
359f43cf1b1SMichael Neumann if (save->crtc_enabled[i]) {
360f43cf1b1SMichael Neumann tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
361f43cf1b1SMichael Neumann if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
362f43cf1b1SMichael Neumann tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
363f43cf1b1SMichael Neumann WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
364f43cf1b1SMichael Neumann }
365f43cf1b1SMichael Neumann tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
366f43cf1b1SMichael Neumann if (!(tmp & 1)) {
367f43cf1b1SMichael Neumann tmp |= 1;
368f43cf1b1SMichael Neumann WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
369f43cf1b1SMichael Neumann }
370f43cf1b1SMichael Neumann }
371f43cf1b1SMichael Neumann }
372926deccbSFrançois Tigeot }
373926deccbSFrançois Tigeot
rv515_mc_resume(struct radeon_device * rdev,struct rv515_mc_save * save)374926deccbSFrançois Tigeot void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
375926deccbSFrançois Tigeot {
376926deccbSFrançois Tigeot u32 tmp, frame_count;
377926deccbSFrançois Tigeot int i, j;
378926deccbSFrançois Tigeot
379926deccbSFrançois Tigeot /* update crtc base addresses */
380926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) {
381926deccbSFrançois Tigeot if (rdev->family >= CHIP_RV770) {
382f43cf1b1SMichael Neumann if (i == 0) {
383926deccbSFrançois Tigeot WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
384926deccbSFrançois Tigeot upper_32_bits(rdev->mc.vram_start));
385926deccbSFrançois Tigeot WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
386926deccbSFrançois Tigeot upper_32_bits(rdev->mc.vram_start));
387926deccbSFrançois Tigeot } else {
388926deccbSFrançois Tigeot WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
389926deccbSFrançois Tigeot upper_32_bits(rdev->mc.vram_start));
390926deccbSFrançois Tigeot WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
391926deccbSFrançois Tigeot upper_32_bits(rdev->mc.vram_start));
392926deccbSFrançois Tigeot }
393926deccbSFrançois Tigeot }
394926deccbSFrançois Tigeot WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
395926deccbSFrançois Tigeot (u32)rdev->mc.vram_start);
396926deccbSFrançois Tigeot WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
397926deccbSFrançois Tigeot (u32)rdev->mc.vram_start);
398926deccbSFrançois Tigeot }
399926deccbSFrançois Tigeot WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
400926deccbSFrançois Tigeot
401f43cf1b1SMichael Neumann /* unlock regs and wait for update */
402f43cf1b1SMichael Neumann for (i = 0; i < rdev->num_crtc; i++) {
403f43cf1b1SMichael Neumann if (save->crtc_enabled[i]) {
404f43cf1b1SMichael Neumann tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
405c6f73aabSFrançois Tigeot if ((tmp & 0x7) != 3) {
406c6f73aabSFrançois Tigeot tmp &= ~0x7;
407c6f73aabSFrançois Tigeot tmp |= 0x3;
408f43cf1b1SMichael Neumann WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
409f43cf1b1SMichael Neumann }
410f43cf1b1SMichael Neumann tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
411f43cf1b1SMichael Neumann if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
412f43cf1b1SMichael Neumann tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
413f43cf1b1SMichael Neumann WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
414f43cf1b1SMichael Neumann }
415f43cf1b1SMichael Neumann tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
416f43cf1b1SMichael Neumann if (tmp & 1) {
417f43cf1b1SMichael Neumann tmp &= ~1;
418f43cf1b1SMichael Neumann WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
419f43cf1b1SMichael Neumann }
420f43cf1b1SMichael Neumann for (j = 0; j < rdev->usec_timeout; j++) {
421f43cf1b1SMichael Neumann tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
422f43cf1b1SMichael Neumann if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
423f43cf1b1SMichael Neumann break;
424c4ef309bSzrj udelay(1);
425f43cf1b1SMichael Neumann }
426f43cf1b1SMichael Neumann }
427f43cf1b1SMichael Neumann }
428f43cf1b1SMichael Neumann
429926deccbSFrançois Tigeot if (rdev->family >= CHIP_R600) {
430926deccbSFrançois Tigeot /* unblackout the MC */
431926deccbSFrançois Tigeot if (rdev->family >= CHIP_RV770)
432926deccbSFrançois Tigeot tmp = RREG32(R700_MC_CITF_CNTL);
433926deccbSFrançois Tigeot else
434926deccbSFrançois Tigeot tmp = RREG32(R600_CITF_CNTL);
435926deccbSFrançois Tigeot tmp &= ~R600_BLACKOUT_MASK;
436926deccbSFrançois Tigeot if (rdev->family >= CHIP_RV770)
437926deccbSFrançois Tigeot WREG32(R700_MC_CITF_CNTL, tmp);
438926deccbSFrançois Tigeot else
439926deccbSFrançois Tigeot WREG32(R600_CITF_CNTL, tmp);
440926deccbSFrançois Tigeot /* allow CPU access */
441926deccbSFrançois Tigeot WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
442926deccbSFrançois Tigeot }
443926deccbSFrançois Tigeot
444926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) {
445926deccbSFrançois Tigeot if (save->crtc_enabled[i]) {
446926deccbSFrançois Tigeot tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
447926deccbSFrançois Tigeot tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
448926deccbSFrançois Tigeot WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
449926deccbSFrançois Tigeot /* wait for the next frame */
450926deccbSFrançois Tigeot frame_count = radeon_get_vblank_counter(rdev, i);
451926deccbSFrançois Tigeot for (j = 0; j < rdev->usec_timeout; j++) {
452926deccbSFrançois Tigeot if (radeon_get_vblank_counter(rdev, i) != frame_count)
453926deccbSFrançois Tigeot break;
454c4ef309bSzrj udelay(1);
455926deccbSFrançois Tigeot }
456926deccbSFrançois Tigeot }
457926deccbSFrançois Tigeot }
458926deccbSFrançois Tigeot /* Unlock vga access */
459926deccbSFrançois Tigeot WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
460c4ef309bSzrj mdelay(1);
461926deccbSFrançois Tigeot WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
462926deccbSFrançois Tigeot }
463926deccbSFrançois Tigeot
rv515_mc_program(struct radeon_device * rdev)464926deccbSFrançois Tigeot static void rv515_mc_program(struct radeon_device *rdev)
465926deccbSFrançois Tigeot {
466926deccbSFrançois Tigeot struct rv515_mc_save save;
467926deccbSFrançois Tigeot
468926deccbSFrançois Tigeot /* Stops all mc clients */
469926deccbSFrançois Tigeot rv515_mc_stop(rdev, &save);
470926deccbSFrançois Tigeot
471926deccbSFrançois Tigeot /* Wait for mc idle */
472926deccbSFrançois Tigeot if (rv515_mc_wait_for_idle(rdev))
473926deccbSFrançois Tigeot dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
474926deccbSFrançois Tigeot /* Write VRAM size in case we are limiting it */
475926deccbSFrançois Tigeot WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
476926deccbSFrançois Tigeot /* Program MC, should be a 32bits limited address space */
477926deccbSFrançois Tigeot WREG32_MC(R_000001_MC_FB_LOCATION,
478926deccbSFrançois Tigeot S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
479926deccbSFrançois Tigeot S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
480926deccbSFrançois Tigeot WREG32(R_000134_HDP_FB_LOCATION,
481926deccbSFrançois Tigeot S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
482926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
483926deccbSFrançois Tigeot WREG32_MC(R_000002_MC_AGP_LOCATION,
484926deccbSFrançois Tigeot S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
485926deccbSFrançois Tigeot S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
486926deccbSFrançois Tigeot WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
487926deccbSFrançois Tigeot WREG32_MC(R_000004_MC_AGP_BASE_2,
488926deccbSFrançois Tigeot S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
489926deccbSFrançois Tigeot } else {
490926deccbSFrançois Tigeot WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
491926deccbSFrançois Tigeot WREG32_MC(R_000003_MC_AGP_BASE, 0);
492926deccbSFrançois Tigeot WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
493926deccbSFrançois Tigeot }
494926deccbSFrançois Tigeot
495926deccbSFrançois Tigeot rv515_mc_resume(rdev, &save);
496926deccbSFrançois Tigeot }
497926deccbSFrançois Tigeot
rv515_clock_startup(struct radeon_device * rdev)498926deccbSFrançois Tigeot void rv515_clock_startup(struct radeon_device *rdev)
499926deccbSFrançois Tigeot {
500926deccbSFrançois Tigeot if (radeon_dynclks != -1 && radeon_dynclks)
501926deccbSFrançois Tigeot radeon_atom_set_clock_gating(rdev, 1);
502926deccbSFrançois Tigeot /* We need to force on some of the block */
503926deccbSFrançois Tigeot WREG32_PLL(R_00000F_CP_DYN_CNTL,
504926deccbSFrançois Tigeot RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
505926deccbSFrançois Tigeot WREG32_PLL(R_000011_E2_DYN_CNTL,
506926deccbSFrançois Tigeot RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
507926deccbSFrançois Tigeot WREG32_PLL(R_000013_IDCT_DYN_CNTL,
508926deccbSFrançois Tigeot RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
509926deccbSFrançois Tigeot }
510926deccbSFrançois Tigeot
rv515_startup(struct radeon_device * rdev)511926deccbSFrançois Tigeot static int rv515_startup(struct radeon_device *rdev)
512926deccbSFrançois Tigeot {
513926deccbSFrançois Tigeot int r;
514926deccbSFrançois Tigeot
515926deccbSFrançois Tigeot rv515_mc_program(rdev);
516926deccbSFrançois Tigeot /* Resume clock */
517926deccbSFrançois Tigeot rv515_clock_startup(rdev);
518926deccbSFrançois Tigeot /* Initialize GPU configuration (# pipes, ...) */
519926deccbSFrançois Tigeot rv515_gpu_init(rdev);
520926deccbSFrançois Tigeot /* Initialize GART (initialize after TTM so we can allocate
521926deccbSFrançois Tigeot * memory through TTM but finalize after TTM) */
522926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE) {
523926deccbSFrançois Tigeot r = rv370_pcie_gart_enable(rdev);
524926deccbSFrançois Tigeot if (r)
525926deccbSFrançois Tigeot return r;
526926deccbSFrançois Tigeot }
527926deccbSFrançois Tigeot
528926deccbSFrançois Tigeot /* allocate wb buffer */
529926deccbSFrançois Tigeot r = radeon_wb_init(rdev);
530926deccbSFrançois Tigeot if (r)
531926deccbSFrançois Tigeot return r;
532926deccbSFrançois Tigeot
533926deccbSFrançois Tigeot r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
534926deccbSFrançois Tigeot if (r) {
535926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
536926deccbSFrançois Tigeot return r;
537926deccbSFrançois Tigeot }
538926deccbSFrançois Tigeot
539926deccbSFrançois Tigeot /* Enable IRQ */
540f43cf1b1SMichael Neumann if (!rdev->irq.installed) {
541f43cf1b1SMichael Neumann r = radeon_irq_kms_init(rdev);
542f43cf1b1SMichael Neumann if (r)
543f43cf1b1SMichael Neumann return r;
544f43cf1b1SMichael Neumann }
545f43cf1b1SMichael Neumann
546926deccbSFrançois Tigeot rs600_irq_set(rdev);
547926deccbSFrançois Tigeot rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
548926deccbSFrançois Tigeot /* 1M ring buffer */
549926deccbSFrançois Tigeot r = r100_cp_init(rdev, 1024 * 1024);
550926deccbSFrançois Tigeot if (r) {
551926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
552926deccbSFrançois Tigeot return r;
553926deccbSFrançois Tigeot }
554926deccbSFrançois Tigeot
555926deccbSFrançois Tigeot r = radeon_ib_pool_init(rdev);
556926deccbSFrançois Tigeot if (r) {
557926deccbSFrançois Tigeot dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
558926deccbSFrançois Tigeot return r;
559926deccbSFrançois Tigeot }
560926deccbSFrançois Tigeot
561926deccbSFrançois Tigeot return 0;
562926deccbSFrançois Tigeot }
563926deccbSFrançois Tigeot
rv515_resume(struct radeon_device * rdev)564926deccbSFrançois Tigeot int rv515_resume(struct radeon_device *rdev)
565926deccbSFrançois Tigeot {
566926deccbSFrançois Tigeot int r;
567926deccbSFrançois Tigeot
568926deccbSFrançois Tigeot /* Make sur GART are not working */
569926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE)
570926deccbSFrançois Tigeot rv370_pcie_gart_disable(rdev);
571926deccbSFrançois Tigeot /* Resume clock before doing reset */
572926deccbSFrançois Tigeot rv515_clock_startup(rdev);
573926deccbSFrançois Tigeot /* Reset gpu before posting otherwise ATOM will enter infinite loop */
574926deccbSFrançois Tigeot if (radeon_asic_reset(rdev)) {
575926deccbSFrançois Tigeot dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
576926deccbSFrançois Tigeot RREG32(R_000E40_RBBM_STATUS),
577926deccbSFrançois Tigeot RREG32(R_0007C0_CP_STAT));
578926deccbSFrançois Tigeot }
579926deccbSFrançois Tigeot /* post */
580926deccbSFrançois Tigeot atom_asic_init(rdev->mode_info.atom_context);
581926deccbSFrançois Tigeot /* Resume clock after posting */
582926deccbSFrançois Tigeot rv515_clock_startup(rdev);
583926deccbSFrançois Tigeot /* Initialize surface registers */
584926deccbSFrançois Tigeot radeon_surface_init(rdev);
585926deccbSFrançois Tigeot
586926deccbSFrançois Tigeot rdev->accel_working = true;
587926deccbSFrançois Tigeot r = rv515_startup(rdev);
588926deccbSFrançois Tigeot if (r) {
589926deccbSFrançois Tigeot rdev->accel_working = false;
590926deccbSFrançois Tigeot }
591926deccbSFrançois Tigeot return r;
592926deccbSFrançois Tigeot }
593926deccbSFrançois Tigeot
rv515_suspend(struct radeon_device * rdev)594926deccbSFrançois Tigeot int rv515_suspend(struct radeon_device *rdev)
595926deccbSFrançois Tigeot {
596c6f73aabSFrançois Tigeot radeon_pm_suspend(rdev);
597926deccbSFrançois Tigeot r100_cp_disable(rdev);
598926deccbSFrançois Tigeot radeon_wb_disable(rdev);
599926deccbSFrançois Tigeot rs600_irq_disable(rdev);
600926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_PCIE)
601926deccbSFrançois Tigeot rv370_pcie_gart_disable(rdev);
602926deccbSFrançois Tigeot return 0;
603926deccbSFrançois Tigeot }
604926deccbSFrançois Tigeot
rv515_set_safe_registers(struct radeon_device * rdev)605926deccbSFrançois Tigeot void rv515_set_safe_registers(struct radeon_device *rdev)
606926deccbSFrançois Tigeot {
607926deccbSFrançois Tigeot rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
608c4ef309bSzrj rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
609926deccbSFrançois Tigeot }
610926deccbSFrançois Tigeot
rv515_fini(struct radeon_device * rdev)611926deccbSFrançois Tigeot void rv515_fini(struct radeon_device *rdev)
612926deccbSFrançois Tigeot {
613c6f73aabSFrançois Tigeot radeon_pm_fini(rdev);
614926deccbSFrançois Tigeot r100_cp_fini(rdev);
615926deccbSFrançois Tigeot radeon_wb_fini(rdev);
616926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev);
617926deccbSFrançois Tigeot radeon_gem_fini(rdev);
618926deccbSFrançois Tigeot rv370_pcie_gart_fini(rdev);
619926deccbSFrançois Tigeot radeon_agp_fini(rdev);
620926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev);
621926deccbSFrançois Tigeot radeon_fence_driver_fini(rdev);
622926deccbSFrançois Tigeot radeon_bo_fini(rdev);
623926deccbSFrançois Tigeot radeon_atombios_fini(rdev);
624c4ef309bSzrj kfree(rdev->bios);
625926deccbSFrançois Tigeot rdev->bios = NULL;
626926deccbSFrançois Tigeot }
627926deccbSFrançois Tigeot
rv515_init(struct radeon_device * rdev)628926deccbSFrançois Tigeot int rv515_init(struct radeon_device *rdev)
629926deccbSFrançois Tigeot {
630926deccbSFrançois Tigeot int r;
631926deccbSFrançois Tigeot
632926deccbSFrançois Tigeot /* Initialize scratch registers */
633926deccbSFrançois Tigeot radeon_scratch_init(rdev);
634926deccbSFrançois Tigeot /* Initialize surface registers */
635926deccbSFrançois Tigeot radeon_surface_init(rdev);
636926deccbSFrançois Tigeot /* TODO: disable VGA need to use VGA request */
637926deccbSFrançois Tigeot /* restore some register to sane defaults */
638926deccbSFrançois Tigeot r100_restore_sanity(rdev);
639926deccbSFrançois Tigeot /* BIOS*/
640926deccbSFrançois Tigeot if (!radeon_get_bios(rdev)) {
641926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev))
642926deccbSFrançois Tigeot return -EINVAL;
643926deccbSFrançois Tigeot }
644926deccbSFrançois Tigeot if (rdev->is_atom_bios) {
645926deccbSFrançois Tigeot r = radeon_atombios_init(rdev);
646926deccbSFrançois Tigeot if (r)
647926deccbSFrançois Tigeot return r;
648926deccbSFrançois Tigeot } else {
649926deccbSFrançois Tigeot dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
650926deccbSFrançois Tigeot return -EINVAL;
651926deccbSFrançois Tigeot }
652926deccbSFrançois Tigeot /* Reset gpu before posting otherwise ATOM will enter infinite loop */
653926deccbSFrançois Tigeot if (radeon_asic_reset(rdev)) {
654926deccbSFrançois Tigeot dev_warn(rdev->dev,
655926deccbSFrançois Tigeot "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
656926deccbSFrançois Tigeot RREG32(R_000E40_RBBM_STATUS),
657926deccbSFrançois Tigeot RREG32(R_0007C0_CP_STAT));
658926deccbSFrançois Tigeot }
659926deccbSFrançois Tigeot /* check if cards are posted or not */
660926deccbSFrançois Tigeot if (radeon_boot_test_post_card(rdev) == false)
661926deccbSFrançois Tigeot return -EINVAL;
662926deccbSFrançois Tigeot /* Initialize clocks */
663926deccbSFrançois Tigeot radeon_get_clock_info(rdev->ddev);
664926deccbSFrançois Tigeot /* initialize AGP */
665926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
666926deccbSFrançois Tigeot r = radeon_agp_init(rdev);
667926deccbSFrançois Tigeot if (r) {
668926deccbSFrançois Tigeot radeon_agp_disable(rdev);
669926deccbSFrançois Tigeot }
670926deccbSFrançois Tigeot }
671926deccbSFrançois Tigeot /* initialize memory controller */
672926deccbSFrançois Tigeot rv515_mc_init(rdev);
673926deccbSFrançois Tigeot rv515_debugfs(rdev);
674926deccbSFrançois Tigeot /* Fence driver */
675926deccbSFrançois Tigeot r = radeon_fence_driver_init(rdev);
676926deccbSFrançois Tigeot if (r)
677926deccbSFrançois Tigeot return r;
678926deccbSFrançois Tigeot /* Memory manager */
679926deccbSFrançois Tigeot r = radeon_bo_init(rdev);
680926deccbSFrançois Tigeot if (r)
681926deccbSFrançois Tigeot return r;
682926deccbSFrançois Tigeot r = rv370_pcie_gart_init(rdev);
683926deccbSFrançois Tigeot if (r)
684926deccbSFrançois Tigeot return r;
685926deccbSFrançois Tigeot rv515_set_safe_registers(rdev);
686926deccbSFrançois Tigeot
687c6f73aabSFrançois Tigeot /* Initialize power management */
688c6f73aabSFrançois Tigeot radeon_pm_init(rdev);
689c6f73aabSFrançois Tigeot
690926deccbSFrançois Tigeot rdev->accel_working = true;
691926deccbSFrançois Tigeot r = rv515_startup(rdev);
692926deccbSFrançois Tigeot if (r) {
693926deccbSFrançois Tigeot /* Somethings want wront with the accel init stop accel */
694926deccbSFrançois Tigeot dev_err(rdev->dev, "Disabling GPU acceleration\n");
695926deccbSFrançois Tigeot r100_cp_fini(rdev);
696926deccbSFrançois Tigeot radeon_wb_fini(rdev);
697926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev);
698926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev);
699926deccbSFrançois Tigeot rv370_pcie_gart_fini(rdev);
700926deccbSFrançois Tigeot radeon_agp_fini(rdev);
701926deccbSFrançois Tigeot rdev->accel_working = false;
702926deccbSFrançois Tigeot }
703926deccbSFrançois Tigeot return 0;
704926deccbSFrançois Tigeot }
705926deccbSFrançois Tigeot
atom_rv515_force_tv_scaler(struct radeon_device * rdev,struct radeon_crtc * crtc)706926deccbSFrançois Tigeot void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
707926deccbSFrançois Tigeot {
708926deccbSFrançois Tigeot int index_reg = 0x6578 + crtc->crtc_offset;
709926deccbSFrançois Tigeot int data_reg = 0x657c + crtc->crtc_offset;
710926deccbSFrançois Tigeot
711926deccbSFrançois Tigeot WREG32(0x659C + crtc->crtc_offset, 0x0);
712926deccbSFrançois Tigeot WREG32(0x6594 + crtc->crtc_offset, 0x705);
713926deccbSFrançois Tigeot WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
714926deccbSFrançois Tigeot WREG32(0x65D8 + crtc->crtc_offset, 0x0);
715926deccbSFrançois Tigeot WREG32(0x65B0 + crtc->crtc_offset, 0x0);
716926deccbSFrançois Tigeot WREG32(0x65C0 + crtc->crtc_offset, 0x0);
717926deccbSFrançois Tigeot WREG32(0x65D4 + crtc->crtc_offset, 0x0);
718926deccbSFrançois Tigeot WREG32(index_reg, 0x0);
719926deccbSFrançois Tigeot WREG32(data_reg, 0x841880A8);
720926deccbSFrançois Tigeot WREG32(index_reg, 0x1);
721926deccbSFrançois Tigeot WREG32(data_reg, 0x84208680);
722926deccbSFrançois Tigeot WREG32(index_reg, 0x2);
723926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF880B0);
724926deccbSFrançois Tigeot WREG32(index_reg, 0x100);
725926deccbSFrançois Tigeot WREG32(data_reg, 0x83D88088);
726926deccbSFrançois Tigeot WREG32(index_reg, 0x101);
727926deccbSFrançois Tigeot WREG32(data_reg, 0x84608680);
728926deccbSFrançois Tigeot WREG32(index_reg, 0x102);
729926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF080D0);
730926deccbSFrançois Tigeot WREG32(index_reg, 0x200);
731926deccbSFrançois Tigeot WREG32(data_reg, 0x83988068);
732926deccbSFrançois Tigeot WREG32(index_reg, 0x201);
733926deccbSFrançois Tigeot WREG32(data_reg, 0x84A08680);
734926deccbSFrançois Tigeot WREG32(index_reg, 0x202);
735926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF080F8);
736926deccbSFrançois Tigeot WREG32(index_reg, 0x300);
737926deccbSFrançois Tigeot WREG32(data_reg, 0x83588058);
738926deccbSFrançois Tigeot WREG32(index_reg, 0x301);
739926deccbSFrançois Tigeot WREG32(data_reg, 0x84E08660);
740926deccbSFrançois Tigeot WREG32(index_reg, 0x302);
741926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF88120);
742926deccbSFrançois Tigeot WREG32(index_reg, 0x400);
743926deccbSFrançois Tigeot WREG32(data_reg, 0x83188040);
744926deccbSFrançois Tigeot WREG32(index_reg, 0x401);
745926deccbSFrançois Tigeot WREG32(data_reg, 0x85008660);
746926deccbSFrançois Tigeot WREG32(index_reg, 0x402);
747926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF88150);
748926deccbSFrançois Tigeot WREG32(index_reg, 0x500);
749926deccbSFrançois Tigeot WREG32(data_reg, 0x82D88030);
750926deccbSFrançois Tigeot WREG32(index_reg, 0x501);
751926deccbSFrançois Tigeot WREG32(data_reg, 0x85408640);
752926deccbSFrançois Tigeot WREG32(index_reg, 0x502);
753926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF88180);
754926deccbSFrançois Tigeot WREG32(index_reg, 0x600);
755926deccbSFrançois Tigeot WREG32(data_reg, 0x82A08018);
756926deccbSFrançois Tigeot WREG32(index_reg, 0x601);
757926deccbSFrançois Tigeot WREG32(data_reg, 0x85808620);
758926deccbSFrançois Tigeot WREG32(index_reg, 0x602);
759926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF081B8);
760926deccbSFrançois Tigeot WREG32(index_reg, 0x700);
761926deccbSFrançois Tigeot WREG32(data_reg, 0x82608010);
762926deccbSFrançois Tigeot WREG32(index_reg, 0x701);
763926deccbSFrançois Tigeot WREG32(data_reg, 0x85A08600);
764926deccbSFrançois Tigeot WREG32(index_reg, 0x702);
765926deccbSFrançois Tigeot WREG32(data_reg, 0x800081F0);
766926deccbSFrançois Tigeot WREG32(index_reg, 0x800);
767926deccbSFrançois Tigeot WREG32(data_reg, 0x8228BFF8);
768926deccbSFrançois Tigeot WREG32(index_reg, 0x801);
769926deccbSFrançois Tigeot WREG32(data_reg, 0x85E085E0);
770926deccbSFrançois Tigeot WREG32(index_reg, 0x802);
771926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF88228);
772926deccbSFrançois Tigeot WREG32(index_reg, 0x10000);
773926deccbSFrançois Tigeot WREG32(data_reg, 0x82A8BF00);
774926deccbSFrançois Tigeot WREG32(index_reg, 0x10001);
775926deccbSFrançois Tigeot WREG32(data_reg, 0x82A08CC0);
776926deccbSFrançois Tigeot WREG32(index_reg, 0x10002);
777926deccbSFrançois Tigeot WREG32(data_reg, 0x8008BEF8);
778926deccbSFrançois Tigeot WREG32(index_reg, 0x10100);
779926deccbSFrançois Tigeot WREG32(data_reg, 0x81F0BF28);
780926deccbSFrançois Tigeot WREG32(index_reg, 0x10101);
781926deccbSFrançois Tigeot WREG32(data_reg, 0x83608CA0);
782926deccbSFrançois Tigeot WREG32(index_reg, 0x10102);
783926deccbSFrançois Tigeot WREG32(data_reg, 0x8018BED0);
784926deccbSFrançois Tigeot WREG32(index_reg, 0x10200);
785926deccbSFrançois Tigeot WREG32(data_reg, 0x8148BF38);
786926deccbSFrançois Tigeot WREG32(index_reg, 0x10201);
787926deccbSFrançois Tigeot WREG32(data_reg, 0x84408C80);
788926deccbSFrançois Tigeot WREG32(index_reg, 0x10202);
789926deccbSFrançois Tigeot WREG32(data_reg, 0x8008BEB8);
790926deccbSFrançois Tigeot WREG32(index_reg, 0x10300);
791926deccbSFrançois Tigeot WREG32(data_reg, 0x80B0BF78);
792926deccbSFrançois Tigeot WREG32(index_reg, 0x10301);
793926deccbSFrançois Tigeot WREG32(data_reg, 0x85008C20);
794926deccbSFrançois Tigeot WREG32(index_reg, 0x10302);
795926deccbSFrançois Tigeot WREG32(data_reg, 0x8020BEA0);
796926deccbSFrançois Tigeot WREG32(index_reg, 0x10400);
797926deccbSFrançois Tigeot WREG32(data_reg, 0x8028BF90);
798926deccbSFrançois Tigeot WREG32(index_reg, 0x10401);
799926deccbSFrançois Tigeot WREG32(data_reg, 0x85E08BC0);
800926deccbSFrançois Tigeot WREG32(index_reg, 0x10402);
801926deccbSFrançois Tigeot WREG32(data_reg, 0x8018BE90);
802926deccbSFrançois Tigeot WREG32(index_reg, 0x10500);
803926deccbSFrançois Tigeot WREG32(data_reg, 0xBFB8BFB0);
804926deccbSFrançois Tigeot WREG32(index_reg, 0x10501);
805926deccbSFrançois Tigeot WREG32(data_reg, 0x86C08B40);
806926deccbSFrançois Tigeot WREG32(index_reg, 0x10502);
807926deccbSFrançois Tigeot WREG32(data_reg, 0x8010BE90);
808926deccbSFrançois Tigeot WREG32(index_reg, 0x10600);
809926deccbSFrançois Tigeot WREG32(data_reg, 0xBF58BFC8);
810926deccbSFrançois Tigeot WREG32(index_reg, 0x10601);
811926deccbSFrançois Tigeot WREG32(data_reg, 0x87A08AA0);
812926deccbSFrançois Tigeot WREG32(index_reg, 0x10602);
813926deccbSFrançois Tigeot WREG32(data_reg, 0x8010BE98);
814926deccbSFrançois Tigeot WREG32(index_reg, 0x10700);
815926deccbSFrançois Tigeot WREG32(data_reg, 0xBF10BFF0);
816926deccbSFrançois Tigeot WREG32(index_reg, 0x10701);
817926deccbSFrançois Tigeot WREG32(data_reg, 0x886089E0);
818926deccbSFrançois Tigeot WREG32(index_reg, 0x10702);
819926deccbSFrançois Tigeot WREG32(data_reg, 0x8018BEB0);
820926deccbSFrançois Tigeot WREG32(index_reg, 0x10800);
821926deccbSFrançois Tigeot WREG32(data_reg, 0xBED8BFE8);
822926deccbSFrançois Tigeot WREG32(index_reg, 0x10801);
823926deccbSFrançois Tigeot WREG32(data_reg, 0x89408940);
824926deccbSFrançois Tigeot WREG32(index_reg, 0x10802);
825926deccbSFrançois Tigeot WREG32(data_reg, 0xBFE8BED8);
826926deccbSFrançois Tigeot WREG32(index_reg, 0x20000);
827926deccbSFrançois Tigeot WREG32(data_reg, 0x80008000);
828926deccbSFrançois Tigeot WREG32(index_reg, 0x20001);
829926deccbSFrançois Tigeot WREG32(data_reg, 0x90008000);
830926deccbSFrançois Tigeot WREG32(index_reg, 0x20002);
831926deccbSFrançois Tigeot WREG32(data_reg, 0x80008000);
832926deccbSFrançois Tigeot WREG32(index_reg, 0x20003);
833926deccbSFrançois Tigeot WREG32(data_reg, 0x80008000);
834926deccbSFrançois Tigeot WREG32(index_reg, 0x20100);
835926deccbSFrançois Tigeot WREG32(data_reg, 0x80108000);
836926deccbSFrançois Tigeot WREG32(index_reg, 0x20101);
837926deccbSFrançois Tigeot WREG32(data_reg, 0x8FE0BF70);
838926deccbSFrançois Tigeot WREG32(index_reg, 0x20102);
839926deccbSFrançois Tigeot WREG32(data_reg, 0xBFE880C0);
840926deccbSFrançois Tigeot WREG32(index_reg, 0x20103);
841926deccbSFrançois Tigeot WREG32(data_reg, 0x80008000);
842926deccbSFrançois Tigeot WREG32(index_reg, 0x20200);
843926deccbSFrançois Tigeot WREG32(data_reg, 0x8018BFF8);
844926deccbSFrançois Tigeot WREG32(index_reg, 0x20201);
845926deccbSFrançois Tigeot WREG32(data_reg, 0x8F80BF08);
846926deccbSFrançois Tigeot WREG32(index_reg, 0x20202);
847926deccbSFrançois Tigeot WREG32(data_reg, 0xBFD081A0);
848926deccbSFrançois Tigeot WREG32(index_reg, 0x20203);
849926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF88000);
850926deccbSFrançois Tigeot WREG32(index_reg, 0x20300);
851926deccbSFrançois Tigeot WREG32(data_reg, 0x80188000);
852926deccbSFrançois Tigeot WREG32(index_reg, 0x20301);
853926deccbSFrançois Tigeot WREG32(data_reg, 0x8EE0BEC0);
854926deccbSFrançois Tigeot WREG32(index_reg, 0x20302);
855926deccbSFrançois Tigeot WREG32(data_reg, 0xBFB082A0);
856926deccbSFrançois Tigeot WREG32(index_reg, 0x20303);
857926deccbSFrançois Tigeot WREG32(data_reg, 0x80008000);
858926deccbSFrançois Tigeot WREG32(index_reg, 0x20400);
859926deccbSFrançois Tigeot WREG32(data_reg, 0x80188000);
860926deccbSFrançois Tigeot WREG32(index_reg, 0x20401);
861926deccbSFrançois Tigeot WREG32(data_reg, 0x8E00BEA0);
862926deccbSFrançois Tigeot WREG32(index_reg, 0x20402);
863926deccbSFrançois Tigeot WREG32(data_reg, 0xBF8883C0);
864926deccbSFrançois Tigeot WREG32(index_reg, 0x20403);
865926deccbSFrançois Tigeot WREG32(data_reg, 0x80008000);
866926deccbSFrançois Tigeot WREG32(index_reg, 0x20500);
867926deccbSFrançois Tigeot WREG32(data_reg, 0x80188000);
868926deccbSFrançois Tigeot WREG32(index_reg, 0x20501);
869926deccbSFrançois Tigeot WREG32(data_reg, 0x8D00BE90);
870926deccbSFrançois Tigeot WREG32(index_reg, 0x20502);
871926deccbSFrançois Tigeot WREG32(data_reg, 0xBF588500);
872926deccbSFrançois Tigeot WREG32(index_reg, 0x20503);
873926deccbSFrançois Tigeot WREG32(data_reg, 0x80008008);
874926deccbSFrançois Tigeot WREG32(index_reg, 0x20600);
875926deccbSFrançois Tigeot WREG32(data_reg, 0x80188000);
876926deccbSFrançois Tigeot WREG32(index_reg, 0x20601);
877926deccbSFrançois Tigeot WREG32(data_reg, 0x8BC0BE98);
878926deccbSFrançois Tigeot WREG32(index_reg, 0x20602);
879926deccbSFrançois Tigeot WREG32(data_reg, 0xBF308660);
880926deccbSFrançois Tigeot WREG32(index_reg, 0x20603);
881926deccbSFrançois Tigeot WREG32(data_reg, 0x80008008);
882926deccbSFrançois Tigeot WREG32(index_reg, 0x20700);
883926deccbSFrançois Tigeot WREG32(data_reg, 0x80108000);
884926deccbSFrançois Tigeot WREG32(index_reg, 0x20701);
885926deccbSFrançois Tigeot WREG32(data_reg, 0x8A80BEB0);
886926deccbSFrançois Tigeot WREG32(index_reg, 0x20702);
887926deccbSFrançois Tigeot WREG32(data_reg, 0xBF0087C0);
888926deccbSFrançois Tigeot WREG32(index_reg, 0x20703);
889926deccbSFrançois Tigeot WREG32(data_reg, 0x80008008);
890926deccbSFrançois Tigeot WREG32(index_reg, 0x20800);
891926deccbSFrançois Tigeot WREG32(data_reg, 0x80108000);
892926deccbSFrançois Tigeot WREG32(index_reg, 0x20801);
893926deccbSFrançois Tigeot WREG32(data_reg, 0x8920BED0);
894926deccbSFrançois Tigeot WREG32(index_reg, 0x20802);
895926deccbSFrançois Tigeot WREG32(data_reg, 0xBED08920);
896926deccbSFrançois Tigeot WREG32(index_reg, 0x20803);
897926deccbSFrançois Tigeot WREG32(data_reg, 0x80008010);
898926deccbSFrançois Tigeot WREG32(index_reg, 0x30000);
899926deccbSFrançois Tigeot WREG32(data_reg, 0x90008000);
900926deccbSFrançois Tigeot WREG32(index_reg, 0x30001);
901926deccbSFrançois Tigeot WREG32(data_reg, 0x80008000);
902926deccbSFrançois Tigeot WREG32(index_reg, 0x30100);
903926deccbSFrançois Tigeot WREG32(data_reg, 0x8FE0BF90);
904926deccbSFrançois Tigeot WREG32(index_reg, 0x30101);
905926deccbSFrançois Tigeot WREG32(data_reg, 0xBFF880A0);
906926deccbSFrançois Tigeot WREG32(index_reg, 0x30200);
907926deccbSFrançois Tigeot WREG32(data_reg, 0x8F60BF40);
908926deccbSFrançois Tigeot WREG32(index_reg, 0x30201);
909926deccbSFrançois Tigeot WREG32(data_reg, 0xBFE88180);
910926deccbSFrançois Tigeot WREG32(index_reg, 0x30300);
911926deccbSFrançois Tigeot WREG32(data_reg, 0x8EC0BF00);
912926deccbSFrançois Tigeot WREG32(index_reg, 0x30301);
913926deccbSFrançois Tigeot WREG32(data_reg, 0xBFC88280);
914926deccbSFrançois Tigeot WREG32(index_reg, 0x30400);
915926deccbSFrançois Tigeot WREG32(data_reg, 0x8DE0BEE0);
916926deccbSFrançois Tigeot WREG32(index_reg, 0x30401);
917926deccbSFrançois Tigeot WREG32(data_reg, 0xBFA083A0);
918926deccbSFrançois Tigeot WREG32(index_reg, 0x30500);
919926deccbSFrançois Tigeot WREG32(data_reg, 0x8CE0BED0);
920926deccbSFrançois Tigeot WREG32(index_reg, 0x30501);
921926deccbSFrançois Tigeot WREG32(data_reg, 0xBF7884E0);
922926deccbSFrançois Tigeot WREG32(index_reg, 0x30600);
923926deccbSFrançois Tigeot WREG32(data_reg, 0x8BA0BED8);
924926deccbSFrançois Tigeot WREG32(index_reg, 0x30601);
925926deccbSFrançois Tigeot WREG32(data_reg, 0xBF508640);
926926deccbSFrançois Tigeot WREG32(index_reg, 0x30700);
927926deccbSFrançois Tigeot WREG32(data_reg, 0x8A60BEE8);
928926deccbSFrançois Tigeot WREG32(index_reg, 0x30701);
929926deccbSFrançois Tigeot WREG32(data_reg, 0xBF2087A0);
930926deccbSFrançois Tigeot WREG32(index_reg, 0x30800);
931926deccbSFrançois Tigeot WREG32(data_reg, 0x8900BF00);
932926deccbSFrançois Tigeot WREG32(index_reg, 0x30801);
933926deccbSFrançois Tigeot WREG32(data_reg, 0xBF008900);
934926deccbSFrançois Tigeot }
935926deccbSFrançois Tigeot
936926deccbSFrançois Tigeot struct rv515_watermark {
937926deccbSFrançois Tigeot u32 lb_request_fifo_depth;
938926deccbSFrançois Tigeot fixed20_12 num_line_pair;
939926deccbSFrançois Tigeot fixed20_12 estimated_width;
940926deccbSFrançois Tigeot fixed20_12 worst_case_latency;
941926deccbSFrançois Tigeot fixed20_12 consumption_rate;
942926deccbSFrançois Tigeot fixed20_12 active_time;
943926deccbSFrançois Tigeot fixed20_12 dbpp;
944926deccbSFrançois Tigeot fixed20_12 priority_mark_max;
945926deccbSFrançois Tigeot fixed20_12 priority_mark;
946926deccbSFrançois Tigeot fixed20_12 sclk;
947926deccbSFrançois Tigeot };
948926deccbSFrançois Tigeot
rv515_crtc_bandwidth_compute(struct radeon_device * rdev,struct radeon_crtc * crtc,struct rv515_watermark * wm,bool low)949926deccbSFrançois Tigeot static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
950926deccbSFrançois Tigeot struct radeon_crtc *crtc,
95157e252bfSMichael Neumann struct rv515_watermark *wm,
95257e252bfSMichael Neumann bool low)
953926deccbSFrançois Tigeot {
954926deccbSFrançois Tigeot struct drm_display_mode *mode = &crtc->base.mode;
955926deccbSFrançois Tigeot fixed20_12 a, b, c;
956926deccbSFrançois Tigeot fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
957926deccbSFrançois Tigeot fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
95857e252bfSMichael Neumann fixed20_12 sclk;
95957e252bfSMichael Neumann u32 selected_sclk;
960926deccbSFrançois Tigeot
961926deccbSFrançois Tigeot if (!crtc->base.enabled) {
962926deccbSFrançois Tigeot /* FIXME: wouldn't it better to set priority mark to maximum */
963926deccbSFrançois Tigeot wm->lb_request_fifo_depth = 4;
964926deccbSFrançois Tigeot return;
965926deccbSFrançois Tigeot }
966926deccbSFrançois Tigeot
96757e252bfSMichael Neumann /* rv6xx, rv7xx */
96857e252bfSMichael Neumann if ((rdev->family >= CHIP_RV610) &&
96957e252bfSMichael Neumann (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
97057e252bfSMichael Neumann selected_sclk = radeon_dpm_get_sclk(rdev, low);
97157e252bfSMichael Neumann else
97257e252bfSMichael Neumann selected_sclk = rdev->pm.current_sclk;
97357e252bfSMichael Neumann
97457e252bfSMichael Neumann /* sclk in Mhz */
97557e252bfSMichael Neumann a.full = dfixed_const(100);
97657e252bfSMichael Neumann sclk.full = dfixed_const(selected_sclk);
97757e252bfSMichael Neumann sclk.full = dfixed_div(sclk, a);
97857e252bfSMichael Neumann
979926deccbSFrançois Tigeot if (crtc->vsc.full > dfixed_const(2))
980926deccbSFrançois Tigeot wm->num_line_pair.full = dfixed_const(2);
981926deccbSFrançois Tigeot else
982926deccbSFrançois Tigeot wm->num_line_pair.full = dfixed_const(1);
983926deccbSFrançois Tigeot
984926deccbSFrançois Tigeot b.full = dfixed_const(mode->crtc_hdisplay);
985926deccbSFrançois Tigeot c.full = dfixed_const(256);
986926deccbSFrançois Tigeot a.full = dfixed_div(b, c);
987926deccbSFrançois Tigeot request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
988926deccbSFrançois Tigeot request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
989926deccbSFrançois Tigeot if (a.full < dfixed_const(4)) {
990926deccbSFrançois Tigeot wm->lb_request_fifo_depth = 4;
991926deccbSFrançois Tigeot } else {
992926deccbSFrançois Tigeot wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
993926deccbSFrançois Tigeot }
994926deccbSFrançois Tigeot
995926deccbSFrançois Tigeot /* Determine consumption rate
996926deccbSFrançois Tigeot * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
997926deccbSFrançois Tigeot * vtaps = number of vertical taps,
998926deccbSFrançois Tigeot * vsc = vertical scaling ratio, defined as source/destination
999926deccbSFrançois Tigeot * hsc = horizontal scaling ration, defined as source/destination
1000926deccbSFrançois Tigeot */
1001926deccbSFrançois Tigeot a.full = dfixed_const(mode->clock);
1002926deccbSFrançois Tigeot b.full = dfixed_const(1000);
1003926deccbSFrançois Tigeot a.full = dfixed_div(a, b);
1004926deccbSFrançois Tigeot pclk.full = dfixed_div(b, a);
1005926deccbSFrançois Tigeot if (crtc->rmx_type != RMX_OFF) {
1006926deccbSFrançois Tigeot b.full = dfixed_const(2);
1007926deccbSFrançois Tigeot if (crtc->vsc.full > b.full)
1008926deccbSFrançois Tigeot b.full = crtc->vsc.full;
1009926deccbSFrançois Tigeot b.full = dfixed_mul(b, crtc->hsc);
1010926deccbSFrançois Tigeot c.full = dfixed_const(2);
1011926deccbSFrançois Tigeot b.full = dfixed_div(b, c);
1012926deccbSFrançois Tigeot consumption_time.full = dfixed_div(pclk, b);
1013926deccbSFrançois Tigeot } else {
1014926deccbSFrançois Tigeot consumption_time.full = pclk.full;
1015926deccbSFrançois Tigeot }
1016926deccbSFrançois Tigeot a.full = dfixed_const(1);
1017926deccbSFrançois Tigeot wm->consumption_rate.full = dfixed_div(a, consumption_time);
1018926deccbSFrançois Tigeot
1019926deccbSFrançois Tigeot
1020926deccbSFrançois Tigeot /* Determine line time
1021926deccbSFrançois Tigeot * LineTime = total time for one line of displayhtotal
1022926deccbSFrançois Tigeot * LineTime = total number of horizontal pixels
1023926deccbSFrançois Tigeot * pclk = pixel clock period(ns)
1024926deccbSFrançois Tigeot */
1025926deccbSFrançois Tigeot a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1026926deccbSFrançois Tigeot line_time.full = dfixed_mul(a, pclk);
1027926deccbSFrançois Tigeot
1028926deccbSFrançois Tigeot /* Determine active time
1029926deccbSFrançois Tigeot * ActiveTime = time of active region of display within one line,
1030926deccbSFrançois Tigeot * hactive = total number of horizontal active pixels
1031926deccbSFrançois Tigeot * htotal = total number of horizontal pixels
1032926deccbSFrançois Tigeot */
1033926deccbSFrançois Tigeot a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1034926deccbSFrançois Tigeot b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1035926deccbSFrançois Tigeot wm->active_time.full = dfixed_mul(line_time, b);
1036926deccbSFrançois Tigeot wm->active_time.full = dfixed_div(wm->active_time, a);
1037926deccbSFrançois Tigeot
1038926deccbSFrançois Tigeot /* Determine chunk time
1039926deccbSFrançois Tigeot * ChunkTime = the time it takes the DCP to send one chunk of data
1040926deccbSFrançois Tigeot * to the LB which consists of pipeline delay and inter chunk gap
1041926deccbSFrançois Tigeot * sclk = system clock(Mhz)
1042926deccbSFrançois Tigeot */
1043926deccbSFrançois Tigeot a.full = dfixed_const(600 * 1000);
104457e252bfSMichael Neumann chunk_time.full = dfixed_div(a, sclk);
1045926deccbSFrançois Tigeot read_delay_latency.full = dfixed_const(1000);
1046926deccbSFrançois Tigeot
1047926deccbSFrançois Tigeot /* Determine the worst case latency
1048926deccbSFrançois Tigeot * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1049926deccbSFrançois Tigeot * WorstCaseLatency = worst case time from urgent to when the MC starts
1050926deccbSFrançois Tigeot * to return data
1051926deccbSFrançois Tigeot * READ_DELAY_IDLE_MAX = constant of 1us
1052926deccbSFrançois Tigeot * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1053926deccbSFrançois Tigeot * which consists of pipeline delay and inter chunk gap
1054926deccbSFrançois Tigeot */
1055926deccbSFrançois Tigeot if (dfixed_trunc(wm->num_line_pair) > 1) {
1056926deccbSFrançois Tigeot a.full = dfixed_const(3);
1057926deccbSFrançois Tigeot wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1058926deccbSFrançois Tigeot wm->worst_case_latency.full += read_delay_latency.full;
1059926deccbSFrançois Tigeot } else {
1060926deccbSFrançois Tigeot wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1061926deccbSFrançois Tigeot }
1062926deccbSFrançois Tigeot
1063926deccbSFrançois Tigeot /* Determine the tolerable latency
1064926deccbSFrançois Tigeot * TolerableLatency = Any given request has only 1 line time
1065926deccbSFrançois Tigeot * for the data to be returned
1066926deccbSFrançois Tigeot * LBRequestFifoDepth = Number of chunk requests the LB can
1067926deccbSFrançois Tigeot * put into the request FIFO for a display
1068926deccbSFrançois Tigeot * LineTime = total time for one line of display
1069926deccbSFrançois Tigeot * ChunkTime = the time it takes the DCP to send one chunk
1070926deccbSFrançois Tigeot * of data to the LB which consists of
1071926deccbSFrançois Tigeot * pipeline delay and inter chunk gap
1072926deccbSFrançois Tigeot */
1073926deccbSFrançois Tigeot if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1074926deccbSFrançois Tigeot tolerable_latency.full = line_time.full;
1075926deccbSFrançois Tigeot } else {
1076926deccbSFrançois Tigeot tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1077926deccbSFrançois Tigeot tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1078926deccbSFrançois Tigeot tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1079926deccbSFrançois Tigeot tolerable_latency.full = line_time.full - tolerable_latency.full;
1080926deccbSFrançois Tigeot }
1081926deccbSFrançois Tigeot /* We assume worst case 32bits (4 bytes) */
1082926deccbSFrançois Tigeot wm->dbpp.full = dfixed_const(2 * 16);
1083926deccbSFrançois Tigeot
1084926deccbSFrançois Tigeot /* Determine the maximum priority mark
1085926deccbSFrançois Tigeot * width = viewport width in pixels
1086926deccbSFrançois Tigeot */
1087926deccbSFrançois Tigeot a.full = dfixed_const(16);
1088926deccbSFrançois Tigeot wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1089926deccbSFrançois Tigeot wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1090926deccbSFrançois Tigeot wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1091926deccbSFrançois Tigeot
1092926deccbSFrançois Tigeot /* Determine estimated width */
1093926deccbSFrançois Tigeot estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1094926deccbSFrançois Tigeot estimated_width.full = dfixed_div(estimated_width, consumption_time);
1095926deccbSFrançois Tigeot if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1096926deccbSFrançois Tigeot wm->priority_mark.full = wm->priority_mark_max.full;
1097926deccbSFrançois Tigeot } else {
1098926deccbSFrançois Tigeot a.full = dfixed_const(16);
1099926deccbSFrançois Tigeot wm->priority_mark.full = dfixed_div(estimated_width, a);
1100926deccbSFrançois Tigeot wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1101926deccbSFrançois Tigeot wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1102926deccbSFrançois Tigeot }
1103926deccbSFrançois Tigeot }
1104926deccbSFrançois Tigeot
rv515_compute_mode_priority(struct radeon_device * rdev,struct rv515_watermark * wm0,struct rv515_watermark * wm1,struct drm_display_mode * mode0,struct drm_display_mode * mode1,u32 * d1mode_priority_a_cnt,u32 * d2mode_priority_a_cnt)110557e252bfSMichael Neumann static void rv515_compute_mode_priority(struct radeon_device *rdev,
110657e252bfSMichael Neumann struct rv515_watermark *wm0,
110757e252bfSMichael Neumann struct rv515_watermark *wm1,
110857e252bfSMichael Neumann struct drm_display_mode *mode0,
110957e252bfSMichael Neumann struct drm_display_mode *mode1,
111057e252bfSMichael Neumann u32 *d1mode_priority_a_cnt,
111157e252bfSMichael Neumann u32 *d2mode_priority_a_cnt)
111257e252bfSMichael Neumann {
111357e252bfSMichael Neumann fixed20_12 priority_mark02, priority_mark12, fill_rate;
111457e252bfSMichael Neumann fixed20_12 a, b;
111557e252bfSMichael Neumann
111657e252bfSMichael Neumann *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
111757e252bfSMichael Neumann *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
111857e252bfSMichael Neumann
111957e252bfSMichael Neumann if (mode0 && mode1) {
112057e252bfSMichael Neumann if (dfixed_trunc(wm0->dbpp) > 64)
112157e252bfSMichael Neumann a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
112257e252bfSMichael Neumann else
112357e252bfSMichael Neumann a.full = wm0->num_line_pair.full;
112457e252bfSMichael Neumann if (dfixed_trunc(wm1->dbpp) > 64)
112557e252bfSMichael Neumann b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
112657e252bfSMichael Neumann else
112757e252bfSMichael Neumann b.full = wm1->num_line_pair.full;
112857e252bfSMichael Neumann a.full += b.full;
112957e252bfSMichael Neumann fill_rate.full = dfixed_div(wm0->sclk, a);
113057e252bfSMichael Neumann if (wm0->consumption_rate.full > fill_rate.full) {
113157e252bfSMichael Neumann b.full = wm0->consumption_rate.full - fill_rate.full;
113257e252bfSMichael Neumann b.full = dfixed_mul(b, wm0->active_time);
113357e252bfSMichael Neumann a.full = dfixed_const(16);
113457e252bfSMichael Neumann b.full = dfixed_div(b, a);
113557e252bfSMichael Neumann a.full = dfixed_mul(wm0->worst_case_latency,
113657e252bfSMichael Neumann wm0->consumption_rate);
113757e252bfSMichael Neumann priority_mark02.full = a.full + b.full;
113857e252bfSMichael Neumann } else {
113957e252bfSMichael Neumann a.full = dfixed_mul(wm0->worst_case_latency,
114057e252bfSMichael Neumann wm0->consumption_rate);
114157e252bfSMichael Neumann b.full = dfixed_const(16 * 1000);
114257e252bfSMichael Neumann priority_mark02.full = dfixed_div(a, b);
114357e252bfSMichael Neumann }
114457e252bfSMichael Neumann if (wm1->consumption_rate.full > fill_rate.full) {
114557e252bfSMichael Neumann b.full = wm1->consumption_rate.full - fill_rate.full;
114657e252bfSMichael Neumann b.full = dfixed_mul(b, wm1->active_time);
114757e252bfSMichael Neumann a.full = dfixed_const(16);
114857e252bfSMichael Neumann b.full = dfixed_div(b, a);
114957e252bfSMichael Neumann a.full = dfixed_mul(wm1->worst_case_latency,
115057e252bfSMichael Neumann wm1->consumption_rate);
115157e252bfSMichael Neumann priority_mark12.full = a.full + b.full;
115257e252bfSMichael Neumann } else {
115357e252bfSMichael Neumann a.full = dfixed_mul(wm1->worst_case_latency,
115457e252bfSMichael Neumann wm1->consumption_rate);
115557e252bfSMichael Neumann b.full = dfixed_const(16 * 1000);
115657e252bfSMichael Neumann priority_mark12.full = dfixed_div(a, b);
115757e252bfSMichael Neumann }
115857e252bfSMichael Neumann if (wm0->priority_mark.full > priority_mark02.full)
115957e252bfSMichael Neumann priority_mark02.full = wm0->priority_mark.full;
116057e252bfSMichael Neumann if (wm0->priority_mark_max.full > priority_mark02.full)
116157e252bfSMichael Neumann priority_mark02.full = wm0->priority_mark_max.full;
116257e252bfSMichael Neumann if (wm1->priority_mark.full > priority_mark12.full)
116357e252bfSMichael Neumann priority_mark12.full = wm1->priority_mark.full;
116457e252bfSMichael Neumann if (wm1->priority_mark_max.full > priority_mark12.full)
116557e252bfSMichael Neumann priority_mark12.full = wm1->priority_mark_max.full;
116657e252bfSMichael Neumann *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
116757e252bfSMichael Neumann *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
116857e252bfSMichael Neumann if (rdev->disp_priority == 2) {
116957e252bfSMichael Neumann *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
117057e252bfSMichael Neumann *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
117157e252bfSMichael Neumann }
117257e252bfSMichael Neumann } else if (mode0) {
117357e252bfSMichael Neumann if (dfixed_trunc(wm0->dbpp) > 64)
117457e252bfSMichael Neumann a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
117557e252bfSMichael Neumann else
117657e252bfSMichael Neumann a.full = wm0->num_line_pair.full;
117757e252bfSMichael Neumann fill_rate.full = dfixed_div(wm0->sclk, a);
117857e252bfSMichael Neumann if (wm0->consumption_rate.full > fill_rate.full) {
117957e252bfSMichael Neumann b.full = wm0->consumption_rate.full - fill_rate.full;
118057e252bfSMichael Neumann b.full = dfixed_mul(b, wm0->active_time);
118157e252bfSMichael Neumann a.full = dfixed_const(16);
118257e252bfSMichael Neumann b.full = dfixed_div(b, a);
118357e252bfSMichael Neumann a.full = dfixed_mul(wm0->worst_case_latency,
118457e252bfSMichael Neumann wm0->consumption_rate);
118557e252bfSMichael Neumann priority_mark02.full = a.full + b.full;
118657e252bfSMichael Neumann } else {
118757e252bfSMichael Neumann a.full = dfixed_mul(wm0->worst_case_latency,
118857e252bfSMichael Neumann wm0->consumption_rate);
118957e252bfSMichael Neumann b.full = dfixed_const(16);
119057e252bfSMichael Neumann priority_mark02.full = dfixed_div(a, b);
119157e252bfSMichael Neumann }
119257e252bfSMichael Neumann if (wm0->priority_mark.full > priority_mark02.full)
119357e252bfSMichael Neumann priority_mark02.full = wm0->priority_mark.full;
119457e252bfSMichael Neumann if (wm0->priority_mark_max.full > priority_mark02.full)
119557e252bfSMichael Neumann priority_mark02.full = wm0->priority_mark_max.full;
119657e252bfSMichael Neumann *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
119757e252bfSMichael Neumann if (rdev->disp_priority == 2)
119857e252bfSMichael Neumann *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
119957e252bfSMichael Neumann } else if (mode1) {
120057e252bfSMichael Neumann if (dfixed_trunc(wm1->dbpp) > 64)
120157e252bfSMichael Neumann a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
120257e252bfSMichael Neumann else
120357e252bfSMichael Neumann a.full = wm1->num_line_pair.full;
120457e252bfSMichael Neumann fill_rate.full = dfixed_div(wm1->sclk, a);
120557e252bfSMichael Neumann if (wm1->consumption_rate.full > fill_rate.full) {
120657e252bfSMichael Neumann b.full = wm1->consumption_rate.full - fill_rate.full;
120757e252bfSMichael Neumann b.full = dfixed_mul(b, wm1->active_time);
120857e252bfSMichael Neumann a.full = dfixed_const(16);
120957e252bfSMichael Neumann b.full = dfixed_div(b, a);
121057e252bfSMichael Neumann a.full = dfixed_mul(wm1->worst_case_latency,
121157e252bfSMichael Neumann wm1->consumption_rate);
121257e252bfSMichael Neumann priority_mark12.full = a.full + b.full;
121357e252bfSMichael Neumann } else {
121457e252bfSMichael Neumann a.full = dfixed_mul(wm1->worst_case_latency,
121557e252bfSMichael Neumann wm1->consumption_rate);
121657e252bfSMichael Neumann b.full = dfixed_const(16 * 1000);
121757e252bfSMichael Neumann priority_mark12.full = dfixed_div(a, b);
121857e252bfSMichael Neumann }
121957e252bfSMichael Neumann if (wm1->priority_mark.full > priority_mark12.full)
122057e252bfSMichael Neumann priority_mark12.full = wm1->priority_mark.full;
122157e252bfSMichael Neumann if (wm1->priority_mark_max.full > priority_mark12.full)
122257e252bfSMichael Neumann priority_mark12.full = wm1->priority_mark_max.full;
122357e252bfSMichael Neumann *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
122457e252bfSMichael Neumann if (rdev->disp_priority == 2)
122557e252bfSMichael Neumann *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
122657e252bfSMichael Neumann }
122757e252bfSMichael Neumann }
122857e252bfSMichael Neumann
rv515_bandwidth_avivo_update(struct radeon_device * rdev)1229926deccbSFrançois Tigeot void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1230926deccbSFrançois Tigeot {
1231926deccbSFrançois Tigeot struct drm_display_mode *mode0 = NULL;
1232926deccbSFrançois Tigeot struct drm_display_mode *mode1 = NULL;
123357e252bfSMichael Neumann struct rv515_watermark wm0_high, wm0_low;
123457e252bfSMichael Neumann struct rv515_watermark wm1_high, wm1_low;
1235926deccbSFrançois Tigeot u32 tmp;
123657e252bfSMichael Neumann u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
123757e252bfSMichael Neumann u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1238926deccbSFrançois Tigeot
1239926deccbSFrançois Tigeot if (rdev->mode_info.crtcs[0]->base.enabled)
1240926deccbSFrançois Tigeot mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1241926deccbSFrançois Tigeot if (rdev->mode_info.crtcs[1]->base.enabled)
1242926deccbSFrançois Tigeot mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1243926deccbSFrançois Tigeot rs690_line_buffer_adjust(rdev, mode0, mode1);
1244926deccbSFrançois Tigeot
124557e252bfSMichael Neumann rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
124657e252bfSMichael Neumann rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1247926deccbSFrançois Tigeot
124857e252bfSMichael Neumann rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
124957e252bfSMichael Neumann rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
125057e252bfSMichael Neumann
125157e252bfSMichael Neumann tmp = wm0_high.lb_request_fifo_depth;
125257e252bfSMichael Neumann tmp |= wm1_high.lb_request_fifo_depth << 16;
1253926deccbSFrançois Tigeot WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1254926deccbSFrançois Tigeot
125557e252bfSMichael Neumann rv515_compute_mode_priority(rdev,
125657e252bfSMichael Neumann &wm0_high, &wm1_high,
125757e252bfSMichael Neumann mode0, mode1,
125857e252bfSMichael Neumann &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
125957e252bfSMichael Neumann rv515_compute_mode_priority(rdev,
126057e252bfSMichael Neumann &wm0_low, &wm1_low,
126157e252bfSMichael Neumann mode0, mode1,
126257e252bfSMichael Neumann &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1263926deccbSFrançois Tigeot
1264926deccbSFrançois Tigeot WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
126557e252bfSMichael Neumann WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1266926deccbSFrançois Tigeot WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
126757e252bfSMichael Neumann WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1268926deccbSFrançois Tigeot }
1269926deccbSFrançois Tigeot
rv515_bandwidth_update(struct radeon_device * rdev)1270926deccbSFrançois Tigeot void rv515_bandwidth_update(struct radeon_device *rdev)
1271926deccbSFrançois Tigeot {
1272926deccbSFrançois Tigeot uint32_t tmp;
1273926deccbSFrançois Tigeot struct drm_display_mode *mode0 = NULL;
1274926deccbSFrançois Tigeot struct drm_display_mode *mode1 = NULL;
1275926deccbSFrançois Tigeot
1276591d5043SFrançois Tigeot if (!rdev->mode_info.mode_config_initialized)
1277591d5043SFrançois Tigeot return;
1278591d5043SFrançois Tigeot
1279926deccbSFrançois Tigeot radeon_update_display_priority(rdev);
1280926deccbSFrançois Tigeot
1281926deccbSFrançois Tigeot if (rdev->mode_info.crtcs[0]->base.enabled)
1282926deccbSFrançois Tigeot mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1283926deccbSFrançois Tigeot if (rdev->mode_info.crtcs[1]->base.enabled)
1284926deccbSFrançois Tigeot mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1285926deccbSFrançois Tigeot /*
1286926deccbSFrançois Tigeot * Set display0/1 priority up in the memory controller for
1287926deccbSFrançois Tigeot * modes if the user specifies HIGH for displaypriority
1288926deccbSFrançois Tigeot * option.
1289926deccbSFrançois Tigeot */
1290926deccbSFrançois Tigeot if ((rdev->disp_priority == 2) &&
1291926deccbSFrançois Tigeot (rdev->family == CHIP_RV515)) {
1292926deccbSFrançois Tigeot tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1293926deccbSFrançois Tigeot tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1294926deccbSFrançois Tigeot tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1295926deccbSFrançois Tigeot if (mode1)
1296926deccbSFrançois Tigeot tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1297926deccbSFrançois Tigeot if (mode0)
1298926deccbSFrançois Tigeot tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1299926deccbSFrançois Tigeot WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1300926deccbSFrançois Tigeot }
1301926deccbSFrançois Tigeot rv515_bandwidth_avivo_update(rdev);
1302926deccbSFrançois Tigeot }
1303