1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "rv515d.h" 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include "rv515_reg_safe.h" 34 35 /* This files gather functions specifics to: rv515 */ 36 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 37 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 38 static void rv515_gpu_init(struct radeon_device *rdev); 39 40 static const u32 crtc_offsets[2] = 41 { 42 0, 43 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 44 }; 45 46 void rv515_debugfs(struct radeon_device *rdev) 47 { 48 if (r100_debugfs_rbbm_init(rdev)) { 49 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 50 } 51 if (rv515_debugfs_pipes_info_init(rdev)) { 52 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 53 } 54 if (rv515_debugfs_ga_info_init(rdev)) { 55 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 56 } 57 } 58 59 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 60 { 61 int r; 62 63 r = radeon_ring_lock(rdev, ring, 64); 64 if (r) { 65 return; 66 } 67 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 68 radeon_ring_write(ring, 69 ISYNC_ANY2D_IDLE3D | 70 ISYNC_ANY3D_IDLE2D | 71 ISYNC_WAIT_IDLEGUI | 72 ISYNC_CPSCRATCH_IDLEGUI); 73 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 74 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 75 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 76 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 77 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 78 radeon_ring_write(ring, 0); 79 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 80 radeon_ring_write(ring, 0); 81 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 82 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 83 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 84 radeon_ring_write(ring, 0); 85 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 86 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 87 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 88 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 89 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 90 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 91 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 92 radeon_ring_write(ring, 0); 93 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 94 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 95 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 96 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 97 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 98 radeon_ring_write(ring, 99 ((6 << MS_X0_SHIFT) | 100 (6 << MS_Y0_SHIFT) | 101 (6 << MS_X1_SHIFT) | 102 (6 << MS_Y1_SHIFT) | 103 (6 << MS_X2_SHIFT) | 104 (6 << MS_Y2_SHIFT) | 105 (6 << MSBD0_Y_SHIFT) | 106 (6 << MSBD0_X_SHIFT))); 107 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 108 radeon_ring_write(ring, 109 ((6 << MS_X3_SHIFT) | 110 (6 << MS_Y3_SHIFT) | 111 (6 << MS_X4_SHIFT) | 112 (6 << MS_Y4_SHIFT) | 113 (6 << MS_X5_SHIFT) | 114 (6 << MS_Y5_SHIFT) | 115 (6 << MSBD1_SHIFT))); 116 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 117 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 118 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 119 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 120 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 121 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 122 radeon_ring_write(ring, PACKET0(0x20C8, 0)); 123 radeon_ring_write(ring, 0); 124 radeon_ring_unlock_commit(rdev, ring); 125 } 126 127 int rv515_mc_wait_for_idle(struct radeon_device *rdev) 128 { 129 unsigned i; 130 uint32_t tmp; 131 132 for (i = 0; i < rdev->usec_timeout; i++) { 133 /* read MC_STATUS */ 134 tmp = RREG32_MC(MC_STATUS); 135 if (tmp & MC_STATUS_IDLE) { 136 return 0; 137 } 138 DRM_UDELAY(1); 139 } 140 return -1; 141 } 142 143 void rv515_vga_render_disable(struct radeon_device *rdev) 144 { 145 WREG32(R_000300_VGA_RENDER_CONTROL, 146 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 147 } 148 149 static void rv515_gpu_init(struct radeon_device *rdev) 150 { 151 unsigned pipe_select_current, gb_pipe_select, tmp; 152 153 if (r100_gui_wait_for_idle(rdev)) { 154 printk(KERN_WARNING "Failed to wait GUI idle while " 155 "resetting GPU. Bad things might happen.\n"); 156 } 157 rv515_vga_render_disable(rdev); 158 r420_pipes_init(rdev); 159 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 160 tmp = RREG32(R300_DST_PIPE_CONFIG); 161 pipe_select_current = (tmp >> 2) & 3; 162 tmp = (1 << pipe_select_current) | 163 (((gb_pipe_select >> 8) & 0xF) << 4); 164 WREG32_PLL(0x000D, tmp); 165 if (r100_gui_wait_for_idle(rdev)) { 166 printk(KERN_WARNING "Failed to wait GUI idle while " 167 "resetting GPU. Bad things might happen.\n"); 168 } 169 if (rv515_mc_wait_for_idle(rdev)) { 170 printk(KERN_WARNING "Failed to wait MC idle while " 171 "programming pipes. Bad things might happen.\n"); 172 } 173 } 174 175 static void rv515_vram_get_type(struct radeon_device *rdev) 176 { 177 uint32_t tmp; 178 179 rdev->mc.vram_width = 128; 180 rdev->mc.vram_is_ddr = true; 181 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 182 switch (tmp) { 183 case 0: 184 rdev->mc.vram_width = 64; 185 break; 186 case 1: 187 rdev->mc.vram_width = 128; 188 break; 189 default: 190 rdev->mc.vram_width = 128; 191 break; 192 } 193 } 194 195 static void rv515_mc_init(struct radeon_device *rdev) 196 { 197 198 rv515_vram_get_type(rdev); 199 r100_vram_init_sizes(rdev); 200 radeon_vram_location(rdev, &rdev->mc, 0); 201 rdev->mc.gtt_base_align = 0; 202 if (!(rdev->flags & RADEON_IS_AGP)) 203 radeon_gtt_location(rdev, &rdev->mc); 204 radeon_update_bandwidth_info(rdev); 205 } 206 207 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 208 { 209 uint32_t r; 210 211 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 212 r = RREG32(MC_IND_DATA); 213 WREG32(MC_IND_INDEX, 0); 214 return r; 215 } 216 217 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 218 { 219 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 220 WREG32(MC_IND_DATA, (v)); 221 WREG32(MC_IND_INDEX, 0); 222 } 223 224 #if defined(CONFIG_DEBUG_FS) 225 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 226 { 227 struct drm_info_node *node = (struct drm_info_node *) m->private; 228 struct drm_device *dev = node->minor->dev; 229 struct radeon_device *rdev = dev->dev_private; 230 uint32_t tmp; 231 232 tmp = RREG32(GB_PIPE_SELECT); 233 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 234 tmp = RREG32(SU_REG_DEST); 235 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 236 tmp = RREG32(GB_TILE_CONFIG); 237 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 238 tmp = RREG32(DST_PIPE_CONFIG); 239 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 240 return 0; 241 } 242 243 static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 244 { 245 struct drm_info_node *node = (struct drm_info_node *) m->private; 246 struct drm_device *dev = node->minor->dev; 247 struct radeon_device *rdev = dev->dev_private; 248 uint32_t tmp; 249 250 tmp = RREG32(0x2140); 251 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 252 radeon_asic_reset(rdev); 253 tmp = RREG32(0x425C); 254 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 255 return 0; 256 } 257 258 static struct drm_info_list rv515_pipes_info_list[] = { 259 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 260 }; 261 262 static struct drm_info_list rv515_ga_info_list[] = { 263 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 264 }; 265 #endif 266 267 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 268 { 269 #if defined(CONFIG_DEBUG_FS) 270 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 271 #else 272 return 0; 273 #endif 274 } 275 276 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 277 { 278 #if defined(CONFIG_DEBUG_FS) 279 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 280 #else 281 return 0; 282 #endif 283 } 284 285 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 286 { 287 u32 crtc_enabled, tmp, frame_count, blackout; 288 int i, j; 289 290 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 291 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 292 293 /* disable VGA render */ 294 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 295 /* blank the display controllers */ 296 for (i = 0; i < rdev->num_crtc; i++) { 297 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 298 if (crtc_enabled) { 299 save->crtc_enabled[i] = true; 300 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 301 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 302 radeon_wait_for_vblank(rdev, i); 303 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 304 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 305 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 306 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 307 } 308 /* wait for the next frame */ 309 frame_count = radeon_get_vblank_counter(rdev, i); 310 for (j = 0; j < rdev->usec_timeout; j++) { 311 if (radeon_get_vblank_counter(rdev, i) != frame_count) 312 break; 313 udelay(1); 314 } 315 316 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 317 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 318 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 319 tmp &= ~AVIVO_CRTC_EN; 320 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 321 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 322 save->crtc_enabled[i] = false; 323 /* ***** */ 324 } else { 325 save->crtc_enabled[i] = false; 326 } 327 } 328 329 radeon_mc_wait_for_idle(rdev); 330 331 if (rdev->family >= CHIP_R600) { 332 if (rdev->family >= CHIP_RV770) 333 blackout = RREG32(R700_MC_CITF_CNTL); 334 else 335 blackout = RREG32(R600_CITF_CNTL); 336 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 337 /* Block CPU access */ 338 WREG32(R600_BIF_FB_EN, 0); 339 /* blackout the MC */ 340 blackout |= R600_BLACKOUT_MASK; 341 if (rdev->family >= CHIP_RV770) 342 WREG32(R700_MC_CITF_CNTL, blackout); 343 else 344 WREG32(R600_CITF_CNTL, blackout); 345 } 346 } 347 /* wait for the MC to settle */ 348 udelay(100); 349 350 /* lock double buffered regs */ 351 for (i = 0; i < rdev->num_crtc; i++) { 352 if (save->crtc_enabled[i]) { 353 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 354 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { 355 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 356 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 357 } 358 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 359 if (!(tmp & 1)) { 360 tmp |= 1; 361 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 362 } 363 } 364 } 365 } 366 367 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 368 { 369 u32 tmp, frame_count; 370 int i, j; 371 372 /* update crtc base addresses */ 373 for (i = 0; i < rdev->num_crtc; i++) { 374 if (rdev->family >= CHIP_RV770) { 375 if (i == 0) { 376 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 377 upper_32_bits(rdev->mc.vram_start)); 378 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 379 upper_32_bits(rdev->mc.vram_start)); 380 } else { 381 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 382 upper_32_bits(rdev->mc.vram_start)); 383 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 384 upper_32_bits(rdev->mc.vram_start)); 385 } 386 } 387 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 388 (u32)rdev->mc.vram_start); 389 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 390 (u32)rdev->mc.vram_start); 391 } 392 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 393 394 /* unlock regs and wait for update */ 395 for (i = 0; i < rdev->num_crtc; i++) { 396 if (save->crtc_enabled[i]) { 397 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 398 if ((tmp & 0x3) != 0) { 399 tmp &= ~0x3; 400 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 401 } 402 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 403 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { 404 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 405 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 406 } 407 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 408 if (tmp & 1) { 409 tmp &= ~1; 410 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 411 } 412 for (j = 0; j < rdev->usec_timeout; j++) { 413 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 414 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) 415 break; 416 udelay(1); 417 } 418 } 419 } 420 421 if (rdev->family >= CHIP_R600) { 422 /* unblackout the MC */ 423 if (rdev->family >= CHIP_RV770) 424 tmp = RREG32(R700_MC_CITF_CNTL); 425 else 426 tmp = RREG32(R600_CITF_CNTL); 427 tmp &= ~R600_BLACKOUT_MASK; 428 if (rdev->family >= CHIP_RV770) 429 WREG32(R700_MC_CITF_CNTL, tmp); 430 else 431 WREG32(R600_CITF_CNTL, tmp); 432 /* allow CPU access */ 433 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 434 } 435 436 for (i = 0; i < rdev->num_crtc; i++) { 437 if (save->crtc_enabled[i]) { 438 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 439 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 440 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 441 /* wait for the next frame */ 442 frame_count = radeon_get_vblank_counter(rdev, i); 443 for (j = 0; j < rdev->usec_timeout; j++) { 444 if (radeon_get_vblank_counter(rdev, i) != frame_count) 445 break; 446 udelay(1); 447 } 448 } 449 } 450 /* Unlock vga access */ 451 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 452 mdelay(1); 453 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 454 } 455 456 static void rv515_mc_program(struct radeon_device *rdev) 457 { 458 struct rv515_mc_save save; 459 460 /* Stops all mc clients */ 461 rv515_mc_stop(rdev, &save); 462 463 /* Wait for mc idle */ 464 if (rv515_mc_wait_for_idle(rdev)) 465 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 466 /* Write VRAM size in case we are limiting it */ 467 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 468 /* Program MC, should be a 32bits limited address space */ 469 WREG32_MC(R_000001_MC_FB_LOCATION, 470 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 471 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 472 WREG32(R_000134_HDP_FB_LOCATION, 473 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 474 if (rdev->flags & RADEON_IS_AGP) { 475 WREG32_MC(R_000002_MC_AGP_LOCATION, 476 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 477 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 478 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 479 WREG32_MC(R_000004_MC_AGP_BASE_2, 480 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 481 } else { 482 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 483 WREG32_MC(R_000003_MC_AGP_BASE, 0); 484 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 485 } 486 487 rv515_mc_resume(rdev, &save); 488 } 489 490 void rv515_clock_startup(struct radeon_device *rdev) 491 { 492 if (radeon_dynclks != -1 && radeon_dynclks) 493 radeon_atom_set_clock_gating(rdev, 1); 494 /* We need to force on some of the block */ 495 WREG32_PLL(R_00000F_CP_DYN_CNTL, 496 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 497 WREG32_PLL(R_000011_E2_DYN_CNTL, 498 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 499 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 500 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 501 } 502 503 static int rv515_startup(struct radeon_device *rdev) 504 { 505 int r; 506 507 rv515_mc_program(rdev); 508 /* Resume clock */ 509 rv515_clock_startup(rdev); 510 /* Initialize GPU configuration (# pipes, ...) */ 511 rv515_gpu_init(rdev); 512 /* Initialize GART (initialize after TTM so we can allocate 513 * memory through TTM but finalize after TTM) */ 514 if (rdev->flags & RADEON_IS_PCIE) { 515 r = rv370_pcie_gart_enable(rdev); 516 if (r) 517 return r; 518 } 519 520 /* allocate wb buffer */ 521 r = radeon_wb_init(rdev); 522 if (r) 523 return r; 524 525 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 526 if (r) { 527 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 528 return r; 529 } 530 531 /* Enable IRQ */ 532 if (!rdev->irq.installed) { 533 r = radeon_irq_kms_init(rdev); 534 if (r) 535 return r; 536 } 537 538 rs600_irq_set(rdev); 539 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 540 /* 1M ring buffer */ 541 r = r100_cp_init(rdev, 1024 * 1024); 542 if (r) { 543 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 544 return r; 545 } 546 547 r = radeon_ib_pool_init(rdev); 548 if (r) { 549 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 550 return r; 551 } 552 553 return 0; 554 } 555 556 int rv515_resume(struct radeon_device *rdev) 557 { 558 int r; 559 560 /* Make sur GART are not working */ 561 if (rdev->flags & RADEON_IS_PCIE) 562 rv370_pcie_gart_disable(rdev); 563 /* Resume clock before doing reset */ 564 rv515_clock_startup(rdev); 565 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 566 if (radeon_asic_reset(rdev)) { 567 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 568 RREG32(R_000E40_RBBM_STATUS), 569 RREG32(R_0007C0_CP_STAT)); 570 } 571 /* post */ 572 atom_asic_init(rdev->mode_info.atom_context); 573 /* Resume clock after posting */ 574 rv515_clock_startup(rdev); 575 /* Initialize surface registers */ 576 radeon_surface_init(rdev); 577 578 rdev->accel_working = true; 579 r = rv515_startup(rdev); 580 if (r) { 581 rdev->accel_working = false; 582 } 583 return r; 584 } 585 586 int rv515_suspend(struct radeon_device *rdev) 587 { 588 r100_cp_disable(rdev); 589 radeon_wb_disable(rdev); 590 rs600_irq_disable(rdev); 591 if (rdev->flags & RADEON_IS_PCIE) 592 rv370_pcie_gart_disable(rdev); 593 return 0; 594 } 595 596 void rv515_set_safe_registers(struct radeon_device *rdev) 597 { 598 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 599 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 600 } 601 602 void rv515_fini(struct radeon_device *rdev) 603 { 604 r100_cp_fini(rdev); 605 radeon_wb_fini(rdev); 606 radeon_ib_pool_fini(rdev); 607 radeon_gem_fini(rdev); 608 rv370_pcie_gart_fini(rdev); 609 radeon_agp_fini(rdev); 610 radeon_irq_kms_fini(rdev); 611 radeon_fence_driver_fini(rdev); 612 radeon_bo_fini(rdev); 613 radeon_atombios_fini(rdev); 614 kfree(rdev->bios); 615 rdev->bios = NULL; 616 } 617 618 int rv515_init(struct radeon_device *rdev) 619 { 620 int r; 621 622 /* Initialize scratch registers */ 623 radeon_scratch_init(rdev); 624 /* Initialize surface registers */ 625 radeon_surface_init(rdev); 626 /* TODO: disable VGA need to use VGA request */ 627 /* restore some register to sane defaults */ 628 r100_restore_sanity(rdev); 629 /* BIOS*/ 630 if (!radeon_get_bios(rdev)) { 631 if (ASIC_IS_AVIVO(rdev)) 632 return -EINVAL; 633 } 634 if (rdev->is_atom_bios) { 635 r = radeon_atombios_init(rdev); 636 if (r) 637 return r; 638 } else { 639 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 640 return -EINVAL; 641 } 642 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 643 if (radeon_asic_reset(rdev)) { 644 dev_warn(rdev->dev, 645 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 646 RREG32(R_000E40_RBBM_STATUS), 647 RREG32(R_0007C0_CP_STAT)); 648 } 649 /* check if cards are posted or not */ 650 if (radeon_boot_test_post_card(rdev) == false) 651 return -EINVAL; 652 /* Initialize clocks */ 653 radeon_get_clock_info(rdev->ddev); 654 /* initialize AGP */ 655 if (rdev->flags & RADEON_IS_AGP) { 656 r = radeon_agp_init(rdev); 657 if (r) { 658 radeon_agp_disable(rdev); 659 } 660 } 661 /* initialize memory controller */ 662 rv515_mc_init(rdev); 663 rv515_debugfs(rdev); 664 /* Fence driver */ 665 r = radeon_fence_driver_init(rdev); 666 if (r) 667 return r; 668 /* Memory manager */ 669 r = radeon_bo_init(rdev); 670 if (r) 671 return r; 672 r = rv370_pcie_gart_init(rdev); 673 if (r) 674 return r; 675 rv515_set_safe_registers(rdev); 676 677 rdev->accel_working = true; 678 r = rv515_startup(rdev); 679 if (r) { 680 /* Somethings want wront with the accel init stop accel */ 681 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 682 r100_cp_fini(rdev); 683 radeon_wb_fini(rdev); 684 radeon_ib_pool_fini(rdev); 685 radeon_irq_kms_fini(rdev); 686 rv370_pcie_gart_fini(rdev); 687 radeon_agp_fini(rdev); 688 rdev->accel_working = false; 689 } 690 return 0; 691 } 692 693 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 694 { 695 int index_reg = 0x6578 + crtc->crtc_offset; 696 int data_reg = 0x657c + crtc->crtc_offset; 697 698 WREG32(0x659C + crtc->crtc_offset, 0x0); 699 WREG32(0x6594 + crtc->crtc_offset, 0x705); 700 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 701 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 702 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 703 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 704 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 705 WREG32(index_reg, 0x0); 706 WREG32(data_reg, 0x841880A8); 707 WREG32(index_reg, 0x1); 708 WREG32(data_reg, 0x84208680); 709 WREG32(index_reg, 0x2); 710 WREG32(data_reg, 0xBFF880B0); 711 WREG32(index_reg, 0x100); 712 WREG32(data_reg, 0x83D88088); 713 WREG32(index_reg, 0x101); 714 WREG32(data_reg, 0x84608680); 715 WREG32(index_reg, 0x102); 716 WREG32(data_reg, 0xBFF080D0); 717 WREG32(index_reg, 0x200); 718 WREG32(data_reg, 0x83988068); 719 WREG32(index_reg, 0x201); 720 WREG32(data_reg, 0x84A08680); 721 WREG32(index_reg, 0x202); 722 WREG32(data_reg, 0xBFF080F8); 723 WREG32(index_reg, 0x300); 724 WREG32(data_reg, 0x83588058); 725 WREG32(index_reg, 0x301); 726 WREG32(data_reg, 0x84E08660); 727 WREG32(index_reg, 0x302); 728 WREG32(data_reg, 0xBFF88120); 729 WREG32(index_reg, 0x400); 730 WREG32(data_reg, 0x83188040); 731 WREG32(index_reg, 0x401); 732 WREG32(data_reg, 0x85008660); 733 WREG32(index_reg, 0x402); 734 WREG32(data_reg, 0xBFF88150); 735 WREG32(index_reg, 0x500); 736 WREG32(data_reg, 0x82D88030); 737 WREG32(index_reg, 0x501); 738 WREG32(data_reg, 0x85408640); 739 WREG32(index_reg, 0x502); 740 WREG32(data_reg, 0xBFF88180); 741 WREG32(index_reg, 0x600); 742 WREG32(data_reg, 0x82A08018); 743 WREG32(index_reg, 0x601); 744 WREG32(data_reg, 0x85808620); 745 WREG32(index_reg, 0x602); 746 WREG32(data_reg, 0xBFF081B8); 747 WREG32(index_reg, 0x700); 748 WREG32(data_reg, 0x82608010); 749 WREG32(index_reg, 0x701); 750 WREG32(data_reg, 0x85A08600); 751 WREG32(index_reg, 0x702); 752 WREG32(data_reg, 0x800081F0); 753 WREG32(index_reg, 0x800); 754 WREG32(data_reg, 0x8228BFF8); 755 WREG32(index_reg, 0x801); 756 WREG32(data_reg, 0x85E085E0); 757 WREG32(index_reg, 0x802); 758 WREG32(data_reg, 0xBFF88228); 759 WREG32(index_reg, 0x10000); 760 WREG32(data_reg, 0x82A8BF00); 761 WREG32(index_reg, 0x10001); 762 WREG32(data_reg, 0x82A08CC0); 763 WREG32(index_reg, 0x10002); 764 WREG32(data_reg, 0x8008BEF8); 765 WREG32(index_reg, 0x10100); 766 WREG32(data_reg, 0x81F0BF28); 767 WREG32(index_reg, 0x10101); 768 WREG32(data_reg, 0x83608CA0); 769 WREG32(index_reg, 0x10102); 770 WREG32(data_reg, 0x8018BED0); 771 WREG32(index_reg, 0x10200); 772 WREG32(data_reg, 0x8148BF38); 773 WREG32(index_reg, 0x10201); 774 WREG32(data_reg, 0x84408C80); 775 WREG32(index_reg, 0x10202); 776 WREG32(data_reg, 0x8008BEB8); 777 WREG32(index_reg, 0x10300); 778 WREG32(data_reg, 0x80B0BF78); 779 WREG32(index_reg, 0x10301); 780 WREG32(data_reg, 0x85008C20); 781 WREG32(index_reg, 0x10302); 782 WREG32(data_reg, 0x8020BEA0); 783 WREG32(index_reg, 0x10400); 784 WREG32(data_reg, 0x8028BF90); 785 WREG32(index_reg, 0x10401); 786 WREG32(data_reg, 0x85E08BC0); 787 WREG32(index_reg, 0x10402); 788 WREG32(data_reg, 0x8018BE90); 789 WREG32(index_reg, 0x10500); 790 WREG32(data_reg, 0xBFB8BFB0); 791 WREG32(index_reg, 0x10501); 792 WREG32(data_reg, 0x86C08B40); 793 WREG32(index_reg, 0x10502); 794 WREG32(data_reg, 0x8010BE90); 795 WREG32(index_reg, 0x10600); 796 WREG32(data_reg, 0xBF58BFC8); 797 WREG32(index_reg, 0x10601); 798 WREG32(data_reg, 0x87A08AA0); 799 WREG32(index_reg, 0x10602); 800 WREG32(data_reg, 0x8010BE98); 801 WREG32(index_reg, 0x10700); 802 WREG32(data_reg, 0xBF10BFF0); 803 WREG32(index_reg, 0x10701); 804 WREG32(data_reg, 0x886089E0); 805 WREG32(index_reg, 0x10702); 806 WREG32(data_reg, 0x8018BEB0); 807 WREG32(index_reg, 0x10800); 808 WREG32(data_reg, 0xBED8BFE8); 809 WREG32(index_reg, 0x10801); 810 WREG32(data_reg, 0x89408940); 811 WREG32(index_reg, 0x10802); 812 WREG32(data_reg, 0xBFE8BED8); 813 WREG32(index_reg, 0x20000); 814 WREG32(data_reg, 0x80008000); 815 WREG32(index_reg, 0x20001); 816 WREG32(data_reg, 0x90008000); 817 WREG32(index_reg, 0x20002); 818 WREG32(data_reg, 0x80008000); 819 WREG32(index_reg, 0x20003); 820 WREG32(data_reg, 0x80008000); 821 WREG32(index_reg, 0x20100); 822 WREG32(data_reg, 0x80108000); 823 WREG32(index_reg, 0x20101); 824 WREG32(data_reg, 0x8FE0BF70); 825 WREG32(index_reg, 0x20102); 826 WREG32(data_reg, 0xBFE880C0); 827 WREG32(index_reg, 0x20103); 828 WREG32(data_reg, 0x80008000); 829 WREG32(index_reg, 0x20200); 830 WREG32(data_reg, 0x8018BFF8); 831 WREG32(index_reg, 0x20201); 832 WREG32(data_reg, 0x8F80BF08); 833 WREG32(index_reg, 0x20202); 834 WREG32(data_reg, 0xBFD081A0); 835 WREG32(index_reg, 0x20203); 836 WREG32(data_reg, 0xBFF88000); 837 WREG32(index_reg, 0x20300); 838 WREG32(data_reg, 0x80188000); 839 WREG32(index_reg, 0x20301); 840 WREG32(data_reg, 0x8EE0BEC0); 841 WREG32(index_reg, 0x20302); 842 WREG32(data_reg, 0xBFB082A0); 843 WREG32(index_reg, 0x20303); 844 WREG32(data_reg, 0x80008000); 845 WREG32(index_reg, 0x20400); 846 WREG32(data_reg, 0x80188000); 847 WREG32(index_reg, 0x20401); 848 WREG32(data_reg, 0x8E00BEA0); 849 WREG32(index_reg, 0x20402); 850 WREG32(data_reg, 0xBF8883C0); 851 WREG32(index_reg, 0x20403); 852 WREG32(data_reg, 0x80008000); 853 WREG32(index_reg, 0x20500); 854 WREG32(data_reg, 0x80188000); 855 WREG32(index_reg, 0x20501); 856 WREG32(data_reg, 0x8D00BE90); 857 WREG32(index_reg, 0x20502); 858 WREG32(data_reg, 0xBF588500); 859 WREG32(index_reg, 0x20503); 860 WREG32(data_reg, 0x80008008); 861 WREG32(index_reg, 0x20600); 862 WREG32(data_reg, 0x80188000); 863 WREG32(index_reg, 0x20601); 864 WREG32(data_reg, 0x8BC0BE98); 865 WREG32(index_reg, 0x20602); 866 WREG32(data_reg, 0xBF308660); 867 WREG32(index_reg, 0x20603); 868 WREG32(data_reg, 0x80008008); 869 WREG32(index_reg, 0x20700); 870 WREG32(data_reg, 0x80108000); 871 WREG32(index_reg, 0x20701); 872 WREG32(data_reg, 0x8A80BEB0); 873 WREG32(index_reg, 0x20702); 874 WREG32(data_reg, 0xBF0087C0); 875 WREG32(index_reg, 0x20703); 876 WREG32(data_reg, 0x80008008); 877 WREG32(index_reg, 0x20800); 878 WREG32(data_reg, 0x80108000); 879 WREG32(index_reg, 0x20801); 880 WREG32(data_reg, 0x8920BED0); 881 WREG32(index_reg, 0x20802); 882 WREG32(data_reg, 0xBED08920); 883 WREG32(index_reg, 0x20803); 884 WREG32(data_reg, 0x80008010); 885 WREG32(index_reg, 0x30000); 886 WREG32(data_reg, 0x90008000); 887 WREG32(index_reg, 0x30001); 888 WREG32(data_reg, 0x80008000); 889 WREG32(index_reg, 0x30100); 890 WREG32(data_reg, 0x8FE0BF90); 891 WREG32(index_reg, 0x30101); 892 WREG32(data_reg, 0xBFF880A0); 893 WREG32(index_reg, 0x30200); 894 WREG32(data_reg, 0x8F60BF40); 895 WREG32(index_reg, 0x30201); 896 WREG32(data_reg, 0xBFE88180); 897 WREG32(index_reg, 0x30300); 898 WREG32(data_reg, 0x8EC0BF00); 899 WREG32(index_reg, 0x30301); 900 WREG32(data_reg, 0xBFC88280); 901 WREG32(index_reg, 0x30400); 902 WREG32(data_reg, 0x8DE0BEE0); 903 WREG32(index_reg, 0x30401); 904 WREG32(data_reg, 0xBFA083A0); 905 WREG32(index_reg, 0x30500); 906 WREG32(data_reg, 0x8CE0BED0); 907 WREG32(index_reg, 0x30501); 908 WREG32(data_reg, 0xBF7884E0); 909 WREG32(index_reg, 0x30600); 910 WREG32(data_reg, 0x8BA0BED8); 911 WREG32(index_reg, 0x30601); 912 WREG32(data_reg, 0xBF508640); 913 WREG32(index_reg, 0x30700); 914 WREG32(data_reg, 0x8A60BEE8); 915 WREG32(index_reg, 0x30701); 916 WREG32(data_reg, 0xBF2087A0); 917 WREG32(index_reg, 0x30800); 918 WREG32(data_reg, 0x8900BF00); 919 WREG32(index_reg, 0x30801); 920 WREG32(data_reg, 0xBF008900); 921 } 922 923 struct rv515_watermark { 924 u32 lb_request_fifo_depth; 925 fixed20_12 num_line_pair; 926 fixed20_12 estimated_width; 927 fixed20_12 worst_case_latency; 928 fixed20_12 consumption_rate; 929 fixed20_12 active_time; 930 fixed20_12 dbpp; 931 fixed20_12 priority_mark_max; 932 fixed20_12 priority_mark; 933 fixed20_12 sclk; 934 }; 935 936 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 937 struct radeon_crtc *crtc, 938 struct rv515_watermark *wm, 939 bool low) 940 { 941 struct drm_display_mode *mode = &crtc->base.mode; 942 fixed20_12 a, b, c; 943 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 944 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 945 fixed20_12 sclk; 946 u32 selected_sclk; 947 948 if (!crtc->base.enabled) { 949 /* FIXME: wouldn't it better to set priority mark to maximum */ 950 wm->lb_request_fifo_depth = 4; 951 return; 952 } 953 954 /* rv6xx, rv7xx */ 955 if ((rdev->family >= CHIP_RV610) && 956 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 957 selected_sclk = radeon_dpm_get_sclk(rdev, low); 958 else 959 selected_sclk = rdev->pm.current_sclk; 960 961 /* sclk in Mhz */ 962 a.full = dfixed_const(100); 963 sclk.full = dfixed_const(selected_sclk); 964 sclk.full = dfixed_div(sclk, a); 965 966 if (crtc->vsc.full > dfixed_const(2)) 967 wm->num_line_pair.full = dfixed_const(2); 968 else 969 wm->num_line_pair.full = dfixed_const(1); 970 971 b.full = dfixed_const(mode->crtc_hdisplay); 972 c.full = dfixed_const(256); 973 a.full = dfixed_div(b, c); 974 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 975 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 976 if (a.full < dfixed_const(4)) { 977 wm->lb_request_fifo_depth = 4; 978 } else { 979 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 980 } 981 982 /* Determine consumption rate 983 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 984 * vtaps = number of vertical taps, 985 * vsc = vertical scaling ratio, defined as source/destination 986 * hsc = horizontal scaling ration, defined as source/destination 987 */ 988 a.full = dfixed_const(mode->clock); 989 b.full = dfixed_const(1000); 990 a.full = dfixed_div(a, b); 991 pclk.full = dfixed_div(b, a); 992 if (crtc->rmx_type != RMX_OFF) { 993 b.full = dfixed_const(2); 994 if (crtc->vsc.full > b.full) 995 b.full = crtc->vsc.full; 996 b.full = dfixed_mul(b, crtc->hsc); 997 c.full = dfixed_const(2); 998 b.full = dfixed_div(b, c); 999 consumption_time.full = dfixed_div(pclk, b); 1000 } else { 1001 consumption_time.full = pclk.full; 1002 } 1003 a.full = dfixed_const(1); 1004 wm->consumption_rate.full = dfixed_div(a, consumption_time); 1005 1006 1007 /* Determine line time 1008 * LineTime = total time for one line of displayhtotal 1009 * LineTime = total number of horizontal pixels 1010 * pclk = pixel clock period(ns) 1011 */ 1012 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1013 line_time.full = dfixed_mul(a, pclk); 1014 1015 /* Determine active time 1016 * ActiveTime = time of active region of display within one line, 1017 * hactive = total number of horizontal active pixels 1018 * htotal = total number of horizontal pixels 1019 */ 1020 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1021 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1022 wm->active_time.full = dfixed_mul(line_time, b); 1023 wm->active_time.full = dfixed_div(wm->active_time, a); 1024 1025 /* Determine chunk time 1026 * ChunkTime = the time it takes the DCP to send one chunk of data 1027 * to the LB which consists of pipeline delay and inter chunk gap 1028 * sclk = system clock(Mhz) 1029 */ 1030 a.full = dfixed_const(600 * 1000); 1031 chunk_time.full = dfixed_div(a, sclk); 1032 read_delay_latency.full = dfixed_const(1000); 1033 1034 /* Determine the worst case latency 1035 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 1036 * WorstCaseLatency = worst case time from urgent to when the MC starts 1037 * to return data 1038 * READ_DELAY_IDLE_MAX = constant of 1us 1039 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 1040 * which consists of pipeline delay and inter chunk gap 1041 */ 1042 if (dfixed_trunc(wm->num_line_pair) > 1) { 1043 a.full = dfixed_const(3); 1044 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 1045 wm->worst_case_latency.full += read_delay_latency.full; 1046 } else { 1047 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 1048 } 1049 1050 /* Determine the tolerable latency 1051 * TolerableLatency = Any given request has only 1 line time 1052 * for the data to be returned 1053 * LBRequestFifoDepth = Number of chunk requests the LB can 1054 * put into the request FIFO for a display 1055 * LineTime = total time for one line of display 1056 * ChunkTime = the time it takes the DCP to send one chunk 1057 * of data to the LB which consists of 1058 * pipeline delay and inter chunk gap 1059 */ 1060 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 1061 tolerable_latency.full = line_time.full; 1062 } else { 1063 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 1064 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 1065 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 1066 tolerable_latency.full = line_time.full - tolerable_latency.full; 1067 } 1068 /* We assume worst case 32bits (4 bytes) */ 1069 wm->dbpp.full = dfixed_const(2 * 16); 1070 1071 /* Determine the maximum priority mark 1072 * width = viewport width in pixels 1073 */ 1074 a.full = dfixed_const(16); 1075 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1076 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 1077 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1078 1079 /* Determine estimated width */ 1080 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 1081 estimated_width.full = dfixed_div(estimated_width, consumption_time); 1082 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 1083 wm->priority_mark.full = wm->priority_mark_max.full; 1084 } else { 1085 a.full = dfixed_const(16); 1086 wm->priority_mark.full = dfixed_div(estimated_width, a); 1087 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1088 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1089 } 1090 } 1091 1092 static void rv515_compute_mode_priority(struct radeon_device *rdev, 1093 struct rv515_watermark *wm0, 1094 struct rv515_watermark *wm1, 1095 struct drm_display_mode *mode0, 1096 struct drm_display_mode *mode1, 1097 u32 *d1mode_priority_a_cnt, 1098 u32 *d2mode_priority_a_cnt) 1099 { 1100 fixed20_12 priority_mark02, priority_mark12, fill_rate; 1101 fixed20_12 a, b; 1102 1103 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 1104 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 1105 1106 if (mode0 && mode1) { 1107 if (dfixed_trunc(wm0->dbpp) > 64) 1108 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1109 else 1110 a.full = wm0->num_line_pair.full; 1111 if (dfixed_trunc(wm1->dbpp) > 64) 1112 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1113 else 1114 b.full = wm1->num_line_pair.full; 1115 a.full += b.full; 1116 fill_rate.full = dfixed_div(wm0->sclk, a); 1117 if (wm0->consumption_rate.full > fill_rate.full) { 1118 b.full = wm0->consumption_rate.full - fill_rate.full; 1119 b.full = dfixed_mul(b, wm0->active_time); 1120 a.full = dfixed_const(16); 1121 b.full = dfixed_div(b, a); 1122 a.full = dfixed_mul(wm0->worst_case_latency, 1123 wm0->consumption_rate); 1124 priority_mark02.full = a.full + b.full; 1125 } else { 1126 a.full = dfixed_mul(wm0->worst_case_latency, 1127 wm0->consumption_rate); 1128 b.full = dfixed_const(16 * 1000); 1129 priority_mark02.full = dfixed_div(a, b); 1130 } 1131 if (wm1->consumption_rate.full > fill_rate.full) { 1132 b.full = wm1->consumption_rate.full - fill_rate.full; 1133 b.full = dfixed_mul(b, wm1->active_time); 1134 a.full = dfixed_const(16); 1135 b.full = dfixed_div(b, a); 1136 a.full = dfixed_mul(wm1->worst_case_latency, 1137 wm1->consumption_rate); 1138 priority_mark12.full = a.full + b.full; 1139 } else { 1140 a.full = dfixed_mul(wm1->worst_case_latency, 1141 wm1->consumption_rate); 1142 b.full = dfixed_const(16 * 1000); 1143 priority_mark12.full = dfixed_div(a, b); 1144 } 1145 if (wm0->priority_mark.full > priority_mark02.full) 1146 priority_mark02.full = wm0->priority_mark.full; 1147 if (dfixed_trunc(priority_mark02) < 0) 1148 priority_mark02.full = 0; 1149 if (wm0->priority_mark_max.full > priority_mark02.full) 1150 priority_mark02.full = wm0->priority_mark_max.full; 1151 if (wm1->priority_mark.full > priority_mark12.full) 1152 priority_mark12.full = wm1->priority_mark.full; 1153 if (dfixed_trunc(priority_mark12) < 0) 1154 priority_mark12.full = 0; 1155 if (wm1->priority_mark_max.full > priority_mark12.full) 1156 priority_mark12.full = wm1->priority_mark_max.full; 1157 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1158 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1159 if (rdev->disp_priority == 2) { 1160 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1161 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1162 } 1163 } else if (mode0) { 1164 if (dfixed_trunc(wm0->dbpp) > 64) 1165 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1166 else 1167 a.full = wm0->num_line_pair.full; 1168 fill_rate.full = dfixed_div(wm0->sclk, a); 1169 if (wm0->consumption_rate.full > fill_rate.full) { 1170 b.full = wm0->consumption_rate.full - fill_rate.full; 1171 b.full = dfixed_mul(b, wm0->active_time); 1172 a.full = dfixed_const(16); 1173 b.full = dfixed_div(b, a); 1174 a.full = dfixed_mul(wm0->worst_case_latency, 1175 wm0->consumption_rate); 1176 priority_mark02.full = a.full + b.full; 1177 } else { 1178 a.full = dfixed_mul(wm0->worst_case_latency, 1179 wm0->consumption_rate); 1180 b.full = dfixed_const(16); 1181 priority_mark02.full = dfixed_div(a, b); 1182 } 1183 if (wm0->priority_mark.full > priority_mark02.full) 1184 priority_mark02.full = wm0->priority_mark.full; 1185 if (dfixed_trunc(priority_mark02) < 0) 1186 priority_mark02.full = 0; 1187 if (wm0->priority_mark_max.full > priority_mark02.full) 1188 priority_mark02.full = wm0->priority_mark_max.full; 1189 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1190 if (rdev->disp_priority == 2) 1191 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1192 } else if (mode1) { 1193 if (dfixed_trunc(wm1->dbpp) > 64) 1194 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1195 else 1196 a.full = wm1->num_line_pair.full; 1197 fill_rate.full = dfixed_div(wm1->sclk, a); 1198 if (wm1->consumption_rate.full > fill_rate.full) { 1199 b.full = wm1->consumption_rate.full - fill_rate.full; 1200 b.full = dfixed_mul(b, wm1->active_time); 1201 a.full = dfixed_const(16); 1202 b.full = dfixed_div(b, a); 1203 a.full = dfixed_mul(wm1->worst_case_latency, 1204 wm1->consumption_rate); 1205 priority_mark12.full = a.full + b.full; 1206 } else { 1207 a.full = dfixed_mul(wm1->worst_case_latency, 1208 wm1->consumption_rate); 1209 b.full = dfixed_const(16 * 1000); 1210 priority_mark12.full = dfixed_div(a, b); 1211 } 1212 if (wm1->priority_mark.full > priority_mark12.full) 1213 priority_mark12.full = wm1->priority_mark.full; 1214 if (dfixed_trunc(priority_mark12) < 0) 1215 priority_mark12.full = 0; 1216 if (wm1->priority_mark_max.full > priority_mark12.full) 1217 priority_mark12.full = wm1->priority_mark_max.full; 1218 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1219 if (rdev->disp_priority == 2) 1220 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1221 } 1222 } 1223 1224 void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1225 { 1226 struct drm_display_mode *mode0 = NULL; 1227 struct drm_display_mode *mode1 = NULL; 1228 struct rv515_watermark wm0_high, wm0_low; 1229 struct rv515_watermark wm1_high, wm1_low; 1230 u32 tmp; 1231 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 1232 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 1233 1234 if (rdev->mode_info.crtcs[0]->base.enabled) 1235 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1236 if (rdev->mode_info.crtcs[1]->base.enabled) 1237 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1238 rs690_line_buffer_adjust(rdev, mode0, mode1); 1239 1240 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 1241 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 1242 1243 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); 1244 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); 1245 1246 tmp = wm0_high.lb_request_fifo_depth; 1247 tmp |= wm1_high.lb_request_fifo_depth << 16; 1248 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1249 1250 rv515_compute_mode_priority(rdev, 1251 &wm0_high, &wm1_high, 1252 mode0, mode1, 1253 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 1254 rv515_compute_mode_priority(rdev, 1255 &wm0_low, &wm1_low, 1256 mode0, mode1, 1257 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 1258 1259 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1260 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 1261 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1262 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 1263 } 1264 1265 void rv515_bandwidth_update(struct radeon_device *rdev) 1266 { 1267 uint32_t tmp; 1268 struct drm_display_mode *mode0 = NULL; 1269 struct drm_display_mode *mode1 = NULL; 1270 1271 radeon_update_display_priority(rdev); 1272 1273 if (rdev->mode_info.crtcs[0]->base.enabled) 1274 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1275 if (rdev->mode_info.crtcs[1]->base.enabled) 1276 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1277 /* 1278 * Set display0/1 priority up in the memory controller for 1279 * modes if the user specifies HIGH for displaypriority 1280 * option. 1281 */ 1282 if ((rdev->disp_priority == 2) && 1283 (rdev->family == CHIP_RV515)) { 1284 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1285 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1286 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1287 if (mode1) 1288 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1289 if (mode0) 1290 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1291 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1292 } 1293 rv515_bandwidth_avivo_update(rdev); 1294 } 1295