1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/rv515.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "rv515d.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 #include "rv515_reg_safe.h" 37 38 /* This files gather functions specifics to: rv515 */ 39 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 40 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 41 static void rv515_gpu_init(struct radeon_device *rdev); 42 43 static const u32 crtc_offsets[2] = 44 { 45 0, 46 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 47 }; 48 49 void rv515_debugfs(struct radeon_device *rdev) 50 { 51 if (r100_debugfs_rbbm_init(rdev)) { 52 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 53 } 54 if (rv515_debugfs_pipes_info_init(rdev)) { 55 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 56 } 57 if (rv515_debugfs_ga_info_init(rdev)) { 58 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 59 } 60 } 61 62 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 63 { 64 int r; 65 66 r = radeon_ring_lock(rdev, ring, 64); 67 if (r) { 68 return; 69 } 70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 71 radeon_ring_write(ring, 72 ISYNC_ANY2D_IDLE3D | 73 ISYNC_ANY3D_IDLE2D | 74 ISYNC_WAIT_IDLEGUI | 75 ISYNC_CPSCRATCH_IDLEGUI); 76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 77 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 79 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 81 radeon_ring_write(ring, 0); 82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 83 radeon_ring_write(ring, 0); 84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 85 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 87 radeon_ring_write(ring, 0); 88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 89 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 91 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 93 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 94 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 95 radeon_ring_write(ring, 0); 96 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 97 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 98 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 99 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 100 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 101 radeon_ring_write(ring, 102 ((6 << MS_X0_SHIFT) | 103 (6 << MS_Y0_SHIFT) | 104 (6 << MS_X1_SHIFT) | 105 (6 << MS_Y1_SHIFT) | 106 (6 << MS_X2_SHIFT) | 107 (6 << MS_Y2_SHIFT) | 108 (6 << MSBD0_Y_SHIFT) | 109 (6 << MSBD0_X_SHIFT))); 110 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 111 radeon_ring_write(ring, 112 ((6 << MS_X3_SHIFT) | 113 (6 << MS_Y3_SHIFT) | 114 (6 << MS_X4_SHIFT) | 115 (6 << MS_Y4_SHIFT) | 116 (6 << MS_X5_SHIFT) | 117 (6 << MS_Y5_SHIFT) | 118 (6 << MSBD1_SHIFT))); 119 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 120 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 121 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 122 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 123 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 124 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 125 radeon_ring_write(ring, PACKET0(0x20C8, 0)); 126 radeon_ring_write(ring, 0); 127 radeon_ring_unlock_commit(rdev, ring); 128 } 129 130 int rv515_mc_wait_for_idle(struct radeon_device *rdev) 131 { 132 unsigned i; 133 uint32_t tmp; 134 135 for (i = 0; i < rdev->usec_timeout; i++) { 136 /* read MC_STATUS */ 137 tmp = RREG32_MC(MC_STATUS); 138 if (tmp & MC_STATUS_IDLE) { 139 return 0; 140 } 141 DRM_UDELAY(1); 142 } 143 return -1; 144 } 145 146 void rv515_vga_render_disable(struct radeon_device *rdev) 147 { 148 WREG32(R_000300_VGA_RENDER_CONTROL, 149 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 150 } 151 152 static void rv515_gpu_init(struct radeon_device *rdev) 153 { 154 unsigned pipe_select_current, gb_pipe_select, tmp; 155 156 if (r100_gui_wait_for_idle(rdev)) { 157 DRM_ERROR("Failed to wait GUI idle while " 158 "resetting GPU. Bad things might happen.\n"); 159 } 160 rv515_vga_render_disable(rdev); 161 r420_pipes_init(rdev); 162 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 163 tmp = RREG32(R300_DST_PIPE_CONFIG); 164 pipe_select_current = (tmp >> 2) & 3; 165 tmp = (1 << pipe_select_current) | 166 (((gb_pipe_select >> 8) & 0xF) << 4); 167 WREG32_PLL(0x000D, tmp); 168 if (r100_gui_wait_for_idle(rdev)) { 169 DRM_ERROR("Failed to wait GUI idle while " 170 "resetting GPU. Bad things might happen.\n"); 171 } 172 if (rv515_mc_wait_for_idle(rdev)) { 173 DRM_ERROR("Failed to wait MC idle while " 174 "programming pipes. Bad things might happen.\n"); 175 } 176 } 177 178 static void rv515_vram_get_type(struct radeon_device *rdev) 179 { 180 uint32_t tmp; 181 182 rdev->mc.vram_width = 128; 183 rdev->mc.vram_is_ddr = true; 184 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 185 switch (tmp) { 186 case 0: 187 rdev->mc.vram_width = 64; 188 break; 189 case 1: 190 rdev->mc.vram_width = 128; 191 break; 192 default: 193 rdev->mc.vram_width = 128; 194 break; 195 } 196 } 197 198 static void rv515_mc_init(struct radeon_device *rdev) 199 { 200 201 rv515_vram_get_type(rdev); 202 r100_vram_init_sizes(rdev); 203 radeon_vram_location(rdev, &rdev->mc, 0); 204 rdev->mc.gtt_base_align = 0; 205 if (!(rdev->flags & RADEON_IS_AGP)) 206 radeon_gtt_location(rdev, &rdev->mc); 207 radeon_update_bandwidth_info(rdev); 208 } 209 210 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 211 { 212 uint32_t r; 213 214 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 215 r = RREG32(MC_IND_DATA); 216 WREG32(MC_IND_INDEX, 0); 217 return r; 218 } 219 220 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 221 { 222 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 223 WREG32(MC_IND_DATA, (v)); 224 WREG32(MC_IND_INDEX, 0); 225 } 226 227 #if defined(CONFIG_DEBUG_FS) 228 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 229 { 230 struct drm_info_node *node = (struct drm_info_node *) m->private; 231 struct drm_device *dev = node->minor->dev; 232 struct radeon_device *rdev = dev->dev_private; 233 uint32_t tmp; 234 235 tmp = RREG32(GB_PIPE_SELECT); 236 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 237 tmp = RREG32(SU_REG_DEST); 238 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 239 tmp = RREG32(GB_TILE_CONFIG); 240 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 241 tmp = RREG32(DST_PIPE_CONFIG); 242 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 243 return 0; 244 } 245 246 static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 247 { 248 struct drm_info_node *node = (struct drm_info_node *) m->private; 249 struct drm_device *dev = node->minor->dev; 250 struct radeon_device *rdev = dev->dev_private; 251 uint32_t tmp; 252 253 tmp = RREG32(0x2140); 254 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 255 radeon_asic_reset(rdev); 256 tmp = RREG32(0x425C); 257 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 258 return 0; 259 } 260 261 static struct drm_info_list rv515_pipes_info_list[] = { 262 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 263 }; 264 265 static struct drm_info_list rv515_ga_info_list[] = { 266 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 267 }; 268 #endif 269 270 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 271 { 272 #if defined(CONFIG_DEBUG_FS) 273 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 274 #else 275 return 0; 276 #endif 277 } 278 279 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 280 { 281 #if defined(CONFIG_DEBUG_FS) 282 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 283 #else 284 return 0; 285 #endif 286 } 287 288 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 289 { 290 u32 crtc_enabled, tmp, frame_count, blackout; 291 int i, j; 292 293 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 294 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 295 296 /* disable VGA render */ 297 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 298 /* blank the display controllers */ 299 for (i = 0; i < rdev->num_crtc; i++) { 300 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 301 if (crtc_enabled) { 302 save->crtc_enabled[i] = true; 303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 305 radeon_wait_for_vblank(rdev, i); 306 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 307 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 308 } 309 /* wait for the next frame */ 310 frame_count = radeon_get_vblank_counter(rdev, i); 311 for (j = 0; j < rdev->usec_timeout; j++) { 312 if (radeon_get_vblank_counter(rdev, i) != frame_count) 313 break; 314 DRM_UDELAY(1); 315 } 316 } else { 317 save->crtc_enabled[i] = false; 318 } 319 } 320 321 radeon_mc_wait_for_idle(rdev); 322 323 if (rdev->family >= CHIP_R600) { 324 if (rdev->family >= CHIP_RV770) 325 blackout = RREG32(R700_MC_CITF_CNTL); 326 else 327 blackout = RREG32(R600_CITF_CNTL); 328 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 329 /* Block CPU access */ 330 WREG32(R600_BIF_FB_EN, 0); 331 /* blackout the MC */ 332 blackout |= R600_BLACKOUT_MASK; 333 if (rdev->family >= CHIP_RV770) 334 WREG32(R700_MC_CITF_CNTL, blackout); 335 else 336 WREG32(R600_CITF_CNTL, blackout); 337 } 338 } 339 /* wait for the MC to settle */ 340 DRM_UDELAY(100); 341 } 342 343 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 344 { 345 u32 tmp, frame_count; 346 int i, j; 347 348 /* update crtc base addresses */ 349 for (i = 0; i < rdev->num_crtc; i++) { 350 if (rdev->family >= CHIP_RV770) { 351 if (i == 1) { 352 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 353 upper_32_bits(rdev->mc.vram_start)); 354 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 355 upper_32_bits(rdev->mc.vram_start)); 356 } else { 357 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 358 upper_32_bits(rdev->mc.vram_start)); 359 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 360 upper_32_bits(rdev->mc.vram_start)); 361 } 362 } 363 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 364 (u32)rdev->mc.vram_start); 365 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 366 (u32)rdev->mc.vram_start); 367 } 368 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 369 370 if (rdev->family >= CHIP_R600) { 371 /* unblackout the MC */ 372 if (rdev->family >= CHIP_RV770) 373 tmp = RREG32(R700_MC_CITF_CNTL); 374 else 375 tmp = RREG32(R600_CITF_CNTL); 376 tmp &= ~R600_BLACKOUT_MASK; 377 if (rdev->family >= CHIP_RV770) 378 WREG32(R700_MC_CITF_CNTL, tmp); 379 else 380 WREG32(R600_CITF_CNTL, tmp); 381 /* allow CPU access */ 382 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 383 } 384 385 for (i = 0; i < rdev->num_crtc; i++) { 386 if (save->crtc_enabled[i]) { 387 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 388 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 389 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 390 /* wait for the next frame */ 391 frame_count = radeon_get_vblank_counter(rdev, i); 392 for (j = 0; j < rdev->usec_timeout; j++) { 393 if (radeon_get_vblank_counter(rdev, i) != frame_count) 394 break; 395 DRM_UDELAY(1); 396 } 397 } 398 } 399 /* Unlock vga access */ 400 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 401 DRM_MDELAY(1); 402 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 403 } 404 405 static void rv515_mc_program(struct radeon_device *rdev) 406 { 407 struct rv515_mc_save save; 408 409 /* Stops all mc clients */ 410 rv515_mc_stop(rdev, &save); 411 412 /* Wait for mc idle */ 413 if (rv515_mc_wait_for_idle(rdev)) 414 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 415 /* Write VRAM size in case we are limiting it */ 416 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 417 /* Program MC, should be a 32bits limited address space */ 418 WREG32_MC(R_000001_MC_FB_LOCATION, 419 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 420 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 421 WREG32(R_000134_HDP_FB_LOCATION, 422 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 423 if (rdev->flags & RADEON_IS_AGP) { 424 WREG32_MC(R_000002_MC_AGP_LOCATION, 425 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 426 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 427 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 428 WREG32_MC(R_000004_MC_AGP_BASE_2, 429 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 430 } else { 431 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 432 WREG32_MC(R_000003_MC_AGP_BASE, 0); 433 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 434 } 435 436 rv515_mc_resume(rdev, &save); 437 } 438 439 void rv515_clock_startup(struct radeon_device *rdev) 440 { 441 if (radeon_dynclks != -1 && radeon_dynclks) 442 radeon_atom_set_clock_gating(rdev, 1); 443 /* We need to force on some of the block */ 444 WREG32_PLL(R_00000F_CP_DYN_CNTL, 445 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 446 WREG32_PLL(R_000011_E2_DYN_CNTL, 447 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 448 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 449 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 450 } 451 452 static int rv515_startup(struct radeon_device *rdev) 453 { 454 int r; 455 456 rv515_mc_program(rdev); 457 /* Resume clock */ 458 rv515_clock_startup(rdev); 459 /* Initialize GPU configuration (# pipes, ...) */ 460 rv515_gpu_init(rdev); 461 /* Initialize GART (initialize after TTM so we can allocate 462 * memory through TTM but finalize after TTM) */ 463 if (rdev->flags & RADEON_IS_PCIE) { 464 r = rv370_pcie_gart_enable(rdev); 465 if (r) 466 return r; 467 } 468 469 /* allocate wb buffer */ 470 r = radeon_wb_init(rdev); 471 if (r) 472 return r; 473 474 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 475 if (r) { 476 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 477 return r; 478 } 479 480 /* Enable IRQ */ 481 rs600_irq_set(rdev); 482 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 483 /* 1M ring buffer */ 484 r = r100_cp_init(rdev, 1024 * 1024); 485 if (r) { 486 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 487 return r; 488 } 489 490 r = radeon_ib_pool_init(rdev); 491 if (r) { 492 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 493 return r; 494 } 495 496 return 0; 497 } 498 499 int rv515_resume(struct radeon_device *rdev) 500 { 501 int r; 502 503 /* Make sur GART are not working */ 504 if (rdev->flags & RADEON_IS_PCIE) 505 rv370_pcie_gart_disable(rdev); 506 /* Resume clock before doing reset */ 507 rv515_clock_startup(rdev); 508 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 509 if (radeon_asic_reset(rdev)) { 510 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 511 RREG32(R_000E40_RBBM_STATUS), 512 RREG32(R_0007C0_CP_STAT)); 513 } 514 /* post */ 515 atom_asic_init(rdev->mode_info.atom_context); 516 /* Resume clock after posting */ 517 rv515_clock_startup(rdev); 518 /* Initialize surface registers */ 519 radeon_surface_init(rdev); 520 521 rdev->accel_working = true; 522 r = rv515_startup(rdev); 523 if (r) { 524 rdev->accel_working = false; 525 } 526 return r; 527 } 528 529 int rv515_suspend(struct radeon_device *rdev) 530 { 531 r100_cp_disable(rdev); 532 radeon_wb_disable(rdev); 533 rs600_irq_disable(rdev); 534 if (rdev->flags & RADEON_IS_PCIE) 535 rv370_pcie_gart_disable(rdev); 536 return 0; 537 } 538 539 void rv515_set_safe_registers(struct radeon_device *rdev) 540 { 541 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 542 rdev->config.r300.reg_safe_bm_size = DRM_ARRAY_SIZE(rv515_reg_safe_bm); 543 } 544 545 void rv515_fini(struct radeon_device *rdev) 546 { 547 r100_cp_fini(rdev); 548 radeon_wb_fini(rdev); 549 radeon_ib_pool_fini(rdev); 550 radeon_gem_fini(rdev); 551 rv370_pcie_gart_fini(rdev); 552 radeon_agp_fini(rdev); 553 radeon_irq_kms_fini(rdev); 554 radeon_fence_driver_fini(rdev); 555 radeon_bo_fini(rdev); 556 radeon_atombios_fini(rdev); 557 drm_free(rdev->bios, DRM_MEM_DRIVER); 558 rdev->bios = NULL; 559 } 560 561 int rv515_init(struct radeon_device *rdev) 562 { 563 int r; 564 565 /* Initialize scratch registers */ 566 radeon_scratch_init(rdev); 567 /* Initialize surface registers */ 568 radeon_surface_init(rdev); 569 /* TODO: disable VGA need to use VGA request */ 570 /* restore some register to sane defaults */ 571 r100_restore_sanity(rdev); 572 /* BIOS*/ 573 if (!radeon_get_bios(rdev)) { 574 if (ASIC_IS_AVIVO(rdev)) 575 return -EINVAL; 576 } 577 if (rdev->is_atom_bios) { 578 r = radeon_atombios_init(rdev); 579 if (r) 580 return r; 581 } else { 582 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 583 return -EINVAL; 584 } 585 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 586 if (radeon_asic_reset(rdev)) { 587 dev_warn(rdev->dev, 588 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 589 RREG32(R_000E40_RBBM_STATUS), 590 RREG32(R_0007C0_CP_STAT)); 591 } 592 /* check if cards are posted or not */ 593 if (radeon_boot_test_post_card(rdev) == false) 594 return -EINVAL; 595 /* Initialize clocks */ 596 radeon_get_clock_info(rdev->ddev); 597 /* initialize AGP */ 598 if (rdev->flags & RADEON_IS_AGP) { 599 r = radeon_agp_init(rdev); 600 if (r) { 601 radeon_agp_disable(rdev); 602 } 603 } 604 /* initialize memory controller */ 605 rv515_mc_init(rdev); 606 rv515_debugfs(rdev); 607 /* Fence driver */ 608 r = radeon_fence_driver_init(rdev); 609 if (r) 610 return r; 611 r = radeon_irq_kms_init(rdev); 612 if (r) 613 return r; 614 /* Memory manager */ 615 r = radeon_bo_init(rdev); 616 if (r) 617 return r; 618 r = rv370_pcie_gart_init(rdev); 619 if (r) 620 return r; 621 rv515_set_safe_registers(rdev); 622 623 rdev->accel_working = true; 624 r = rv515_startup(rdev); 625 if (r) { 626 /* Somethings want wront with the accel init stop accel */ 627 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 628 r100_cp_fini(rdev); 629 radeon_wb_fini(rdev); 630 radeon_ib_pool_fini(rdev); 631 radeon_irq_kms_fini(rdev); 632 rv370_pcie_gart_fini(rdev); 633 radeon_agp_fini(rdev); 634 rdev->accel_working = false; 635 } 636 return 0; 637 } 638 639 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 640 { 641 int index_reg = 0x6578 + crtc->crtc_offset; 642 int data_reg = 0x657c + crtc->crtc_offset; 643 644 WREG32(0x659C + crtc->crtc_offset, 0x0); 645 WREG32(0x6594 + crtc->crtc_offset, 0x705); 646 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 647 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 648 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 649 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 650 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 651 WREG32(index_reg, 0x0); 652 WREG32(data_reg, 0x841880A8); 653 WREG32(index_reg, 0x1); 654 WREG32(data_reg, 0x84208680); 655 WREG32(index_reg, 0x2); 656 WREG32(data_reg, 0xBFF880B0); 657 WREG32(index_reg, 0x100); 658 WREG32(data_reg, 0x83D88088); 659 WREG32(index_reg, 0x101); 660 WREG32(data_reg, 0x84608680); 661 WREG32(index_reg, 0x102); 662 WREG32(data_reg, 0xBFF080D0); 663 WREG32(index_reg, 0x200); 664 WREG32(data_reg, 0x83988068); 665 WREG32(index_reg, 0x201); 666 WREG32(data_reg, 0x84A08680); 667 WREG32(index_reg, 0x202); 668 WREG32(data_reg, 0xBFF080F8); 669 WREG32(index_reg, 0x300); 670 WREG32(data_reg, 0x83588058); 671 WREG32(index_reg, 0x301); 672 WREG32(data_reg, 0x84E08660); 673 WREG32(index_reg, 0x302); 674 WREG32(data_reg, 0xBFF88120); 675 WREG32(index_reg, 0x400); 676 WREG32(data_reg, 0x83188040); 677 WREG32(index_reg, 0x401); 678 WREG32(data_reg, 0x85008660); 679 WREG32(index_reg, 0x402); 680 WREG32(data_reg, 0xBFF88150); 681 WREG32(index_reg, 0x500); 682 WREG32(data_reg, 0x82D88030); 683 WREG32(index_reg, 0x501); 684 WREG32(data_reg, 0x85408640); 685 WREG32(index_reg, 0x502); 686 WREG32(data_reg, 0xBFF88180); 687 WREG32(index_reg, 0x600); 688 WREG32(data_reg, 0x82A08018); 689 WREG32(index_reg, 0x601); 690 WREG32(data_reg, 0x85808620); 691 WREG32(index_reg, 0x602); 692 WREG32(data_reg, 0xBFF081B8); 693 WREG32(index_reg, 0x700); 694 WREG32(data_reg, 0x82608010); 695 WREG32(index_reg, 0x701); 696 WREG32(data_reg, 0x85A08600); 697 WREG32(index_reg, 0x702); 698 WREG32(data_reg, 0x800081F0); 699 WREG32(index_reg, 0x800); 700 WREG32(data_reg, 0x8228BFF8); 701 WREG32(index_reg, 0x801); 702 WREG32(data_reg, 0x85E085E0); 703 WREG32(index_reg, 0x802); 704 WREG32(data_reg, 0xBFF88228); 705 WREG32(index_reg, 0x10000); 706 WREG32(data_reg, 0x82A8BF00); 707 WREG32(index_reg, 0x10001); 708 WREG32(data_reg, 0x82A08CC0); 709 WREG32(index_reg, 0x10002); 710 WREG32(data_reg, 0x8008BEF8); 711 WREG32(index_reg, 0x10100); 712 WREG32(data_reg, 0x81F0BF28); 713 WREG32(index_reg, 0x10101); 714 WREG32(data_reg, 0x83608CA0); 715 WREG32(index_reg, 0x10102); 716 WREG32(data_reg, 0x8018BED0); 717 WREG32(index_reg, 0x10200); 718 WREG32(data_reg, 0x8148BF38); 719 WREG32(index_reg, 0x10201); 720 WREG32(data_reg, 0x84408C80); 721 WREG32(index_reg, 0x10202); 722 WREG32(data_reg, 0x8008BEB8); 723 WREG32(index_reg, 0x10300); 724 WREG32(data_reg, 0x80B0BF78); 725 WREG32(index_reg, 0x10301); 726 WREG32(data_reg, 0x85008C20); 727 WREG32(index_reg, 0x10302); 728 WREG32(data_reg, 0x8020BEA0); 729 WREG32(index_reg, 0x10400); 730 WREG32(data_reg, 0x8028BF90); 731 WREG32(index_reg, 0x10401); 732 WREG32(data_reg, 0x85E08BC0); 733 WREG32(index_reg, 0x10402); 734 WREG32(data_reg, 0x8018BE90); 735 WREG32(index_reg, 0x10500); 736 WREG32(data_reg, 0xBFB8BFB0); 737 WREG32(index_reg, 0x10501); 738 WREG32(data_reg, 0x86C08B40); 739 WREG32(index_reg, 0x10502); 740 WREG32(data_reg, 0x8010BE90); 741 WREG32(index_reg, 0x10600); 742 WREG32(data_reg, 0xBF58BFC8); 743 WREG32(index_reg, 0x10601); 744 WREG32(data_reg, 0x87A08AA0); 745 WREG32(index_reg, 0x10602); 746 WREG32(data_reg, 0x8010BE98); 747 WREG32(index_reg, 0x10700); 748 WREG32(data_reg, 0xBF10BFF0); 749 WREG32(index_reg, 0x10701); 750 WREG32(data_reg, 0x886089E0); 751 WREG32(index_reg, 0x10702); 752 WREG32(data_reg, 0x8018BEB0); 753 WREG32(index_reg, 0x10800); 754 WREG32(data_reg, 0xBED8BFE8); 755 WREG32(index_reg, 0x10801); 756 WREG32(data_reg, 0x89408940); 757 WREG32(index_reg, 0x10802); 758 WREG32(data_reg, 0xBFE8BED8); 759 WREG32(index_reg, 0x20000); 760 WREG32(data_reg, 0x80008000); 761 WREG32(index_reg, 0x20001); 762 WREG32(data_reg, 0x90008000); 763 WREG32(index_reg, 0x20002); 764 WREG32(data_reg, 0x80008000); 765 WREG32(index_reg, 0x20003); 766 WREG32(data_reg, 0x80008000); 767 WREG32(index_reg, 0x20100); 768 WREG32(data_reg, 0x80108000); 769 WREG32(index_reg, 0x20101); 770 WREG32(data_reg, 0x8FE0BF70); 771 WREG32(index_reg, 0x20102); 772 WREG32(data_reg, 0xBFE880C0); 773 WREG32(index_reg, 0x20103); 774 WREG32(data_reg, 0x80008000); 775 WREG32(index_reg, 0x20200); 776 WREG32(data_reg, 0x8018BFF8); 777 WREG32(index_reg, 0x20201); 778 WREG32(data_reg, 0x8F80BF08); 779 WREG32(index_reg, 0x20202); 780 WREG32(data_reg, 0xBFD081A0); 781 WREG32(index_reg, 0x20203); 782 WREG32(data_reg, 0xBFF88000); 783 WREG32(index_reg, 0x20300); 784 WREG32(data_reg, 0x80188000); 785 WREG32(index_reg, 0x20301); 786 WREG32(data_reg, 0x8EE0BEC0); 787 WREG32(index_reg, 0x20302); 788 WREG32(data_reg, 0xBFB082A0); 789 WREG32(index_reg, 0x20303); 790 WREG32(data_reg, 0x80008000); 791 WREG32(index_reg, 0x20400); 792 WREG32(data_reg, 0x80188000); 793 WREG32(index_reg, 0x20401); 794 WREG32(data_reg, 0x8E00BEA0); 795 WREG32(index_reg, 0x20402); 796 WREG32(data_reg, 0xBF8883C0); 797 WREG32(index_reg, 0x20403); 798 WREG32(data_reg, 0x80008000); 799 WREG32(index_reg, 0x20500); 800 WREG32(data_reg, 0x80188000); 801 WREG32(index_reg, 0x20501); 802 WREG32(data_reg, 0x8D00BE90); 803 WREG32(index_reg, 0x20502); 804 WREG32(data_reg, 0xBF588500); 805 WREG32(index_reg, 0x20503); 806 WREG32(data_reg, 0x80008008); 807 WREG32(index_reg, 0x20600); 808 WREG32(data_reg, 0x80188000); 809 WREG32(index_reg, 0x20601); 810 WREG32(data_reg, 0x8BC0BE98); 811 WREG32(index_reg, 0x20602); 812 WREG32(data_reg, 0xBF308660); 813 WREG32(index_reg, 0x20603); 814 WREG32(data_reg, 0x80008008); 815 WREG32(index_reg, 0x20700); 816 WREG32(data_reg, 0x80108000); 817 WREG32(index_reg, 0x20701); 818 WREG32(data_reg, 0x8A80BEB0); 819 WREG32(index_reg, 0x20702); 820 WREG32(data_reg, 0xBF0087C0); 821 WREG32(index_reg, 0x20703); 822 WREG32(data_reg, 0x80008008); 823 WREG32(index_reg, 0x20800); 824 WREG32(data_reg, 0x80108000); 825 WREG32(index_reg, 0x20801); 826 WREG32(data_reg, 0x8920BED0); 827 WREG32(index_reg, 0x20802); 828 WREG32(data_reg, 0xBED08920); 829 WREG32(index_reg, 0x20803); 830 WREG32(data_reg, 0x80008010); 831 WREG32(index_reg, 0x30000); 832 WREG32(data_reg, 0x90008000); 833 WREG32(index_reg, 0x30001); 834 WREG32(data_reg, 0x80008000); 835 WREG32(index_reg, 0x30100); 836 WREG32(data_reg, 0x8FE0BF90); 837 WREG32(index_reg, 0x30101); 838 WREG32(data_reg, 0xBFF880A0); 839 WREG32(index_reg, 0x30200); 840 WREG32(data_reg, 0x8F60BF40); 841 WREG32(index_reg, 0x30201); 842 WREG32(data_reg, 0xBFE88180); 843 WREG32(index_reg, 0x30300); 844 WREG32(data_reg, 0x8EC0BF00); 845 WREG32(index_reg, 0x30301); 846 WREG32(data_reg, 0xBFC88280); 847 WREG32(index_reg, 0x30400); 848 WREG32(data_reg, 0x8DE0BEE0); 849 WREG32(index_reg, 0x30401); 850 WREG32(data_reg, 0xBFA083A0); 851 WREG32(index_reg, 0x30500); 852 WREG32(data_reg, 0x8CE0BED0); 853 WREG32(index_reg, 0x30501); 854 WREG32(data_reg, 0xBF7884E0); 855 WREG32(index_reg, 0x30600); 856 WREG32(data_reg, 0x8BA0BED8); 857 WREG32(index_reg, 0x30601); 858 WREG32(data_reg, 0xBF508640); 859 WREG32(index_reg, 0x30700); 860 WREG32(data_reg, 0x8A60BEE8); 861 WREG32(index_reg, 0x30701); 862 WREG32(data_reg, 0xBF2087A0); 863 WREG32(index_reg, 0x30800); 864 WREG32(data_reg, 0x8900BF00); 865 WREG32(index_reg, 0x30801); 866 WREG32(data_reg, 0xBF008900); 867 } 868 869 struct rv515_watermark { 870 u32 lb_request_fifo_depth; 871 fixed20_12 num_line_pair; 872 fixed20_12 estimated_width; 873 fixed20_12 worst_case_latency; 874 fixed20_12 consumption_rate; 875 fixed20_12 active_time; 876 fixed20_12 dbpp; 877 fixed20_12 priority_mark_max; 878 fixed20_12 priority_mark; 879 fixed20_12 sclk; 880 }; 881 882 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 883 struct radeon_crtc *crtc, 884 struct rv515_watermark *wm) 885 { 886 struct drm_display_mode *mode = &crtc->base.mode; 887 fixed20_12 a, b, c; 888 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 889 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 890 891 if (!crtc->base.enabled) { 892 /* FIXME: wouldn't it better to set priority mark to maximum */ 893 wm->lb_request_fifo_depth = 4; 894 return; 895 } 896 897 if (crtc->vsc.full > dfixed_const(2)) 898 wm->num_line_pair.full = dfixed_const(2); 899 else 900 wm->num_line_pair.full = dfixed_const(1); 901 902 b.full = dfixed_const(mode->crtc_hdisplay); 903 c.full = dfixed_const(256); 904 a.full = dfixed_div(b, c); 905 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 906 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 907 if (a.full < dfixed_const(4)) { 908 wm->lb_request_fifo_depth = 4; 909 } else { 910 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 911 } 912 913 /* Determine consumption rate 914 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 915 * vtaps = number of vertical taps, 916 * vsc = vertical scaling ratio, defined as source/destination 917 * hsc = horizontal scaling ration, defined as source/destination 918 */ 919 a.full = dfixed_const(mode->clock); 920 b.full = dfixed_const(1000); 921 a.full = dfixed_div(a, b); 922 pclk.full = dfixed_div(b, a); 923 if (crtc->rmx_type != RMX_OFF) { 924 b.full = dfixed_const(2); 925 if (crtc->vsc.full > b.full) 926 b.full = crtc->vsc.full; 927 b.full = dfixed_mul(b, crtc->hsc); 928 c.full = dfixed_const(2); 929 b.full = dfixed_div(b, c); 930 consumption_time.full = dfixed_div(pclk, b); 931 } else { 932 consumption_time.full = pclk.full; 933 } 934 a.full = dfixed_const(1); 935 wm->consumption_rate.full = dfixed_div(a, consumption_time); 936 937 938 /* Determine line time 939 * LineTime = total time for one line of displayhtotal 940 * LineTime = total number of horizontal pixels 941 * pclk = pixel clock period(ns) 942 */ 943 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 944 line_time.full = dfixed_mul(a, pclk); 945 946 /* Determine active time 947 * ActiveTime = time of active region of display within one line, 948 * hactive = total number of horizontal active pixels 949 * htotal = total number of horizontal pixels 950 */ 951 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 952 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 953 wm->active_time.full = dfixed_mul(line_time, b); 954 wm->active_time.full = dfixed_div(wm->active_time, a); 955 956 /* Determine chunk time 957 * ChunkTime = the time it takes the DCP to send one chunk of data 958 * to the LB which consists of pipeline delay and inter chunk gap 959 * sclk = system clock(Mhz) 960 */ 961 a.full = dfixed_const(600 * 1000); 962 chunk_time.full = dfixed_div(a, rdev->pm.sclk); 963 read_delay_latency.full = dfixed_const(1000); 964 965 /* Determine the worst case latency 966 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 967 * WorstCaseLatency = worst case time from urgent to when the MC starts 968 * to return data 969 * READ_DELAY_IDLE_MAX = constant of 1us 970 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 971 * which consists of pipeline delay and inter chunk gap 972 */ 973 if (dfixed_trunc(wm->num_line_pair) > 1) { 974 a.full = dfixed_const(3); 975 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 976 wm->worst_case_latency.full += read_delay_latency.full; 977 } else { 978 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 979 } 980 981 /* Determine the tolerable latency 982 * TolerableLatency = Any given request has only 1 line time 983 * for the data to be returned 984 * LBRequestFifoDepth = Number of chunk requests the LB can 985 * put into the request FIFO for a display 986 * LineTime = total time for one line of display 987 * ChunkTime = the time it takes the DCP to send one chunk 988 * of data to the LB which consists of 989 * pipeline delay and inter chunk gap 990 */ 991 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 992 tolerable_latency.full = line_time.full; 993 } else { 994 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 995 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 996 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 997 tolerable_latency.full = line_time.full - tolerable_latency.full; 998 } 999 /* We assume worst case 32bits (4 bytes) */ 1000 wm->dbpp.full = dfixed_const(2 * 16); 1001 1002 /* Determine the maximum priority mark 1003 * width = viewport width in pixels 1004 */ 1005 a.full = dfixed_const(16); 1006 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1007 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 1008 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1009 1010 /* Determine estimated width */ 1011 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 1012 estimated_width.full = dfixed_div(estimated_width, consumption_time); 1013 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 1014 wm->priority_mark.full = wm->priority_mark_max.full; 1015 } else { 1016 a.full = dfixed_const(16); 1017 wm->priority_mark.full = dfixed_div(estimated_width, a); 1018 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1019 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1020 } 1021 } 1022 1023 void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1024 { 1025 struct drm_display_mode *mode0 = NULL; 1026 struct drm_display_mode *mode1 = NULL; 1027 struct rv515_watermark wm0; 1028 struct rv515_watermark wm1; 1029 u32 tmp; 1030 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 1031 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 1032 fixed20_12 priority_mark02, priority_mark12, fill_rate; 1033 fixed20_12 a, b; 1034 1035 if (rdev->mode_info.crtcs[0]->base.enabled) 1036 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1037 if (rdev->mode_info.crtcs[1]->base.enabled) 1038 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1039 rs690_line_buffer_adjust(rdev, mode0, mode1); 1040 1041 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 1042 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 1043 1044 tmp = wm0.lb_request_fifo_depth; 1045 tmp |= wm1.lb_request_fifo_depth << 16; 1046 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1047 1048 if (mode0 && mode1) { 1049 if (dfixed_trunc(wm0.dbpp) > 64) 1050 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 1051 else 1052 a.full = wm0.num_line_pair.full; 1053 if (dfixed_trunc(wm1.dbpp) > 64) 1054 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 1055 else 1056 b.full = wm1.num_line_pair.full; 1057 a.full += b.full; 1058 fill_rate.full = dfixed_div(wm0.sclk, a); 1059 if (wm0.consumption_rate.full > fill_rate.full) { 1060 b.full = wm0.consumption_rate.full - fill_rate.full; 1061 b.full = dfixed_mul(b, wm0.active_time); 1062 a.full = dfixed_const(16); 1063 b.full = dfixed_div(b, a); 1064 a.full = dfixed_mul(wm0.worst_case_latency, 1065 wm0.consumption_rate); 1066 priority_mark02.full = a.full + b.full; 1067 } else { 1068 a.full = dfixed_mul(wm0.worst_case_latency, 1069 wm0.consumption_rate); 1070 b.full = dfixed_const(16 * 1000); 1071 priority_mark02.full = dfixed_div(a, b); 1072 } 1073 if (wm1.consumption_rate.full > fill_rate.full) { 1074 b.full = wm1.consumption_rate.full - fill_rate.full; 1075 b.full = dfixed_mul(b, wm1.active_time); 1076 a.full = dfixed_const(16); 1077 b.full = dfixed_div(b, a); 1078 a.full = dfixed_mul(wm1.worst_case_latency, 1079 wm1.consumption_rate); 1080 priority_mark12.full = a.full + b.full; 1081 } else { 1082 a.full = dfixed_mul(wm1.worst_case_latency, 1083 wm1.consumption_rate); 1084 b.full = dfixed_const(16 * 1000); 1085 priority_mark12.full = dfixed_div(a, b); 1086 } 1087 if (wm0.priority_mark.full > priority_mark02.full) 1088 priority_mark02.full = wm0.priority_mark.full; 1089 if (dfixed_trunc(priority_mark02) < 0) 1090 priority_mark02.full = 0; 1091 if (wm0.priority_mark_max.full > priority_mark02.full) 1092 priority_mark02.full = wm0.priority_mark_max.full; 1093 if (wm1.priority_mark.full > priority_mark12.full) 1094 priority_mark12.full = wm1.priority_mark.full; 1095 if (dfixed_trunc(priority_mark12) < 0) 1096 priority_mark12.full = 0; 1097 if (wm1.priority_mark_max.full > priority_mark12.full) 1098 priority_mark12.full = wm1.priority_mark_max.full; 1099 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1100 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1101 if (rdev->disp_priority == 2) { 1102 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1103 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1104 } 1105 } else if (mode0) { 1106 if (dfixed_trunc(wm0.dbpp) > 64) 1107 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 1108 else 1109 a.full = wm0.num_line_pair.full; 1110 fill_rate.full = dfixed_div(wm0.sclk, a); 1111 if (wm0.consumption_rate.full > fill_rate.full) { 1112 b.full = wm0.consumption_rate.full - fill_rate.full; 1113 b.full = dfixed_mul(b, wm0.active_time); 1114 a.full = dfixed_const(16); 1115 b.full = dfixed_div(b, a); 1116 a.full = dfixed_mul(wm0.worst_case_latency, 1117 wm0.consumption_rate); 1118 priority_mark02.full = a.full + b.full; 1119 } else { 1120 a.full = dfixed_mul(wm0.worst_case_latency, 1121 wm0.consumption_rate); 1122 b.full = dfixed_const(16); 1123 priority_mark02.full = dfixed_div(a, b); 1124 } 1125 if (wm0.priority_mark.full > priority_mark02.full) 1126 priority_mark02.full = wm0.priority_mark.full; 1127 if (dfixed_trunc(priority_mark02) < 0) 1128 priority_mark02.full = 0; 1129 if (wm0.priority_mark_max.full > priority_mark02.full) 1130 priority_mark02.full = wm0.priority_mark_max.full; 1131 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1132 if (rdev->disp_priority == 2) 1133 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1134 } else if (mode1) { 1135 if (dfixed_trunc(wm1.dbpp) > 64) 1136 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 1137 else 1138 a.full = wm1.num_line_pair.full; 1139 fill_rate.full = dfixed_div(wm1.sclk, a); 1140 if (wm1.consumption_rate.full > fill_rate.full) { 1141 b.full = wm1.consumption_rate.full - fill_rate.full; 1142 b.full = dfixed_mul(b, wm1.active_time); 1143 a.full = dfixed_const(16); 1144 b.full = dfixed_div(b, a); 1145 a.full = dfixed_mul(wm1.worst_case_latency, 1146 wm1.consumption_rate); 1147 priority_mark12.full = a.full + b.full; 1148 } else { 1149 a.full = dfixed_mul(wm1.worst_case_latency, 1150 wm1.consumption_rate); 1151 b.full = dfixed_const(16 * 1000); 1152 priority_mark12.full = dfixed_div(a, b); 1153 } 1154 if (wm1.priority_mark.full > priority_mark12.full) 1155 priority_mark12.full = wm1.priority_mark.full; 1156 if (dfixed_trunc(priority_mark12) < 0) 1157 priority_mark12.full = 0; 1158 if (wm1.priority_mark_max.full > priority_mark12.full) 1159 priority_mark12.full = wm1.priority_mark_max.full; 1160 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1161 if (rdev->disp_priority == 2) 1162 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1163 } 1164 1165 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1166 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 1167 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1168 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 1169 } 1170 1171 void rv515_bandwidth_update(struct radeon_device *rdev) 1172 { 1173 uint32_t tmp; 1174 struct drm_display_mode *mode0 = NULL; 1175 struct drm_display_mode *mode1 = NULL; 1176 1177 radeon_update_display_priority(rdev); 1178 1179 if (rdev->mode_info.crtcs[0]->base.enabled) 1180 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1181 if (rdev->mode_info.crtcs[1]->base.enabled) 1182 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1183 /* 1184 * Set display0/1 priority up in the memory controller for 1185 * modes if the user specifies HIGH for displaypriority 1186 * option. 1187 */ 1188 if ((rdev->disp_priority == 2) && 1189 (rdev->family == CHIP_RV515)) { 1190 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1191 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1192 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1193 if (mode1) 1194 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1195 if (mode0) 1196 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1197 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1198 } 1199 rv515_bandwidth_avivo_update(rdev); 1200 } 1201