1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include "rv515d.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 #include "rv515_reg_safe.h" 36 37 /* This files gather functions specifics to: rv515 */ 38 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 39 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 40 static void rv515_gpu_init(struct radeon_device *rdev); 41 42 static const u32 crtc_offsets[2] = 43 { 44 0, 45 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 46 }; 47 48 void rv515_debugfs(struct radeon_device *rdev) 49 { 50 if (r100_debugfs_rbbm_init(rdev)) { 51 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 52 } 53 if (rv515_debugfs_pipes_info_init(rdev)) { 54 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 55 } 56 if (rv515_debugfs_ga_info_init(rdev)) { 57 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 58 } 59 } 60 61 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 62 { 63 int r; 64 65 r = radeon_ring_lock(rdev, ring, 64); 66 if (r) { 67 return; 68 } 69 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); 70 radeon_ring_write(ring, 71 ISYNC_ANY2D_IDLE3D | 72 ISYNC_ANY3D_IDLE2D | 73 ISYNC_WAIT_IDLEGUI | 74 ISYNC_CPSCRATCH_IDLEGUI); 75 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 76 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 77 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 78 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 79 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); 80 radeon_ring_write(ring, 0); 81 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); 82 radeon_ring_write(ring, 0); 83 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); 84 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); 85 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); 86 radeon_ring_write(ring, 0); 87 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 88 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 89 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 90 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 91 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); 92 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 93 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); 94 radeon_ring_write(ring, 0); 95 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 96 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); 97 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 98 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); 99 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); 100 radeon_ring_write(ring, 101 ((6 << MS_X0_SHIFT) | 102 (6 << MS_Y0_SHIFT) | 103 (6 << MS_X1_SHIFT) | 104 (6 << MS_Y1_SHIFT) | 105 (6 << MS_X2_SHIFT) | 106 (6 << MS_Y2_SHIFT) | 107 (6 << MSBD0_Y_SHIFT) | 108 (6 << MSBD0_X_SHIFT))); 109 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); 110 radeon_ring_write(ring, 111 ((6 << MS_X3_SHIFT) | 112 (6 << MS_Y3_SHIFT) | 113 (6 << MS_X4_SHIFT) | 114 (6 << MS_Y4_SHIFT) | 115 (6 << MS_X5_SHIFT) | 116 (6 << MS_Y5_SHIFT) | 117 (6 << MSBD1_SHIFT))); 118 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); 119 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 120 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); 121 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 122 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); 123 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 124 radeon_ring_write(ring, PACKET0(0x20C8, 0)); 125 radeon_ring_write(ring, 0); 126 radeon_ring_unlock_commit(rdev, ring, false); 127 } 128 129 int rv515_mc_wait_for_idle(struct radeon_device *rdev) 130 { 131 unsigned i; 132 uint32_t tmp; 133 134 for (i = 0; i < rdev->usec_timeout; i++) { 135 /* read MC_STATUS */ 136 tmp = RREG32_MC(MC_STATUS); 137 if (tmp & MC_STATUS_IDLE) { 138 return 0; 139 } 140 DRM_UDELAY(1); 141 } 142 return -1; 143 } 144 145 void rv515_vga_render_disable(struct radeon_device *rdev) 146 { 147 WREG32(R_000300_VGA_RENDER_CONTROL, 148 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 149 } 150 151 static void rv515_gpu_init(struct radeon_device *rdev) 152 { 153 unsigned pipe_select_current, gb_pipe_select, tmp; 154 155 if (r100_gui_wait_for_idle(rdev)) { 156 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 157 } 158 rv515_vga_render_disable(rdev); 159 r420_pipes_init(rdev); 160 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 161 tmp = RREG32(R300_DST_PIPE_CONFIG); 162 pipe_select_current = (tmp >> 2) & 3; 163 tmp = (1 << pipe_select_current) | 164 (((gb_pipe_select >> 8) & 0xF) << 4); 165 WREG32_PLL(0x000D, tmp); 166 if (r100_gui_wait_for_idle(rdev)) { 167 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"); 168 } 169 if (rv515_mc_wait_for_idle(rdev)) { 170 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 171 } 172 } 173 174 static void rv515_vram_get_type(struct radeon_device *rdev) 175 { 176 uint32_t tmp; 177 178 rdev->mc.vram_width = 128; 179 rdev->mc.vram_is_ddr = true; 180 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 181 switch (tmp) { 182 case 0: 183 rdev->mc.vram_width = 64; 184 break; 185 case 1: 186 rdev->mc.vram_width = 128; 187 break; 188 default: 189 rdev->mc.vram_width = 128; 190 break; 191 } 192 } 193 194 static void rv515_mc_init(struct radeon_device *rdev) 195 { 196 197 rv515_vram_get_type(rdev); 198 r100_vram_init_sizes(rdev); 199 radeon_vram_location(rdev, &rdev->mc, 0); 200 rdev->mc.gtt_base_align = 0; 201 if (!(rdev->flags & RADEON_IS_AGP)) 202 radeon_gtt_location(rdev, &rdev->mc); 203 radeon_update_bandwidth_info(rdev); 204 } 205 206 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 207 { 208 unsigned long flags; 209 uint32_t r; 210 211 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 212 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 213 r = RREG32(MC_IND_DATA); 214 WREG32(MC_IND_INDEX, 0); 215 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 216 217 return r; 218 } 219 220 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 221 { 222 unsigned long flags; 223 224 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 225 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 226 WREG32(MC_IND_DATA, (v)); 227 WREG32(MC_IND_INDEX, 0); 228 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 229 } 230 231 #if defined(CONFIG_DEBUG_FS) 232 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 233 { 234 struct drm_info_node *node = (struct drm_info_node *) m->private; 235 struct drm_device *dev = node->minor->dev; 236 struct radeon_device *rdev = dev->dev_private; 237 uint32_t tmp; 238 239 tmp = RREG32(GB_PIPE_SELECT); 240 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 241 tmp = RREG32(SU_REG_DEST); 242 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 243 tmp = RREG32(GB_TILE_CONFIG); 244 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 245 tmp = RREG32(DST_PIPE_CONFIG); 246 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 247 return 0; 248 } 249 250 static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 251 { 252 struct drm_info_node *node = (struct drm_info_node *) m->private; 253 struct drm_device *dev = node->minor->dev; 254 struct radeon_device *rdev = dev->dev_private; 255 uint32_t tmp; 256 257 tmp = RREG32(0x2140); 258 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 259 radeon_asic_reset(rdev); 260 tmp = RREG32(0x425C); 261 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 262 return 0; 263 } 264 265 static struct drm_info_list rv515_pipes_info_list[] = { 266 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 267 }; 268 269 static struct drm_info_list rv515_ga_info_list[] = { 270 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 271 }; 272 #endif 273 274 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 275 { 276 #if defined(CONFIG_DEBUG_FS) 277 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 278 #else 279 return 0; 280 #endif 281 } 282 283 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 284 { 285 #if defined(CONFIG_DEBUG_FS) 286 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 287 #else 288 return 0; 289 #endif 290 } 291 292 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 293 { 294 u32 crtc_enabled, tmp, frame_count, blackout; 295 int i, j; 296 297 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 298 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 299 300 /* disable VGA render */ 301 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 302 /* blank the display controllers */ 303 for (i = 0; i < rdev->num_crtc; i++) { 304 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; 305 if (crtc_enabled) { 306 save->crtc_enabled[i] = true; 307 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 308 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 309 radeon_wait_for_vblank(rdev, i); 310 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 311 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 312 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 313 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 314 } 315 /* wait for the next frame */ 316 frame_count = radeon_get_vblank_counter(rdev, i); 317 for (j = 0; j < rdev->usec_timeout; j++) { 318 if (radeon_get_vblank_counter(rdev, i) != frame_count) 319 break; 320 udelay(1); 321 } 322 323 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 325 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 326 tmp &= ~AVIVO_CRTC_EN; 327 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 328 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 329 save->crtc_enabled[i] = false; 330 /* ***** */ 331 } else { 332 save->crtc_enabled[i] = false; 333 } 334 } 335 336 radeon_mc_wait_for_idle(rdev); 337 338 if (rdev->family >= CHIP_R600) { 339 if (rdev->family >= CHIP_RV770) 340 blackout = RREG32(R700_MC_CITF_CNTL); 341 else 342 blackout = RREG32(R600_CITF_CNTL); 343 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { 344 /* Block CPU access */ 345 WREG32(R600_BIF_FB_EN, 0); 346 /* blackout the MC */ 347 blackout |= R600_BLACKOUT_MASK; 348 if (rdev->family >= CHIP_RV770) 349 WREG32(R700_MC_CITF_CNTL, blackout); 350 else 351 WREG32(R600_CITF_CNTL, blackout); 352 } 353 } 354 /* wait for the MC to settle */ 355 udelay(100); 356 357 /* lock double buffered regs */ 358 for (i = 0; i < rdev->num_crtc; i++) { 359 if (save->crtc_enabled[i]) { 360 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 361 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { 362 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 363 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 364 } 365 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 366 if (!(tmp & 1)) { 367 tmp |= 1; 368 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 369 } 370 } 371 } 372 } 373 374 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 375 { 376 u32 tmp, frame_count; 377 int i, j; 378 379 /* update crtc base addresses */ 380 for (i = 0; i < rdev->num_crtc; i++) { 381 if (rdev->family >= CHIP_RV770) { 382 if (i == 0) { 383 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 384 upper_32_bits(rdev->mc.vram_start)); 385 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 386 upper_32_bits(rdev->mc.vram_start)); 387 } else { 388 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 389 upper_32_bits(rdev->mc.vram_start)); 390 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 391 upper_32_bits(rdev->mc.vram_start)); 392 } 393 } 394 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 395 (u32)rdev->mc.vram_start); 396 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 397 (u32)rdev->mc.vram_start); 398 } 399 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 400 401 /* unlock regs and wait for update */ 402 for (i = 0; i < rdev->num_crtc; i++) { 403 if (save->crtc_enabled[i]) { 404 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); 405 if ((tmp & 0x7) != 3) { 406 tmp &= ~0x7; 407 tmp |= 0x3; 408 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 409 } 410 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 411 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { 412 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 413 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); 414 } 415 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); 416 if (tmp & 1) { 417 tmp &= ~1; 418 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 419 } 420 for (j = 0; j < rdev->usec_timeout; j++) { 421 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); 422 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) 423 break; 424 udelay(1); 425 } 426 } 427 } 428 429 if (rdev->family >= CHIP_R600) { 430 /* unblackout the MC */ 431 if (rdev->family >= CHIP_RV770) 432 tmp = RREG32(R700_MC_CITF_CNTL); 433 else 434 tmp = RREG32(R600_CITF_CNTL); 435 tmp &= ~R600_BLACKOUT_MASK; 436 if (rdev->family >= CHIP_RV770) 437 WREG32(R700_MC_CITF_CNTL, tmp); 438 else 439 WREG32(R600_CITF_CNTL, tmp); 440 /* allow CPU access */ 441 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); 442 } 443 444 for (i = 0; i < rdev->num_crtc; i++) { 445 if (save->crtc_enabled[i]) { 446 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 447 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 448 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 449 /* wait for the next frame */ 450 frame_count = radeon_get_vblank_counter(rdev, i); 451 for (j = 0; j < rdev->usec_timeout; j++) { 452 if (radeon_get_vblank_counter(rdev, i) != frame_count) 453 break; 454 udelay(1); 455 } 456 } 457 } 458 /* Unlock vga access */ 459 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 460 mdelay(1); 461 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 462 } 463 464 static void rv515_mc_program(struct radeon_device *rdev) 465 { 466 struct rv515_mc_save save; 467 468 /* Stops all mc clients */ 469 rv515_mc_stop(rdev, &save); 470 471 /* Wait for mc idle */ 472 if (rv515_mc_wait_for_idle(rdev)) 473 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 474 /* Write VRAM size in case we are limiting it */ 475 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 476 /* Program MC, should be a 32bits limited address space */ 477 WREG32_MC(R_000001_MC_FB_LOCATION, 478 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 479 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 480 WREG32(R_000134_HDP_FB_LOCATION, 481 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 482 if (rdev->flags & RADEON_IS_AGP) { 483 WREG32_MC(R_000002_MC_AGP_LOCATION, 484 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 485 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 486 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 487 WREG32_MC(R_000004_MC_AGP_BASE_2, 488 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 489 } else { 490 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 491 WREG32_MC(R_000003_MC_AGP_BASE, 0); 492 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 493 } 494 495 rv515_mc_resume(rdev, &save); 496 } 497 498 void rv515_clock_startup(struct radeon_device *rdev) 499 { 500 if (radeon_dynclks != -1 && radeon_dynclks) 501 radeon_atom_set_clock_gating(rdev, 1); 502 /* We need to force on some of the block */ 503 WREG32_PLL(R_00000F_CP_DYN_CNTL, 504 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 505 WREG32_PLL(R_000011_E2_DYN_CNTL, 506 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 507 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 508 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 509 } 510 511 static int rv515_startup(struct radeon_device *rdev) 512 { 513 int r; 514 515 rv515_mc_program(rdev); 516 /* Resume clock */ 517 rv515_clock_startup(rdev); 518 /* Initialize GPU configuration (# pipes, ...) */ 519 rv515_gpu_init(rdev); 520 /* Initialize GART (initialize after TTM so we can allocate 521 * memory through TTM but finalize after TTM) */ 522 if (rdev->flags & RADEON_IS_PCIE) { 523 r = rv370_pcie_gart_enable(rdev); 524 if (r) 525 return r; 526 } 527 528 /* allocate wb buffer */ 529 r = radeon_wb_init(rdev); 530 if (r) 531 return r; 532 533 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 534 if (r) { 535 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 536 return r; 537 } 538 539 /* Enable IRQ */ 540 if (!rdev->irq.installed) { 541 r = radeon_irq_kms_init(rdev); 542 if (r) 543 return r; 544 } 545 546 rs600_irq_set(rdev); 547 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 548 /* 1M ring buffer */ 549 r = r100_cp_init(rdev, 1024 * 1024); 550 if (r) { 551 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 552 return r; 553 } 554 555 r = radeon_ib_pool_init(rdev); 556 if (r) { 557 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 558 return r; 559 } 560 561 return 0; 562 } 563 564 int rv515_resume(struct radeon_device *rdev) 565 { 566 int r; 567 568 /* Make sur GART are not working */ 569 if (rdev->flags & RADEON_IS_PCIE) 570 rv370_pcie_gart_disable(rdev); 571 /* Resume clock before doing reset */ 572 rv515_clock_startup(rdev); 573 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 574 if (radeon_asic_reset(rdev)) { 575 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 576 RREG32(R_000E40_RBBM_STATUS), 577 RREG32(R_0007C0_CP_STAT)); 578 } 579 /* post */ 580 atom_asic_init(rdev->mode_info.atom_context); 581 /* Resume clock after posting */ 582 rv515_clock_startup(rdev); 583 /* Initialize surface registers */ 584 radeon_surface_init(rdev); 585 586 rdev->accel_working = true; 587 r = rv515_startup(rdev); 588 if (r) { 589 rdev->accel_working = false; 590 } 591 return r; 592 } 593 594 int rv515_suspend(struct radeon_device *rdev) 595 { 596 radeon_pm_suspend(rdev); 597 r100_cp_disable(rdev); 598 radeon_wb_disable(rdev); 599 rs600_irq_disable(rdev); 600 if (rdev->flags & RADEON_IS_PCIE) 601 rv370_pcie_gart_disable(rdev); 602 return 0; 603 } 604 605 void rv515_set_safe_registers(struct radeon_device *rdev) 606 { 607 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 608 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 609 } 610 611 void rv515_fini(struct radeon_device *rdev) 612 { 613 radeon_pm_fini(rdev); 614 r100_cp_fini(rdev); 615 radeon_wb_fini(rdev); 616 radeon_ib_pool_fini(rdev); 617 radeon_gem_fini(rdev); 618 rv370_pcie_gart_fini(rdev); 619 radeon_agp_fini(rdev); 620 radeon_irq_kms_fini(rdev); 621 radeon_fence_driver_fini(rdev); 622 radeon_bo_fini(rdev); 623 radeon_atombios_fini(rdev); 624 kfree(rdev->bios); 625 rdev->bios = NULL; 626 } 627 628 int rv515_init(struct radeon_device *rdev) 629 { 630 int r; 631 632 /* Initialize scratch registers */ 633 radeon_scratch_init(rdev); 634 /* Initialize surface registers */ 635 radeon_surface_init(rdev); 636 /* TODO: disable VGA need to use VGA request */ 637 /* restore some register to sane defaults */ 638 r100_restore_sanity(rdev); 639 /* BIOS*/ 640 if (!radeon_get_bios(rdev)) { 641 if (ASIC_IS_AVIVO(rdev)) 642 return -EINVAL; 643 } 644 if (rdev->is_atom_bios) { 645 r = radeon_atombios_init(rdev); 646 if (r) 647 return r; 648 } else { 649 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 650 return -EINVAL; 651 } 652 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 653 if (radeon_asic_reset(rdev)) { 654 dev_warn(rdev->dev, 655 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 656 RREG32(R_000E40_RBBM_STATUS), 657 RREG32(R_0007C0_CP_STAT)); 658 } 659 /* check if cards are posted or not */ 660 if (radeon_boot_test_post_card(rdev) == false) 661 return -EINVAL; 662 /* Initialize clocks */ 663 radeon_get_clock_info(rdev->ddev); 664 /* initialize AGP */ 665 if (rdev->flags & RADEON_IS_AGP) { 666 r = radeon_agp_init(rdev); 667 if (r) { 668 radeon_agp_disable(rdev); 669 } 670 } 671 /* initialize memory controller */ 672 rv515_mc_init(rdev); 673 rv515_debugfs(rdev); 674 /* Fence driver */ 675 r = radeon_fence_driver_init(rdev); 676 if (r) 677 return r; 678 /* Memory manager */ 679 r = radeon_bo_init(rdev); 680 if (r) 681 return r; 682 r = rv370_pcie_gart_init(rdev); 683 if (r) 684 return r; 685 rv515_set_safe_registers(rdev); 686 687 /* Initialize power management */ 688 radeon_pm_init(rdev); 689 690 rdev->accel_working = true; 691 r = rv515_startup(rdev); 692 if (r) { 693 /* Somethings want wront with the accel init stop accel */ 694 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 695 r100_cp_fini(rdev); 696 radeon_wb_fini(rdev); 697 radeon_ib_pool_fini(rdev); 698 radeon_irq_kms_fini(rdev); 699 rv370_pcie_gart_fini(rdev); 700 radeon_agp_fini(rdev); 701 rdev->accel_working = false; 702 } 703 return 0; 704 } 705 706 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 707 { 708 int index_reg = 0x6578 + crtc->crtc_offset; 709 int data_reg = 0x657c + crtc->crtc_offset; 710 711 WREG32(0x659C + crtc->crtc_offset, 0x0); 712 WREG32(0x6594 + crtc->crtc_offset, 0x705); 713 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 714 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 715 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 716 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 717 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 718 WREG32(index_reg, 0x0); 719 WREG32(data_reg, 0x841880A8); 720 WREG32(index_reg, 0x1); 721 WREG32(data_reg, 0x84208680); 722 WREG32(index_reg, 0x2); 723 WREG32(data_reg, 0xBFF880B0); 724 WREG32(index_reg, 0x100); 725 WREG32(data_reg, 0x83D88088); 726 WREG32(index_reg, 0x101); 727 WREG32(data_reg, 0x84608680); 728 WREG32(index_reg, 0x102); 729 WREG32(data_reg, 0xBFF080D0); 730 WREG32(index_reg, 0x200); 731 WREG32(data_reg, 0x83988068); 732 WREG32(index_reg, 0x201); 733 WREG32(data_reg, 0x84A08680); 734 WREG32(index_reg, 0x202); 735 WREG32(data_reg, 0xBFF080F8); 736 WREG32(index_reg, 0x300); 737 WREG32(data_reg, 0x83588058); 738 WREG32(index_reg, 0x301); 739 WREG32(data_reg, 0x84E08660); 740 WREG32(index_reg, 0x302); 741 WREG32(data_reg, 0xBFF88120); 742 WREG32(index_reg, 0x400); 743 WREG32(data_reg, 0x83188040); 744 WREG32(index_reg, 0x401); 745 WREG32(data_reg, 0x85008660); 746 WREG32(index_reg, 0x402); 747 WREG32(data_reg, 0xBFF88150); 748 WREG32(index_reg, 0x500); 749 WREG32(data_reg, 0x82D88030); 750 WREG32(index_reg, 0x501); 751 WREG32(data_reg, 0x85408640); 752 WREG32(index_reg, 0x502); 753 WREG32(data_reg, 0xBFF88180); 754 WREG32(index_reg, 0x600); 755 WREG32(data_reg, 0x82A08018); 756 WREG32(index_reg, 0x601); 757 WREG32(data_reg, 0x85808620); 758 WREG32(index_reg, 0x602); 759 WREG32(data_reg, 0xBFF081B8); 760 WREG32(index_reg, 0x700); 761 WREG32(data_reg, 0x82608010); 762 WREG32(index_reg, 0x701); 763 WREG32(data_reg, 0x85A08600); 764 WREG32(index_reg, 0x702); 765 WREG32(data_reg, 0x800081F0); 766 WREG32(index_reg, 0x800); 767 WREG32(data_reg, 0x8228BFF8); 768 WREG32(index_reg, 0x801); 769 WREG32(data_reg, 0x85E085E0); 770 WREG32(index_reg, 0x802); 771 WREG32(data_reg, 0xBFF88228); 772 WREG32(index_reg, 0x10000); 773 WREG32(data_reg, 0x82A8BF00); 774 WREG32(index_reg, 0x10001); 775 WREG32(data_reg, 0x82A08CC0); 776 WREG32(index_reg, 0x10002); 777 WREG32(data_reg, 0x8008BEF8); 778 WREG32(index_reg, 0x10100); 779 WREG32(data_reg, 0x81F0BF28); 780 WREG32(index_reg, 0x10101); 781 WREG32(data_reg, 0x83608CA0); 782 WREG32(index_reg, 0x10102); 783 WREG32(data_reg, 0x8018BED0); 784 WREG32(index_reg, 0x10200); 785 WREG32(data_reg, 0x8148BF38); 786 WREG32(index_reg, 0x10201); 787 WREG32(data_reg, 0x84408C80); 788 WREG32(index_reg, 0x10202); 789 WREG32(data_reg, 0x8008BEB8); 790 WREG32(index_reg, 0x10300); 791 WREG32(data_reg, 0x80B0BF78); 792 WREG32(index_reg, 0x10301); 793 WREG32(data_reg, 0x85008C20); 794 WREG32(index_reg, 0x10302); 795 WREG32(data_reg, 0x8020BEA0); 796 WREG32(index_reg, 0x10400); 797 WREG32(data_reg, 0x8028BF90); 798 WREG32(index_reg, 0x10401); 799 WREG32(data_reg, 0x85E08BC0); 800 WREG32(index_reg, 0x10402); 801 WREG32(data_reg, 0x8018BE90); 802 WREG32(index_reg, 0x10500); 803 WREG32(data_reg, 0xBFB8BFB0); 804 WREG32(index_reg, 0x10501); 805 WREG32(data_reg, 0x86C08B40); 806 WREG32(index_reg, 0x10502); 807 WREG32(data_reg, 0x8010BE90); 808 WREG32(index_reg, 0x10600); 809 WREG32(data_reg, 0xBF58BFC8); 810 WREG32(index_reg, 0x10601); 811 WREG32(data_reg, 0x87A08AA0); 812 WREG32(index_reg, 0x10602); 813 WREG32(data_reg, 0x8010BE98); 814 WREG32(index_reg, 0x10700); 815 WREG32(data_reg, 0xBF10BFF0); 816 WREG32(index_reg, 0x10701); 817 WREG32(data_reg, 0x886089E0); 818 WREG32(index_reg, 0x10702); 819 WREG32(data_reg, 0x8018BEB0); 820 WREG32(index_reg, 0x10800); 821 WREG32(data_reg, 0xBED8BFE8); 822 WREG32(index_reg, 0x10801); 823 WREG32(data_reg, 0x89408940); 824 WREG32(index_reg, 0x10802); 825 WREG32(data_reg, 0xBFE8BED8); 826 WREG32(index_reg, 0x20000); 827 WREG32(data_reg, 0x80008000); 828 WREG32(index_reg, 0x20001); 829 WREG32(data_reg, 0x90008000); 830 WREG32(index_reg, 0x20002); 831 WREG32(data_reg, 0x80008000); 832 WREG32(index_reg, 0x20003); 833 WREG32(data_reg, 0x80008000); 834 WREG32(index_reg, 0x20100); 835 WREG32(data_reg, 0x80108000); 836 WREG32(index_reg, 0x20101); 837 WREG32(data_reg, 0x8FE0BF70); 838 WREG32(index_reg, 0x20102); 839 WREG32(data_reg, 0xBFE880C0); 840 WREG32(index_reg, 0x20103); 841 WREG32(data_reg, 0x80008000); 842 WREG32(index_reg, 0x20200); 843 WREG32(data_reg, 0x8018BFF8); 844 WREG32(index_reg, 0x20201); 845 WREG32(data_reg, 0x8F80BF08); 846 WREG32(index_reg, 0x20202); 847 WREG32(data_reg, 0xBFD081A0); 848 WREG32(index_reg, 0x20203); 849 WREG32(data_reg, 0xBFF88000); 850 WREG32(index_reg, 0x20300); 851 WREG32(data_reg, 0x80188000); 852 WREG32(index_reg, 0x20301); 853 WREG32(data_reg, 0x8EE0BEC0); 854 WREG32(index_reg, 0x20302); 855 WREG32(data_reg, 0xBFB082A0); 856 WREG32(index_reg, 0x20303); 857 WREG32(data_reg, 0x80008000); 858 WREG32(index_reg, 0x20400); 859 WREG32(data_reg, 0x80188000); 860 WREG32(index_reg, 0x20401); 861 WREG32(data_reg, 0x8E00BEA0); 862 WREG32(index_reg, 0x20402); 863 WREG32(data_reg, 0xBF8883C0); 864 WREG32(index_reg, 0x20403); 865 WREG32(data_reg, 0x80008000); 866 WREG32(index_reg, 0x20500); 867 WREG32(data_reg, 0x80188000); 868 WREG32(index_reg, 0x20501); 869 WREG32(data_reg, 0x8D00BE90); 870 WREG32(index_reg, 0x20502); 871 WREG32(data_reg, 0xBF588500); 872 WREG32(index_reg, 0x20503); 873 WREG32(data_reg, 0x80008008); 874 WREG32(index_reg, 0x20600); 875 WREG32(data_reg, 0x80188000); 876 WREG32(index_reg, 0x20601); 877 WREG32(data_reg, 0x8BC0BE98); 878 WREG32(index_reg, 0x20602); 879 WREG32(data_reg, 0xBF308660); 880 WREG32(index_reg, 0x20603); 881 WREG32(data_reg, 0x80008008); 882 WREG32(index_reg, 0x20700); 883 WREG32(data_reg, 0x80108000); 884 WREG32(index_reg, 0x20701); 885 WREG32(data_reg, 0x8A80BEB0); 886 WREG32(index_reg, 0x20702); 887 WREG32(data_reg, 0xBF0087C0); 888 WREG32(index_reg, 0x20703); 889 WREG32(data_reg, 0x80008008); 890 WREG32(index_reg, 0x20800); 891 WREG32(data_reg, 0x80108000); 892 WREG32(index_reg, 0x20801); 893 WREG32(data_reg, 0x8920BED0); 894 WREG32(index_reg, 0x20802); 895 WREG32(data_reg, 0xBED08920); 896 WREG32(index_reg, 0x20803); 897 WREG32(data_reg, 0x80008010); 898 WREG32(index_reg, 0x30000); 899 WREG32(data_reg, 0x90008000); 900 WREG32(index_reg, 0x30001); 901 WREG32(data_reg, 0x80008000); 902 WREG32(index_reg, 0x30100); 903 WREG32(data_reg, 0x8FE0BF90); 904 WREG32(index_reg, 0x30101); 905 WREG32(data_reg, 0xBFF880A0); 906 WREG32(index_reg, 0x30200); 907 WREG32(data_reg, 0x8F60BF40); 908 WREG32(index_reg, 0x30201); 909 WREG32(data_reg, 0xBFE88180); 910 WREG32(index_reg, 0x30300); 911 WREG32(data_reg, 0x8EC0BF00); 912 WREG32(index_reg, 0x30301); 913 WREG32(data_reg, 0xBFC88280); 914 WREG32(index_reg, 0x30400); 915 WREG32(data_reg, 0x8DE0BEE0); 916 WREG32(index_reg, 0x30401); 917 WREG32(data_reg, 0xBFA083A0); 918 WREG32(index_reg, 0x30500); 919 WREG32(data_reg, 0x8CE0BED0); 920 WREG32(index_reg, 0x30501); 921 WREG32(data_reg, 0xBF7884E0); 922 WREG32(index_reg, 0x30600); 923 WREG32(data_reg, 0x8BA0BED8); 924 WREG32(index_reg, 0x30601); 925 WREG32(data_reg, 0xBF508640); 926 WREG32(index_reg, 0x30700); 927 WREG32(data_reg, 0x8A60BEE8); 928 WREG32(index_reg, 0x30701); 929 WREG32(data_reg, 0xBF2087A0); 930 WREG32(index_reg, 0x30800); 931 WREG32(data_reg, 0x8900BF00); 932 WREG32(index_reg, 0x30801); 933 WREG32(data_reg, 0xBF008900); 934 } 935 936 struct rv515_watermark { 937 u32 lb_request_fifo_depth; 938 fixed20_12 num_line_pair; 939 fixed20_12 estimated_width; 940 fixed20_12 worst_case_latency; 941 fixed20_12 consumption_rate; 942 fixed20_12 active_time; 943 fixed20_12 dbpp; 944 fixed20_12 priority_mark_max; 945 fixed20_12 priority_mark; 946 fixed20_12 sclk; 947 }; 948 949 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 950 struct radeon_crtc *crtc, 951 struct rv515_watermark *wm, 952 bool low) 953 { 954 struct drm_display_mode *mode = &crtc->base.mode; 955 fixed20_12 a, b, c; 956 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 957 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 958 fixed20_12 sclk; 959 u32 selected_sclk; 960 961 if (!crtc->base.enabled) { 962 /* FIXME: wouldn't it better to set priority mark to maximum */ 963 wm->lb_request_fifo_depth = 4; 964 return; 965 } 966 967 /* rv6xx, rv7xx */ 968 if ((rdev->family >= CHIP_RV610) && 969 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 970 selected_sclk = radeon_dpm_get_sclk(rdev, low); 971 else 972 selected_sclk = rdev->pm.current_sclk; 973 974 /* sclk in Mhz */ 975 a.full = dfixed_const(100); 976 sclk.full = dfixed_const(selected_sclk); 977 sclk.full = dfixed_div(sclk, a); 978 979 if (crtc->vsc.full > dfixed_const(2)) 980 wm->num_line_pair.full = dfixed_const(2); 981 else 982 wm->num_line_pair.full = dfixed_const(1); 983 984 b.full = dfixed_const(mode->crtc_hdisplay); 985 c.full = dfixed_const(256); 986 a.full = dfixed_div(b, c); 987 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 988 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 989 if (a.full < dfixed_const(4)) { 990 wm->lb_request_fifo_depth = 4; 991 } else { 992 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 993 } 994 995 /* Determine consumption rate 996 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 997 * vtaps = number of vertical taps, 998 * vsc = vertical scaling ratio, defined as source/destination 999 * hsc = horizontal scaling ration, defined as source/destination 1000 */ 1001 a.full = dfixed_const(mode->clock); 1002 b.full = dfixed_const(1000); 1003 a.full = dfixed_div(a, b); 1004 pclk.full = dfixed_div(b, a); 1005 if (crtc->rmx_type != RMX_OFF) { 1006 b.full = dfixed_const(2); 1007 if (crtc->vsc.full > b.full) 1008 b.full = crtc->vsc.full; 1009 b.full = dfixed_mul(b, crtc->hsc); 1010 c.full = dfixed_const(2); 1011 b.full = dfixed_div(b, c); 1012 consumption_time.full = dfixed_div(pclk, b); 1013 } else { 1014 consumption_time.full = pclk.full; 1015 } 1016 a.full = dfixed_const(1); 1017 wm->consumption_rate.full = dfixed_div(a, consumption_time); 1018 1019 1020 /* Determine line time 1021 * LineTime = total time for one line of displayhtotal 1022 * LineTime = total number of horizontal pixels 1023 * pclk = pixel clock period(ns) 1024 */ 1025 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1026 line_time.full = dfixed_mul(a, pclk); 1027 1028 /* Determine active time 1029 * ActiveTime = time of active region of display within one line, 1030 * hactive = total number of horizontal active pixels 1031 * htotal = total number of horizontal pixels 1032 */ 1033 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 1034 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1035 wm->active_time.full = dfixed_mul(line_time, b); 1036 wm->active_time.full = dfixed_div(wm->active_time, a); 1037 1038 /* Determine chunk time 1039 * ChunkTime = the time it takes the DCP to send one chunk of data 1040 * to the LB which consists of pipeline delay and inter chunk gap 1041 * sclk = system clock(Mhz) 1042 */ 1043 a.full = dfixed_const(600 * 1000); 1044 chunk_time.full = dfixed_div(a, sclk); 1045 read_delay_latency.full = dfixed_const(1000); 1046 1047 /* Determine the worst case latency 1048 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 1049 * WorstCaseLatency = worst case time from urgent to when the MC starts 1050 * to return data 1051 * READ_DELAY_IDLE_MAX = constant of 1us 1052 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 1053 * which consists of pipeline delay and inter chunk gap 1054 */ 1055 if (dfixed_trunc(wm->num_line_pair) > 1) { 1056 a.full = dfixed_const(3); 1057 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 1058 wm->worst_case_latency.full += read_delay_latency.full; 1059 } else { 1060 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 1061 } 1062 1063 /* Determine the tolerable latency 1064 * TolerableLatency = Any given request has only 1 line time 1065 * for the data to be returned 1066 * LBRequestFifoDepth = Number of chunk requests the LB can 1067 * put into the request FIFO for a display 1068 * LineTime = total time for one line of display 1069 * ChunkTime = the time it takes the DCP to send one chunk 1070 * of data to the LB which consists of 1071 * pipeline delay and inter chunk gap 1072 */ 1073 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 1074 tolerable_latency.full = line_time.full; 1075 } else { 1076 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 1077 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 1078 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 1079 tolerable_latency.full = line_time.full - tolerable_latency.full; 1080 } 1081 /* We assume worst case 32bits (4 bytes) */ 1082 wm->dbpp.full = dfixed_const(2 * 16); 1083 1084 /* Determine the maximum priority mark 1085 * width = viewport width in pixels 1086 */ 1087 a.full = dfixed_const(16); 1088 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 1089 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 1090 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 1091 1092 /* Determine estimated width */ 1093 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 1094 estimated_width.full = dfixed_div(estimated_width, consumption_time); 1095 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 1096 wm->priority_mark.full = wm->priority_mark_max.full; 1097 } else { 1098 a.full = dfixed_const(16); 1099 wm->priority_mark.full = dfixed_div(estimated_width, a); 1100 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 1101 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 1102 } 1103 } 1104 1105 static void rv515_compute_mode_priority(struct radeon_device *rdev, 1106 struct rv515_watermark *wm0, 1107 struct rv515_watermark *wm1, 1108 struct drm_display_mode *mode0, 1109 struct drm_display_mode *mode1, 1110 u32 *d1mode_priority_a_cnt, 1111 u32 *d2mode_priority_a_cnt) 1112 { 1113 fixed20_12 priority_mark02, priority_mark12, fill_rate; 1114 fixed20_12 a, b; 1115 1116 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 1117 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 1118 1119 if (mode0 && mode1) { 1120 if (dfixed_trunc(wm0->dbpp) > 64) 1121 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1122 else 1123 a.full = wm0->num_line_pair.full; 1124 if (dfixed_trunc(wm1->dbpp) > 64) 1125 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1126 else 1127 b.full = wm1->num_line_pair.full; 1128 a.full += b.full; 1129 fill_rate.full = dfixed_div(wm0->sclk, a); 1130 if (wm0->consumption_rate.full > fill_rate.full) { 1131 b.full = wm0->consumption_rate.full - fill_rate.full; 1132 b.full = dfixed_mul(b, wm0->active_time); 1133 a.full = dfixed_const(16); 1134 b.full = dfixed_div(b, a); 1135 a.full = dfixed_mul(wm0->worst_case_latency, 1136 wm0->consumption_rate); 1137 priority_mark02.full = a.full + b.full; 1138 } else { 1139 a.full = dfixed_mul(wm0->worst_case_latency, 1140 wm0->consumption_rate); 1141 b.full = dfixed_const(16 * 1000); 1142 priority_mark02.full = dfixed_div(a, b); 1143 } 1144 if (wm1->consumption_rate.full > fill_rate.full) { 1145 b.full = wm1->consumption_rate.full - fill_rate.full; 1146 b.full = dfixed_mul(b, wm1->active_time); 1147 a.full = dfixed_const(16); 1148 b.full = dfixed_div(b, a); 1149 a.full = dfixed_mul(wm1->worst_case_latency, 1150 wm1->consumption_rate); 1151 priority_mark12.full = a.full + b.full; 1152 } else { 1153 a.full = dfixed_mul(wm1->worst_case_latency, 1154 wm1->consumption_rate); 1155 b.full = dfixed_const(16 * 1000); 1156 priority_mark12.full = dfixed_div(a, b); 1157 } 1158 if (wm0->priority_mark.full > priority_mark02.full) 1159 priority_mark02.full = wm0->priority_mark.full; 1160 if (wm0->priority_mark_max.full > priority_mark02.full) 1161 priority_mark02.full = wm0->priority_mark_max.full; 1162 if (wm1->priority_mark.full > priority_mark12.full) 1163 priority_mark12.full = wm1->priority_mark.full; 1164 if (wm1->priority_mark_max.full > priority_mark12.full) 1165 priority_mark12.full = wm1->priority_mark_max.full; 1166 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1167 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1168 if (rdev->disp_priority == 2) { 1169 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1170 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1171 } 1172 } else if (mode0) { 1173 if (dfixed_trunc(wm0->dbpp) > 64) 1174 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); 1175 else 1176 a.full = wm0->num_line_pair.full; 1177 fill_rate.full = dfixed_div(wm0->sclk, a); 1178 if (wm0->consumption_rate.full > fill_rate.full) { 1179 b.full = wm0->consumption_rate.full - fill_rate.full; 1180 b.full = dfixed_mul(b, wm0->active_time); 1181 a.full = dfixed_const(16); 1182 b.full = dfixed_div(b, a); 1183 a.full = dfixed_mul(wm0->worst_case_latency, 1184 wm0->consumption_rate); 1185 priority_mark02.full = a.full + b.full; 1186 } else { 1187 a.full = dfixed_mul(wm0->worst_case_latency, 1188 wm0->consumption_rate); 1189 b.full = dfixed_const(16); 1190 priority_mark02.full = dfixed_div(a, b); 1191 } 1192 if (wm0->priority_mark.full > priority_mark02.full) 1193 priority_mark02.full = wm0->priority_mark.full; 1194 if (wm0->priority_mark_max.full > priority_mark02.full) 1195 priority_mark02.full = wm0->priority_mark_max.full; 1196 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1197 if (rdev->disp_priority == 2) 1198 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1199 } else if (mode1) { 1200 if (dfixed_trunc(wm1->dbpp) > 64) 1201 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); 1202 else 1203 a.full = wm1->num_line_pair.full; 1204 fill_rate.full = dfixed_div(wm1->sclk, a); 1205 if (wm1->consumption_rate.full > fill_rate.full) { 1206 b.full = wm1->consumption_rate.full - fill_rate.full; 1207 b.full = dfixed_mul(b, wm1->active_time); 1208 a.full = dfixed_const(16); 1209 b.full = dfixed_div(b, a); 1210 a.full = dfixed_mul(wm1->worst_case_latency, 1211 wm1->consumption_rate); 1212 priority_mark12.full = a.full + b.full; 1213 } else { 1214 a.full = dfixed_mul(wm1->worst_case_latency, 1215 wm1->consumption_rate); 1216 b.full = dfixed_const(16 * 1000); 1217 priority_mark12.full = dfixed_div(a, b); 1218 } 1219 if (wm1->priority_mark.full > priority_mark12.full) 1220 priority_mark12.full = wm1->priority_mark.full; 1221 if (wm1->priority_mark_max.full > priority_mark12.full) 1222 priority_mark12.full = wm1->priority_mark_max.full; 1223 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1224 if (rdev->disp_priority == 2) 1225 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1226 } 1227 } 1228 1229 void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 1230 { 1231 struct drm_display_mode *mode0 = NULL; 1232 struct drm_display_mode *mode1 = NULL; 1233 struct rv515_watermark wm0_high, wm0_low; 1234 struct rv515_watermark wm1_high, wm1_low; 1235 u32 tmp; 1236 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 1237 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 1238 1239 if (rdev->mode_info.crtcs[0]->base.enabled) 1240 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1241 if (rdev->mode_info.crtcs[1]->base.enabled) 1242 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1243 rs690_line_buffer_adjust(rdev, mode0, mode1); 1244 1245 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 1246 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 1247 1248 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); 1249 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); 1250 1251 tmp = wm0_high.lb_request_fifo_depth; 1252 tmp |= wm1_high.lb_request_fifo_depth << 16; 1253 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 1254 1255 rv515_compute_mode_priority(rdev, 1256 &wm0_high, &wm1_high, 1257 mode0, mode1, 1258 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 1259 rv515_compute_mode_priority(rdev, 1260 &wm0_low, &wm1_low, 1261 mode0, mode1, 1262 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 1263 1264 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1265 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 1266 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1267 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 1268 } 1269 1270 void rv515_bandwidth_update(struct radeon_device *rdev) 1271 { 1272 uint32_t tmp; 1273 struct drm_display_mode *mode0 = NULL; 1274 struct drm_display_mode *mode1 = NULL; 1275 1276 if (!rdev->mode_info.mode_config_initialized) 1277 return; 1278 1279 radeon_update_display_priority(rdev); 1280 1281 if (rdev->mode_info.crtcs[0]->base.enabled) 1282 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1283 if (rdev->mode_info.crtcs[1]->base.enabled) 1284 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1285 /* 1286 * Set display0/1 priority up in the memory controller for 1287 * modes if the user specifies HIGH for displaypriority 1288 * option. 1289 */ 1290 if ((rdev->disp_priority == 2) && 1291 (rdev->family == CHIP_RV515)) { 1292 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1293 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1294 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1295 if (mode1) 1296 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1297 if (mode0) 1298 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1299 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1300 } 1301 rv515_bandwidth_avivo_update(rdev); 1302 } 1303