1926deccbSFrançois Tigeot /*
2926deccbSFrançois Tigeot * Copyright 2008 Advanced Micro Devices, Inc.
3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc.
4926deccbSFrançois Tigeot * Copyright 2009 Jerome Glisse.
5926deccbSFrançois Tigeot *
6926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a
7926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"),
8926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation
9926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the
11926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions:
12926deccbSFrançois Tigeot *
13926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in
14926deccbSFrançois Tigeot * all copies or substantial portions of the Software.
15926deccbSFrançois Tigeot *
16926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE.
23926deccbSFrançois Tigeot *
24926deccbSFrançois Tigeot * Authors: Dave Airlie
25926deccbSFrançois Tigeot * Alex Deucher
26926deccbSFrançois Tigeot * Jerome Glisse
27926deccbSFrançois Tigeot */
28c4ef309bSzrj #include <linux/firmware.h>
29926deccbSFrançois Tigeot #include <drm/drmP.h>
30926deccbSFrançois Tigeot #include "radeon.h"
31926deccbSFrançois Tigeot #include "radeon_asic.h"
32c59a5c48SFrançois Tigeot #include "radeon_audio.h"
3383b4b9b9SFrançois Tigeot #include <drm/radeon_drm.h>
34926deccbSFrançois Tigeot #include "rv770d.h"
35926deccbSFrançois Tigeot #include "atom.h"
36926deccbSFrançois Tigeot #include "avivod.h"
37926deccbSFrançois Tigeot
38926deccbSFrançois Tigeot #define R700_PFP_UCODE_SIZE 848
39926deccbSFrançois Tigeot #define R700_PM4_UCODE_SIZE 1360
40926deccbSFrançois Tigeot
41926deccbSFrançois Tigeot static void rv770_gpu_init(struct radeon_device *rdev);
42926deccbSFrançois Tigeot static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
43926deccbSFrançois Tigeot
rv770_set_uvd_clocks(struct radeon_device * rdev,u32 vclk,u32 dclk)44f43cf1b1SMichael Neumann int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
45f43cf1b1SMichael Neumann {
46f43cf1b1SMichael Neumann unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
47f43cf1b1SMichael Neumann int r;
48f43cf1b1SMichael Neumann
49f43cf1b1SMichael Neumann /* RV740 uses evergreen uvd clk programming */
50f43cf1b1SMichael Neumann if (rdev->family == CHIP_RV740)
51f43cf1b1SMichael Neumann return evergreen_set_uvd_clocks(rdev, vclk, dclk);
52f43cf1b1SMichael Neumann
53f43cf1b1SMichael Neumann /* bypass vclk and dclk with bclk */
54f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_2,
55f43cf1b1SMichael Neumann VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
56f43cf1b1SMichael Neumann ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
57f43cf1b1SMichael Neumann
58f43cf1b1SMichael Neumann if (!vclk || !dclk) {
59f43cf1b1SMichael Neumann /* keep the Bypass mode, put PLL to sleep */
60f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
61f43cf1b1SMichael Neumann return 0;
62f43cf1b1SMichael Neumann }
63f43cf1b1SMichael Neumann
64f43cf1b1SMichael Neumann r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
65f43cf1b1SMichael Neumann 43663, 0x03FFFFFE, 1, 30, ~0,
66f43cf1b1SMichael Neumann &fb_div, &vclk_div, &dclk_div);
67f43cf1b1SMichael Neumann if (r)
68f43cf1b1SMichael Neumann return r;
69f43cf1b1SMichael Neumann
70f43cf1b1SMichael Neumann fb_div |= 1;
71f43cf1b1SMichael Neumann vclk_div -= 1;
72f43cf1b1SMichael Neumann dclk_div -= 1;
73f43cf1b1SMichael Neumann
74f43cf1b1SMichael Neumann /* set UPLL_FB_DIV to 0x50000 */
75f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
76f43cf1b1SMichael Neumann
77f43cf1b1SMichael Neumann /* deassert UPLL_RESET and UPLL_SLEEP */
78f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
79f43cf1b1SMichael Neumann
80f43cf1b1SMichael Neumann /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
81f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
82f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
83f43cf1b1SMichael Neumann
84f43cf1b1SMichael Neumann r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
85f43cf1b1SMichael Neumann if (r)
86f43cf1b1SMichael Neumann return r;
87f43cf1b1SMichael Neumann
88f43cf1b1SMichael Neumann /* assert PLL_RESET */
89f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
90f43cf1b1SMichael Neumann
91f43cf1b1SMichael Neumann /* set the required FB_DIV, REF_DIV, Post divder values */
92f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
93f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_2,
94f43cf1b1SMichael Neumann UPLL_SW_HILEN(vclk_div >> 1) |
95f43cf1b1SMichael Neumann UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
96f43cf1b1SMichael Neumann UPLL_SW_HILEN2(dclk_div >> 1) |
97f43cf1b1SMichael Neumann UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
98f43cf1b1SMichael Neumann ~UPLL_SW_MASK);
99f43cf1b1SMichael Neumann
100f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
101f43cf1b1SMichael Neumann ~UPLL_FB_DIV_MASK);
102f43cf1b1SMichael Neumann
103f43cf1b1SMichael Neumann /* give the PLL some time to settle */
104c4ef309bSzrj mdelay(15);
105f43cf1b1SMichael Neumann
106f43cf1b1SMichael Neumann /* deassert PLL_RESET */
107f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
108f43cf1b1SMichael Neumann
109c4ef309bSzrj mdelay(15);
110f43cf1b1SMichael Neumann
111f43cf1b1SMichael Neumann /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
112f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
113f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
114f43cf1b1SMichael Neumann
115f43cf1b1SMichael Neumann r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
116f43cf1b1SMichael Neumann if (r)
117f43cf1b1SMichael Neumann return r;
118f43cf1b1SMichael Neumann
119f43cf1b1SMichael Neumann /* switch VCLK and DCLK selection */
120f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_2,
121f43cf1b1SMichael Neumann VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
122f43cf1b1SMichael Neumann ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
123f43cf1b1SMichael Neumann
124c4ef309bSzrj mdelay(100);
125f43cf1b1SMichael Neumann
126f43cf1b1SMichael Neumann return 0;
127f43cf1b1SMichael Neumann }
128f43cf1b1SMichael Neumann
129f43cf1b1SMichael Neumann static const u32 r7xx_golden_registers[] =
130f43cf1b1SMichael Neumann {
131f43cf1b1SMichael Neumann 0x8d00, 0xffffffff, 0x0e0e0074,
132f43cf1b1SMichael Neumann 0x8d04, 0xffffffff, 0x013a2b34,
133f43cf1b1SMichael Neumann 0x9508, 0xffffffff, 0x00000002,
134f43cf1b1SMichael Neumann 0x8b20, 0xffffffff, 0,
135f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x000000c2,
136f43cf1b1SMichael Neumann 0x28350, 0xffffffff, 0,
137f43cf1b1SMichael Neumann 0x9058, 0xffffffff, 0x0fffc40f,
138f43cf1b1SMichael Neumann 0x240c, 0xffffffff, 0x00000380,
139f43cf1b1SMichael Neumann 0x733c, 0xffffffff, 0x00000002,
140f43cf1b1SMichael Neumann 0x2650, 0x00040000, 0,
141f43cf1b1SMichael Neumann 0x20bc, 0x00040000, 0,
142f43cf1b1SMichael Neumann 0x7300, 0xffffffff, 0x001000f0
143f43cf1b1SMichael Neumann };
144f43cf1b1SMichael Neumann
145f43cf1b1SMichael Neumann static const u32 r7xx_golden_dyn_gpr_registers[] =
146f43cf1b1SMichael Neumann {
147f43cf1b1SMichael Neumann 0x8db0, 0xffffffff, 0x98989898,
148f43cf1b1SMichael Neumann 0x8db4, 0xffffffff, 0x98989898,
149f43cf1b1SMichael Neumann 0x8db8, 0xffffffff, 0x98989898,
150f43cf1b1SMichael Neumann 0x8dbc, 0xffffffff, 0x98989898,
151f43cf1b1SMichael Neumann 0x8dc0, 0xffffffff, 0x98989898,
152f43cf1b1SMichael Neumann 0x8dc4, 0xffffffff, 0x98989898,
153f43cf1b1SMichael Neumann 0x8dc8, 0xffffffff, 0x98989898,
154f43cf1b1SMichael Neumann 0x8dcc, 0xffffffff, 0x98989898,
155f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x00000082
156f43cf1b1SMichael Neumann };
157f43cf1b1SMichael Neumann
158f43cf1b1SMichael Neumann static const u32 rv770_golden_registers[] =
159f43cf1b1SMichael Neumann {
160f43cf1b1SMichael Neumann 0x562c, 0xffffffff, 0,
161f43cf1b1SMichael Neumann 0x3f90, 0xffffffff, 0,
162f43cf1b1SMichael Neumann 0x9148, 0xffffffff, 0,
163f43cf1b1SMichael Neumann 0x3f94, 0xffffffff, 0,
164f43cf1b1SMichael Neumann 0x914c, 0xffffffff, 0,
165f43cf1b1SMichael Neumann 0x9698, 0x18000000, 0x18000000
166f43cf1b1SMichael Neumann };
167f43cf1b1SMichael Neumann
168f43cf1b1SMichael Neumann static const u32 rv770ce_golden_registers[] =
169f43cf1b1SMichael Neumann {
170f43cf1b1SMichael Neumann 0x562c, 0xffffffff, 0,
171f43cf1b1SMichael Neumann 0x3f90, 0xffffffff, 0x00cc0000,
172f43cf1b1SMichael Neumann 0x9148, 0xffffffff, 0x00cc0000,
173f43cf1b1SMichael Neumann 0x3f94, 0xffffffff, 0x00cc0000,
174f43cf1b1SMichael Neumann 0x914c, 0xffffffff, 0x00cc0000,
175f43cf1b1SMichael Neumann 0x9b7c, 0xffffffff, 0x00fa0000,
176f43cf1b1SMichael Neumann 0x3f8c, 0xffffffff, 0x00fa0000,
177f43cf1b1SMichael Neumann 0x9698, 0x18000000, 0x18000000
178f43cf1b1SMichael Neumann };
179f43cf1b1SMichael Neumann
180f43cf1b1SMichael Neumann static const u32 rv770_mgcg_init[] =
181f43cf1b1SMichael Neumann {
182f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x130300f9,
183f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100,
184f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100,
185f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100,
186f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100,
187f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100,
188f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100,
189f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x8000100,
190f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x3c000100,
191f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100,
192f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000,
193f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
194f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10001,
195f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
196f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10002,
197f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
198f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10003,
199f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
200f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0,
201f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100,
202f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100,
203f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0,
204f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
205f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1,
206f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
207f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x2,
208f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
209f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x3,
210f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
211f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x4,
212f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
213f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x5,
214f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
215f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x6,
216f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
217f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x7,
218f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
219f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8,
220f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
221f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x9,
222f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
223f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000,
224f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0,
225f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
226f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1,
227f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
228f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x2,
229f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
230f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x3,
231f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
232f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x4,
233f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
234f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x5,
235f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
236f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x6,
237f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
238f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x7,
239f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
240f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8,
241f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
242f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x9,
243f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
244f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000,
245f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0,
246f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
247f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1,
248f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
249f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x2,
250f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
251f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x3,
252f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
253f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x4,
254f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
255f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x5,
256f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
257f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x6,
258f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
259f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x7,
260f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
261f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x8,
262f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
263f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x9,
264f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
265f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000,
266f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100,
267f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100,
268f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100,
269f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100,
270f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100,
271f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100,
272f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100,
273f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100,
274f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100,
275f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100,
276f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001,
277f43cf1b1SMichael Neumann 0x9160, 0xffffffff, 0x00040003,
278f43cf1b1SMichael Neumann 0x916c, 0xffffffff, 0x00060005,
279f43cf1b1SMichael Neumann 0x9170, 0xffffffff, 0x00080007,
280f43cf1b1SMichael Neumann 0x9174, 0xffffffff, 0x000a0009,
281f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x000c000b,
282f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x000e000d,
283f43cf1b1SMichael Neumann 0x9180, 0xffffffff, 0x0010000f,
284f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00120011,
285f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00140013,
286f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00020001,
287f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00040003,
288f43cf1b1SMichael Neumann 0x919c, 0xffffffff, 0x00060005,
289f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00080007,
290f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x000a0009,
291f43cf1b1SMichael Neumann 0x91b0, 0xffffffff, 0x000c000b,
292f43cf1b1SMichael Neumann 0x91b4, 0xffffffff, 0x000e000d,
293f43cf1b1SMichael Neumann 0x91b8, 0xffffffff, 0x0010000f,
294f43cf1b1SMichael Neumann 0x91c4, 0xffffffff, 0x00120011,
295f43cf1b1SMichael Neumann 0x91c8, 0xffffffff, 0x00140013,
296f43cf1b1SMichael Neumann 0x91cc, 0xffffffff, 0x00020001,
297f43cf1b1SMichael Neumann 0x91d0, 0xffffffff, 0x00040003,
298f43cf1b1SMichael Neumann 0x91d4, 0xffffffff, 0x00060005,
299f43cf1b1SMichael Neumann 0x91e0, 0xffffffff, 0x00080007,
300f43cf1b1SMichael Neumann 0x91e4, 0xffffffff, 0x000a0009,
301f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x000c000b,
302f43cf1b1SMichael Neumann 0x91ec, 0xffffffff, 0x00020001,
303f43cf1b1SMichael Neumann 0x91f0, 0xffffffff, 0x00040003,
304f43cf1b1SMichael Neumann 0x91f4, 0xffffffff, 0x00060005,
305f43cf1b1SMichael Neumann 0x9200, 0xffffffff, 0x00080007,
306f43cf1b1SMichael Neumann 0x9204, 0xffffffff, 0x000a0009,
307f43cf1b1SMichael Neumann 0x9208, 0xffffffff, 0x000c000b,
308f43cf1b1SMichael Neumann 0x920c, 0xffffffff, 0x000e000d,
309f43cf1b1SMichael Neumann 0x9210, 0xffffffff, 0x0010000f,
310f43cf1b1SMichael Neumann 0x921c, 0xffffffff, 0x00120011,
311f43cf1b1SMichael Neumann 0x9220, 0xffffffff, 0x00140013,
312f43cf1b1SMichael Neumann 0x9224, 0xffffffff, 0x00020001,
313f43cf1b1SMichael Neumann 0x9228, 0xffffffff, 0x00040003,
314f43cf1b1SMichael Neumann 0x922c, 0xffffffff, 0x00060005,
315f43cf1b1SMichael Neumann 0x9238, 0xffffffff, 0x00080007,
316f43cf1b1SMichael Neumann 0x923c, 0xffffffff, 0x000a0009,
317f43cf1b1SMichael Neumann 0x9240, 0xffffffff, 0x000c000b,
318f43cf1b1SMichael Neumann 0x9244, 0xffffffff, 0x000e000d,
319f43cf1b1SMichael Neumann 0x9248, 0xffffffff, 0x0010000f,
320f43cf1b1SMichael Neumann 0x9254, 0xffffffff, 0x00120011,
321f43cf1b1SMichael Neumann 0x9258, 0xffffffff, 0x00140013,
322f43cf1b1SMichael Neumann 0x925c, 0xffffffff, 0x00020001,
323f43cf1b1SMichael Neumann 0x9260, 0xffffffff, 0x00040003,
324f43cf1b1SMichael Neumann 0x9264, 0xffffffff, 0x00060005,
325f43cf1b1SMichael Neumann 0x9270, 0xffffffff, 0x00080007,
326f43cf1b1SMichael Neumann 0x9274, 0xffffffff, 0x000a0009,
327f43cf1b1SMichael Neumann 0x9278, 0xffffffff, 0x000c000b,
328f43cf1b1SMichael Neumann 0x927c, 0xffffffff, 0x000e000d,
329f43cf1b1SMichael Neumann 0x9280, 0xffffffff, 0x0010000f,
330f43cf1b1SMichael Neumann 0x928c, 0xffffffff, 0x00120011,
331f43cf1b1SMichael Neumann 0x9290, 0xffffffff, 0x00140013,
332f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00020001,
333f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00040003,
334f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00060005,
335f43cf1b1SMichael Neumann 0x92a4, 0xffffffff, 0x00080007
336f43cf1b1SMichael Neumann };
337f43cf1b1SMichael Neumann
338f43cf1b1SMichael Neumann static const u32 rv710_golden_registers[] =
339f43cf1b1SMichael Neumann {
340f43cf1b1SMichael Neumann 0x3f90, 0x00ff0000, 0x00fc0000,
341f43cf1b1SMichael Neumann 0x9148, 0x00ff0000, 0x00fc0000,
342f43cf1b1SMichael Neumann 0x3f94, 0x00ff0000, 0x00fc0000,
343f43cf1b1SMichael Neumann 0x914c, 0x00ff0000, 0x00fc0000,
344f43cf1b1SMichael Neumann 0xb4c, 0x00000020, 0x00000020,
345f43cf1b1SMichael Neumann 0xa180, 0xffffffff, 0x00003f3f
346f43cf1b1SMichael Neumann };
347f43cf1b1SMichael Neumann
348f43cf1b1SMichael Neumann static const u32 rv710_mgcg_init[] =
349f43cf1b1SMichael Neumann {
350f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x13030040,
351f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100,
352f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100,
353f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100,
354f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100,
355f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100,
356f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100,
357f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x8000100,
358f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x3c000100,
359f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100,
360f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000,
361f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
362f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0,
363f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100,
364f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100,
365f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0,
366f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
367f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1,
368f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
369f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000,
370f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0,
371f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
372f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1,
373f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
374f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000,
375f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0,
376f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
377f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1,
378f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
379f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000,
380f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100,
381f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100,
382f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100,
383f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100,
384f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100,
385f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100,
386f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100,
387f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100,
388f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100,
389f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100,
390f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001,
391f43cf1b1SMichael Neumann 0x9174, 0xffffffff, 0x00000003,
392f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x00050001,
393f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x00030002,
394f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00000004,
395f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00070006,
396f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00050001,
397f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00030002,
398f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00000004,
399f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x00070006,
400f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x00000001,
401f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00000001,
402f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00000002,
403f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00040003,
404f43cf1b1SMichael Neumann 0x9150, 0xffffffff, 0x4d940000
405f43cf1b1SMichael Neumann };
406f43cf1b1SMichael Neumann
407f43cf1b1SMichael Neumann static const u32 rv730_golden_registers[] =
408f43cf1b1SMichael Neumann {
409f43cf1b1SMichael Neumann 0x3f90, 0x00ff0000, 0x00f00000,
410f43cf1b1SMichael Neumann 0x9148, 0x00ff0000, 0x00f00000,
411f43cf1b1SMichael Neumann 0x3f94, 0x00ff0000, 0x00f00000,
412f43cf1b1SMichael Neumann 0x914c, 0x00ff0000, 0x00f00000,
413f43cf1b1SMichael Neumann 0x900c, 0xffffffff, 0x003b033f,
414f43cf1b1SMichael Neumann 0xb4c, 0x00000020, 0x00000020,
415f43cf1b1SMichael Neumann 0xa180, 0xffffffff, 0x00003f3f
416f43cf1b1SMichael Neumann };
417f43cf1b1SMichael Neumann
418f43cf1b1SMichael Neumann static const u32 rv730_mgcg_init[] =
419f43cf1b1SMichael Neumann {
420f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x130300f9,
421f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100,
422f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100,
423f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100,
424f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100,
425f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100,
426f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100,
427f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x8000100,
428f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x3c000100,
429f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100,
430f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000,
431f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
432f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10001,
433f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
434f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0,
435f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100,
436f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100,
437f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0,
438f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
439f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1,
440f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
441f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x2,
442f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
443f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x3,
444f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
445f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x4,
446f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
447f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x5,
448f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
449f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x6,
450f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
451f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x7,
452f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
453f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000,
454f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0,
455f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
456f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1,
457f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
458f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x2,
459f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
460f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x3,
461f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
462f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x4,
463f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
464f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x5,
465f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
466f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x6,
467f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
468f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x7,
469f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
470f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000,
471f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0,
472f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
473f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1,
474f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
475f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x2,
476f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
477f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x3,
478f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
479f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x4,
480f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
481f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x5,
482f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
483f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x6,
484f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
485f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x7,
486f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
487f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000,
488f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100,
489f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100,
490f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100,
491f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100,
492f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100,
493f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100,
494f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100,
495f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100,
496f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100,
497f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100,
498f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001,
499f43cf1b1SMichael Neumann 0x916c, 0xffffffff, 0x00040003,
500f43cf1b1SMichael Neumann 0x9170, 0xffffffff, 0x00000005,
501f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x00050001,
502f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x00030002,
503f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00000004,
504f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00070006,
505f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00050001,
506f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00030002,
507f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00000004,
508f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x00070006,
509f43cf1b1SMichael Neumann 0x91b0, 0xffffffff, 0x00050001,
510f43cf1b1SMichael Neumann 0x91b4, 0xffffffff, 0x00030002,
511f43cf1b1SMichael Neumann 0x91c4, 0xffffffff, 0x00000004,
512f43cf1b1SMichael Neumann 0x91c8, 0xffffffff, 0x00070006,
513f43cf1b1SMichael Neumann 0x91cc, 0xffffffff, 0x00050001,
514f43cf1b1SMichael Neumann 0x91d0, 0xffffffff, 0x00030002,
515f43cf1b1SMichael Neumann 0x91e0, 0xffffffff, 0x00000004,
516f43cf1b1SMichael Neumann 0x91e4, 0xffffffff, 0x00070006,
517f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x00000001,
518f43cf1b1SMichael Neumann 0x91ec, 0xffffffff, 0x00050001,
519f43cf1b1SMichael Neumann 0x91f0, 0xffffffff, 0x00030002,
520f43cf1b1SMichael Neumann 0x9200, 0xffffffff, 0x00000004,
521f43cf1b1SMichael Neumann 0x9204, 0xffffffff, 0x00070006,
522f43cf1b1SMichael Neumann 0x9208, 0xffffffff, 0x00050001,
523f43cf1b1SMichael Neumann 0x920c, 0xffffffff, 0x00030002,
524f43cf1b1SMichael Neumann 0x921c, 0xffffffff, 0x00000004,
525f43cf1b1SMichael Neumann 0x9220, 0xffffffff, 0x00070006,
526f43cf1b1SMichael Neumann 0x9224, 0xffffffff, 0x00050001,
527f43cf1b1SMichael Neumann 0x9228, 0xffffffff, 0x00030002,
528f43cf1b1SMichael Neumann 0x9238, 0xffffffff, 0x00000004,
529f43cf1b1SMichael Neumann 0x923c, 0xffffffff, 0x00070006,
530f43cf1b1SMichael Neumann 0x9240, 0xffffffff, 0x00050001,
531f43cf1b1SMichael Neumann 0x9244, 0xffffffff, 0x00030002,
532f43cf1b1SMichael Neumann 0x9254, 0xffffffff, 0x00000004,
533f43cf1b1SMichael Neumann 0x9258, 0xffffffff, 0x00070006,
534f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00000001,
535f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00000002,
536f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00040003,
537f43cf1b1SMichael Neumann 0x92a4, 0xffffffff, 0x00000005
538f43cf1b1SMichael Neumann };
539f43cf1b1SMichael Neumann
540f43cf1b1SMichael Neumann static const u32 rv740_golden_registers[] =
541f43cf1b1SMichael Neumann {
542f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x00000082,
543f43cf1b1SMichael Neumann 0x28a50, 0xfffffffc, 0x00000004,
544f43cf1b1SMichael Neumann 0x2650, 0x00040000, 0,
545f43cf1b1SMichael Neumann 0x20bc, 0x00040000, 0,
546f43cf1b1SMichael Neumann 0x733c, 0xffffffff, 0x00000002,
547f43cf1b1SMichael Neumann 0x7300, 0xffffffff, 0x001000f0,
548f43cf1b1SMichael Neumann 0x3f90, 0x00ff0000, 0,
549f43cf1b1SMichael Neumann 0x9148, 0x00ff0000, 0,
550f43cf1b1SMichael Neumann 0x3f94, 0x00ff0000, 0,
551f43cf1b1SMichael Neumann 0x914c, 0x00ff0000, 0,
552f43cf1b1SMichael Neumann 0x240c, 0xffffffff, 0x00000380,
553f43cf1b1SMichael Neumann 0x8a14, 0x00000007, 0x00000007,
554f43cf1b1SMichael Neumann 0x8b24, 0xffffffff, 0x00ff0fff,
555f43cf1b1SMichael Neumann 0x28a4c, 0xffffffff, 0x00004000,
556f43cf1b1SMichael Neumann 0xa180, 0xffffffff, 0x00003f3f,
557f43cf1b1SMichael Neumann 0x8d00, 0xffffffff, 0x0e0e003a,
558f43cf1b1SMichael Neumann 0x8d04, 0xffffffff, 0x013a0e2a,
559f43cf1b1SMichael Neumann 0x8c00, 0xffffffff, 0xe400000f,
560f43cf1b1SMichael Neumann 0x8db0, 0xffffffff, 0x98989898,
561f43cf1b1SMichael Neumann 0x8db4, 0xffffffff, 0x98989898,
562f43cf1b1SMichael Neumann 0x8db8, 0xffffffff, 0x98989898,
563f43cf1b1SMichael Neumann 0x8dbc, 0xffffffff, 0x98989898,
564f43cf1b1SMichael Neumann 0x8dc0, 0xffffffff, 0x98989898,
565f43cf1b1SMichael Neumann 0x8dc4, 0xffffffff, 0x98989898,
566f43cf1b1SMichael Neumann 0x8dc8, 0xffffffff, 0x98989898,
567f43cf1b1SMichael Neumann 0x8dcc, 0xffffffff, 0x98989898,
568f43cf1b1SMichael Neumann 0x9058, 0xffffffff, 0x0fffc40f,
569f43cf1b1SMichael Neumann 0x900c, 0xffffffff, 0x003b033f,
570f43cf1b1SMichael Neumann 0x28350, 0xffffffff, 0,
571f43cf1b1SMichael Neumann 0x8cf0, 0x1fffffff, 0x08e00420,
572f43cf1b1SMichael Neumann 0x9508, 0xffffffff, 0x00000002,
573f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x000000c2,
574f43cf1b1SMichael Neumann 0x9698, 0x18000000, 0x18000000
575f43cf1b1SMichael Neumann };
576f43cf1b1SMichael Neumann
577f43cf1b1SMichael Neumann static const u32 rv740_mgcg_init[] =
578f43cf1b1SMichael Neumann {
579f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x13030100,
580f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100,
581f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100,
582f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100,
583f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100,
584f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100,
585f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100,
586f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x100,
587f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x100,
588f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100,
589f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000,
590f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
591f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10001,
592f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
593f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10002,
594f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
595f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10003,
596f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100,
597f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0,
598f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100,
599f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100,
600f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0,
601f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
602f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1,
603f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
604f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x2,
605f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
606f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x3,
607f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
608f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x4,
609f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
610f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x5,
611f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
612f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x6,
613f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
614f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x7,
615f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100,
616f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000,
617f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0,
618f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
619f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1,
620f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
621f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x2,
622f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
623f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x3,
624f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
625f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x4,
626f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
627f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x5,
628f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
629f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x6,
630f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
631f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x7,
632f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100,
633f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000,
634f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0,
635f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
636f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1,
637f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
638f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x2,
639f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
640f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x3,
641f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
642f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x4,
643f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
644f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x5,
645f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
646f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x6,
647f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
648f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x7,
649f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100,
650f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000,
651f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100,
652f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100,
653f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100,
654f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100,
655f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100,
656f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100,
657f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100,
658f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100,
659f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100,
660f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100,
661f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001,
662f43cf1b1SMichael Neumann 0x9160, 0xffffffff, 0x00040003,
663f43cf1b1SMichael Neumann 0x916c, 0xffffffff, 0x00060005,
664f43cf1b1SMichael Neumann 0x9170, 0xffffffff, 0x00080007,
665f43cf1b1SMichael Neumann 0x9174, 0xffffffff, 0x000a0009,
666f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x000c000b,
667f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x000e000d,
668f43cf1b1SMichael Neumann 0x9180, 0xffffffff, 0x0010000f,
669f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00120011,
670f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00140013,
671f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00020001,
672f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00040003,
673f43cf1b1SMichael Neumann 0x919c, 0xffffffff, 0x00060005,
674f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00080007,
675f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x000a0009,
676f43cf1b1SMichael Neumann 0x91b0, 0xffffffff, 0x000c000b,
677f43cf1b1SMichael Neumann 0x91b4, 0xffffffff, 0x000e000d,
678f43cf1b1SMichael Neumann 0x91b8, 0xffffffff, 0x0010000f,
679f43cf1b1SMichael Neumann 0x91c4, 0xffffffff, 0x00120011,
680f43cf1b1SMichael Neumann 0x91c8, 0xffffffff, 0x00140013,
681f43cf1b1SMichael Neumann 0x91cc, 0xffffffff, 0x00020001,
682f43cf1b1SMichael Neumann 0x91d0, 0xffffffff, 0x00040003,
683f43cf1b1SMichael Neumann 0x91d4, 0xffffffff, 0x00060005,
684f43cf1b1SMichael Neumann 0x91e0, 0xffffffff, 0x00080007,
685f43cf1b1SMichael Neumann 0x91e4, 0xffffffff, 0x000a0009,
686f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x000c000b,
687f43cf1b1SMichael Neumann 0x91ec, 0xffffffff, 0x00020001,
688f43cf1b1SMichael Neumann 0x91f0, 0xffffffff, 0x00040003,
689f43cf1b1SMichael Neumann 0x91f4, 0xffffffff, 0x00060005,
690f43cf1b1SMichael Neumann 0x9200, 0xffffffff, 0x00080007,
691f43cf1b1SMichael Neumann 0x9204, 0xffffffff, 0x000a0009,
692f43cf1b1SMichael Neumann 0x9208, 0xffffffff, 0x000c000b,
693f43cf1b1SMichael Neumann 0x920c, 0xffffffff, 0x000e000d,
694f43cf1b1SMichael Neumann 0x9210, 0xffffffff, 0x0010000f,
695f43cf1b1SMichael Neumann 0x921c, 0xffffffff, 0x00120011,
696f43cf1b1SMichael Neumann 0x9220, 0xffffffff, 0x00140013,
697f43cf1b1SMichael Neumann 0x9224, 0xffffffff, 0x00020001,
698f43cf1b1SMichael Neumann 0x9228, 0xffffffff, 0x00040003,
699f43cf1b1SMichael Neumann 0x922c, 0xffffffff, 0x00060005,
700f43cf1b1SMichael Neumann 0x9238, 0xffffffff, 0x00080007,
701f43cf1b1SMichael Neumann 0x923c, 0xffffffff, 0x000a0009,
702f43cf1b1SMichael Neumann 0x9240, 0xffffffff, 0x000c000b,
703f43cf1b1SMichael Neumann 0x9244, 0xffffffff, 0x000e000d,
704f43cf1b1SMichael Neumann 0x9248, 0xffffffff, 0x0010000f,
705f43cf1b1SMichael Neumann 0x9254, 0xffffffff, 0x00120011,
706f43cf1b1SMichael Neumann 0x9258, 0xffffffff, 0x00140013,
707f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00020001,
708f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00040003,
709f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00060005,
710f43cf1b1SMichael Neumann 0x92a4, 0xffffffff, 0x00080007
711f43cf1b1SMichael Neumann };
712f43cf1b1SMichael Neumann
rv770_init_golden_registers(struct radeon_device * rdev)713f43cf1b1SMichael Neumann static void rv770_init_golden_registers(struct radeon_device *rdev)
714f43cf1b1SMichael Neumann {
715f43cf1b1SMichael Neumann switch (rdev->family) {
716f43cf1b1SMichael Neumann case CHIP_RV770:
717f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
718f43cf1b1SMichael Neumann r7xx_golden_registers,
719f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_registers));
720f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
721f43cf1b1SMichael Neumann r7xx_golden_dyn_gpr_registers,
722f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
723c6f73aabSFrançois Tigeot if (rdev->pdev->device == 0x994e)
724f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
725f43cf1b1SMichael Neumann rv770ce_golden_registers,
726f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(rv770ce_golden_registers));
727f43cf1b1SMichael Neumann else
728f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
729f43cf1b1SMichael Neumann rv770_golden_registers,
730f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(rv770_golden_registers));
731f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
732f43cf1b1SMichael Neumann rv770_mgcg_init,
733f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(rv770_mgcg_init));
734f43cf1b1SMichael Neumann break;
735f43cf1b1SMichael Neumann case CHIP_RV730:
736f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
737f43cf1b1SMichael Neumann r7xx_golden_registers,
738f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_registers));
739f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
740f43cf1b1SMichael Neumann r7xx_golden_dyn_gpr_registers,
741f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
742f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
743f43cf1b1SMichael Neumann rv730_golden_registers,
74457e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv730_golden_registers));
745f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
746f43cf1b1SMichael Neumann rv730_mgcg_init,
74757e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv730_mgcg_init));
748f43cf1b1SMichael Neumann break;
749f43cf1b1SMichael Neumann case CHIP_RV710:
750f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
751f43cf1b1SMichael Neumann r7xx_golden_registers,
752f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_registers));
753f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
754f43cf1b1SMichael Neumann r7xx_golden_dyn_gpr_registers,
755f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
756f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
757f43cf1b1SMichael Neumann rv710_golden_registers,
75857e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv710_golden_registers));
759f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
760f43cf1b1SMichael Neumann rv710_mgcg_init,
76157e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv710_mgcg_init));
762f43cf1b1SMichael Neumann break;
763f43cf1b1SMichael Neumann case CHIP_RV740:
764f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
765f43cf1b1SMichael Neumann rv740_golden_registers,
76657e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv740_golden_registers));
767f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev,
768f43cf1b1SMichael Neumann rv740_mgcg_init,
76957e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv740_mgcg_init));
770f43cf1b1SMichael Neumann break;
771f43cf1b1SMichael Neumann default:
772f43cf1b1SMichael Neumann break;
773f43cf1b1SMichael Neumann }
774f43cf1b1SMichael Neumann }
775f43cf1b1SMichael Neumann
776b403bed8SMichael Neumann #define PCIE_BUS_CLK 10000
777b403bed8SMichael Neumann #define TCLK (PCIE_BUS_CLK / 10)
778b403bed8SMichael Neumann
779b403bed8SMichael Neumann /**
780b403bed8SMichael Neumann * rv770_get_xclk - get the xclk
781b403bed8SMichael Neumann *
782b403bed8SMichael Neumann * @rdev: radeon_device pointer
783b403bed8SMichael Neumann *
784b403bed8SMichael Neumann * Returns the reference clock used by the gfx engine
785b403bed8SMichael Neumann * (r7xx-cayman).
786b403bed8SMichael Neumann */
rv770_get_xclk(struct radeon_device * rdev)787b403bed8SMichael Neumann u32 rv770_get_xclk(struct radeon_device *rdev)
788b403bed8SMichael Neumann {
789b403bed8SMichael Neumann u32 reference_clock = rdev->clock.spll.reference_freq;
790b403bed8SMichael Neumann u32 tmp = RREG32(CG_CLKPIN_CNTL);
791b403bed8SMichael Neumann
792b403bed8SMichael Neumann if (tmp & MUX_TCLK_TO_XCLK)
793b403bed8SMichael Neumann return TCLK;
794b403bed8SMichael Neumann
795b403bed8SMichael Neumann if (tmp & XTALIN_DIVIDE)
796b403bed8SMichael Neumann return reference_clock / 4;
797b403bed8SMichael Neumann
798b403bed8SMichael Neumann return reference_clock;
799b403bed8SMichael Neumann }
800b403bed8SMichael Neumann
rv770_page_flip(struct radeon_device * rdev,int crtc_id,u64 crtc_base,bool async)801d78d3a22SFrançois Tigeot void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
802926deccbSFrançois Tigeot {
803926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
804926deccbSFrançois Tigeot u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
805926deccbSFrançois Tigeot int i;
806926deccbSFrançois Tigeot
807926deccbSFrançois Tigeot /* Lock the graphics update lock */
808926deccbSFrançois Tigeot tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
809926deccbSFrançois Tigeot WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
810926deccbSFrançois Tigeot
811926deccbSFrançois Tigeot /* update the scanout addresses */
812d78d3a22SFrançois Tigeot WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
813d78d3a22SFrançois Tigeot async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
814926deccbSFrançois Tigeot if (radeon_crtc->crtc_id) {
815926deccbSFrançois Tigeot WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
816926deccbSFrançois Tigeot WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
817926deccbSFrançois Tigeot } else {
818926deccbSFrançois Tigeot WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
819926deccbSFrançois Tigeot WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
820926deccbSFrançois Tigeot }
821926deccbSFrançois Tigeot WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
822926deccbSFrançois Tigeot (u32)crtc_base);
823926deccbSFrançois Tigeot WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
824926deccbSFrançois Tigeot (u32)crtc_base);
825926deccbSFrançois Tigeot
826926deccbSFrançois Tigeot /* Wait for update_pending to go high. */
827926deccbSFrançois Tigeot for (i = 0; i < rdev->usec_timeout; i++) {
828926deccbSFrançois Tigeot if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
829926deccbSFrançois Tigeot break;
830c4ef309bSzrj udelay(1);
831926deccbSFrançois Tigeot }
832926deccbSFrançois Tigeot DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
833926deccbSFrançois Tigeot
834926deccbSFrançois Tigeot /* Unlock the lock, so double-buffering can take place inside vblank */
835926deccbSFrançois Tigeot tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
836926deccbSFrançois Tigeot WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
837c6f73aabSFrançois Tigeot }
838c6f73aabSFrançois Tigeot
rv770_page_flip_pending(struct radeon_device * rdev,int crtc_id)839c6f73aabSFrançois Tigeot bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id)
840c6f73aabSFrançois Tigeot {
841c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
842926deccbSFrançois Tigeot
843926deccbSFrançois Tigeot /* Return current update_pending status: */
844c6f73aabSFrançois Tigeot return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
845c6f73aabSFrançois Tigeot AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
846926deccbSFrançois Tigeot }
847926deccbSFrançois Tigeot
848926deccbSFrançois Tigeot /* get temperature in millidegrees */
rv770_get_temp(struct radeon_device * rdev)849926deccbSFrançois Tigeot int rv770_get_temp(struct radeon_device *rdev)
850926deccbSFrançois Tigeot {
851926deccbSFrançois Tigeot u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
852926deccbSFrançois Tigeot ASIC_T_SHIFT;
853926deccbSFrançois Tigeot int actual_temp;
854926deccbSFrançois Tigeot
855926deccbSFrançois Tigeot if (temp & 0x400)
856926deccbSFrançois Tigeot actual_temp = -256;
857926deccbSFrançois Tigeot else if (temp & 0x200)
858926deccbSFrançois Tigeot actual_temp = 255;
859926deccbSFrançois Tigeot else if (temp & 0x100) {
860926deccbSFrançois Tigeot actual_temp = temp & 0x1ff;
861926deccbSFrançois Tigeot actual_temp |= ~0x1ff;
862926deccbSFrançois Tigeot } else
863926deccbSFrançois Tigeot actual_temp = temp & 0xff;
864926deccbSFrançois Tigeot
865926deccbSFrançois Tigeot return (actual_temp * 1000) / 2;
866926deccbSFrançois Tigeot }
867926deccbSFrançois Tigeot
rv770_pm_misc(struct radeon_device * rdev)868926deccbSFrançois Tigeot void rv770_pm_misc(struct radeon_device *rdev)
869926deccbSFrançois Tigeot {
870926deccbSFrançois Tigeot int req_ps_idx = rdev->pm.requested_power_state_index;
871926deccbSFrançois Tigeot int req_cm_idx = rdev->pm.requested_clock_mode_index;
872926deccbSFrançois Tigeot struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
873926deccbSFrançois Tigeot struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
874926deccbSFrançois Tigeot
875926deccbSFrançois Tigeot if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
876926deccbSFrançois Tigeot /* 0xff01 is a flag rather then an actual voltage */
877926deccbSFrançois Tigeot if (voltage->voltage == 0xff01)
878926deccbSFrançois Tigeot return;
879926deccbSFrançois Tigeot if (voltage->voltage != rdev->pm.current_vddc) {
880926deccbSFrançois Tigeot radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
881926deccbSFrançois Tigeot rdev->pm.current_vddc = voltage->voltage;
882926deccbSFrançois Tigeot DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
883926deccbSFrançois Tigeot }
884926deccbSFrançois Tigeot }
885926deccbSFrançois Tigeot }
886926deccbSFrançois Tigeot
887926deccbSFrançois Tigeot /*
888926deccbSFrançois Tigeot * GART
889926deccbSFrançois Tigeot */
rv770_pcie_gart_enable(struct radeon_device * rdev)890926deccbSFrançois Tigeot static int rv770_pcie_gart_enable(struct radeon_device *rdev)
891926deccbSFrançois Tigeot {
892926deccbSFrançois Tigeot u32 tmp;
893926deccbSFrançois Tigeot int r, i;
894926deccbSFrançois Tigeot
895926deccbSFrançois Tigeot if (rdev->gart.robj == NULL) {
896926deccbSFrançois Tigeot dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
897926deccbSFrançois Tigeot return -EINVAL;
898926deccbSFrançois Tigeot }
899926deccbSFrançois Tigeot r = radeon_gart_table_vram_pin(rdev);
900926deccbSFrançois Tigeot if (r)
901926deccbSFrançois Tigeot return r;
902926deccbSFrançois Tigeot /* Setup L2 cache */
903926deccbSFrançois Tigeot WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
904926deccbSFrançois Tigeot ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
905926deccbSFrançois Tigeot EFFECTIVE_L2_QUEUE_SIZE(7));
906926deccbSFrançois Tigeot WREG32(VM_L2_CNTL2, 0);
907926deccbSFrançois Tigeot WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
908926deccbSFrançois Tigeot /* Setup TLB control */
909926deccbSFrançois Tigeot tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
910926deccbSFrançois Tigeot SYSTEM_ACCESS_MODE_NOT_IN_SYS |
911926deccbSFrançois Tigeot SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
912926deccbSFrançois Tigeot EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
913926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
914926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
915926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
916926deccbSFrançois Tigeot if (rdev->family == CHIP_RV740)
917926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
918926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
919926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
920926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
921926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
922926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
923926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
924926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
925926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
926926deccbSFrançois Tigeot RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
927926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
928926deccbSFrançois Tigeot (u32)(rdev->dummy_page.addr >> 12));
929926deccbSFrançois Tigeot for (i = 1; i < 7; i++)
930926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
931926deccbSFrançois Tigeot
932926deccbSFrançois Tigeot r600_pcie_gart_tlb_flush(rdev);
933926deccbSFrançois Tigeot DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
934926deccbSFrançois Tigeot (unsigned)(rdev->mc.gtt_size >> 20),
935926deccbSFrançois Tigeot (unsigned long long)rdev->gart.table_addr);
936926deccbSFrançois Tigeot rdev->gart.ready = true;
937926deccbSFrançois Tigeot return 0;
938926deccbSFrançois Tigeot }
939926deccbSFrançois Tigeot
rv770_pcie_gart_disable(struct radeon_device * rdev)940926deccbSFrançois Tigeot static void rv770_pcie_gart_disable(struct radeon_device *rdev)
941926deccbSFrançois Tigeot {
942926deccbSFrançois Tigeot u32 tmp;
943926deccbSFrançois Tigeot int i;
944926deccbSFrançois Tigeot
945926deccbSFrançois Tigeot /* Disable all tables */
946926deccbSFrançois Tigeot for (i = 0; i < 7; i++)
947926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
948926deccbSFrançois Tigeot
949926deccbSFrançois Tigeot /* Setup L2 cache */
950926deccbSFrançois Tigeot WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
951926deccbSFrançois Tigeot EFFECTIVE_L2_QUEUE_SIZE(7));
952926deccbSFrançois Tigeot WREG32(VM_L2_CNTL2, 0);
953926deccbSFrançois Tigeot WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
954926deccbSFrançois Tigeot /* Setup TLB control */
955926deccbSFrançois Tigeot tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
956926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
957926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
958926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
959926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
960926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
961926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
962926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
963926deccbSFrançois Tigeot radeon_gart_table_vram_unpin(rdev);
964926deccbSFrançois Tigeot }
965926deccbSFrançois Tigeot
rv770_pcie_gart_fini(struct radeon_device * rdev)966926deccbSFrançois Tigeot static void rv770_pcie_gart_fini(struct radeon_device *rdev)
967926deccbSFrançois Tigeot {
968926deccbSFrançois Tigeot radeon_gart_fini(rdev);
969926deccbSFrançois Tigeot rv770_pcie_gart_disable(rdev);
970926deccbSFrançois Tigeot radeon_gart_table_vram_free(rdev);
971926deccbSFrançois Tigeot }
972926deccbSFrançois Tigeot
973926deccbSFrançois Tigeot
rv770_agp_enable(struct radeon_device * rdev)974926deccbSFrançois Tigeot static void rv770_agp_enable(struct radeon_device *rdev)
975926deccbSFrançois Tigeot {
976926deccbSFrançois Tigeot u32 tmp;
977926deccbSFrançois Tigeot int i;
978926deccbSFrançois Tigeot
979926deccbSFrançois Tigeot /* Setup L2 cache */
980926deccbSFrançois Tigeot WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
981926deccbSFrançois Tigeot ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
982926deccbSFrançois Tigeot EFFECTIVE_L2_QUEUE_SIZE(7));
983926deccbSFrançois Tigeot WREG32(VM_L2_CNTL2, 0);
984926deccbSFrançois Tigeot WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
985926deccbSFrançois Tigeot /* Setup TLB control */
986926deccbSFrançois Tigeot tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
987926deccbSFrançois Tigeot SYSTEM_ACCESS_MODE_NOT_IN_SYS |
988926deccbSFrançois Tigeot SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
989926deccbSFrançois Tigeot EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
990926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
991926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
992926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
993926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
994926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
995926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
996926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
997926deccbSFrançois Tigeot for (i = 0; i < 7; i++)
998926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
999926deccbSFrançois Tigeot }
1000926deccbSFrançois Tigeot
rv770_mc_program(struct radeon_device * rdev)1001926deccbSFrançois Tigeot static void rv770_mc_program(struct radeon_device *rdev)
1002926deccbSFrançois Tigeot {
1003926deccbSFrançois Tigeot struct rv515_mc_save save;
1004926deccbSFrançois Tigeot u32 tmp;
1005926deccbSFrançois Tigeot int i, j;
1006926deccbSFrançois Tigeot
1007926deccbSFrançois Tigeot /* Initialize HDP */
1008926deccbSFrançois Tigeot for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1009926deccbSFrançois Tigeot WREG32((0x2c14 + j), 0x00000000);
1010926deccbSFrançois Tigeot WREG32((0x2c18 + j), 0x00000000);
1011926deccbSFrançois Tigeot WREG32((0x2c1c + j), 0x00000000);
1012926deccbSFrançois Tigeot WREG32((0x2c20 + j), 0x00000000);
1013926deccbSFrançois Tigeot WREG32((0x2c24 + j), 0x00000000);
1014926deccbSFrançois Tigeot }
1015926deccbSFrançois Tigeot /* r7xx hw bug. Read from HDP_DEBUG1 rather
1016926deccbSFrançois Tigeot * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
1017926deccbSFrançois Tigeot */
1018926deccbSFrançois Tigeot tmp = RREG32(HDP_DEBUG1);
1019926deccbSFrançois Tigeot
1020926deccbSFrançois Tigeot rv515_mc_stop(rdev, &save);
1021926deccbSFrançois Tigeot if (r600_mc_wait_for_idle(rdev)) {
1022926deccbSFrançois Tigeot dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1023926deccbSFrançois Tigeot }
1024926deccbSFrançois Tigeot /* Lockout access through VGA aperture*/
1025926deccbSFrançois Tigeot WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1026926deccbSFrançois Tigeot /* Update configuration */
1027926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
1028926deccbSFrançois Tigeot if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1029926deccbSFrançois Tigeot /* VRAM before AGP */
1030926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1031926deccbSFrançois Tigeot rdev->mc.vram_start >> 12);
1032926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1033926deccbSFrançois Tigeot rdev->mc.gtt_end >> 12);
1034926deccbSFrançois Tigeot } else {
1035926deccbSFrançois Tigeot /* VRAM after AGP */
1036926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1037926deccbSFrançois Tigeot rdev->mc.gtt_start >> 12);
1038926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1039926deccbSFrançois Tigeot rdev->mc.vram_end >> 12);
1040926deccbSFrançois Tigeot }
1041926deccbSFrançois Tigeot } else {
1042926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1043926deccbSFrançois Tigeot rdev->mc.vram_start >> 12);
1044926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1045926deccbSFrançois Tigeot rdev->mc.vram_end >> 12);
1046926deccbSFrançois Tigeot }
1047926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1048926deccbSFrançois Tigeot tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1049926deccbSFrançois Tigeot tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1050926deccbSFrançois Tigeot WREG32(MC_VM_FB_LOCATION, tmp);
1051926deccbSFrançois Tigeot WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1052926deccbSFrançois Tigeot WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1053926deccbSFrançois Tigeot WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1054926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
1055926deccbSFrançois Tigeot WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1056926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1057926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1058926deccbSFrançois Tigeot } else {
1059926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BASE, 0);
1060926deccbSFrançois Tigeot WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1061926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1062926deccbSFrançois Tigeot }
1063926deccbSFrançois Tigeot if (r600_mc_wait_for_idle(rdev)) {
1064926deccbSFrançois Tigeot dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1065926deccbSFrançois Tigeot }
1066926deccbSFrançois Tigeot rv515_mc_resume(rdev, &save);
1067926deccbSFrançois Tigeot /* we need to own VRAM, so turn off the VGA renderer here
1068926deccbSFrançois Tigeot * to stop it overwriting our objects */
1069926deccbSFrançois Tigeot rv515_vga_render_disable(rdev);
1070926deccbSFrançois Tigeot }
1071926deccbSFrançois Tigeot
1072926deccbSFrançois Tigeot
1073926deccbSFrançois Tigeot /*
1074926deccbSFrançois Tigeot * CP.
1075926deccbSFrançois Tigeot */
r700_cp_stop(struct radeon_device * rdev)1076926deccbSFrançois Tigeot void r700_cp_stop(struct radeon_device *rdev)
1077926deccbSFrançois Tigeot {
1078c6f73aabSFrançois Tigeot if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1079926deccbSFrançois Tigeot radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1080926deccbSFrançois Tigeot WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1081926deccbSFrançois Tigeot WREG32(SCRATCH_UMSK, 0);
1082926deccbSFrançois Tigeot rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1083926deccbSFrançois Tigeot }
1084926deccbSFrançois Tigeot
rv770_cp_load_microcode(struct radeon_device * rdev)1085926deccbSFrançois Tigeot static int rv770_cp_load_microcode(struct radeon_device *rdev)
1086926deccbSFrançois Tigeot {
1087926deccbSFrançois Tigeot const __be32 *fw_data;
1088926deccbSFrançois Tigeot int i;
1089926deccbSFrançois Tigeot
1090926deccbSFrançois Tigeot if (!rdev->me_fw || !rdev->pfp_fw)
1091926deccbSFrançois Tigeot return -EINVAL;
1092926deccbSFrançois Tigeot
1093926deccbSFrançois Tigeot r700_cp_stop(rdev);
1094926deccbSFrançois Tigeot WREG32(CP_RB_CNTL,
1095926deccbSFrançois Tigeot #ifdef __BIG_ENDIAN
1096926deccbSFrançois Tigeot BUF_SWAP_32BIT |
1097926deccbSFrançois Tigeot #endif
1098926deccbSFrançois Tigeot RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1099926deccbSFrançois Tigeot
1100926deccbSFrançois Tigeot /* Reset cp */
1101926deccbSFrançois Tigeot WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1102926deccbSFrançois Tigeot RREG32(GRBM_SOFT_RESET);
1103c4ef309bSzrj mdelay(15);
1104926deccbSFrançois Tigeot WREG32(GRBM_SOFT_RESET, 0);
1105926deccbSFrançois Tigeot
1106926deccbSFrançois Tigeot fw_data = (const __be32 *)rdev->pfp_fw->data;
1107926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_ADDR, 0);
1108926deccbSFrançois Tigeot for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
1109926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1110926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_ADDR, 0);
1111926deccbSFrançois Tigeot
1112926deccbSFrançois Tigeot fw_data = (const __be32 *)rdev->me_fw->data;
1113926deccbSFrançois Tigeot WREG32(CP_ME_RAM_WADDR, 0);
1114926deccbSFrançois Tigeot for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
1115926deccbSFrançois Tigeot WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1116926deccbSFrançois Tigeot
1117926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_ADDR, 0);
1118926deccbSFrançois Tigeot WREG32(CP_ME_RAM_WADDR, 0);
1119926deccbSFrançois Tigeot WREG32(CP_ME_RAM_RADDR, 0);
1120926deccbSFrançois Tigeot return 0;
1121926deccbSFrançois Tigeot }
1122926deccbSFrançois Tigeot
r700_cp_fini(struct radeon_device * rdev)1123926deccbSFrançois Tigeot void r700_cp_fini(struct radeon_device *rdev)
1124926deccbSFrançois Tigeot {
1125926deccbSFrançois Tigeot struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1126926deccbSFrançois Tigeot r700_cp_stop(rdev);
1127926deccbSFrançois Tigeot radeon_ring_fini(rdev, ring);
1128926deccbSFrançois Tigeot radeon_scratch_free(rdev, ring->rptr_save_reg);
1129926deccbSFrançois Tigeot }
1130926deccbSFrançois Tigeot
rv770_set_clk_bypass_mode(struct radeon_device * rdev)1131c6f73aabSFrançois Tigeot void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
1132c6f73aabSFrançois Tigeot {
1133c6f73aabSFrançois Tigeot u32 tmp, i;
1134c6f73aabSFrançois Tigeot
1135c6f73aabSFrançois Tigeot if (rdev->flags & RADEON_IS_IGP)
1136c6f73aabSFrançois Tigeot return;
1137c6f73aabSFrançois Tigeot
1138c6f73aabSFrançois Tigeot tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1139c6f73aabSFrançois Tigeot tmp &= SCLK_MUX_SEL_MASK;
1140c6f73aabSFrançois Tigeot tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
1141c6f73aabSFrançois Tigeot WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1142c6f73aabSFrançois Tigeot
1143c6f73aabSFrançois Tigeot for (i = 0; i < rdev->usec_timeout; i++) {
1144c6f73aabSFrançois Tigeot if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
1145c6f73aabSFrançois Tigeot break;
1146c6f73aabSFrançois Tigeot udelay(1);
1147c6f73aabSFrançois Tigeot }
1148c6f73aabSFrançois Tigeot
1149c6f73aabSFrançois Tigeot tmp &= ~SCLK_MUX_UPDATE;
1150c6f73aabSFrançois Tigeot WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1151c6f73aabSFrançois Tigeot
1152c6f73aabSFrançois Tigeot tmp = RREG32(MPLL_CNTL_MODE);
1153c6f73aabSFrançois Tigeot if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1154c6f73aabSFrançois Tigeot tmp &= ~RV730_MPLL_MCLK_SEL;
1155c6f73aabSFrançois Tigeot else
1156c6f73aabSFrançois Tigeot tmp &= ~MPLL_MCLK_SEL;
1157c6f73aabSFrançois Tigeot WREG32(MPLL_CNTL_MODE, tmp);
1158c6f73aabSFrançois Tigeot }
1159c6f73aabSFrançois Tigeot
1160926deccbSFrançois Tigeot /*
1161926deccbSFrançois Tigeot * Core functions
1162926deccbSFrançois Tigeot */
rv770_gpu_init(struct radeon_device * rdev)1163926deccbSFrançois Tigeot static void rv770_gpu_init(struct radeon_device *rdev)
1164926deccbSFrançois Tigeot {
1165926deccbSFrançois Tigeot int i, j, num_qd_pipes;
1166926deccbSFrançois Tigeot u32 ta_aux_cntl;
1167926deccbSFrançois Tigeot u32 sx_debug_1;
1168926deccbSFrançois Tigeot u32 smx_dc_ctl0;
1169926deccbSFrançois Tigeot u32 db_debug3;
1170926deccbSFrançois Tigeot u32 num_gs_verts_per_thread;
1171926deccbSFrançois Tigeot u32 vgt_gs_per_es;
1172926deccbSFrançois Tigeot u32 gs_prim_buffer_depth = 0;
1173926deccbSFrançois Tigeot u32 sq_ms_fifo_sizes;
1174926deccbSFrançois Tigeot u32 sq_config;
1175926deccbSFrançois Tigeot u32 sq_thread_resource_mgmt;
1176926deccbSFrançois Tigeot u32 hdp_host_path_cntl;
1177926deccbSFrançois Tigeot u32 sq_dyn_gpr_size_simd_ab_0;
1178926deccbSFrançois Tigeot u32 gb_tiling_config = 0;
1179926deccbSFrançois Tigeot u32 cc_gc_shader_pipe_config = 0;
1180926deccbSFrançois Tigeot u32 mc_arb_ramcfg;
1181926deccbSFrançois Tigeot u32 db_debug4, tmp;
1182926deccbSFrançois Tigeot u32 inactive_pipes, shader_pipe_config;
1183926deccbSFrançois Tigeot u32 disabled_rb_mask;
1184926deccbSFrançois Tigeot unsigned active_number;
1185926deccbSFrançois Tigeot
1186926deccbSFrançois Tigeot /* setup chip specs */
1187926deccbSFrançois Tigeot rdev->config.rv770.tiling_group_size = 256;
1188926deccbSFrançois Tigeot switch (rdev->family) {
1189926deccbSFrançois Tigeot case CHIP_RV770:
1190926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 4;
1191926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 8;
1192926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 10;
1193926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 4;
1194926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 256;
1195926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 248;
1196926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 512;
1197926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 8;
1198926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 16 * 2;
1199926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 128;
1200926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 16;
1201926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 112;
1202926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 2;
1203926deccbSFrançois Tigeot
1204926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7;
1205926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0xF9;
1206926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1207926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1208926deccbSFrançois Tigeot break;
1209926deccbSFrançois Tigeot case CHIP_RV730:
1210926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 2;
1211926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 4;
1212926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 8;
1213926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 2;
1214926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 128;
1215926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 248;
1216926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 256;
1217926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 8;
1218926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 16 * 2;
1219926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 256;
1220926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 32;
1221926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 224;
1222926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 2;
1223926deccbSFrançois Tigeot
1224926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7;
1225926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0xf9;
1226926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1227926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1228926deccbSFrançois Tigeot if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1229926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size -= 16;
1230926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size += 16;
1231926deccbSFrançois Tigeot }
1232926deccbSFrançois Tigeot break;
1233926deccbSFrançois Tigeot case CHIP_RV710:
1234926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 2;
1235926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 2;
1236926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 2;
1237926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 1;
1238926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 256;
1239926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 192;
1240926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 256;
1241926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 4;
1242926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 8 * 2;
1243926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 128;
1244926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 16;
1245926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 112;
1246926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 1;
1247926deccbSFrançois Tigeot
1248926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7;
1249926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0x40;
1250926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1251926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1252926deccbSFrançois Tigeot break;
1253926deccbSFrançois Tigeot case CHIP_RV740:
1254926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 4;
1255926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 4;
1256926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 8;
1257926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 4;
1258926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 256;
1259926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 248;
1260926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 512;
1261926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 8;
1262926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 16 * 2;
1263926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 256;
1264926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 32;
1265926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 224;
1266926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 2;
1267926deccbSFrançois Tigeot
1268926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7;
1269926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0x100;
1270926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1271926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1272926deccbSFrançois Tigeot
1273926deccbSFrançois Tigeot if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1274926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size -= 16;
1275926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size += 16;
1276926deccbSFrançois Tigeot }
1277926deccbSFrançois Tigeot break;
1278926deccbSFrançois Tigeot default:
1279926deccbSFrançois Tigeot break;
1280926deccbSFrançois Tigeot }
1281926deccbSFrançois Tigeot
1282926deccbSFrançois Tigeot /* Initialize HDP */
1283926deccbSFrançois Tigeot j = 0;
1284926deccbSFrançois Tigeot for (i = 0; i < 32; i++) {
1285926deccbSFrançois Tigeot WREG32((0x2c14 + j), 0x00000000);
1286926deccbSFrançois Tigeot WREG32((0x2c18 + j), 0x00000000);
1287926deccbSFrançois Tigeot WREG32((0x2c1c + j), 0x00000000);
1288926deccbSFrançois Tigeot WREG32((0x2c20 + j), 0x00000000);
1289926deccbSFrançois Tigeot WREG32((0x2c24 + j), 0x00000000);
1290926deccbSFrançois Tigeot j += 0x18;
1291926deccbSFrançois Tigeot }
1292926deccbSFrançois Tigeot
1293926deccbSFrançois Tigeot WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1294926deccbSFrançois Tigeot
1295926deccbSFrançois Tigeot /* setup tiling, simd, pipe config */
1296926deccbSFrançois Tigeot mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1297926deccbSFrançois Tigeot
1298926deccbSFrançois Tigeot shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
1299926deccbSFrançois Tigeot inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
1300926deccbSFrançois Tigeot for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1301926deccbSFrançois Tigeot if (!(inactive_pipes & tmp)) {
1302926deccbSFrançois Tigeot active_number++;
1303926deccbSFrançois Tigeot }
1304926deccbSFrançois Tigeot tmp <<= 1;
1305926deccbSFrançois Tigeot }
1306926deccbSFrançois Tigeot if (active_number == 1) {
1307926deccbSFrançois Tigeot WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
1308926deccbSFrançois Tigeot } else {
1309926deccbSFrançois Tigeot WREG32(SPI_CONFIG_CNTL, 0);
1310926deccbSFrançois Tigeot }
1311926deccbSFrançois Tigeot
1312926deccbSFrançois Tigeot cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1313c6f73aabSFrançois Tigeot tmp = rdev->config.rv770.max_simds -
1314c6f73aabSFrançois Tigeot r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
1315c6f73aabSFrançois Tigeot rdev->config.rv770.active_simds = tmp;
1316926deccbSFrançois Tigeot
1317926deccbSFrançois Tigeot switch (rdev->config.rv770.max_tile_pipes) {
1318926deccbSFrançois Tigeot case 1:
1319926deccbSFrançois Tigeot default:
1320926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(0);
1321926deccbSFrançois Tigeot break;
1322926deccbSFrançois Tigeot case 2:
1323926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(1);
1324926deccbSFrançois Tigeot break;
1325926deccbSFrançois Tigeot case 4:
1326926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(2);
1327926deccbSFrançois Tigeot break;
1328926deccbSFrançois Tigeot case 8:
1329926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(3);
1330926deccbSFrançois Tigeot break;
1331926deccbSFrançois Tigeot }
1332926deccbSFrançois Tigeot rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
1333926deccbSFrançois Tigeot
1334926deccbSFrançois Tigeot disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
1335c6f73aabSFrançois Tigeot tmp = 0;
1336c6f73aabSFrançois Tigeot for (i = 0; i < rdev->config.rv770.max_backends; i++)
1337c6f73aabSFrançois Tigeot tmp |= (1 << i);
1338c6f73aabSFrançois Tigeot /* if all the backends are disabled, fix it up here */
1339c6f73aabSFrançois Tigeot if ((disabled_rb_mask & tmp) == tmp) {
1340c6f73aabSFrançois Tigeot for (i = 0; i < rdev->config.rv770.max_backends; i++)
1341c6f73aabSFrançois Tigeot disabled_rb_mask &= ~(1 << i);
1342c6f73aabSFrançois Tigeot }
1343926deccbSFrançois Tigeot tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1344926deccbSFrançois Tigeot tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1345926deccbSFrançois Tigeot R7XX_MAX_BACKENDS, disabled_rb_mask);
1346926deccbSFrançois Tigeot gb_tiling_config |= tmp << 16;
1347926deccbSFrançois Tigeot rdev->config.rv770.backend_map = tmp;
1348926deccbSFrançois Tigeot
1349926deccbSFrançois Tigeot if (rdev->family == CHIP_RV770)
1350926deccbSFrançois Tigeot gb_tiling_config |= BANK_TILING(1);
1351926deccbSFrançois Tigeot else {
1352926deccbSFrançois Tigeot if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1353926deccbSFrançois Tigeot gb_tiling_config |= BANK_TILING(1);
1354926deccbSFrançois Tigeot else
1355926deccbSFrançois Tigeot gb_tiling_config |= BANK_TILING(0);
1356926deccbSFrançois Tigeot }
1357926deccbSFrançois Tigeot rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
1358926deccbSFrançois Tigeot gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1359926deccbSFrançois Tigeot if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1360926deccbSFrançois Tigeot gb_tiling_config |= ROW_TILING(3);
1361926deccbSFrançois Tigeot gb_tiling_config |= SAMPLE_SPLIT(3);
1362926deccbSFrançois Tigeot } else {
1363926deccbSFrançois Tigeot gb_tiling_config |=
1364926deccbSFrançois Tigeot ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1365926deccbSFrançois Tigeot gb_tiling_config |=
1366926deccbSFrançois Tigeot SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1367926deccbSFrançois Tigeot }
1368926deccbSFrançois Tigeot
1369926deccbSFrançois Tigeot gb_tiling_config |= BANK_SWAPS(1);
1370926deccbSFrançois Tigeot rdev->config.rv770.tile_config = gb_tiling_config;
1371926deccbSFrançois Tigeot
1372926deccbSFrançois Tigeot WREG32(GB_TILING_CONFIG, gb_tiling_config);
1373926deccbSFrançois Tigeot WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1374926deccbSFrançois Tigeot WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1375926deccbSFrançois Tigeot WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
1376926deccbSFrançois Tigeot WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1377f43cf1b1SMichael Neumann if (rdev->family == CHIP_RV730) {
1378f43cf1b1SMichael Neumann WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1379f43cf1b1SMichael Neumann WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1380f43cf1b1SMichael Neumann WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1381f43cf1b1SMichael Neumann }
1382926deccbSFrançois Tigeot
1383926deccbSFrançois Tigeot WREG32(CGTS_SYS_TCC_DISABLE, 0);
1384926deccbSFrançois Tigeot WREG32(CGTS_TCC_DISABLE, 0);
1385926deccbSFrançois Tigeot WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1386926deccbSFrançois Tigeot WREG32(CGTS_USER_TCC_DISABLE, 0);
1387926deccbSFrançois Tigeot
1388926deccbSFrançois Tigeot
1389926deccbSFrançois Tigeot num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1390926deccbSFrançois Tigeot WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
1391926deccbSFrançois Tigeot WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1392926deccbSFrançois Tigeot
1393926deccbSFrançois Tigeot /* set HW defaults for 3D engine */
1394926deccbSFrançois Tigeot WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1395926deccbSFrançois Tigeot ROQ_IB2_START(0x2b)));
1396926deccbSFrançois Tigeot
1397926deccbSFrançois Tigeot WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1398926deccbSFrançois Tigeot
1399926deccbSFrançois Tigeot ta_aux_cntl = RREG32(TA_CNTL_AUX);
1400926deccbSFrançois Tigeot WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
1401926deccbSFrançois Tigeot
1402926deccbSFrançois Tigeot sx_debug_1 = RREG32(SX_DEBUG_1);
1403926deccbSFrançois Tigeot sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1404926deccbSFrançois Tigeot WREG32(SX_DEBUG_1, sx_debug_1);
1405926deccbSFrançois Tigeot
1406926deccbSFrançois Tigeot smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1407926deccbSFrançois Tigeot smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
1408926deccbSFrançois Tigeot smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
1409926deccbSFrançois Tigeot WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1410926deccbSFrançois Tigeot
1411926deccbSFrançois Tigeot if (rdev->family != CHIP_RV740)
1412926deccbSFrançois Tigeot WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
1413926deccbSFrançois Tigeot GS_FLUSH_CTL(4) |
1414926deccbSFrançois Tigeot ACK_FLUSH_CTL(3) |
1415926deccbSFrançois Tigeot SYNC_FLUSH_CTL));
1416926deccbSFrançois Tigeot
1417926deccbSFrançois Tigeot if (rdev->family != CHIP_RV770)
1418926deccbSFrançois Tigeot WREG32(SMX_SAR_CTL0, 0x00003f3f);
1419926deccbSFrançois Tigeot
1420926deccbSFrançois Tigeot db_debug3 = RREG32(DB_DEBUG3);
1421926deccbSFrançois Tigeot db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
1422926deccbSFrançois Tigeot switch (rdev->family) {
1423926deccbSFrançois Tigeot case CHIP_RV770:
1424926deccbSFrançois Tigeot case CHIP_RV740:
1425926deccbSFrançois Tigeot db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
1426926deccbSFrançois Tigeot break;
1427926deccbSFrançois Tigeot case CHIP_RV710:
1428926deccbSFrançois Tigeot case CHIP_RV730:
1429926deccbSFrançois Tigeot default:
1430926deccbSFrançois Tigeot db_debug3 |= DB_CLK_OFF_DELAY(2);
1431926deccbSFrançois Tigeot break;
1432926deccbSFrançois Tigeot }
1433926deccbSFrançois Tigeot WREG32(DB_DEBUG3, db_debug3);
1434926deccbSFrançois Tigeot
1435926deccbSFrançois Tigeot if (rdev->family != CHIP_RV770) {
1436926deccbSFrançois Tigeot db_debug4 = RREG32(DB_DEBUG4);
1437926deccbSFrançois Tigeot db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
1438926deccbSFrançois Tigeot WREG32(DB_DEBUG4, db_debug4);
1439926deccbSFrançois Tigeot }
1440926deccbSFrançois Tigeot
1441926deccbSFrançois Tigeot WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1442926deccbSFrançois Tigeot POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
1443926deccbSFrançois Tigeot SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
1444926deccbSFrançois Tigeot
1445926deccbSFrançois Tigeot WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1446926deccbSFrançois Tigeot SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
1447926deccbSFrançois Tigeot SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
1448926deccbSFrançois Tigeot
1449926deccbSFrançois Tigeot WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1450926deccbSFrançois Tigeot
1451926deccbSFrançois Tigeot WREG32(VGT_NUM_INSTANCES, 1);
1452926deccbSFrançois Tigeot
1453926deccbSFrançois Tigeot WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1454926deccbSFrançois Tigeot
1455926deccbSFrançois Tigeot WREG32(CP_PERFMON_CNTL, 0);
1456926deccbSFrançois Tigeot
1457926deccbSFrançois Tigeot sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
1458926deccbSFrançois Tigeot DONE_FIFO_HIWATER(0xe0) |
1459926deccbSFrançois Tigeot ALU_UPDATE_FIFO_HIWATER(0x8));
1460926deccbSFrançois Tigeot switch (rdev->family) {
1461926deccbSFrançois Tigeot case CHIP_RV770:
1462926deccbSFrançois Tigeot case CHIP_RV730:
1463926deccbSFrançois Tigeot case CHIP_RV710:
1464926deccbSFrançois Tigeot sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
1465926deccbSFrançois Tigeot break;
1466926deccbSFrançois Tigeot case CHIP_RV740:
1467926deccbSFrançois Tigeot default:
1468926deccbSFrançois Tigeot sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
1469926deccbSFrançois Tigeot break;
1470926deccbSFrançois Tigeot }
1471926deccbSFrançois Tigeot WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1472926deccbSFrançois Tigeot
1473926deccbSFrançois Tigeot /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1474926deccbSFrançois Tigeot * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1475926deccbSFrançois Tigeot */
1476926deccbSFrançois Tigeot sq_config = RREG32(SQ_CONFIG);
1477926deccbSFrançois Tigeot sq_config &= ~(PS_PRIO(3) |
1478926deccbSFrançois Tigeot VS_PRIO(3) |
1479926deccbSFrançois Tigeot GS_PRIO(3) |
1480926deccbSFrançois Tigeot ES_PRIO(3));
1481926deccbSFrançois Tigeot sq_config |= (DX9_CONSTS |
1482926deccbSFrançois Tigeot VC_ENABLE |
1483926deccbSFrançois Tigeot EXPORT_SRC_C |
1484926deccbSFrançois Tigeot PS_PRIO(0) |
1485926deccbSFrançois Tigeot VS_PRIO(1) |
1486926deccbSFrançois Tigeot GS_PRIO(2) |
1487926deccbSFrançois Tigeot ES_PRIO(3));
1488926deccbSFrançois Tigeot if (rdev->family == CHIP_RV710)
1489926deccbSFrançois Tigeot /* no vertex cache */
1490926deccbSFrançois Tigeot sq_config &= ~VC_ENABLE;
1491926deccbSFrançois Tigeot
1492926deccbSFrançois Tigeot WREG32(SQ_CONFIG, sq_config);
1493926deccbSFrançois Tigeot
1494926deccbSFrançois Tigeot WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1495926deccbSFrançois Tigeot NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1496926deccbSFrançois Tigeot NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
1497926deccbSFrançois Tigeot
1498926deccbSFrançois Tigeot WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1499926deccbSFrançois Tigeot NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
1500926deccbSFrançois Tigeot
1501926deccbSFrançois Tigeot sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
1502926deccbSFrançois Tigeot NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
1503926deccbSFrançois Tigeot NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
1504926deccbSFrançois Tigeot if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
1505926deccbSFrançois Tigeot sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
1506926deccbSFrançois Tigeot else
1507926deccbSFrançois Tigeot sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
1508926deccbSFrançois Tigeot WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1509926deccbSFrançois Tigeot
1510926deccbSFrançois Tigeot WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1511926deccbSFrançois Tigeot NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1512926deccbSFrançois Tigeot
1513926deccbSFrançois Tigeot WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1514926deccbSFrançois Tigeot NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1515926deccbSFrançois Tigeot
1516926deccbSFrançois Tigeot sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1517926deccbSFrançois Tigeot SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
1518926deccbSFrançois Tigeot SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1519926deccbSFrançois Tigeot SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
1520926deccbSFrançois Tigeot
1521926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1522926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1523926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1524926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1525926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1526926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1527926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1528926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1529926deccbSFrançois Tigeot
1530926deccbSFrançois Tigeot WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1531926deccbSFrançois Tigeot FORCE_EOV_MAX_REZ_CNT(255)));
1532926deccbSFrançois Tigeot
1533926deccbSFrançois Tigeot if (rdev->family == CHIP_RV710)
1534926deccbSFrançois Tigeot WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
1535926deccbSFrançois Tigeot AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1536926deccbSFrançois Tigeot else
1537926deccbSFrançois Tigeot WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
1538926deccbSFrançois Tigeot AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1539926deccbSFrançois Tigeot
1540926deccbSFrançois Tigeot switch (rdev->family) {
1541926deccbSFrançois Tigeot case CHIP_RV770:
1542926deccbSFrançois Tigeot case CHIP_RV730:
1543926deccbSFrançois Tigeot case CHIP_RV740:
1544926deccbSFrançois Tigeot gs_prim_buffer_depth = 384;
1545926deccbSFrançois Tigeot break;
1546926deccbSFrançois Tigeot case CHIP_RV710:
1547926deccbSFrançois Tigeot gs_prim_buffer_depth = 128;
1548926deccbSFrançois Tigeot break;
1549926deccbSFrançois Tigeot default:
1550926deccbSFrançois Tigeot break;
1551926deccbSFrançois Tigeot }
1552926deccbSFrançois Tigeot
1553926deccbSFrançois Tigeot num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
1554926deccbSFrançois Tigeot vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1555926deccbSFrançois Tigeot /* Max value for this is 256 */
1556926deccbSFrançois Tigeot if (vgt_gs_per_es > 256)
1557926deccbSFrançois Tigeot vgt_gs_per_es = 256;
1558926deccbSFrançois Tigeot
1559926deccbSFrançois Tigeot WREG32(VGT_ES_PER_GS, 128);
1560926deccbSFrançois Tigeot WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
1561926deccbSFrançois Tigeot WREG32(VGT_GS_PER_VS, 2);
1562926deccbSFrançois Tigeot
1563926deccbSFrançois Tigeot /* more default values. 2D/3D driver should adjust as needed */
1564926deccbSFrançois Tigeot WREG32(VGT_GS_VERTEX_REUSE, 16);
1565926deccbSFrançois Tigeot WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1566926deccbSFrançois Tigeot WREG32(VGT_STRMOUT_EN, 0);
1567926deccbSFrançois Tigeot WREG32(SX_MISC, 0);
1568926deccbSFrançois Tigeot WREG32(PA_SC_MODE_CNTL, 0);
1569926deccbSFrançois Tigeot WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
1570926deccbSFrançois Tigeot WREG32(PA_SC_AA_CONFIG, 0);
1571926deccbSFrançois Tigeot WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
1572926deccbSFrançois Tigeot WREG32(PA_SC_LINE_STIPPLE, 0);
1573926deccbSFrançois Tigeot WREG32(SPI_INPUT_Z, 0);
1574926deccbSFrançois Tigeot WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1575926deccbSFrançois Tigeot WREG32(CB_COLOR7_FRAG, 0);
1576926deccbSFrançois Tigeot
1577926deccbSFrançois Tigeot /* clear render buffer base addresses */
1578926deccbSFrançois Tigeot WREG32(CB_COLOR0_BASE, 0);
1579926deccbSFrançois Tigeot WREG32(CB_COLOR1_BASE, 0);
1580926deccbSFrançois Tigeot WREG32(CB_COLOR2_BASE, 0);
1581926deccbSFrançois Tigeot WREG32(CB_COLOR3_BASE, 0);
1582926deccbSFrançois Tigeot WREG32(CB_COLOR4_BASE, 0);
1583926deccbSFrançois Tigeot WREG32(CB_COLOR5_BASE, 0);
1584926deccbSFrançois Tigeot WREG32(CB_COLOR6_BASE, 0);
1585926deccbSFrançois Tigeot WREG32(CB_COLOR7_BASE, 0);
1586926deccbSFrançois Tigeot
1587926deccbSFrançois Tigeot WREG32(TCP_CNTL, 0);
1588926deccbSFrançois Tigeot
1589926deccbSFrançois Tigeot hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1590926deccbSFrançois Tigeot WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1591926deccbSFrançois Tigeot
1592926deccbSFrançois Tigeot WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1593926deccbSFrançois Tigeot
1594926deccbSFrançois Tigeot WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1595926deccbSFrançois Tigeot NUM_CLIP_SEQ(3)));
1596926deccbSFrançois Tigeot WREG32(VC_ENHANCE, 0);
1597926deccbSFrançois Tigeot }
1598926deccbSFrançois Tigeot
r700_vram_gtt_location(struct radeon_device * rdev,struct radeon_mc * mc)1599926deccbSFrançois Tigeot void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1600926deccbSFrançois Tigeot {
1601926deccbSFrançois Tigeot u64 size_bf, size_af;
1602926deccbSFrançois Tigeot
1603926deccbSFrançois Tigeot if (mc->mc_vram_size > 0xE0000000) {
1604926deccbSFrançois Tigeot /* leave room for at least 512M GTT */
1605926deccbSFrançois Tigeot dev_warn(rdev->dev, "limiting VRAM\n");
1606926deccbSFrançois Tigeot mc->real_vram_size = 0xE0000000;
1607926deccbSFrançois Tigeot mc->mc_vram_size = 0xE0000000;
1608926deccbSFrançois Tigeot }
1609926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
1610926deccbSFrançois Tigeot size_bf = mc->gtt_start;
1611f43cf1b1SMichael Neumann size_af = mc->mc_mask - mc->gtt_end;
1612926deccbSFrançois Tigeot if (size_bf > size_af) {
1613926deccbSFrançois Tigeot if (mc->mc_vram_size > size_bf) {
1614926deccbSFrançois Tigeot dev_warn(rdev->dev, "limiting VRAM\n");
1615926deccbSFrançois Tigeot mc->real_vram_size = size_bf;
1616926deccbSFrançois Tigeot mc->mc_vram_size = size_bf;
1617926deccbSFrançois Tigeot }
1618926deccbSFrançois Tigeot mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1619926deccbSFrançois Tigeot } else {
1620926deccbSFrançois Tigeot if (mc->mc_vram_size > size_af) {
1621926deccbSFrançois Tigeot dev_warn(rdev->dev, "limiting VRAM\n");
1622926deccbSFrançois Tigeot mc->real_vram_size = size_af;
1623926deccbSFrançois Tigeot mc->mc_vram_size = size_af;
1624926deccbSFrançois Tigeot }
1625926deccbSFrançois Tigeot mc->vram_start = mc->gtt_end + 1;
1626926deccbSFrançois Tigeot }
1627926deccbSFrançois Tigeot mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1628f77dbd6cSFrançois Tigeot dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
16294cd92098Szrj mc->mc_vram_size >> 20, mc->vram_start,
16304cd92098Szrj mc->vram_end, mc->real_vram_size >> 20);
1631926deccbSFrançois Tigeot } else {
1632926deccbSFrançois Tigeot radeon_vram_location(rdev, &rdev->mc, 0);
1633926deccbSFrançois Tigeot rdev->mc.gtt_base_align = 0;
1634926deccbSFrançois Tigeot radeon_gtt_location(rdev, mc);
1635926deccbSFrançois Tigeot }
1636926deccbSFrançois Tigeot }
1637926deccbSFrançois Tigeot
rv770_mc_init(struct radeon_device * rdev)1638926deccbSFrançois Tigeot static int rv770_mc_init(struct radeon_device *rdev)
1639926deccbSFrançois Tigeot {
1640926deccbSFrançois Tigeot u32 tmp;
1641926deccbSFrançois Tigeot int chansize, numchan;
1642926deccbSFrançois Tigeot
1643926deccbSFrançois Tigeot /* Get VRAM informations */
1644926deccbSFrançois Tigeot rdev->mc.vram_is_ddr = true;
1645926deccbSFrançois Tigeot tmp = RREG32(MC_ARB_RAMCFG);
1646926deccbSFrançois Tigeot if (tmp & CHANSIZE_OVERRIDE) {
1647926deccbSFrançois Tigeot chansize = 16;
1648926deccbSFrançois Tigeot } else if (tmp & CHANSIZE_MASK) {
1649926deccbSFrançois Tigeot chansize = 64;
1650926deccbSFrançois Tigeot } else {
1651926deccbSFrançois Tigeot chansize = 32;
1652926deccbSFrançois Tigeot }
1653926deccbSFrançois Tigeot tmp = RREG32(MC_SHARED_CHMAP);
1654926deccbSFrançois Tigeot switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1655926deccbSFrançois Tigeot case 0:
1656926deccbSFrançois Tigeot default:
1657926deccbSFrançois Tigeot numchan = 1;
1658926deccbSFrançois Tigeot break;
1659926deccbSFrançois Tigeot case 1:
1660926deccbSFrançois Tigeot numchan = 2;
1661926deccbSFrançois Tigeot break;
1662926deccbSFrançois Tigeot case 2:
1663926deccbSFrançois Tigeot numchan = 4;
1664926deccbSFrançois Tigeot break;
1665926deccbSFrançois Tigeot case 3:
1666926deccbSFrançois Tigeot numchan = 8;
1667926deccbSFrançois Tigeot break;
1668926deccbSFrançois Tigeot }
1669926deccbSFrançois Tigeot rdev->mc.vram_width = numchan * chansize;
1670926deccbSFrançois Tigeot /* Could aper size report 0 ? */
16714a26d795SImre Vadasz rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
16724a26d795SImre Vadasz rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1673926deccbSFrançois Tigeot /* Setup GPU memory space */
1674926deccbSFrançois Tigeot rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1675926deccbSFrançois Tigeot rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1676926deccbSFrançois Tigeot rdev->mc.visible_vram_size = rdev->mc.aper_size;
1677926deccbSFrançois Tigeot r700_vram_gtt_location(rdev, &rdev->mc);
1678926deccbSFrançois Tigeot radeon_update_bandwidth_info(rdev);
1679926deccbSFrançois Tigeot
1680926deccbSFrançois Tigeot return 0;
1681926deccbSFrançois Tigeot }
1682926deccbSFrançois Tigeot
rv770_uvd_init(struct radeon_device * rdev)1683d78d3a22SFrançois Tigeot static void rv770_uvd_init(struct radeon_device *rdev)
1684d78d3a22SFrançois Tigeot {
1685d78d3a22SFrançois Tigeot int r;
1686d78d3a22SFrançois Tigeot
1687d78d3a22SFrançois Tigeot if (!rdev->has_uvd)
1688d78d3a22SFrançois Tigeot return;
1689d78d3a22SFrançois Tigeot
1690d78d3a22SFrançois Tigeot r = radeon_uvd_init(rdev);
1691d78d3a22SFrançois Tigeot if (r) {
1692d78d3a22SFrançois Tigeot dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
1693d78d3a22SFrançois Tigeot /*
1694d78d3a22SFrançois Tigeot * At this point rdev->uvd.vcpu_bo is NULL which trickles down
1695d78d3a22SFrançois Tigeot * to early fails uvd_v2_2_resume() and thus nothing happens
1696d78d3a22SFrançois Tigeot * there. So it is pointless to try to go through that code
1697d78d3a22SFrançois Tigeot * hence why we disable uvd here.
1698d78d3a22SFrançois Tigeot */
1699d78d3a22SFrançois Tigeot rdev->has_uvd = 0;
1700d78d3a22SFrançois Tigeot return;
1701d78d3a22SFrançois Tigeot }
1702d78d3a22SFrançois Tigeot rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1703d78d3a22SFrançois Tigeot r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
1704d78d3a22SFrançois Tigeot }
1705d78d3a22SFrançois Tigeot
rv770_uvd_start(struct radeon_device * rdev)1706d78d3a22SFrançois Tigeot static void rv770_uvd_start(struct radeon_device *rdev)
1707d78d3a22SFrançois Tigeot {
1708d78d3a22SFrançois Tigeot int r;
1709d78d3a22SFrançois Tigeot
1710d78d3a22SFrançois Tigeot if (!rdev->has_uvd)
1711d78d3a22SFrançois Tigeot return;
1712d78d3a22SFrançois Tigeot
1713d78d3a22SFrançois Tigeot r = uvd_v2_2_resume(rdev);
1714d78d3a22SFrançois Tigeot if (r) {
1715d78d3a22SFrançois Tigeot dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
1716d78d3a22SFrançois Tigeot goto error;
1717d78d3a22SFrançois Tigeot }
1718d78d3a22SFrançois Tigeot r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
1719d78d3a22SFrançois Tigeot if (r) {
1720d78d3a22SFrançois Tigeot dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
1721d78d3a22SFrançois Tigeot goto error;
1722d78d3a22SFrançois Tigeot }
1723d78d3a22SFrançois Tigeot return;
1724d78d3a22SFrançois Tigeot
1725d78d3a22SFrançois Tigeot error:
1726d78d3a22SFrançois Tigeot rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1727d78d3a22SFrançois Tigeot }
1728d78d3a22SFrançois Tigeot
rv770_uvd_resume(struct radeon_device * rdev)1729d78d3a22SFrançois Tigeot static void rv770_uvd_resume(struct radeon_device *rdev)
1730d78d3a22SFrançois Tigeot {
1731d78d3a22SFrançois Tigeot struct radeon_ring *ring;
1732d78d3a22SFrançois Tigeot int r;
1733d78d3a22SFrançois Tigeot
1734d78d3a22SFrançois Tigeot if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
1735d78d3a22SFrançois Tigeot return;
1736d78d3a22SFrançois Tigeot
1737d78d3a22SFrançois Tigeot ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1738*1dedbd3bSFrançois Tigeot r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
1739d78d3a22SFrançois Tigeot if (r) {
1740d78d3a22SFrançois Tigeot dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
1741d78d3a22SFrançois Tigeot return;
1742d78d3a22SFrançois Tigeot }
1743d78d3a22SFrançois Tigeot r = uvd_v1_0_init(rdev);
1744d78d3a22SFrançois Tigeot if (r) {
1745d78d3a22SFrançois Tigeot dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
1746d78d3a22SFrançois Tigeot return;
1747d78d3a22SFrançois Tigeot }
1748d78d3a22SFrançois Tigeot }
1749d78d3a22SFrançois Tigeot
rv770_startup(struct radeon_device * rdev)1750926deccbSFrançois Tigeot static int rv770_startup(struct radeon_device *rdev)
1751926deccbSFrançois Tigeot {
1752926deccbSFrançois Tigeot struct radeon_ring *ring;
1753926deccbSFrançois Tigeot int r;
1754926deccbSFrançois Tigeot
1755926deccbSFrançois Tigeot /* enable pcie gen2 link */
1756926deccbSFrançois Tigeot rv770_pcie_gen2_enable(rdev);
1757926deccbSFrançois Tigeot
17584cd92098Szrj /* scratch needs to be initialized before MC */
17594cd92098Szrj r = r600_vram_scratch_init(rdev);
17604cd92098Szrj if (r)
17614cd92098Szrj return r;
17624cd92098Szrj
176357e252bfSMichael Neumann rv770_mc_program(rdev);
176457e252bfSMichael Neumann
1765926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
1766926deccbSFrançois Tigeot rv770_agp_enable(rdev);
1767926deccbSFrançois Tigeot } else {
1768926deccbSFrançois Tigeot r = rv770_pcie_gart_enable(rdev);
1769926deccbSFrançois Tigeot if (r)
1770926deccbSFrançois Tigeot return r;
1771926deccbSFrançois Tigeot }
1772926deccbSFrançois Tigeot
1773926deccbSFrançois Tigeot rv770_gpu_init(rdev);
1774926deccbSFrançois Tigeot
1775926deccbSFrançois Tigeot /* allocate wb buffer */
1776926deccbSFrançois Tigeot r = radeon_wb_init(rdev);
1777926deccbSFrançois Tigeot if (r)
1778926deccbSFrançois Tigeot return r;
1779926deccbSFrançois Tigeot
1780926deccbSFrançois Tigeot r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1781926deccbSFrançois Tigeot if (r) {
1782926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1783926deccbSFrançois Tigeot return r;
1784926deccbSFrançois Tigeot }
1785926deccbSFrançois Tigeot
1786926deccbSFrançois Tigeot r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1787926deccbSFrançois Tigeot if (r) {
1788926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1789926deccbSFrançois Tigeot return r;
1790926deccbSFrançois Tigeot }
1791926deccbSFrançois Tigeot
1792d78d3a22SFrançois Tigeot rv770_uvd_start(rdev);
1793f43cf1b1SMichael Neumann
1794926deccbSFrançois Tigeot /* Enable IRQ */
1795f43cf1b1SMichael Neumann if (!rdev->irq.installed) {
1796f43cf1b1SMichael Neumann r = radeon_irq_kms_init(rdev);
1797f43cf1b1SMichael Neumann if (r)
1798f43cf1b1SMichael Neumann return r;
1799f43cf1b1SMichael Neumann }
1800f43cf1b1SMichael Neumann
1801926deccbSFrançois Tigeot r = r600_irq_init(rdev);
1802926deccbSFrançois Tigeot if (r) {
1803926deccbSFrançois Tigeot DRM_ERROR("radeon: IH init failed (%d).\n", r);
1804926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev);
1805926deccbSFrançois Tigeot return r;
1806926deccbSFrançois Tigeot }
1807926deccbSFrançois Tigeot r600_irq_set(rdev);
1808926deccbSFrançois Tigeot
1809926deccbSFrançois Tigeot ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1810926deccbSFrançois Tigeot r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
18114cd92098Szrj RADEON_CP_PACKET2);
1812926deccbSFrançois Tigeot if (r)
1813926deccbSFrançois Tigeot return r;
1814926deccbSFrançois Tigeot
1815926deccbSFrançois Tigeot ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1816926deccbSFrançois Tigeot r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
18174cd92098Szrj DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1818926deccbSFrançois Tigeot if (r)
1819926deccbSFrançois Tigeot return r;
1820926deccbSFrançois Tigeot
1821926deccbSFrançois Tigeot r = rv770_cp_load_microcode(rdev);
1822926deccbSFrançois Tigeot if (r)
1823926deccbSFrançois Tigeot return r;
1824926deccbSFrançois Tigeot r = r600_cp_resume(rdev);
1825926deccbSFrançois Tigeot if (r)
1826926deccbSFrançois Tigeot return r;
1827926deccbSFrançois Tigeot
1828926deccbSFrançois Tigeot r = r600_dma_resume(rdev);
1829926deccbSFrançois Tigeot if (r)
1830926deccbSFrançois Tigeot return r;
1831926deccbSFrançois Tigeot
1832d78d3a22SFrançois Tigeot rv770_uvd_resume(rdev);
1833f43cf1b1SMichael Neumann
1834926deccbSFrançois Tigeot r = radeon_ib_pool_init(rdev);
1835926deccbSFrançois Tigeot if (r) {
1836926deccbSFrançois Tigeot dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1837926deccbSFrançois Tigeot return r;
1838926deccbSFrançois Tigeot }
1839926deccbSFrançois Tigeot
1840c59a5c48SFrançois Tigeot r = radeon_audio_init(rdev);
1841926deccbSFrançois Tigeot if (r) {
1842926deccbSFrançois Tigeot DRM_ERROR("radeon: audio init failed\n");
1843926deccbSFrançois Tigeot return r;
1844926deccbSFrançois Tigeot }
1845926deccbSFrançois Tigeot
1846926deccbSFrançois Tigeot return 0;
1847926deccbSFrançois Tigeot }
1848926deccbSFrançois Tigeot
rv770_resume(struct radeon_device * rdev)1849926deccbSFrançois Tigeot int rv770_resume(struct radeon_device *rdev)
1850926deccbSFrançois Tigeot {
1851926deccbSFrançois Tigeot int r;
1852926deccbSFrançois Tigeot
1853926deccbSFrançois Tigeot /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1854926deccbSFrançois Tigeot * posting will perform necessary task to bring back GPU into good
1855926deccbSFrançois Tigeot * shape.
1856926deccbSFrançois Tigeot */
1857926deccbSFrançois Tigeot /* post card */
1858926deccbSFrançois Tigeot atom_asic_init(rdev->mode_info.atom_context);
1859926deccbSFrançois Tigeot
1860f43cf1b1SMichael Neumann /* init golden registers */
1861f43cf1b1SMichael Neumann rv770_init_golden_registers(rdev);
1862f43cf1b1SMichael Neumann
1863c6f73aabSFrançois Tigeot if (rdev->pm.pm_method == PM_METHOD_DPM)
1864c6f73aabSFrançois Tigeot radeon_pm_resume(rdev);
1865c6f73aabSFrançois Tigeot
1866926deccbSFrançois Tigeot rdev->accel_working = true;
1867926deccbSFrançois Tigeot r = rv770_startup(rdev);
1868926deccbSFrançois Tigeot if (r) {
1869926deccbSFrançois Tigeot DRM_ERROR("r600 startup failed on resume\n");
1870926deccbSFrançois Tigeot rdev->accel_working = false;
1871926deccbSFrançois Tigeot return r;
1872926deccbSFrançois Tigeot }
1873926deccbSFrançois Tigeot
1874926deccbSFrançois Tigeot return r;
1875926deccbSFrançois Tigeot
1876926deccbSFrançois Tigeot }
1877926deccbSFrançois Tigeot
rv770_suspend(struct radeon_device * rdev)1878926deccbSFrançois Tigeot int rv770_suspend(struct radeon_device *rdev)
1879926deccbSFrançois Tigeot {
1880c6f73aabSFrançois Tigeot radeon_pm_suspend(rdev);
1881c59a5c48SFrançois Tigeot radeon_audio_fini(rdev);
1882d78d3a22SFrançois Tigeot if (rdev->has_uvd) {
18834cd92098Szrj uvd_v1_0_fini(rdev);
1884f43cf1b1SMichael Neumann radeon_uvd_suspend(rdev);
1885d78d3a22SFrançois Tigeot }
1886926deccbSFrançois Tigeot r700_cp_stop(rdev);
1887926deccbSFrançois Tigeot r600_dma_stop(rdev);
1888926deccbSFrançois Tigeot r600_irq_suspend(rdev);
1889926deccbSFrançois Tigeot radeon_wb_disable(rdev);
1890926deccbSFrançois Tigeot rv770_pcie_gart_disable(rdev);
1891926deccbSFrançois Tigeot
1892926deccbSFrançois Tigeot return 0;
1893926deccbSFrançois Tigeot }
1894926deccbSFrançois Tigeot
1895926deccbSFrançois Tigeot /* Plan is to move initialization in that function and use
1896926deccbSFrançois Tigeot * helper function so that radeon_device_init pretty much
1897926deccbSFrançois Tigeot * do nothing more than calling asic specific function. This
1898926deccbSFrançois Tigeot * should also allow to remove a bunch of callback function
1899926deccbSFrançois Tigeot * like vram_info.
1900926deccbSFrançois Tigeot */
rv770_init(struct radeon_device * rdev)1901926deccbSFrançois Tigeot int rv770_init(struct radeon_device *rdev)
1902926deccbSFrançois Tigeot {
1903926deccbSFrançois Tigeot int r;
1904926deccbSFrançois Tigeot
1905926deccbSFrançois Tigeot /* Read BIOS */
1906926deccbSFrançois Tigeot if (!radeon_get_bios(rdev)) {
1907926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev))
1908926deccbSFrançois Tigeot return -EINVAL;
1909926deccbSFrançois Tigeot }
1910926deccbSFrançois Tigeot /* Must be an ATOMBIOS */
1911926deccbSFrançois Tigeot if (!rdev->is_atom_bios) {
1912926deccbSFrançois Tigeot dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1913926deccbSFrançois Tigeot return -EINVAL;
1914926deccbSFrançois Tigeot }
1915926deccbSFrançois Tigeot r = radeon_atombios_init(rdev);
1916926deccbSFrançois Tigeot if (r)
1917926deccbSFrançois Tigeot return r;
1918926deccbSFrançois Tigeot /* Post card if necessary */
1919926deccbSFrançois Tigeot if (!radeon_card_posted(rdev)) {
1920926deccbSFrançois Tigeot if (!rdev->bios) {
1921926deccbSFrançois Tigeot dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1922926deccbSFrançois Tigeot return -EINVAL;
1923926deccbSFrançois Tigeot }
1924926deccbSFrançois Tigeot DRM_INFO("GPU not posted. posting now...\n");
1925926deccbSFrançois Tigeot atom_asic_init(rdev->mode_info.atom_context);
1926926deccbSFrançois Tigeot }
1927f43cf1b1SMichael Neumann /* init golden registers */
1928f43cf1b1SMichael Neumann rv770_init_golden_registers(rdev);
1929926deccbSFrançois Tigeot /* Initialize scratch registers */
1930926deccbSFrançois Tigeot r600_scratch_init(rdev);
1931926deccbSFrançois Tigeot /* Initialize surface registers */
1932926deccbSFrançois Tigeot radeon_surface_init(rdev);
1933926deccbSFrançois Tigeot /* Initialize clocks */
1934926deccbSFrançois Tigeot radeon_get_clock_info(rdev->ddev);
1935926deccbSFrançois Tigeot /* Fence driver */
1936926deccbSFrançois Tigeot r = radeon_fence_driver_init(rdev);
1937926deccbSFrançois Tigeot if (r)
1938926deccbSFrançois Tigeot return r;
1939926deccbSFrançois Tigeot /* initialize AGP */
1940926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) {
1941926deccbSFrançois Tigeot r = radeon_agp_init(rdev);
1942926deccbSFrançois Tigeot if (r)
1943926deccbSFrançois Tigeot radeon_agp_disable(rdev);
1944926deccbSFrançois Tigeot }
1945926deccbSFrançois Tigeot r = rv770_mc_init(rdev);
1946926deccbSFrançois Tigeot if (r)
1947926deccbSFrançois Tigeot return r;
1948926deccbSFrançois Tigeot /* Memory manager */
1949926deccbSFrançois Tigeot r = radeon_bo_init(rdev);
1950926deccbSFrançois Tigeot if (r)
1951926deccbSFrançois Tigeot return r;
1952926deccbSFrançois Tigeot
1953c6f73aabSFrançois Tigeot if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1954c6f73aabSFrançois Tigeot r = r600_init_microcode(rdev);
1955c6f73aabSFrançois Tigeot if (r) {
1956c6f73aabSFrançois Tigeot DRM_ERROR("Failed to load firmware!\n");
1957c6f73aabSFrançois Tigeot return r;
1958c6f73aabSFrançois Tigeot }
1959c6f73aabSFrançois Tigeot }
1960c6f73aabSFrançois Tigeot
1961c6f73aabSFrançois Tigeot /* Initialize power management */
1962c6f73aabSFrançois Tigeot radeon_pm_init(rdev);
1963c6f73aabSFrançois Tigeot
1964926deccbSFrançois Tigeot rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1965926deccbSFrançois Tigeot r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1966926deccbSFrançois Tigeot
1967926deccbSFrançois Tigeot rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1968926deccbSFrançois Tigeot r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1969926deccbSFrançois Tigeot
1970d78d3a22SFrançois Tigeot rv770_uvd_init(rdev);
1971f43cf1b1SMichael Neumann
1972926deccbSFrançois Tigeot rdev->ih.ring_obj = NULL;
1973926deccbSFrançois Tigeot r600_ih_ring_init(rdev, 64 * 1024);
1974926deccbSFrançois Tigeot
1975926deccbSFrançois Tigeot r = r600_pcie_gart_init(rdev);
1976926deccbSFrançois Tigeot if (r)
1977926deccbSFrançois Tigeot return r;
1978926deccbSFrançois Tigeot
1979926deccbSFrançois Tigeot rdev->accel_working = true;
1980926deccbSFrançois Tigeot r = rv770_startup(rdev);
1981926deccbSFrançois Tigeot if (r) {
1982926deccbSFrançois Tigeot dev_err(rdev->dev, "disabling GPU acceleration\n");
1983926deccbSFrançois Tigeot r700_cp_fini(rdev);
1984926deccbSFrançois Tigeot r600_dma_fini(rdev);
1985926deccbSFrançois Tigeot r600_irq_fini(rdev);
1986926deccbSFrançois Tigeot radeon_wb_fini(rdev);
1987926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev);
1988926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev);
1989926deccbSFrançois Tigeot rv770_pcie_gart_fini(rdev);
1990926deccbSFrançois Tigeot rdev->accel_working = false;
1991926deccbSFrançois Tigeot }
1992926deccbSFrançois Tigeot
1993926deccbSFrançois Tigeot return 0;
1994926deccbSFrançois Tigeot }
1995926deccbSFrançois Tigeot
rv770_fini(struct radeon_device * rdev)1996926deccbSFrançois Tigeot void rv770_fini(struct radeon_device *rdev)
1997926deccbSFrançois Tigeot {
1998c6f73aabSFrançois Tigeot radeon_pm_fini(rdev);
1999926deccbSFrançois Tigeot r700_cp_fini(rdev);
2000926deccbSFrançois Tigeot r600_dma_fini(rdev);
2001926deccbSFrançois Tigeot r600_irq_fini(rdev);
2002926deccbSFrançois Tigeot radeon_wb_fini(rdev);
2003926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev);
2004926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev);
20054cd92098Szrj uvd_v1_0_fini(rdev);
2006f43cf1b1SMichael Neumann radeon_uvd_fini(rdev);
2007c6f73aabSFrançois Tigeot rv770_pcie_gart_fini(rdev);
2008926deccbSFrançois Tigeot r600_vram_scratch_fini(rdev);
2009926deccbSFrançois Tigeot radeon_gem_fini(rdev);
2010926deccbSFrançois Tigeot radeon_fence_driver_fini(rdev);
2011926deccbSFrançois Tigeot radeon_agp_fini(rdev);
2012926deccbSFrançois Tigeot radeon_bo_fini(rdev);
2013926deccbSFrançois Tigeot radeon_atombios_fini(rdev);
2014926deccbSFrançois Tigeot r600_fini_microcode(rdev);
2015c4ef309bSzrj kfree(rdev->bios);
2016926deccbSFrançois Tigeot rdev->bios = NULL;
2017926deccbSFrançois Tigeot }
2018926deccbSFrançois Tigeot
rv770_pcie_gen2_enable(struct radeon_device * rdev)2019926deccbSFrançois Tigeot static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
2020926deccbSFrançois Tigeot {
2021926deccbSFrançois Tigeot u32 link_width_cntl, lanes, speed_cntl, tmp;
2022926deccbSFrançois Tigeot u16 link_cntl2;
2023926deccbSFrançois Tigeot u32 mask;
2024926deccbSFrançois Tigeot int ret;
2025926deccbSFrançois Tigeot
2026926deccbSFrançois Tigeot if (radeon_pcie_gen2 == 0)
2027926deccbSFrançois Tigeot return;
2028926deccbSFrançois Tigeot
2029926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_IGP)
2030926deccbSFrançois Tigeot return;
2031926deccbSFrançois Tigeot
2032926deccbSFrançois Tigeot if (!(rdev->flags & RADEON_IS_PCIE))
2033926deccbSFrançois Tigeot return;
2034926deccbSFrançois Tigeot
2035926deccbSFrançois Tigeot /* x2 cards have a special sequence */
2036926deccbSFrançois Tigeot if (ASIC_IS_X2(rdev))
2037926deccbSFrançois Tigeot return;
2038926deccbSFrançois Tigeot
2039926deccbSFrançois Tigeot ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
2040926deccbSFrançois Tigeot if (ret != 0)
2041926deccbSFrançois Tigeot return;
2042926deccbSFrançois Tigeot
2043ee479021SImre Vadász if (!(mask & DRM_PCIE_SPEED_50))
2044926deccbSFrançois Tigeot return;
2045926deccbSFrançois Tigeot
2046926deccbSFrançois Tigeot DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
2047926deccbSFrançois Tigeot
2048926deccbSFrançois Tigeot /* advertise upconfig capability */
2049f43cf1b1SMichael Neumann link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2050926deccbSFrançois Tigeot link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2051f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2052f43cf1b1SMichael Neumann link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2053926deccbSFrançois Tigeot if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
2054926deccbSFrançois Tigeot lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2055926deccbSFrançois Tigeot link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
2056926deccbSFrançois Tigeot LC_RECONFIG_ARC_MISSING_ESCAPE);
2057926deccbSFrançois Tigeot link_width_cntl |= lanes | LC_RECONFIG_NOW |
2058926deccbSFrançois Tigeot LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
2059f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2060926deccbSFrançois Tigeot } else {
2061926deccbSFrançois Tigeot link_width_cntl |= LC_UPCONFIGURE_DIS;
2062f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2063926deccbSFrançois Tigeot }
2064926deccbSFrançois Tigeot
2065f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2066926deccbSFrançois Tigeot if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
2067926deccbSFrançois Tigeot (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
2068926deccbSFrançois Tigeot
2069926deccbSFrançois Tigeot tmp = RREG32(0x541c);
2070926deccbSFrançois Tigeot WREG32(0x541c, tmp | 0x8);
2071926deccbSFrançois Tigeot WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
2072926deccbSFrançois Tigeot link_cntl2 = RREG16(0x4088);
2073926deccbSFrançois Tigeot link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
2074926deccbSFrançois Tigeot link_cntl2 |= 0x2;
2075926deccbSFrançois Tigeot WREG16(0x4088, link_cntl2);
2076926deccbSFrançois Tigeot WREG32(MM_CFGREGS_CNTL, 0);
2077926deccbSFrançois Tigeot
2078f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2079926deccbSFrançois Tigeot speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
2080f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2081926deccbSFrançois Tigeot
2082f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2083926deccbSFrançois Tigeot speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
2084f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2085926deccbSFrançois Tigeot
2086f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2087926deccbSFrançois Tigeot speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
2088f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2089926deccbSFrançois Tigeot
2090f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2091926deccbSFrançois Tigeot speed_cntl |= LC_GEN2_EN_STRAP;
2092f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2093926deccbSFrançois Tigeot
2094926deccbSFrançois Tigeot } else {
2095f43cf1b1SMichael Neumann link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2096926deccbSFrançois Tigeot /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
2097926deccbSFrançois Tigeot if (1)
2098926deccbSFrançois Tigeot link_width_cntl |= LC_UPCONFIGURE_DIS;
2099926deccbSFrançois Tigeot else
2100926deccbSFrançois Tigeot link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2101f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2102926deccbSFrançois Tigeot }
2103926deccbSFrançois Tigeot }
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