1926deccbSFrançois Tigeot /* 2926deccbSFrançois Tigeot * Copyright 2008 Advanced Micro Devices, Inc. 3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc. 4926deccbSFrançois Tigeot * Copyright 2009 Jerome Glisse. 5926deccbSFrançois Tigeot * 6926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 7926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 8926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation 9926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 11926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 12926deccbSFrançois Tigeot * 13926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 14926deccbSFrançois Tigeot * all copies or substantial portions of the Software. 15926deccbSFrançois Tigeot * 16926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 23926deccbSFrançois Tigeot * 24926deccbSFrançois Tigeot * Authors: Dave Airlie 25926deccbSFrançois Tigeot * Alex Deucher 26926deccbSFrançois Tigeot * Jerome Glisse 27926deccbSFrançois Tigeot * 28926deccbSFrançois Tigeot * $FreeBSD: head/sys/dev/drm2/radeon/rv770.c 254885 2013-08-25 19:37:15Z dumbbell $ 29926deccbSFrançois Tigeot */ 30926deccbSFrançois Tigeot 31926deccbSFrançois Tigeot #include <drm/drmP.h> 32926deccbSFrançois Tigeot #include "radeon.h" 33926deccbSFrançois Tigeot #include "radeon_asic.h" 34926deccbSFrançois Tigeot #include <uapi_drm/radeon_drm.h> 35926deccbSFrançois Tigeot #include "rv770d.h" 36926deccbSFrançois Tigeot #include "atom.h" 37926deccbSFrançois Tigeot #include "avivod.h" 38926deccbSFrançois Tigeot 39926deccbSFrançois Tigeot #define R700_PFP_UCODE_SIZE 848 40926deccbSFrançois Tigeot #define R700_PM4_UCODE_SIZE 1360 41926deccbSFrançois Tigeot 42926deccbSFrançois Tigeot static void rv770_gpu_init(struct radeon_device *rdev); 43926deccbSFrançois Tigeot static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 44926deccbSFrançois Tigeot 45f43cf1b1SMichael Neumann int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 46f43cf1b1SMichael Neumann { 47f43cf1b1SMichael Neumann unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; 48f43cf1b1SMichael Neumann int r; 49f43cf1b1SMichael Neumann 50f43cf1b1SMichael Neumann /* RV740 uses evergreen uvd clk programming */ 51f43cf1b1SMichael Neumann if (rdev->family == CHIP_RV740) 52f43cf1b1SMichael Neumann return evergreen_set_uvd_clocks(rdev, vclk, dclk); 53f43cf1b1SMichael Neumann 54f43cf1b1SMichael Neumann /* bypass vclk and dclk with bclk */ 55f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_2, 56f43cf1b1SMichael Neumann VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 57f43cf1b1SMichael Neumann ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 58f43cf1b1SMichael Neumann 59f43cf1b1SMichael Neumann if (!vclk || !dclk) { 60f43cf1b1SMichael Neumann /* keep the Bypass mode, put PLL to sleep */ 61f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 62f43cf1b1SMichael Neumann return 0; 63f43cf1b1SMichael Neumann } 64f43cf1b1SMichael Neumann 65f43cf1b1SMichael Neumann r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 66f43cf1b1SMichael Neumann 43663, 0x03FFFFFE, 1, 30, ~0, 67f43cf1b1SMichael Neumann &fb_div, &vclk_div, &dclk_div); 68f43cf1b1SMichael Neumann if (r) 69f43cf1b1SMichael Neumann return r; 70f43cf1b1SMichael Neumann 71f43cf1b1SMichael Neumann fb_div |= 1; 72f43cf1b1SMichael Neumann vclk_div -= 1; 73f43cf1b1SMichael Neumann dclk_div -= 1; 74f43cf1b1SMichael Neumann 75f43cf1b1SMichael Neumann /* set UPLL_FB_DIV to 0x50000 */ 76f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); 77f43cf1b1SMichael Neumann 78f43cf1b1SMichael Neumann /* deassert UPLL_RESET and UPLL_SLEEP */ 79f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); 80f43cf1b1SMichael Neumann 81f43cf1b1SMichael Neumann /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ 82f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 83f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); 84f43cf1b1SMichael Neumann 85f43cf1b1SMichael Neumann r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 86f43cf1b1SMichael Neumann if (r) 87f43cf1b1SMichael Neumann return r; 88f43cf1b1SMichael Neumann 89f43cf1b1SMichael Neumann /* assert PLL_RESET */ 90f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 91f43cf1b1SMichael Neumann 92f43cf1b1SMichael Neumann /* set the required FB_DIV, REF_DIV, Post divder values */ 93f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); 94f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_2, 95f43cf1b1SMichael Neumann UPLL_SW_HILEN(vclk_div >> 1) | 96f43cf1b1SMichael Neumann UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 97f43cf1b1SMichael Neumann UPLL_SW_HILEN2(dclk_div >> 1) | 98f43cf1b1SMichael Neumann UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), 99f43cf1b1SMichael Neumann ~UPLL_SW_MASK); 100f43cf1b1SMichael Neumann 101f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), 102f43cf1b1SMichael Neumann ~UPLL_FB_DIV_MASK); 103f43cf1b1SMichael Neumann 104f43cf1b1SMichael Neumann /* give the PLL some time to settle */ 105f43cf1b1SMichael Neumann DRM_MDELAY(15); 106f43cf1b1SMichael Neumann 107f43cf1b1SMichael Neumann /* deassert PLL_RESET */ 108f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 109f43cf1b1SMichael Neumann 110f43cf1b1SMichael Neumann DRM_MDELAY(15); 111f43cf1b1SMichael Neumann 112f43cf1b1SMichael Neumann /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ 113f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 114f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); 115f43cf1b1SMichael Neumann 116f43cf1b1SMichael Neumann r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 117f43cf1b1SMichael Neumann if (r) 118f43cf1b1SMichael Neumann return r; 119f43cf1b1SMichael Neumann 120f43cf1b1SMichael Neumann /* switch VCLK and DCLK selection */ 121f43cf1b1SMichael Neumann WREG32_P(CG_UPLL_FUNC_CNTL_2, 122f43cf1b1SMichael Neumann VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 123f43cf1b1SMichael Neumann ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 124f43cf1b1SMichael Neumann 125f43cf1b1SMichael Neumann DRM_MDELAY(100); 126f43cf1b1SMichael Neumann 127f43cf1b1SMichael Neumann return 0; 128f43cf1b1SMichael Neumann } 129f43cf1b1SMichael Neumann 130f43cf1b1SMichael Neumann static const u32 r7xx_golden_registers[] = 131f43cf1b1SMichael Neumann { 132f43cf1b1SMichael Neumann 0x8d00, 0xffffffff, 0x0e0e0074, 133f43cf1b1SMichael Neumann 0x8d04, 0xffffffff, 0x013a2b34, 134f43cf1b1SMichael Neumann 0x9508, 0xffffffff, 0x00000002, 135f43cf1b1SMichael Neumann 0x8b20, 0xffffffff, 0, 136f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x000000c2, 137f43cf1b1SMichael Neumann 0x28350, 0xffffffff, 0, 138f43cf1b1SMichael Neumann 0x9058, 0xffffffff, 0x0fffc40f, 139f43cf1b1SMichael Neumann 0x240c, 0xffffffff, 0x00000380, 140f43cf1b1SMichael Neumann 0x733c, 0xffffffff, 0x00000002, 141f43cf1b1SMichael Neumann 0x2650, 0x00040000, 0, 142f43cf1b1SMichael Neumann 0x20bc, 0x00040000, 0, 143f43cf1b1SMichael Neumann 0x7300, 0xffffffff, 0x001000f0 144f43cf1b1SMichael Neumann }; 145f43cf1b1SMichael Neumann 146f43cf1b1SMichael Neumann static const u32 r7xx_golden_dyn_gpr_registers[] = 147f43cf1b1SMichael Neumann { 148f43cf1b1SMichael Neumann 0x8db0, 0xffffffff, 0x98989898, 149f43cf1b1SMichael Neumann 0x8db4, 0xffffffff, 0x98989898, 150f43cf1b1SMichael Neumann 0x8db8, 0xffffffff, 0x98989898, 151f43cf1b1SMichael Neumann 0x8dbc, 0xffffffff, 0x98989898, 152f43cf1b1SMichael Neumann 0x8dc0, 0xffffffff, 0x98989898, 153f43cf1b1SMichael Neumann 0x8dc4, 0xffffffff, 0x98989898, 154f43cf1b1SMichael Neumann 0x8dc8, 0xffffffff, 0x98989898, 155f43cf1b1SMichael Neumann 0x8dcc, 0xffffffff, 0x98989898, 156f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x00000082 157f43cf1b1SMichael Neumann }; 158f43cf1b1SMichael Neumann 159f43cf1b1SMichael Neumann static const u32 rv770_golden_registers[] = 160f43cf1b1SMichael Neumann { 161f43cf1b1SMichael Neumann 0x562c, 0xffffffff, 0, 162f43cf1b1SMichael Neumann 0x3f90, 0xffffffff, 0, 163f43cf1b1SMichael Neumann 0x9148, 0xffffffff, 0, 164f43cf1b1SMichael Neumann 0x3f94, 0xffffffff, 0, 165f43cf1b1SMichael Neumann 0x914c, 0xffffffff, 0, 166f43cf1b1SMichael Neumann 0x9698, 0x18000000, 0x18000000 167f43cf1b1SMichael Neumann }; 168f43cf1b1SMichael Neumann 169f43cf1b1SMichael Neumann static const u32 rv770ce_golden_registers[] = 170f43cf1b1SMichael Neumann { 171f43cf1b1SMichael Neumann 0x562c, 0xffffffff, 0, 172f43cf1b1SMichael Neumann 0x3f90, 0xffffffff, 0x00cc0000, 173f43cf1b1SMichael Neumann 0x9148, 0xffffffff, 0x00cc0000, 174f43cf1b1SMichael Neumann 0x3f94, 0xffffffff, 0x00cc0000, 175f43cf1b1SMichael Neumann 0x914c, 0xffffffff, 0x00cc0000, 176f43cf1b1SMichael Neumann 0x9b7c, 0xffffffff, 0x00fa0000, 177f43cf1b1SMichael Neumann 0x3f8c, 0xffffffff, 0x00fa0000, 178f43cf1b1SMichael Neumann 0x9698, 0x18000000, 0x18000000 179f43cf1b1SMichael Neumann }; 180f43cf1b1SMichael Neumann 181f43cf1b1SMichael Neumann static const u32 rv770_mgcg_init[] = 182f43cf1b1SMichael Neumann { 183f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x130300f9, 184f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100, 185f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100, 186f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100, 187f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100, 188f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100, 189f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100, 190f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x8000100, 191f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x3c000100, 192f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100, 193f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000, 194f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 195f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10001, 196f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 197f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10002, 198f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 199f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10003, 200f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 201f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0, 202f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100, 203f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100, 204f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0, 205f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 206f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1, 207f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 208f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x2, 209f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 210f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x3, 211f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 212f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x4, 213f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 214f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x5, 215f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 216f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x6, 217f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 218f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x7, 219f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 220f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8, 221f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 222f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x9, 223f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 224f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000, 225f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0, 226f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 227f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1, 228f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 229f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x2, 230f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 231f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x3, 232f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 233f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x4, 234f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 235f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x5, 236f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 237f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x6, 238f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 239f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x7, 240f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 241f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8, 242f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 243f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x9, 244f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 245f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000, 246f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0, 247f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 248f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1, 249f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 250f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x2, 251f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 252f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x3, 253f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 254f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x4, 255f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 256f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x5, 257f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 258f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x6, 259f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 260f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x7, 261f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 262f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x8, 263f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 264f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x9, 265f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 266f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000, 267f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100, 268f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100, 269f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100, 270f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100, 271f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100, 272f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100, 273f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100, 274f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100, 275f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100, 276f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100, 277f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001, 278f43cf1b1SMichael Neumann 0x9160, 0xffffffff, 0x00040003, 279f43cf1b1SMichael Neumann 0x916c, 0xffffffff, 0x00060005, 280f43cf1b1SMichael Neumann 0x9170, 0xffffffff, 0x00080007, 281f43cf1b1SMichael Neumann 0x9174, 0xffffffff, 0x000a0009, 282f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x000c000b, 283f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x000e000d, 284f43cf1b1SMichael Neumann 0x9180, 0xffffffff, 0x0010000f, 285f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00120011, 286f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00140013, 287f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00020001, 288f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00040003, 289f43cf1b1SMichael Neumann 0x919c, 0xffffffff, 0x00060005, 290f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00080007, 291f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x000a0009, 292f43cf1b1SMichael Neumann 0x91b0, 0xffffffff, 0x000c000b, 293f43cf1b1SMichael Neumann 0x91b4, 0xffffffff, 0x000e000d, 294f43cf1b1SMichael Neumann 0x91b8, 0xffffffff, 0x0010000f, 295f43cf1b1SMichael Neumann 0x91c4, 0xffffffff, 0x00120011, 296f43cf1b1SMichael Neumann 0x91c8, 0xffffffff, 0x00140013, 297f43cf1b1SMichael Neumann 0x91cc, 0xffffffff, 0x00020001, 298f43cf1b1SMichael Neumann 0x91d0, 0xffffffff, 0x00040003, 299f43cf1b1SMichael Neumann 0x91d4, 0xffffffff, 0x00060005, 300f43cf1b1SMichael Neumann 0x91e0, 0xffffffff, 0x00080007, 301f43cf1b1SMichael Neumann 0x91e4, 0xffffffff, 0x000a0009, 302f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x000c000b, 303f43cf1b1SMichael Neumann 0x91ec, 0xffffffff, 0x00020001, 304f43cf1b1SMichael Neumann 0x91f0, 0xffffffff, 0x00040003, 305f43cf1b1SMichael Neumann 0x91f4, 0xffffffff, 0x00060005, 306f43cf1b1SMichael Neumann 0x9200, 0xffffffff, 0x00080007, 307f43cf1b1SMichael Neumann 0x9204, 0xffffffff, 0x000a0009, 308f43cf1b1SMichael Neumann 0x9208, 0xffffffff, 0x000c000b, 309f43cf1b1SMichael Neumann 0x920c, 0xffffffff, 0x000e000d, 310f43cf1b1SMichael Neumann 0x9210, 0xffffffff, 0x0010000f, 311f43cf1b1SMichael Neumann 0x921c, 0xffffffff, 0x00120011, 312f43cf1b1SMichael Neumann 0x9220, 0xffffffff, 0x00140013, 313f43cf1b1SMichael Neumann 0x9224, 0xffffffff, 0x00020001, 314f43cf1b1SMichael Neumann 0x9228, 0xffffffff, 0x00040003, 315f43cf1b1SMichael Neumann 0x922c, 0xffffffff, 0x00060005, 316f43cf1b1SMichael Neumann 0x9238, 0xffffffff, 0x00080007, 317f43cf1b1SMichael Neumann 0x923c, 0xffffffff, 0x000a0009, 318f43cf1b1SMichael Neumann 0x9240, 0xffffffff, 0x000c000b, 319f43cf1b1SMichael Neumann 0x9244, 0xffffffff, 0x000e000d, 320f43cf1b1SMichael Neumann 0x9248, 0xffffffff, 0x0010000f, 321f43cf1b1SMichael Neumann 0x9254, 0xffffffff, 0x00120011, 322f43cf1b1SMichael Neumann 0x9258, 0xffffffff, 0x00140013, 323f43cf1b1SMichael Neumann 0x925c, 0xffffffff, 0x00020001, 324f43cf1b1SMichael Neumann 0x9260, 0xffffffff, 0x00040003, 325f43cf1b1SMichael Neumann 0x9264, 0xffffffff, 0x00060005, 326f43cf1b1SMichael Neumann 0x9270, 0xffffffff, 0x00080007, 327f43cf1b1SMichael Neumann 0x9274, 0xffffffff, 0x000a0009, 328f43cf1b1SMichael Neumann 0x9278, 0xffffffff, 0x000c000b, 329f43cf1b1SMichael Neumann 0x927c, 0xffffffff, 0x000e000d, 330f43cf1b1SMichael Neumann 0x9280, 0xffffffff, 0x0010000f, 331f43cf1b1SMichael Neumann 0x928c, 0xffffffff, 0x00120011, 332f43cf1b1SMichael Neumann 0x9290, 0xffffffff, 0x00140013, 333f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00020001, 334f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00040003, 335f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00060005, 336f43cf1b1SMichael Neumann 0x92a4, 0xffffffff, 0x00080007 337f43cf1b1SMichael Neumann }; 338f43cf1b1SMichael Neumann 339f43cf1b1SMichael Neumann static const u32 rv710_golden_registers[] = 340f43cf1b1SMichael Neumann { 341f43cf1b1SMichael Neumann 0x3f90, 0x00ff0000, 0x00fc0000, 342f43cf1b1SMichael Neumann 0x9148, 0x00ff0000, 0x00fc0000, 343f43cf1b1SMichael Neumann 0x3f94, 0x00ff0000, 0x00fc0000, 344f43cf1b1SMichael Neumann 0x914c, 0x00ff0000, 0x00fc0000, 345f43cf1b1SMichael Neumann 0xb4c, 0x00000020, 0x00000020, 346f43cf1b1SMichael Neumann 0xa180, 0xffffffff, 0x00003f3f 347f43cf1b1SMichael Neumann }; 348f43cf1b1SMichael Neumann 349f43cf1b1SMichael Neumann static const u32 rv710_mgcg_init[] = 350f43cf1b1SMichael Neumann { 351f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x13030040, 352f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100, 353f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100, 354f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100, 355f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100, 356f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100, 357f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100, 358f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x8000100, 359f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x3c000100, 360f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100, 361f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000, 362f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 363f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0, 364f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100, 365f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100, 366f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0, 367f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 368f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1, 369f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 370f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000, 371f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0, 372f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 373f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1, 374f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 375f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000, 376f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0, 377f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 378f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1, 379f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 380f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000, 381f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100, 382f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100, 383f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100, 384f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100, 385f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100, 386f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100, 387f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100, 388f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100, 389f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100, 390f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100, 391f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001, 392f43cf1b1SMichael Neumann 0x9174, 0xffffffff, 0x00000003, 393f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x00050001, 394f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x00030002, 395f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00000004, 396f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00070006, 397f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00050001, 398f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00030002, 399f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00000004, 400f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x00070006, 401f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x00000001, 402f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00000001, 403f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00000002, 404f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00040003, 405f43cf1b1SMichael Neumann 0x9150, 0xffffffff, 0x4d940000 406f43cf1b1SMichael Neumann }; 407f43cf1b1SMichael Neumann 408f43cf1b1SMichael Neumann static const u32 rv730_golden_registers[] = 409f43cf1b1SMichael Neumann { 410f43cf1b1SMichael Neumann 0x3f90, 0x00ff0000, 0x00f00000, 411f43cf1b1SMichael Neumann 0x9148, 0x00ff0000, 0x00f00000, 412f43cf1b1SMichael Neumann 0x3f94, 0x00ff0000, 0x00f00000, 413f43cf1b1SMichael Neumann 0x914c, 0x00ff0000, 0x00f00000, 414f43cf1b1SMichael Neumann 0x900c, 0xffffffff, 0x003b033f, 415f43cf1b1SMichael Neumann 0xb4c, 0x00000020, 0x00000020, 416f43cf1b1SMichael Neumann 0xa180, 0xffffffff, 0x00003f3f 417f43cf1b1SMichael Neumann }; 418f43cf1b1SMichael Neumann 419f43cf1b1SMichael Neumann static const u32 rv730_mgcg_init[] = 420f43cf1b1SMichael Neumann { 421f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x130300f9, 422f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100, 423f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100, 424f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100, 425f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100, 426f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100, 427f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100, 428f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x8000100, 429f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x3c000100, 430f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100, 431f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000, 432f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 433f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10001, 434f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 435f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0, 436f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100, 437f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100, 438f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0, 439f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 440f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1, 441f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 442f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x2, 443f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 444f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x3, 445f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 446f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x4, 447f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 448f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x5, 449f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 450f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x6, 451f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 452f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x7, 453f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 454f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000, 455f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0, 456f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 457f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1, 458f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 459f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x2, 460f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 461f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x3, 462f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 463f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x4, 464f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 465f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x5, 466f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 467f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x6, 468f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 469f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x7, 470f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 471f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000, 472f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0, 473f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 474f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1, 475f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 476f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x2, 477f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 478f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x3, 479f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 480f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x4, 481f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 482f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x5, 483f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 484f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x6, 485f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 486f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x7, 487f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 488f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000, 489f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100, 490f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100, 491f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100, 492f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100, 493f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100, 494f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100, 495f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100, 496f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100, 497f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100, 498f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100, 499f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001, 500f43cf1b1SMichael Neumann 0x916c, 0xffffffff, 0x00040003, 501f43cf1b1SMichael Neumann 0x9170, 0xffffffff, 0x00000005, 502f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x00050001, 503f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x00030002, 504f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00000004, 505f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00070006, 506f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00050001, 507f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00030002, 508f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00000004, 509f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x00070006, 510f43cf1b1SMichael Neumann 0x91b0, 0xffffffff, 0x00050001, 511f43cf1b1SMichael Neumann 0x91b4, 0xffffffff, 0x00030002, 512f43cf1b1SMichael Neumann 0x91c4, 0xffffffff, 0x00000004, 513f43cf1b1SMichael Neumann 0x91c8, 0xffffffff, 0x00070006, 514f43cf1b1SMichael Neumann 0x91cc, 0xffffffff, 0x00050001, 515f43cf1b1SMichael Neumann 0x91d0, 0xffffffff, 0x00030002, 516f43cf1b1SMichael Neumann 0x91e0, 0xffffffff, 0x00000004, 517f43cf1b1SMichael Neumann 0x91e4, 0xffffffff, 0x00070006, 518f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x00000001, 519f43cf1b1SMichael Neumann 0x91ec, 0xffffffff, 0x00050001, 520f43cf1b1SMichael Neumann 0x91f0, 0xffffffff, 0x00030002, 521f43cf1b1SMichael Neumann 0x9200, 0xffffffff, 0x00000004, 522f43cf1b1SMichael Neumann 0x9204, 0xffffffff, 0x00070006, 523f43cf1b1SMichael Neumann 0x9208, 0xffffffff, 0x00050001, 524f43cf1b1SMichael Neumann 0x920c, 0xffffffff, 0x00030002, 525f43cf1b1SMichael Neumann 0x921c, 0xffffffff, 0x00000004, 526f43cf1b1SMichael Neumann 0x9220, 0xffffffff, 0x00070006, 527f43cf1b1SMichael Neumann 0x9224, 0xffffffff, 0x00050001, 528f43cf1b1SMichael Neumann 0x9228, 0xffffffff, 0x00030002, 529f43cf1b1SMichael Neumann 0x9238, 0xffffffff, 0x00000004, 530f43cf1b1SMichael Neumann 0x923c, 0xffffffff, 0x00070006, 531f43cf1b1SMichael Neumann 0x9240, 0xffffffff, 0x00050001, 532f43cf1b1SMichael Neumann 0x9244, 0xffffffff, 0x00030002, 533f43cf1b1SMichael Neumann 0x9254, 0xffffffff, 0x00000004, 534f43cf1b1SMichael Neumann 0x9258, 0xffffffff, 0x00070006, 535f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00000001, 536f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00000002, 537f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00040003, 538f43cf1b1SMichael Neumann 0x92a4, 0xffffffff, 0x00000005 539f43cf1b1SMichael Neumann }; 540f43cf1b1SMichael Neumann 541f43cf1b1SMichael Neumann static const u32 rv740_golden_registers[] = 542f43cf1b1SMichael Neumann { 543f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x00000082, 544f43cf1b1SMichael Neumann 0x28a50, 0xfffffffc, 0x00000004, 545f43cf1b1SMichael Neumann 0x2650, 0x00040000, 0, 546f43cf1b1SMichael Neumann 0x20bc, 0x00040000, 0, 547f43cf1b1SMichael Neumann 0x733c, 0xffffffff, 0x00000002, 548f43cf1b1SMichael Neumann 0x7300, 0xffffffff, 0x001000f0, 549f43cf1b1SMichael Neumann 0x3f90, 0x00ff0000, 0, 550f43cf1b1SMichael Neumann 0x9148, 0x00ff0000, 0, 551f43cf1b1SMichael Neumann 0x3f94, 0x00ff0000, 0, 552f43cf1b1SMichael Neumann 0x914c, 0x00ff0000, 0, 553f43cf1b1SMichael Neumann 0x240c, 0xffffffff, 0x00000380, 554f43cf1b1SMichael Neumann 0x8a14, 0x00000007, 0x00000007, 555f43cf1b1SMichael Neumann 0x8b24, 0xffffffff, 0x00ff0fff, 556f43cf1b1SMichael Neumann 0x28a4c, 0xffffffff, 0x00004000, 557f43cf1b1SMichael Neumann 0xa180, 0xffffffff, 0x00003f3f, 558f43cf1b1SMichael Neumann 0x8d00, 0xffffffff, 0x0e0e003a, 559f43cf1b1SMichael Neumann 0x8d04, 0xffffffff, 0x013a0e2a, 560f43cf1b1SMichael Neumann 0x8c00, 0xffffffff, 0xe400000f, 561f43cf1b1SMichael Neumann 0x8db0, 0xffffffff, 0x98989898, 562f43cf1b1SMichael Neumann 0x8db4, 0xffffffff, 0x98989898, 563f43cf1b1SMichael Neumann 0x8db8, 0xffffffff, 0x98989898, 564f43cf1b1SMichael Neumann 0x8dbc, 0xffffffff, 0x98989898, 565f43cf1b1SMichael Neumann 0x8dc0, 0xffffffff, 0x98989898, 566f43cf1b1SMichael Neumann 0x8dc4, 0xffffffff, 0x98989898, 567f43cf1b1SMichael Neumann 0x8dc8, 0xffffffff, 0x98989898, 568f43cf1b1SMichael Neumann 0x8dcc, 0xffffffff, 0x98989898, 569f43cf1b1SMichael Neumann 0x9058, 0xffffffff, 0x0fffc40f, 570f43cf1b1SMichael Neumann 0x900c, 0xffffffff, 0x003b033f, 571f43cf1b1SMichael Neumann 0x28350, 0xffffffff, 0, 572f43cf1b1SMichael Neumann 0x8cf0, 0x1fffffff, 0x08e00420, 573f43cf1b1SMichael Neumann 0x9508, 0xffffffff, 0x00000002, 574f43cf1b1SMichael Neumann 0x88c4, 0xffffffff, 0x000000c2, 575f43cf1b1SMichael Neumann 0x9698, 0x18000000, 0x18000000 576f43cf1b1SMichael Neumann }; 577f43cf1b1SMichael Neumann 578f43cf1b1SMichael Neumann static const u32 rv740_mgcg_init[] = 579f43cf1b1SMichael Neumann { 580f43cf1b1SMichael Neumann 0x8bcc, 0xffffffff, 0x13030100, 581f43cf1b1SMichael Neumann 0x5448, 0xffffffff, 0x100, 582f43cf1b1SMichael Neumann 0x55e4, 0xffffffff, 0x100, 583f43cf1b1SMichael Neumann 0x160c, 0xffffffff, 0x100, 584f43cf1b1SMichael Neumann 0x5644, 0xffffffff, 0x100, 585f43cf1b1SMichael Neumann 0xc164, 0xffffffff, 0x100, 586f43cf1b1SMichael Neumann 0x8a18, 0xffffffff, 0x100, 587f43cf1b1SMichael Neumann 0x897c, 0xffffffff, 0x100, 588f43cf1b1SMichael Neumann 0x8b28, 0xffffffff, 0x100, 589f43cf1b1SMichael Neumann 0x9144, 0xffffffff, 0x100, 590f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10000, 591f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 592f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10001, 593f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 594f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10002, 595f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 596f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x10003, 597f43cf1b1SMichael Neumann 0x9a50, 0xffffffff, 0x100, 598f43cf1b1SMichael Neumann 0x9a1c, 0xffffffff, 0x0, 599f43cf1b1SMichael Neumann 0x9870, 0xffffffff, 0x100, 600f43cf1b1SMichael Neumann 0x8d58, 0xffffffff, 0x100, 601f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x0, 602f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 603f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x1, 604f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 605f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x2, 606f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 607f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x3, 608f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 609f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x4, 610f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 611f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x5, 612f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 613f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x6, 614f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 615f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x7, 616f43cf1b1SMichael Neumann 0x9510, 0xffffffff, 0x100, 617f43cf1b1SMichael Neumann 0x9500, 0xffffffff, 0x8000, 618f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x0, 619f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 620f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x1, 621f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 622f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x2, 623f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 624f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x3, 625f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 626f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x4, 627f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 628f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x5, 629f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 630f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x6, 631f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 632f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x7, 633f43cf1b1SMichael Neumann 0x949c, 0xffffffff, 0x100, 634f43cf1b1SMichael Neumann 0x9490, 0xffffffff, 0x8000, 635f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x0, 636f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 637f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x1, 638f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 639f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x2, 640f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 641f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x3, 642f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 643f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x4, 644f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 645f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x5, 646f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 647f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x6, 648f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 649f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x7, 650f43cf1b1SMichael Neumann 0x9654, 0xffffffff, 0x100, 651f43cf1b1SMichael Neumann 0x9604, 0xffffffff, 0x80000000, 652f43cf1b1SMichael Neumann 0x9030, 0xffffffff, 0x100, 653f43cf1b1SMichael Neumann 0x9034, 0xffffffff, 0x100, 654f43cf1b1SMichael Neumann 0x9038, 0xffffffff, 0x100, 655f43cf1b1SMichael Neumann 0x903c, 0xffffffff, 0x100, 656f43cf1b1SMichael Neumann 0x9040, 0xffffffff, 0x100, 657f43cf1b1SMichael Neumann 0xa200, 0xffffffff, 0x100, 658f43cf1b1SMichael Neumann 0xa204, 0xffffffff, 0x100, 659f43cf1b1SMichael Neumann 0xa208, 0xffffffff, 0x100, 660f43cf1b1SMichael Neumann 0xa20c, 0xffffffff, 0x100, 661f43cf1b1SMichael Neumann 0x971c, 0xffffffff, 0x100, 662f43cf1b1SMichael Neumann 0x915c, 0xffffffff, 0x00020001, 663f43cf1b1SMichael Neumann 0x9160, 0xffffffff, 0x00040003, 664f43cf1b1SMichael Neumann 0x916c, 0xffffffff, 0x00060005, 665f43cf1b1SMichael Neumann 0x9170, 0xffffffff, 0x00080007, 666f43cf1b1SMichael Neumann 0x9174, 0xffffffff, 0x000a0009, 667f43cf1b1SMichael Neumann 0x9178, 0xffffffff, 0x000c000b, 668f43cf1b1SMichael Neumann 0x917c, 0xffffffff, 0x000e000d, 669f43cf1b1SMichael Neumann 0x9180, 0xffffffff, 0x0010000f, 670f43cf1b1SMichael Neumann 0x918c, 0xffffffff, 0x00120011, 671f43cf1b1SMichael Neumann 0x9190, 0xffffffff, 0x00140013, 672f43cf1b1SMichael Neumann 0x9194, 0xffffffff, 0x00020001, 673f43cf1b1SMichael Neumann 0x9198, 0xffffffff, 0x00040003, 674f43cf1b1SMichael Neumann 0x919c, 0xffffffff, 0x00060005, 675f43cf1b1SMichael Neumann 0x91a8, 0xffffffff, 0x00080007, 676f43cf1b1SMichael Neumann 0x91ac, 0xffffffff, 0x000a0009, 677f43cf1b1SMichael Neumann 0x91b0, 0xffffffff, 0x000c000b, 678f43cf1b1SMichael Neumann 0x91b4, 0xffffffff, 0x000e000d, 679f43cf1b1SMichael Neumann 0x91b8, 0xffffffff, 0x0010000f, 680f43cf1b1SMichael Neumann 0x91c4, 0xffffffff, 0x00120011, 681f43cf1b1SMichael Neumann 0x91c8, 0xffffffff, 0x00140013, 682f43cf1b1SMichael Neumann 0x91cc, 0xffffffff, 0x00020001, 683f43cf1b1SMichael Neumann 0x91d0, 0xffffffff, 0x00040003, 684f43cf1b1SMichael Neumann 0x91d4, 0xffffffff, 0x00060005, 685f43cf1b1SMichael Neumann 0x91e0, 0xffffffff, 0x00080007, 686f43cf1b1SMichael Neumann 0x91e4, 0xffffffff, 0x000a0009, 687f43cf1b1SMichael Neumann 0x91e8, 0xffffffff, 0x000c000b, 688f43cf1b1SMichael Neumann 0x91ec, 0xffffffff, 0x00020001, 689f43cf1b1SMichael Neumann 0x91f0, 0xffffffff, 0x00040003, 690f43cf1b1SMichael Neumann 0x91f4, 0xffffffff, 0x00060005, 691f43cf1b1SMichael Neumann 0x9200, 0xffffffff, 0x00080007, 692f43cf1b1SMichael Neumann 0x9204, 0xffffffff, 0x000a0009, 693f43cf1b1SMichael Neumann 0x9208, 0xffffffff, 0x000c000b, 694f43cf1b1SMichael Neumann 0x920c, 0xffffffff, 0x000e000d, 695f43cf1b1SMichael Neumann 0x9210, 0xffffffff, 0x0010000f, 696f43cf1b1SMichael Neumann 0x921c, 0xffffffff, 0x00120011, 697f43cf1b1SMichael Neumann 0x9220, 0xffffffff, 0x00140013, 698f43cf1b1SMichael Neumann 0x9224, 0xffffffff, 0x00020001, 699f43cf1b1SMichael Neumann 0x9228, 0xffffffff, 0x00040003, 700f43cf1b1SMichael Neumann 0x922c, 0xffffffff, 0x00060005, 701f43cf1b1SMichael Neumann 0x9238, 0xffffffff, 0x00080007, 702f43cf1b1SMichael Neumann 0x923c, 0xffffffff, 0x000a0009, 703f43cf1b1SMichael Neumann 0x9240, 0xffffffff, 0x000c000b, 704f43cf1b1SMichael Neumann 0x9244, 0xffffffff, 0x000e000d, 705f43cf1b1SMichael Neumann 0x9248, 0xffffffff, 0x0010000f, 706f43cf1b1SMichael Neumann 0x9254, 0xffffffff, 0x00120011, 707f43cf1b1SMichael Neumann 0x9258, 0xffffffff, 0x00140013, 708f43cf1b1SMichael Neumann 0x9294, 0xffffffff, 0x00020001, 709f43cf1b1SMichael Neumann 0x929c, 0xffffffff, 0x00040003, 710f43cf1b1SMichael Neumann 0x92a0, 0xffffffff, 0x00060005, 711f43cf1b1SMichael Neumann 0x92a4, 0xffffffff, 0x00080007 712f43cf1b1SMichael Neumann }; 713f43cf1b1SMichael Neumann 714f43cf1b1SMichael Neumann static void rv770_init_golden_registers(struct radeon_device *rdev) 715f43cf1b1SMichael Neumann { 716f43cf1b1SMichael Neumann switch (rdev->family) { 717f43cf1b1SMichael Neumann case CHIP_RV770: 718f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 719f43cf1b1SMichael Neumann r7xx_golden_registers, 720f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_registers)); 721f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 722f43cf1b1SMichael Neumann r7xx_golden_dyn_gpr_registers, 723f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 724f43cf1b1SMichael Neumann if (rdev->ddev->pci_device == 0x994e) 725f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 726f43cf1b1SMichael Neumann rv770ce_golden_registers, 727f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(rv770ce_golden_registers)); 728f43cf1b1SMichael Neumann else 729f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 730f43cf1b1SMichael Neumann rv770_golden_registers, 731f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(rv770_golden_registers)); 732f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 733f43cf1b1SMichael Neumann rv770_mgcg_init, 734f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(rv770_mgcg_init)); 735f43cf1b1SMichael Neumann break; 736f43cf1b1SMichael Neumann case CHIP_RV730: 737f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 738f43cf1b1SMichael Neumann r7xx_golden_registers, 739f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_registers)); 740f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 741f43cf1b1SMichael Neumann r7xx_golden_dyn_gpr_registers, 742f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 743f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 744f43cf1b1SMichael Neumann rv730_golden_registers, 745*57e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv730_golden_registers)); 746f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 747f43cf1b1SMichael Neumann rv730_mgcg_init, 748*57e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv730_mgcg_init)); 749f43cf1b1SMichael Neumann break; 750f43cf1b1SMichael Neumann case CHIP_RV710: 751f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 752f43cf1b1SMichael Neumann r7xx_golden_registers, 753f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_registers)); 754f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 755f43cf1b1SMichael Neumann r7xx_golden_dyn_gpr_registers, 756f43cf1b1SMichael Neumann (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 757f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 758f43cf1b1SMichael Neumann rv710_golden_registers, 759*57e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv710_golden_registers)); 760f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 761f43cf1b1SMichael Neumann rv710_mgcg_init, 762*57e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv710_mgcg_init)); 763f43cf1b1SMichael Neumann break; 764f43cf1b1SMichael Neumann case CHIP_RV740: 765f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 766f43cf1b1SMichael Neumann rv740_golden_registers, 767*57e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv740_golden_registers)); 768f43cf1b1SMichael Neumann radeon_program_register_sequence(rdev, 769f43cf1b1SMichael Neumann rv740_mgcg_init, 770*57e252bfSMichael Neumann (const u32)ARRAY_SIZE(rv740_mgcg_init)); 771f43cf1b1SMichael Neumann break; 772f43cf1b1SMichael Neumann default: 773f43cf1b1SMichael Neumann break; 774f43cf1b1SMichael Neumann } 775f43cf1b1SMichael Neumann } 776f43cf1b1SMichael Neumann 777b403bed8SMichael Neumann #define PCIE_BUS_CLK 10000 778b403bed8SMichael Neumann #define TCLK (PCIE_BUS_CLK / 10) 779b403bed8SMichael Neumann 780b403bed8SMichael Neumann /** 781b403bed8SMichael Neumann * rv770_get_xclk - get the xclk 782b403bed8SMichael Neumann * 783b403bed8SMichael Neumann * @rdev: radeon_device pointer 784b403bed8SMichael Neumann * 785b403bed8SMichael Neumann * Returns the reference clock used by the gfx engine 786b403bed8SMichael Neumann * (r7xx-cayman). 787b403bed8SMichael Neumann */ 788b403bed8SMichael Neumann u32 rv770_get_xclk(struct radeon_device *rdev) 789b403bed8SMichael Neumann { 790b403bed8SMichael Neumann u32 reference_clock = rdev->clock.spll.reference_freq; 791b403bed8SMichael Neumann u32 tmp = RREG32(CG_CLKPIN_CNTL); 792b403bed8SMichael Neumann 793b403bed8SMichael Neumann if (tmp & MUX_TCLK_TO_XCLK) 794b403bed8SMichael Neumann return TCLK; 795b403bed8SMichael Neumann 796b403bed8SMichael Neumann if (tmp & XTALIN_DIVIDE) 797b403bed8SMichael Neumann return reference_clock / 4; 798b403bed8SMichael Neumann 799b403bed8SMichael Neumann return reference_clock; 800b403bed8SMichael Neumann } 801b403bed8SMichael Neumann 802f43cf1b1SMichael Neumann int rv770_uvd_resume(struct radeon_device *rdev) 803f43cf1b1SMichael Neumann { 804f43cf1b1SMichael Neumann uint64_t addr; 805f43cf1b1SMichael Neumann uint32_t chip_id, size; 806f43cf1b1SMichael Neumann int r; 807f43cf1b1SMichael Neumann 808f43cf1b1SMichael Neumann r = radeon_uvd_resume(rdev); 809f43cf1b1SMichael Neumann if (r) 810f43cf1b1SMichael Neumann return r; 811f43cf1b1SMichael Neumann 812f43cf1b1SMichael Neumann /* programm the VCPU memory controller bits 0-27 */ 813f43cf1b1SMichael Neumann addr = rdev->uvd.gpu_addr >> 3; 814f43cf1b1SMichael Neumann size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 4) >> 3; 815f43cf1b1SMichael Neumann WREG32(UVD_VCPU_CACHE_OFFSET0, addr); 816f43cf1b1SMichael Neumann WREG32(UVD_VCPU_CACHE_SIZE0, size); 817f43cf1b1SMichael Neumann 818f43cf1b1SMichael Neumann addr += size; 819f43cf1b1SMichael Neumann size = RADEON_UVD_STACK_SIZE >> 3; 820f43cf1b1SMichael Neumann WREG32(UVD_VCPU_CACHE_OFFSET1, addr); 821f43cf1b1SMichael Neumann WREG32(UVD_VCPU_CACHE_SIZE1, size); 822f43cf1b1SMichael Neumann 823f43cf1b1SMichael Neumann addr += size; 824f43cf1b1SMichael Neumann size = RADEON_UVD_HEAP_SIZE >> 3; 825f43cf1b1SMichael Neumann WREG32(UVD_VCPU_CACHE_OFFSET2, addr); 826f43cf1b1SMichael Neumann WREG32(UVD_VCPU_CACHE_SIZE2, size); 827f43cf1b1SMichael Neumann 828f43cf1b1SMichael Neumann /* bits 28-31 */ 829f43cf1b1SMichael Neumann addr = (rdev->uvd.gpu_addr >> 28) & 0xF; 830f43cf1b1SMichael Neumann WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 831f43cf1b1SMichael Neumann 832f43cf1b1SMichael Neumann /* bits 32-39 */ 833f43cf1b1SMichael Neumann addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; 834f43cf1b1SMichael Neumann WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 835f43cf1b1SMichael Neumann 836f43cf1b1SMichael Neumann /* tell firmware which hardware it is running on */ 837f43cf1b1SMichael Neumann switch (rdev->family) { 838f43cf1b1SMichael Neumann default: 839f43cf1b1SMichael Neumann return -EINVAL; 840f43cf1b1SMichael Neumann case CHIP_RV710: 841f43cf1b1SMichael Neumann chip_id = 0x01000005; 842f43cf1b1SMichael Neumann break; 843f43cf1b1SMichael Neumann case CHIP_RV730: 844f43cf1b1SMichael Neumann chip_id = 0x01000006; 845f43cf1b1SMichael Neumann break; 846f43cf1b1SMichael Neumann case CHIP_RV740: 847f43cf1b1SMichael Neumann chip_id = 0x01000007; 848f43cf1b1SMichael Neumann break; 849f43cf1b1SMichael Neumann case CHIP_CYPRESS: 850f43cf1b1SMichael Neumann case CHIP_HEMLOCK: 851f43cf1b1SMichael Neumann chip_id = 0x01000008; 852f43cf1b1SMichael Neumann break; 853f43cf1b1SMichael Neumann case CHIP_JUNIPER: 854f43cf1b1SMichael Neumann chip_id = 0x01000009; 855f43cf1b1SMichael Neumann break; 856f43cf1b1SMichael Neumann case CHIP_REDWOOD: 857f43cf1b1SMichael Neumann chip_id = 0x0100000a; 858f43cf1b1SMichael Neumann break; 859f43cf1b1SMichael Neumann case CHIP_CEDAR: 860f43cf1b1SMichael Neumann chip_id = 0x0100000b; 861f43cf1b1SMichael Neumann break; 862f43cf1b1SMichael Neumann case CHIP_SUMO: 863f43cf1b1SMichael Neumann case CHIP_SUMO2: 864f43cf1b1SMichael Neumann chip_id = 0x0100000c; 865f43cf1b1SMichael Neumann break; 866f43cf1b1SMichael Neumann case CHIP_PALM: 867f43cf1b1SMichael Neumann chip_id = 0x0100000e; 868f43cf1b1SMichael Neumann break; 869f43cf1b1SMichael Neumann case CHIP_CAYMAN: 870f43cf1b1SMichael Neumann chip_id = 0x0100000f; 871f43cf1b1SMichael Neumann break; 872f43cf1b1SMichael Neumann case CHIP_BARTS: 873f43cf1b1SMichael Neumann chip_id = 0x01000010; 874f43cf1b1SMichael Neumann break; 875f43cf1b1SMichael Neumann case CHIP_TURKS: 876f43cf1b1SMichael Neumann chip_id = 0x01000011; 877f43cf1b1SMichael Neumann break; 878f43cf1b1SMichael Neumann case CHIP_CAICOS: 879f43cf1b1SMichael Neumann chip_id = 0x01000012; 880f43cf1b1SMichael Neumann break; 881f43cf1b1SMichael Neumann case CHIP_TAHITI: 882f43cf1b1SMichael Neumann chip_id = 0x01000014; 883f43cf1b1SMichael Neumann break; 884f43cf1b1SMichael Neumann case CHIP_VERDE: 885f43cf1b1SMichael Neumann chip_id = 0x01000015; 886f43cf1b1SMichael Neumann break; 887f43cf1b1SMichael Neumann case CHIP_PITCAIRN: 888f43cf1b1SMichael Neumann chip_id = 0x01000016; 889f43cf1b1SMichael Neumann break; 890f43cf1b1SMichael Neumann case CHIP_ARUBA: 891f43cf1b1SMichael Neumann chip_id = 0x01000017; 892f43cf1b1SMichael Neumann break; 893f43cf1b1SMichael Neumann } 894f43cf1b1SMichael Neumann WREG32(UVD_VCPU_CHIP_ID, chip_id); 895f43cf1b1SMichael Neumann 896f43cf1b1SMichael Neumann return 0; 897f43cf1b1SMichael Neumann } 898f43cf1b1SMichael Neumann 899926deccbSFrançois Tigeot u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 900926deccbSFrançois Tigeot { 901926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 902926deccbSFrançois Tigeot u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 903926deccbSFrançois Tigeot int i; 904926deccbSFrançois Tigeot 905926deccbSFrançois Tigeot /* Lock the graphics update lock */ 906926deccbSFrançois Tigeot tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 907926deccbSFrançois Tigeot WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 908926deccbSFrançois Tigeot 909926deccbSFrançois Tigeot /* update the scanout addresses */ 910926deccbSFrançois Tigeot if (radeon_crtc->crtc_id) { 911926deccbSFrançois Tigeot WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 912926deccbSFrançois Tigeot WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 913926deccbSFrançois Tigeot } else { 914926deccbSFrançois Tigeot WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 915926deccbSFrançois Tigeot WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 916926deccbSFrançois Tigeot } 917926deccbSFrançois Tigeot WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 918926deccbSFrançois Tigeot (u32)crtc_base); 919926deccbSFrançois Tigeot WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 920926deccbSFrançois Tigeot (u32)crtc_base); 921926deccbSFrançois Tigeot 922926deccbSFrançois Tigeot /* Wait for update_pending to go high. */ 923926deccbSFrançois Tigeot for (i = 0; i < rdev->usec_timeout; i++) { 924926deccbSFrançois Tigeot if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 925926deccbSFrançois Tigeot break; 926926deccbSFrançois Tigeot DRM_UDELAY(1); 927926deccbSFrançois Tigeot } 928926deccbSFrançois Tigeot DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 929926deccbSFrançois Tigeot 930926deccbSFrançois Tigeot /* Unlock the lock, so double-buffering can take place inside vblank */ 931926deccbSFrançois Tigeot tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 932926deccbSFrançois Tigeot WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 933926deccbSFrançois Tigeot 934926deccbSFrançois Tigeot /* Return current update_pending status: */ 935926deccbSFrançois Tigeot return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 936926deccbSFrançois Tigeot } 937926deccbSFrançois Tigeot 938926deccbSFrançois Tigeot /* get temperature in millidegrees */ 939926deccbSFrançois Tigeot int rv770_get_temp(struct radeon_device *rdev) 940926deccbSFrançois Tigeot { 941926deccbSFrançois Tigeot u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 942926deccbSFrançois Tigeot ASIC_T_SHIFT; 943926deccbSFrançois Tigeot int actual_temp; 944926deccbSFrançois Tigeot 945926deccbSFrançois Tigeot if (temp & 0x400) 946926deccbSFrançois Tigeot actual_temp = -256; 947926deccbSFrançois Tigeot else if (temp & 0x200) 948926deccbSFrançois Tigeot actual_temp = 255; 949926deccbSFrançois Tigeot else if (temp & 0x100) { 950926deccbSFrançois Tigeot actual_temp = temp & 0x1ff; 951926deccbSFrançois Tigeot actual_temp |= ~0x1ff; 952926deccbSFrançois Tigeot } else 953926deccbSFrançois Tigeot actual_temp = temp & 0xff; 954926deccbSFrançois Tigeot 955926deccbSFrançois Tigeot return (actual_temp * 1000) / 2; 956926deccbSFrançois Tigeot } 957926deccbSFrançois Tigeot 958926deccbSFrançois Tigeot void rv770_pm_misc(struct radeon_device *rdev) 959926deccbSFrançois Tigeot { 960926deccbSFrançois Tigeot int req_ps_idx = rdev->pm.requested_power_state_index; 961926deccbSFrançois Tigeot int req_cm_idx = rdev->pm.requested_clock_mode_index; 962926deccbSFrançois Tigeot struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 963926deccbSFrançois Tigeot struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 964926deccbSFrançois Tigeot 965926deccbSFrançois Tigeot if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 966926deccbSFrançois Tigeot /* 0xff01 is a flag rather then an actual voltage */ 967926deccbSFrançois Tigeot if (voltage->voltage == 0xff01) 968926deccbSFrançois Tigeot return; 969926deccbSFrançois Tigeot if (voltage->voltage != rdev->pm.current_vddc) { 970926deccbSFrançois Tigeot radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 971926deccbSFrançois Tigeot rdev->pm.current_vddc = voltage->voltage; 972926deccbSFrançois Tigeot DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 973926deccbSFrançois Tigeot } 974926deccbSFrançois Tigeot } 975926deccbSFrançois Tigeot } 976926deccbSFrançois Tigeot 977926deccbSFrançois Tigeot /* 978926deccbSFrançois Tigeot * GART 979926deccbSFrançois Tigeot */ 980926deccbSFrançois Tigeot static int rv770_pcie_gart_enable(struct radeon_device *rdev) 981926deccbSFrançois Tigeot { 982926deccbSFrançois Tigeot u32 tmp; 983926deccbSFrançois Tigeot int r, i; 984926deccbSFrançois Tigeot 985926deccbSFrançois Tigeot if (rdev->gart.robj == NULL) { 986926deccbSFrançois Tigeot dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 987926deccbSFrançois Tigeot return -EINVAL; 988926deccbSFrançois Tigeot } 989926deccbSFrançois Tigeot r = radeon_gart_table_vram_pin(rdev); 990926deccbSFrançois Tigeot if (r) 991926deccbSFrançois Tigeot return r; 992926deccbSFrançois Tigeot radeon_gart_restore(rdev); 993926deccbSFrançois Tigeot /* Setup L2 cache */ 994926deccbSFrançois Tigeot WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 995926deccbSFrançois Tigeot ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 996926deccbSFrançois Tigeot EFFECTIVE_L2_QUEUE_SIZE(7)); 997926deccbSFrançois Tigeot WREG32(VM_L2_CNTL2, 0); 998926deccbSFrançois Tigeot WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 999926deccbSFrançois Tigeot /* Setup TLB control */ 1000926deccbSFrançois Tigeot tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1001926deccbSFrançois Tigeot SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1002926deccbSFrançois Tigeot SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 1003926deccbSFrançois Tigeot EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1004926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1005926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1006926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1007926deccbSFrançois Tigeot if (rdev->family == CHIP_RV740) 1008926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 1009926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1010926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1011926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1012926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1013926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1014926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1015926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1016926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1017926deccbSFrançois Tigeot RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1018926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1019926deccbSFrançois Tigeot (u32)(rdev->dummy_page.addr >> 12)); 1020926deccbSFrançois Tigeot for (i = 1; i < 7; i++) 1021926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1022926deccbSFrançois Tigeot 1023926deccbSFrançois Tigeot r600_pcie_gart_tlb_flush(rdev); 1024926deccbSFrançois Tigeot DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1025926deccbSFrançois Tigeot (unsigned)(rdev->mc.gtt_size >> 20), 1026926deccbSFrançois Tigeot (unsigned long long)rdev->gart.table_addr); 1027926deccbSFrançois Tigeot rdev->gart.ready = true; 1028926deccbSFrançois Tigeot return 0; 1029926deccbSFrançois Tigeot } 1030926deccbSFrançois Tigeot 1031926deccbSFrançois Tigeot static void rv770_pcie_gart_disable(struct radeon_device *rdev) 1032926deccbSFrançois Tigeot { 1033926deccbSFrançois Tigeot u32 tmp; 1034926deccbSFrançois Tigeot int i; 1035926deccbSFrançois Tigeot 1036926deccbSFrançois Tigeot /* Disable all tables */ 1037926deccbSFrançois Tigeot for (i = 0; i < 7; i++) 1038926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1039926deccbSFrançois Tigeot 1040926deccbSFrançois Tigeot /* Setup L2 cache */ 1041926deccbSFrançois Tigeot WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1042926deccbSFrançois Tigeot EFFECTIVE_L2_QUEUE_SIZE(7)); 1043926deccbSFrançois Tigeot WREG32(VM_L2_CNTL2, 0); 1044926deccbSFrançois Tigeot WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1045926deccbSFrançois Tigeot /* Setup TLB control */ 1046926deccbSFrançois Tigeot tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1047926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1048926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1049926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1050926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1051926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1052926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1053926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1054926deccbSFrançois Tigeot radeon_gart_table_vram_unpin(rdev); 1055926deccbSFrançois Tigeot } 1056926deccbSFrançois Tigeot 1057926deccbSFrançois Tigeot static void rv770_pcie_gart_fini(struct radeon_device *rdev) 1058926deccbSFrançois Tigeot { 1059926deccbSFrançois Tigeot radeon_gart_fini(rdev); 1060926deccbSFrançois Tigeot rv770_pcie_gart_disable(rdev); 1061926deccbSFrançois Tigeot radeon_gart_table_vram_free(rdev); 1062926deccbSFrançois Tigeot } 1063926deccbSFrançois Tigeot 1064926deccbSFrançois Tigeot 1065926deccbSFrançois Tigeot static void rv770_agp_enable(struct radeon_device *rdev) 1066926deccbSFrançois Tigeot { 1067926deccbSFrançois Tigeot u32 tmp; 1068926deccbSFrançois Tigeot int i; 1069926deccbSFrançois Tigeot 1070926deccbSFrançois Tigeot /* Setup L2 cache */ 1071926deccbSFrançois Tigeot WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1072926deccbSFrançois Tigeot ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1073926deccbSFrançois Tigeot EFFECTIVE_L2_QUEUE_SIZE(7)); 1074926deccbSFrançois Tigeot WREG32(VM_L2_CNTL2, 0); 1075926deccbSFrançois Tigeot WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1076926deccbSFrançois Tigeot /* Setup TLB control */ 1077926deccbSFrançois Tigeot tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1078926deccbSFrançois Tigeot SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1079926deccbSFrançois Tigeot SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 1080926deccbSFrançois Tigeot EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1081926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1082926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1083926deccbSFrançois Tigeot WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1084926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1085926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1086926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1087926deccbSFrançois Tigeot WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1088926deccbSFrançois Tigeot for (i = 0; i < 7; i++) 1089926deccbSFrançois Tigeot WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1090926deccbSFrançois Tigeot } 1091926deccbSFrançois Tigeot 1092926deccbSFrançois Tigeot static void rv770_mc_program(struct radeon_device *rdev) 1093926deccbSFrançois Tigeot { 1094926deccbSFrançois Tigeot struct rv515_mc_save save; 1095926deccbSFrançois Tigeot u32 tmp; 1096926deccbSFrançois Tigeot int i, j; 1097926deccbSFrançois Tigeot 1098926deccbSFrançois Tigeot /* Initialize HDP */ 1099926deccbSFrançois Tigeot for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1100926deccbSFrançois Tigeot WREG32((0x2c14 + j), 0x00000000); 1101926deccbSFrançois Tigeot WREG32((0x2c18 + j), 0x00000000); 1102926deccbSFrançois Tigeot WREG32((0x2c1c + j), 0x00000000); 1103926deccbSFrançois Tigeot WREG32((0x2c20 + j), 0x00000000); 1104926deccbSFrançois Tigeot WREG32((0x2c24 + j), 0x00000000); 1105926deccbSFrançois Tigeot } 1106926deccbSFrançois Tigeot /* r7xx hw bug. Read from HDP_DEBUG1 rather 1107926deccbSFrançois Tigeot * than writing to HDP_REG_COHERENCY_FLUSH_CNTL 1108926deccbSFrançois Tigeot */ 1109926deccbSFrançois Tigeot tmp = RREG32(HDP_DEBUG1); 1110926deccbSFrançois Tigeot 1111926deccbSFrançois Tigeot rv515_mc_stop(rdev, &save); 1112926deccbSFrançois Tigeot if (r600_mc_wait_for_idle(rdev)) { 1113926deccbSFrançois Tigeot dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1114926deccbSFrançois Tigeot } 1115926deccbSFrançois Tigeot /* Lockout access through VGA aperture*/ 1116926deccbSFrançois Tigeot WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1117926deccbSFrançois Tigeot /* Update configuration */ 1118926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) { 1119926deccbSFrançois Tigeot if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1120926deccbSFrançois Tigeot /* VRAM before AGP */ 1121926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1122926deccbSFrançois Tigeot rdev->mc.vram_start >> 12); 1123926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1124926deccbSFrançois Tigeot rdev->mc.gtt_end >> 12); 1125926deccbSFrançois Tigeot } else { 1126926deccbSFrançois Tigeot /* VRAM after AGP */ 1127926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1128926deccbSFrançois Tigeot rdev->mc.gtt_start >> 12); 1129926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1130926deccbSFrançois Tigeot rdev->mc.vram_end >> 12); 1131926deccbSFrançois Tigeot } 1132926deccbSFrançois Tigeot } else { 1133926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1134926deccbSFrançois Tigeot rdev->mc.vram_start >> 12); 1135926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1136926deccbSFrançois Tigeot rdev->mc.vram_end >> 12); 1137926deccbSFrançois Tigeot } 1138926deccbSFrançois Tigeot WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1139926deccbSFrançois Tigeot tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1140926deccbSFrançois Tigeot tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1141926deccbSFrançois Tigeot WREG32(MC_VM_FB_LOCATION, tmp); 1142926deccbSFrançois Tigeot WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1143926deccbSFrançois Tigeot WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1144926deccbSFrançois Tigeot WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1145926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) { 1146926deccbSFrançois Tigeot WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1147926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1148926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1149926deccbSFrançois Tigeot } else { 1150926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BASE, 0); 1151926deccbSFrançois Tigeot WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1152926deccbSFrançois Tigeot WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1153926deccbSFrançois Tigeot } 1154926deccbSFrançois Tigeot if (r600_mc_wait_for_idle(rdev)) { 1155926deccbSFrançois Tigeot dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1156926deccbSFrançois Tigeot } 1157926deccbSFrançois Tigeot rv515_mc_resume(rdev, &save); 1158926deccbSFrançois Tigeot /* we need to own VRAM, so turn off the VGA renderer here 1159926deccbSFrançois Tigeot * to stop it overwriting our objects */ 1160926deccbSFrançois Tigeot rv515_vga_render_disable(rdev); 1161926deccbSFrançois Tigeot } 1162926deccbSFrançois Tigeot 1163926deccbSFrançois Tigeot 1164926deccbSFrançois Tigeot /* 1165926deccbSFrançois Tigeot * CP. 1166926deccbSFrançois Tigeot */ 1167926deccbSFrançois Tigeot void r700_cp_stop(struct radeon_device *rdev) 1168926deccbSFrançois Tigeot { 1169926deccbSFrançois Tigeot radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1170926deccbSFrançois Tigeot WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1171926deccbSFrançois Tigeot WREG32(SCRATCH_UMSK, 0); 1172926deccbSFrançois Tigeot rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1173926deccbSFrançois Tigeot } 1174926deccbSFrançois Tigeot 1175926deccbSFrançois Tigeot static int rv770_cp_load_microcode(struct radeon_device *rdev) 1176926deccbSFrançois Tigeot { 1177926deccbSFrançois Tigeot const __be32 *fw_data; 1178926deccbSFrançois Tigeot int i; 1179926deccbSFrançois Tigeot 1180926deccbSFrançois Tigeot if (!rdev->me_fw || !rdev->pfp_fw) 1181926deccbSFrançois Tigeot return -EINVAL; 1182926deccbSFrançois Tigeot 1183926deccbSFrançois Tigeot r700_cp_stop(rdev); 1184926deccbSFrançois Tigeot WREG32(CP_RB_CNTL, 1185926deccbSFrançois Tigeot #ifdef __BIG_ENDIAN 1186926deccbSFrançois Tigeot BUF_SWAP_32BIT | 1187926deccbSFrançois Tigeot #endif 1188926deccbSFrançois Tigeot RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1189926deccbSFrançois Tigeot 1190926deccbSFrançois Tigeot /* Reset cp */ 1191926deccbSFrançois Tigeot WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1192926deccbSFrançois Tigeot RREG32(GRBM_SOFT_RESET); 1193926deccbSFrançois Tigeot DRM_MDELAY(15); 1194926deccbSFrançois Tigeot WREG32(GRBM_SOFT_RESET, 0); 1195926deccbSFrançois Tigeot 1196926deccbSFrançois Tigeot fw_data = (const __be32 *)rdev->pfp_fw->data; 1197926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_ADDR, 0); 1198926deccbSFrançois Tigeot for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 1199926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1200926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_ADDR, 0); 1201926deccbSFrançois Tigeot 1202926deccbSFrançois Tigeot fw_data = (const __be32 *)rdev->me_fw->data; 1203926deccbSFrançois Tigeot WREG32(CP_ME_RAM_WADDR, 0); 1204926deccbSFrançois Tigeot for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 1205926deccbSFrançois Tigeot WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1206926deccbSFrançois Tigeot 1207926deccbSFrançois Tigeot WREG32(CP_PFP_UCODE_ADDR, 0); 1208926deccbSFrançois Tigeot WREG32(CP_ME_RAM_WADDR, 0); 1209926deccbSFrançois Tigeot WREG32(CP_ME_RAM_RADDR, 0); 1210926deccbSFrançois Tigeot return 0; 1211926deccbSFrançois Tigeot } 1212926deccbSFrançois Tigeot 1213926deccbSFrançois Tigeot void r700_cp_fini(struct radeon_device *rdev) 1214926deccbSFrançois Tigeot { 1215926deccbSFrançois Tigeot struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1216926deccbSFrançois Tigeot r700_cp_stop(rdev); 1217926deccbSFrançois Tigeot radeon_ring_fini(rdev, ring); 1218926deccbSFrançois Tigeot radeon_scratch_free(rdev, ring->rptr_save_reg); 1219926deccbSFrançois Tigeot } 1220926deccbSFrançois Tigeot 1221926deccbSFrançois Tigeot /* 1222926deccbSFrançois Tigeot * Core functions 1223926deccbSFrançois Tigeot */ 1224926deccbSFrançois Tigeot static void rv770_gpu_init(struct radeon_device *rdev) 1225926deccbSFrançois Tigeot { 1226926deccbSFrançois Tigeot int i, j, num_qd_pipes; 1227926deccbSFrançois Tigeot u32 ta_aux_cntl; 1228926deccbSFrançois Tigeot u32 sx_debug_1; 1229926deccbSFrançois Tigeot u32 smx_dc_ctl0; 1230926deccbSFrançois Tigeot u32 db_debug3; 1231926deccbSFrançois Tigeot u32 num_gs_verts_per_thread; 1232926deccbSFrançois Tigeot u32 vgt_gs_per_es; 1233926deccbSFrançois Tigeot u32 gs_prim_buffer_depth = 0; 1234926deccbSFrançois Tigeot u32 sq_ms_fifo_sizes; 1235926deccbSFrançois Tigeot u32 sq_config; 1236926deccbSFrançois Tigeot u32 sq_thread_resource_mgmt; 1237926deccbSFrançois Tigeot u32 hdp_host_path_cntl; 1238926deccbSFrançois Tigeot u32 sq_dyn_gpr_size_simd_ab_0; 1239926deccbSFrançois Tigeot u32 gb_tiling_config = 0; 1240926deccbSFrançois Tigeot u32 cc_rb_backend_disable = 0; 1241926deccbSFrançois Tigeot u32 cc_gc_shader_pipe_config = 0; 1242926deccbSFrançois Tigeot u32 mc_arb_ramcfg; 1243926deccbSFrançois Tigeot u32 db_debug4, tmp; 1244926deccbSFrançois Tigeot u32 inactive_pipes, shader_pipe_config; 1245926deccbSFrançois Tigeot u32 disabled_rb_mask; 1246926deccbSFrançois Tigeot unsigned active_number; 1247926deccbSFrançois Tigeot 1248926deccbSFrançois Tigeot /* setup chip specs */ 1249926deccbSFrançois Tigeot rdev->config.rv770.tiling_group_size = 256; 1250926deccbSFrançois Tigeot switch (rdev->family) { 1251926deccbSFrançois Tigeot case CHIP_RV770: 1252926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 4; 1253926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 8; 1254926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 10; 1255926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 4; 1256926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 256; 1257926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 248; 1258926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 512; 1259926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 8; 1260926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 16 * 2; 1261926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 128; 1262926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 16; 1263926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 112; 1264926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 2; 1265926deccbSFrançois Tigeot 1266926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7; 1267926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0xF9; 1268926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1269926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1270926deccbSFrançois Tigeot break; 1271926deccbSFrançois Tigeot case CHIP_RV730: 1272926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 2; 1273926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 4; 1274926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 8; 1275926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 2; 1276926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 128; 1277926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 248; 1278926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 256; 1279926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 8; 1280926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 16 * 2; 1281926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 256; 1282926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 32; 1283926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 224; 1284926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 2; 1285926deccbSFrançois Tigeot 1286926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7; 1287926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0xf9; 1288926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1289926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1290926deccbSFrançois Tigeot if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1291926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size -= 16; 1292926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size += 16; 1293926deccbSFrançois Tigeot } 1294926deccbSFrançois Tigeot break; 1295926deccbSFrançois Tigeot case CHIP_RV710: 1296926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 2; 1297926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 2; 1298926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 2; 1299926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 1; 1300926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 256; 1301926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 192; 1302926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 256; 1303926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 4; 1304926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 8 * 2; 1305926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 128; 1306926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 16; 1307926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 112; 1308926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 1; 1309926deccbSFrançois Tigeot 1310926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7; 1311926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0x40; 1312926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1313926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1314926deccbSFrançois Tigeot break; 1315926deccbSFrançois Tigeot case CHIP_RV740: 1316926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = 4; 1317926deccbSFrançois Tigeot rdev->config.rv770.max_tile_pipes = 4; 1318926deccbSFrançois Tigeot rdev->config.rv770.max_simds = 8; 1319926deccbSFrançois Tigeot rdev->config.rv770.max_backends = 4; 1320926deccbSFrançois Tigeot rdev->config.rv770.max_gprs = 256; 1321926deccbSFrançois Tigeot rdev->config.rv770.max_threads = 248; 1322926deccbSFrançois Tigeot rdev->config.rv770.max_stack_entries = 512; 1323926deccbSFrançois Tigeot rdev->config.rv770.max_hw_contexts = 8; 1324926deccbSFrançois Tigeot rdev->config.rv770.max_gs_threads = 16 * 2; 1325926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_size = 256; 1326926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size = 32; 1327926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size = 224; 1328926deccbSFrançois Tigeot rdev->config.rv770.sq_num_cf_insts = 2; 1329926deccbSFrançois Tigeot 1330926deccbSFrançois Tigeot rdev->config.rv770.sx_num_of_sets = 7; 1331926deccbSFrançois Tigeot rdev->config.rv770.sc_prim_fifo_size = 0x100; 1332926deccbSFrançois Tigeot rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1333926deccbSFrançois Tigeot rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1334926deccbSFrançois Tigeot 1335926deccbSFrançois Tigeot if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1336926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_pos_size -= 16; 1337926deccbSFrançois Tigeot rdev->config.rv770.sx_max_export_smx_size += 16; 1338926deccbSFrançois Tigeot } 1339926deccbSFrançois Tigeot break; 1340926deccbSFrançois Tigeot default: 1341926deccbSFrançois Tigeot break; 1342926deccbSFrançois Tigeot } 1343926deccbSFrançois Tigeot 1344926deccbSFrançois Tigeot /* Initialize HDP */ 1345926deccbSFrançois Tigeot j = 0; 1346926deccbSFrançois Tigeot for (i = 0; i < 32; i++) { 1347926deccbSFrançois Tigeot WREG32((0x2c14 + j), 0x00000000); 1348926deccbSFrançois Tigeot WREG32((0x2c18 + j), 0x00000000); 1349926deccbSFrançois Tigeot WREG32((0x2c1c + j), 0x00000000); 1350926deccbSFrançois Tigeot WREG32((0x2c20 + j), 0x00000000); 1351926deccbSFrançois Tigeot WREG32((0x2c24 + j), 0x00000000); 1352926deccbSFrançois Tigeot j += 0x18; 1353926deccbSFrançois Tigeot } 1354926deccbSFrançois Tigeot 1355926deccbSFrançois Tigeot WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1356926deccbSFrançois Tigeot 1357926deccbSFrançois Tigeot /* setup tiling, simd, pipe config */ 1358926deccbSFrançois Tigeot mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1359926deccbSFrançois Tigeot 1360926deccbSFrançois Tigeot shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 1361926deccbSFrançois Tigeot inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 1362926deccbSFrançois Tigeot for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { 1363926deccbSFrançois Tigeot if (!(inactive_pipes & tmp)) { 1364926deccbSFrançois Tigeot active_number++; 1365926deccbSFrançois Tigeot } 1366926deccbSFrançois Tigeot tmp <<= 1; 1367926deccbSFrançois Tigeot } 1368926deccbSFrançois Tigeot if (active_number == 1) { 1369926deccbSFrançois Tigeot WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); 1370926deccbSFrançois Tigeot } else { 1371926deccbSFrançois Tigeot WREG32(SPI_CONFIG_CNTL, 0); 1372926deccbSFrançois Tigeot } 1373926deccbSFrançois Tigeot 1374926deccbSFrançois Tigeot cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1375926deccbSFrançois Tigeot tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); 1376926deccbSFrançois Tigeot if (tmp < rdev->config.rv770.max_backends) { 1377926deccbSFrançois Tigeot rdev->config.rv770.max_backends = tmp; 1378926deccbSFrançois Tigeot } 1379926deccbSFrançois Tigeot 1380926deccbSFrançois Tigeot cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1381926deccbSFrançois Tigeot tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); 1382926deccbSFrançois Tigeot if (tmp < rdev->config.rv770.max_pipes) { 1383926deccbSFrançois Tigeot rdev->config.rv770.max_pipes = tmp; 1384926deccbSFrançois Tigeot } 1385926deccbSFrançois Tigeot tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); 1386926deccbSFrançois Tigeot if (tmp < rdev->config.rv770.max_simds) { 1387926deccbSFrançois Tigeot rdev->config.rv770.max_simds = tmp; 1388926deccbSFrançois Tigeot } 1389926deccbSFrançois Tigeot 1390926deccbSFrançois Tigeot switch (rdev->config.rv770.max_tile_pipes) { 1391926deccbSFrançois Tigeot case 1: 1392926deccbSFrançois Tigeot default: 1393926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(0); 1394926deccbSFrançois Tigeot break; 1395926deccbSFrançois Tigeot case 2: 1396926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(1); 1397926deccbSFrançois Tigeot break; 1398926deccbSFrançois Tigeot case 4: 1399926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(2); 1400926deccbSFrançois Tigeot break; 1401926deccbSFrançois Tigeot case 8: 1402926deccbSFrançois Tigeot gb_tiling_config = PIPE_TILING(3); 1403926deccbSFrançois Tigeot break; 1404926deccbSFrançois Tigeot } 1405926deccbSFrançois Tigeot rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 1406926deccbSFrançois Tigeot 1407926deccbSFrançois Tigeot disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; 1408926deccbSFrançois Tigeot tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1409926deccbSFrançois Tigeot tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, 1410926deccbSFrançois Tigeot R7XX_MAX_BACKENDS, disabled_rb_mask); 1411926deccbSFrançois Tigeot gb_tiling_config |= tmp << 16; 1412926deccbSFrançois Tigeot rdev->config.rv770.backend_map = tmp; 1413926deccbSFrançois Tigeot 1414926deccbSFrançois Tigeot if (rdev->family == CHIP_RV770) 1415926deccbSFrançois Tigeot gb_tiling_config |= BANK_TILING(1); 1416926deccbSFrançois Tigeot else { 1417926deccbSFrançois Tigeot if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1418926deccbSFrançois Tigeot gb_tiling_config |= BANK_TILING(1); 1419926deccbSFrançois Tigeot else 1420926deccbSFrançois Tigeot gb_tiling_config |= BANK_TILING(0); 1421926deccbSFrançois Tigeot } 1422926deccbSFrançois Tigeot rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 1423926deccbSFrançois Tigeot gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1424926deccbSFrançois Tigeot if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 1425926deccbSFrançois Tigeot gb_tiling_config |= ROW_TILING(3); 1426926deccbSFrançois Tigeot gb_tiling_config |= SAMPLE_SPLIT(3); 1427926deccbSFrançois Tigeot } else { 1428926deccbSFrançois Tigeot gb_tiling_config |= 1429926deccbSFrançois Tigeot ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1430926deccbSFrançois Tigeot gb_tiling_config |= 1431926deccbSFrançois Tigeot SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1432926deccbSFrançois Tigeot } 1433926deccbSFrançois Tigeot 1434926deccbSFrançois Tigeot gb_tiling_config |= BANK_SWAPS(1); 1435926deccbSFrançois Tigeot rdev->config.rv770.tile_config = gb_tiling_config; 1436926deccbSFrançois Tigeot 1437926deccbSFrançois Tigeot WREG32(GB_TILING_CONFIG, gb_tiling_config); 1438926deccbSFrançois Tigeot WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1439926deccbSFrançois Tigeot WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1440926deccbSFrançois Tigeot WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1441926deccbSFrançois Tigeot WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); 1442f43cf1b1SMichael Neumann if (rdev->family == CHIP_RV730) { 1443f43cf1b1SMichael Neumann WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1444f43cf1b1SMichael Neumann WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1445f43cf1b1SMichael Neumann WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1446f43cf1b1SMichael Neumann } 1447926deccbSFrançois Tigeot 1448926deccbSFrançois Tigeot WREG32(CGTS_SYS_TCC_DISABLE, 0); 1449926deccbSFrançois Tigeot WREG32(CGTS_TCC_DISABLE, 0); 1450926deccbSFrançois Tigeot WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 1451926deccbSFrançois Tigeot WREG32(CGTS_USER_TCC_DISABLE, 0); 1452926deccbSFrançois Tigeot 1453926deccbSFrançois Tigeot 1454926deccbSFrançois Tigeot num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1455926deccbSFrançois Tigeot WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 1456926deccbSFrançois Tigeot WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1457926deccbSFrançois Tigeot 1458926deccbSFrançois Tigeot /* set HW defaults for 3D engine */ 1459926deccbSFrançois Tigeot WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1460926deccbSFrançois Tigeot ROQ_IB2_START(0x2b))); 1461926deccbSFrançois Tigeot 1462926deccbSFrançois Tigeot WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 1463926deccbSFrançois Tigeot 1464926deccbSFrançois Tigeot ta_aux_cntl = RREG32(TA_CNTL_AUX); 1465926deccbSFrançois Tigeot WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); 1466926deccbSFrançois Tigeot 1467926deccbSFrançois Tigeot sx_debug_1 = RREG32(SX_DEBUG_1); 1468926deccbSFrançois Tigeot sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1469926deccbSFrançois Tigeot WREG32(SX_DEBUG_1, sx_debug_1); 1470926deccbSFrançois Tigeot 1471926deccbSFrançois Tigeot smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1472926deccbSFrançois Tigeot smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 1473926deccbSFrançois Tigeot smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 1474926deccbSFrançois Tigeot WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1475926deccbSFrançois Tigeot 1476926deccbSFrançois Tigeot if (rdev->family != CHIP_RV740) 1477926deccbSFrançois Tigeot WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 1478926deccbSFrançois Tigeot GS_FLUSH_CTL(4) | 1479926deccbSFrançois Tigeot ACK_FLUSH_CTL(3) | 1480926deccbSFrançois Tigeot SYNC_FLUSH_CTL)); 1481926deccbSFrançois Tigeot 1482926deccbSFrançois Tigeot if (rdev->family != CHIP_RV770) 1483926deccbSFrançois Tigeot WREG32(SMX_SAR_CTL0, 0x00003f3f); 1484926deccbSFrançois Tigeot 1485926deccbSFrançois Tigeot db_debug3 = RREG32(DB_DEBUG3); 1486926deccbSFrançois Tigeot db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 1487926deccbSFrançois Tigeot switch (rdev->family) { 1488926deccbSFrançois Tigeot case CHIP_RV770: 1489926deccbSFrançois Tigeot case CHIP_RV740: 1490926deccbSFrançois Tigeot db_debug3 |= DB_CLK_OFF_DELAY(0x1f); 1491926deccbSFrançois Tigeot break; 1492926deccbSFrançois Tigeot case CHIP_RV710: 1493926deccbSFrançois Tigeot case CHIP_RV730: 1494926deccbSFrançois Tigeot default: 1495926deccbSFrançois Tigeot db_debug3 |= DB_CLK_OFF_DELAY(2); 1496926deccbSFrançois Tigeot break; 1497926deccbSFrançois Tigeot } 1498926deccbSFrançois Tigeot WREG32(DB_DEBUG3, db_debug3); 1499926deccbSFrançois Tigeot 1500926deccbSFrançois Tigeot if (rdev->family != CHIP_RV770) { 1501926deccbSFrançois Tigeot db_debug4 = RREG32(DB_DEBUG4); 1502926deccbSFrançois Tigeot db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 1503926deccbSFrançois Tigeot WREG32(DB_DEBUG4, db_debug4); 1504926deccbSFrançois Tigeot } 1505926deccbSFrançois Tigeot 1506926deccbSFrançois Tigeot WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 1507926deccbSFrançois Tigeot POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 1508926deccbSFrançois Tigeot SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 1509926deccbSFrançois Tigeot 1510926deccbSFrançois Tigeot WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 1511926deccbSFrançois Tigeot SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 1512926deccbSFrançois Tigeot SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 1513926deccbSFrançois Tigeot 1514926deccbSFrançois Tigeot WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1515926deccbSFrançois Tigeot 1516926deccbSFrançois Tigeot WREG32(VGT_NUM_INSTANCES, 1); 1517926deccbSFrançois Tigeot 1518926deccbSFrançois Tigeot WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1519926deccbSFrançois Tigeot 1520926deccbSFrançois Tigeot WREG32(CP_PERFMON_CNTL, 0); 1521926deccbSFrançois Tigeot 1522926deccbSFrançois Tigeot sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 1523926deccbSFrançois Tigeot DONE_FIFO_HIWATER(0xe0) | 1524926deccbSFrançois Tigeot ALU_UPDATE_FIFO_HIWATER(0x8)); 1525926deccbSFrançois Tigeot switch (rdev->family) { 1526926deccbSFrançois Tigeot case CHIP_RV770: 1527926deccbSFrançois Tigeot case CHIP_RV730: 1528926deccbSFrançois Tigeot case CHIP_RV710: 1529926deccbSFrançois Tigeot sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 1530926deccbSFrançois Tigeot break; 1531926deccbSFrançois Tigeot case CHIP_RV740: 1532926deccbSFrançois Tigeot default: 1533926deccbSFrançois Tigeot sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 1534926deccbSFrançois Tigeot break; 1535926deccbSFrançois Tigeot } 1536926deccbSFrançois Tigeot WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1537926deccbSFrançois Tigeot 1538926deccbSFrançois Tigeot /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1539926deccbSFrançois Tigeot * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1540926deccbSFrançois Tigeot */ 1541926deccbSFrançois Tigeot sq_config = RREG32(SQ_CONFIG); 1542926deccbSFrançois Tigeot sq_config &= ~(PS_PRIO(3) | 1543926deccbSFrançois Tigeot VS_PRIO(3) | 1544926deccbSFrançois Tigeot GS_PRIO(3) | 1545926deccbSFrançois Tigeot ES_PRIO(3)); 1546926deccbSFrançois Tigeot sq_config |= (DX9_CONSTS | 1547926deccbSFrançois Tigeot VC_ENABLE | 1548926deccbSFrançois Tigeot EXPORT_SRC_C | 1549926deccbSFrançois Tigeot PS_PRIO(0) | 1550926deccbSFrançois Tigeot VS_PRIO(1) | 1551926deccbSFrançois Tigeot GS_PRIO(2) | 1552926deccbSFrançois Tigeot ES_PRIO(3)); 1553926deccbSFrançois Tigeot if (rdev->family == CHIP_RV710) 1554926deccbSFrançois Tigeot /* no vertex cache */ 1555926deccbSFrançois Tigeot sq_config &= ~VC_ENABLE; 1556926deccbSFrançois Tigeot 1557926deccbSFrançois Tigeot WREG32(SQ_CONFIG, sq_config); 1558926deccbSFrançois Tigeot 1559926deccbSFrançois Tigeot WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1560926deccbSFrançois Tigeot NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1561926deccbSFrançois Tigeot NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 1562926deccbSFrançois Tigeot 1563926deccbSFrançois Tigeot WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 1564926deccbSFrançois Tigeot NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 1565926deccbSFrançois Tigeot 1566926deccbSFrançois Tigeot sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 1567926deccbSFrançois Tigeot NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 1568926deccbSFrançois Tigeot NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 1569926deccbSFrançois Tigeot if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 1570926deccbSFrançois Tigeot sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 1571926deccbSFrançois Tigeot else 1572926deccbSFrançois Tigeot sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 1573926deccbSFrançois Tigeot WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1574926deccbSFrançois Tigeot 1575926deccbSFrançois Tigeot WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1576926deccbSFrançois Tigeot NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1577926deccbSFrançois Tigeot 1578926deccbSFrançois Tigeot WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1579926deccbSFrançois Tigeot NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1580926deccbSFrançois Tigeot 1581926deccbSFrançois Tigeot sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1582926deccbSFrançois Tigeot SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 1583926deccbSFrançois Tigeot SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1584926deccbSFrançois Tigeot SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 1585926deccbSFrançois Tigeot 1586926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1587926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1588926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1589926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1590926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1591926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1592926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1593926deccbSFrançois Tigeot WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1594926deccbSFrançois Tigeot 1595926deccbSFrançois Tigeot WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1596926deccbSFrançois Tigeot FORCE_EOV_MAX_REZ_CNT(255))); 1597926deccbSFrançois Tigeot 1598926deccbSFrançois Tigeot if (rdev->family == CHIP_RV710) 1599926deccbSFrançois Tigeot WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 1600926deccbSFrançois Tigeot AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1601926deccbSFrançois Tigeot else 1602926deccbSFrançois Tigeot WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 1603926deccbSFrançois Tigeot AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1604926deccbSFrançois Tigeot 1605926deccbSFrançois Tigeot switch (rdev->family) { 1606926deccbSFrançois Tigeot case CHIP_RV770: 1607926deccbSFrançois Tigeot case CHIP_RV730: 1608926deccbSFrançois Tigeot case CHIP_RV740: 1609926deccbSFrançois Tigeot gs_prim_buffer_depth = 384; 1610926deccbSFrançois Tigeot break; 1611926deccbSFrançois Tigeot case CHIP_RV710: 1612926deccbSFrançois Tigeot gs_prim_buffer_depth = 128; 1613926deccbSFrançois Tigeot break; 1614926deccbSFrançois Tigeot default: 1615926deccbSFrançois Tigeot break; 1616926deccbSFrançois Tigeot } 1617926deccbSFrançois Tigeot 1618926deccbSFrançois Tigeot num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 1619926deccbSFrançois Tigeot vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1620926deccbSFrançois Tigeot /* Max value for this is 256 */ 1621926deccbSFrançois Tigeot if (vgt_gs_per_es > 256) 1622926deccbSFrançois Tigeot vgt_gs_per_es = 256; 1623926deccbSFrançois Tigeot 1624926deccbSFrançois Tigeot WREG32(VGT_ES_PER_GS, 128); 1625926deccbSFrançois Tigeot WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 1626926deccbSFrançois Tigeot WREG32(VGT_GS_PER_VS, 2); 1627926deccbSFrançois Tigeot 1628926deccbSFrançois Tigeot /* more default values. 2D/3D driver should adjust as needed */ 1629926deccbSFrançois Tigeot WREG32(VGT_GS_VERTEX_REUSE, 16); 1630926deccbSFrançois Tigeot WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1631926deccbSFrançois Tigeot WREG32(VGT_STRMOUT_EN, 0); 1632926deccbSFrançois Tigeot WREG32(SX_MISC, 0); 1633926deccbSFrançois Tigeot WREG32(PA_SC_MODE_CNTL, 0); 1634926deccbSFrançois Tigeot WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 1635926deccbSFrançois Tigeot WREG32(PA_SC_AA_CONFIG, 0); 1636926deccbSFrançois Tigeot WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 1637926deccbSFrançois Tigeot WREG32(PA_SC_LINE_STIPPLE, 0); 1638926deccbSFrançois Tigeot WREG32(SPI_INPUT_Z, 0); 1639926deccbSFrançois Tigeot WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1640926deccbSFrançois Tigeot WREG32(CB_COLOR7_FRAG, 0); 1641926deccbSFrançois Tigeot 1642926deccbSFrançois Tigeot /* clear render buffer base addresses */ 1643926deccbSFrançois Tigeot WREG32(CB_COLOR0_BASE, 0); 1644926deccbSFrançois Tigeot WREG32(CB_COLOR1_BASE, 0); 1645926deccbSFrançois Tigeot WREG32(CB_COLOR2_BASE, 0); 1646926deccbSFrançois Tigeot WREG32(CB_COLOR3_BASE, 0); 1647926deccbSFrançois Tigeot WREG32(CB_COLOR4_BASE, 0); 1648926deccbSFrançois Tigeot WREG32(CB_COLOR5_BASE, 0); 1649926deccbSFrançois Tigeot WREG32(CB_COLOR6_BASE, 0); 1650926deccbSFrançois Tigeot WREG32(CB_COLOR7_BASE, 0); 1651926deccbSFrançois Tigeot 1652926deccbSFrançois Tigeot WREG32(TCP_CNTL, 0); 1653926deccbSFrançois Tigeot 1654926deccbSFrançois Tigeot hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1655926deccbSFrançois Tigeot WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1656926deccbSFrançois Tigeot 1657926deccbSFrançois Tigeot WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1658926deccbSFrançois Tigeot 1659926deccbSFrançois Tigeot WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1660926deccbSFrançois Tigeot NUM_CLIP_SEQ(3))); 1661926deccbSFrançois Tigeot WREG32(VC_ENHANCE, 0); 1662926deccbSFrançois Tigeot } 1663926deccbSFrançois Tigeot 1664926deccbSFrançois Tigeot void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1665926deccbSFrançois Tigeot { 1666926deccbSFrançois Tigeot u64 size_bf, size_af; 1667926deccbSFrançois Tigeot 1668926deccbSFrançois Tigeot if (mc->mc_vram_size > 0xE0000000) { 1669926deccbSFrançois Tigeot /* leave room for at least 512M GTT */ 1670926deccbSFrançois Tigeot dev_warn(rdev->dev, "limiting VRAM\n"); 1671926deccbSFrançois Tigeot mc->real_vram_size = 0xE0000000; 1672926deccbSFrançois Tigeot mc->mc_vram_size = 0xE0000000; 1673926deccbSFrançois Tigeot } 1674926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) { 1675926deccbSFrançois Tigeot size_bf = mc->gtt_start; 1676f43cf1b1SMichael Neumann size_af = mc->mc_mask - mc->gtt_end; 1677926deccbSFrançois Tigeot if (size_bf > size_af) { 1678926deccbSFrançois Tigeot if (mc->mc_vram_size > size_bf) { 1679926deccbSFrançois Tigeot dev_warn(rdev->dev, "limiting VRAM\n"); 1680926deccbSFrançois Tigeot mc->real_vram_size = size_bf; 1681926deccbSFrançois Tigeot mc->mc_vram_size = size_bf; 1682926deccbSFrançois Tigeot } 1683926deccbSFrançois Tigeot mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1684926deccbSFrançois Tigeot } else { 1685926deccbSFrançois Tigeot if (mc->mc_vram_size > size_af) { 1686926deccbSFrançois Tigeot dev_warn(rdev->dev, "limiting VRAM\n"); 1687926deccbSFrançois Tigeot mc->real_vram_size = size_af; 1688926deccbSFrançois Tigeot mc->mc_vram_size = size_af; 1689926deccbSFrançois Tigeot } 1690926deccbSFrançois Tigeot mc->vram_start = mc->gtt_end + 1; 1691926deccbSFrançois Tigeot } 1692926deccbSFrançois Tigeot mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1693926deccbSFrançois Tigeot dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n", 1694926deccbSFrançois Tigeot (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start, 1695926deccbSFrançois Tigeot (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20); 1696926deccbSFrançois Tigeot } else { 1697926deccbSFrançois Tigeot radeon_vram_location(rdev, &rdev->mc, 0); 1698926deccbSFrançois Tigeot rdev->mc.gtt_base_align = 0; 1699926deccbSFrançois Tigeot radeon_gtt_location(rdev, mc); 1700926deccbSFrançois Tigeot } 1701926deccbSFrançois Tigeot } 1702926deccbSFrançois Tigeot 1703926deccbSFrançois Tigeot static int rv770_mc_init(struct radeon_device *rdev) 1704926deccbSFrançois Tigeot { 1705926deccbSFrançois Tigeot u32 tmp; 1706926deccbSFrançois Tigeot int chansize, numchan; 1707926deccbSFrançois Tigeot 1708926deccbSFrançois Tigeot /* Get VRAM informations */ 1709926deccbSFrançois Tigeot rdev->mc.vram_is_ddr = true; 1710926deccbSFrançois Tigeot tmp = RREG32(MC_ARB_RAMCFG); 1711926deccbSFrançois Tigeot if (tmp & CHANSIZE_OVERRIDE) { 1712926deccbSFrançois Tigeot chansize = 16; 1713926deccbSFrançois Tigeot } else if (tmp & CHANSIZE_MASK) { 1714926deccbSFrançois Tigeot chansize = 64; 1715926deccbSFrançois Tigeot } else { 1716926deccbSFrançois Tigeot chansize = 32; 1717926deccbSFrançois Tigeot } 1718926deccbSFrançois Tigeot tmp = RREG32(MC_SHARED_CHMAP); 1719926deccbSFrançois Tigeot switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1720926deccbSFrançois Tigeot case 0: 1721926deccbSFrançois Tigeot default: 1722926deccbSFrançois Tigeot numchan = 1; 1723926deccbSFrançois Tigeot break; 1724926deccbSFrançois Tigeot case 1: 1725926deccbSFrançois Tigeot numchan = 2; 1726926deccbSFrançois Tigeot break; 1727926deccbSFrançois Tigeot case 2: 1728926deccbSFrançois Tigeot numchan = 4; 1729926deccbSFrançois Tigeot break; 1730926deccbSFrançois Tigeot case 3: 1731926deccbSFrançois Tigeot numchan = 8; 1732926deccbSFrançois Tigeot break; 1733926deccbSFrançois Tigeot } 1734926deccbSFrançois Tigeot rdev->mc.vram_width = numchan * chansize; 1735926deccbSFrançois Tigeot /* Could aper size report 0 ? */ 1736926deccbSFrançois Tigeot rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1737926deccbSFrançois Tigeot rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1738926deccbSFrançois Tigeot /* Setup GPU memory space */ 1739926deccbSFrançois Tigeot rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1740926deccbSFrançois Tigeot rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1741926deccbSFrançois Tigeot rdev->mc.visible_vram_size = rdev->mc.aper_size; 1742926deccbSFrançois Tigeot r700_vram_gtt_location(rdev, &rdev->mc); 1743926deccbSFrançois Tigeot radeon_update_bandwidth_info(rdev); 1744926deccbSFrançois Tigeot 1745926deccbSFrançois Tigeot return 0; 1746926deccbSFrançois Tigeot } 1747926deccbSFrançois Tigeot 1748926deccbSFrançois Tigeot /** 1749926deccbSFrançois Tigeot * rv770_copy_dma - copy pages using the DMA engine 1750926deccbSFrançois Tigeot * 1751926deccbSFrançois Tigeot * @rdev: radeon_device pointer 1752926deccbSFrançois Tigeot * @src_offset: src GPU address 1753926deccbSFrançois Tigeot * @dst_offset: dst GPU address 1754926deccbSFrançois Tigeot * @num_gpu_pages: number of GPU pages to xfer 1755926deccbSFrançois Tigeot * @fence: radeon fence object 1756926deccbSFrançois Tigeot * 1757926deccbSFrançois Tigeot * Copy GPU paging using the DMA engine (r7xx). 1758926deccbSFrançois Tigeot * Used by the radeon ttm implementation to move pages if 1759926deccbSFrançois Tigeot * registered as the asic copy callback. 1760926deccbSFrançois Tigeot */ 1761926deccbSFrançois Tigeot int rv770_copy_dma(struct radeon_device *rdev, 1762926deccbSFrançois Tigeot uint64_t src_offset, uint64_t dst_offset, 1763926deccbSFrançois Tigeot unsigned num_gpu_pages, 1764926deccbSFrançois Tigeot struct radeon_fence **fence) 1765926deccbSFrançois Tigeot { 1766926deccbSFrançois Tigeot struct radeon_semaphore *sem = NULL; 1767926deccbSFrançois Tigeot int ring_index = rdev->asic->copy.dma_ring_index; 1768926deccbSFrançois Tigeot struct radeon_ring *ring = &rdev->ring[ring_index]; 1769926deccbSFrançois Tigeot u32 size_in_dw, cur_size_in_dw; 1770926deccbSFrançois Tigeot int i, num_loops; 1771926deccbSFrançois Tigeot int r = 0; 1772926deccbSFrançois Tigeot 1773926deccbSFrançois Tigeot r = radeon_semaphore_create(rdev, &sem); 1774926deccbSFrançois Tigeot if (r) { 1775926deccbSFrançois Tigeot DRM_ERROR("radeon: moving bo (%d).\n", r); 1776926deccbSFrançois Tigeot return r; 1777926deccbSFrançois Tigeot } 1778926deccbSFrançois Tigeot 1779926deccbSFrançois Tigeot size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 1780926deccbSFrançois Tigeot num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF); 1781926deccbSFrançois Tigeot r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8); 1782926deccbSFrançois Tigeot if (r) { 1783926deccbSFrançois Tigeot DRM_ERROR("radeon: moving bo (%d).\n", r); 1784926deccbSFrançois Tigeot radeon_semaphore_free(rdev, &sem, NULL); 1785926deccbSFrançois Tigeot return r; 1786926deccbSFrançois Tigeot } 1787926deccbSFrançois Tigeot 1788926deccbSFrançois Tigeot if (radeon_fence_need_sync(*fence, ring->idx)) { 1789926deccbSFrançois Tigeot radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 1790926deccbSFrançois Tigeot ring->idx); 1791926deccbSFrançois Tigeot radeon_fence_note_sync(*fence, ring->idx); 1792926deccbSFrançois Tigeot } else { 1793926deccbSFrançois Tigeot radeon_semaphore_free(rdev, &sem, NULL); 1794926deccbSFrançois Tigeot } 1795926deccbSFrançois Tigeot 1796926deccbSFrançois Tigeot for (i = 0; i < num_loops; i++) { 1797926deccbSFrançois Tigeot cur_size_in_dw = size_in_dw; 1798926deccbSFrançois Tigeot if (cur_size_in_dw > 0xFFFF) 1799926deccbSFrançois Tigeot cur_size_in_dw = 0xFFFF; 1800926deccbSFrançois Tigeot size_in_dw -= cur_size_in_dw; 1801926deccbSFrançois Tigeot radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 1802926deccbSFrançois Tigeot radeon_ring_write(ring, dst_offset & 0xfffffffc); 1803926deccbSFrançois Tigeot radeon_ring_write(ring, src_offset & 0xfffffffc); 1804926deccbSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 1805926deccbSFrançois Tigeot radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 1806926deccbSFrançois Tigeot src_offset += cur_size_in_dw * 4; 1807926deccbSFrançois Tigeot dst_offset += cur_size_in_dw * 4; 1808926deccbSFrançois Tigeot } 1809926deccbSFrançois Tigeot 1810926deccbSFrançois Tigeot r = radeon_fence_emit(rdev, fence, ring->idx); 1811926deccbSFrançois Tigeot if (r) { 1812926deccbSFrançois Tigeot radeon_ring_unlock_undo(rdev, ring); 1813926deccbSFrançois Tigeot return r; 1814926deccbSFrançois Tigeot } 1815926deccbSFrançois Tigeot 1816926deccbSFrançois Tigeot radeon_ring_unlock_commit(rdev, ring); 1817926deccbSFrançois Tigeot radeon_semaphore_free(rdev, &sem, *fence); 1818926deccbSFrançois Tigeot 1819926deccbSFrançois Tigeot return r; 1820926deccbSFrançois Tigeot } 1821926deccbSFrançois Tigeot 1822926deccbSFrançois Tigeot static int rv770_startup(struct radeon_device *rdev) 1823926deccbSFrançois Tigeot { 1824926deccbSFrançois Tigeot struct radeon_ring *ring; 1825926deccbSFrançois Tigeot int r; 1826926deccbSFrançois Tigeot 1827926deccbSFrançois Tigeot /* enable pcie gen2 link */ 1828926deccbSFrançois Tigeot rv770_pcie_gen2_enable(rdev); 1829926deccbSFrançois Tigeot 1830*57e252bfSMichael Neumann rv770_mc_program(rdev); 1831*57e252bfSMichael Neumann 1832926deccbSFrançois Tigeot if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1833926deccbSFrançois Tigeot r = r600_init_microcode(rdev); 1834926deccbSFrançois Tigeot if (r) { 1835926deccbSFrançois Tigeot DRM_ERROR("Failed to load firmware!\n"); 1836926deccbSFrançois Tigeot return r; 1837926deccbSFrançois Tigeot } 1838926deccbSFrançois Tigeot } 1839926deccbSFrançois Tigeot 1840926deccbSFrançois Tigeot r = r600_vram_scratch_init(rdev); 1841926deccbSFrançois Tigeot if (r) 1842926deccbSFrançois Tigeot return r; 1843926deccbSFrançois Tigeot 1844926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) { 1845926deccbSFrançois Tigeot rv770_agp_enable(rdev); 1846926deccbSFrançois Tigeot } else { 1847926deccbSFrançois Tigeot r = rv770_pcie_gart_enable(rdev); 1848926deccbSFrançois Tigeot if (r) 1849926deccbSFrançois Tigeot return r; 1850926deccbSFrançois Tigeot } 1851926deccbSFrançois Tigeot 1852926deccbSFrançois Tigeot rv770_gpu_init(rdev); 1853926deccbSFrançois Tigeot r = r600_blit_init(rdev); 1854926deccbSFrançois Tigeot if (r) { 1855926deccbSFrançois Tigeot r600_blit_fini(rdev); 1856926deccbSFrançois Tigeot rdev->asic->copy.copy = NULL; 1857926deccbSFrançois Tigeot dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 1858926deccbSFrançois Tigeot } 1859926deccbSFrançois Tigeot 1860926deccbSFrançois Tigeot /* allocate wb buffer */ 1861926deccbSFrançois Tigeot r = radeon_wb_init(rdev); 1862926deccbSFrançois Tigeot if (r) 1863926deccbSFrançois Tigeot return r; 1864926deccbSFrançois Tigeot 1865926deccbSFrançois Tigeot r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1866926deccbSFrançois Tigeot if (r) { 1867926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1868926deccbSFrançois Tigeot return r; 1869926deccbSFrançois Tigeot } 1870926deccbSFrançois Tigeot 1871926deccbSFrançois Tigeot r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 1872926deccbSFrançois Tigeot if (r) { 1873926deccbSFrançois Tigeot dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 1874926deccbSFrançois Tigeot return r; 1875926deccbSFrançois Tigeot } 1876926deccbSFrançois Tigeot 1877f43cf1b1SMichael Neumann r = rv770_uvd_resume(rdev); 1878f43cf1b1SMichael Neumann if (!r) { 1879f43cf1b1SMichael Neumann r = radeon_fence_driver_start_ring(rdev, 1880f43cf1b1SMichael Neumann R600_RING_TYPE_UVD_INDEX); 1881f43cf1b1SMichael Neumann if (r) 1882f43cf1b1SMichael Neumann dev_err(rdev->dev, "UVD fences init error (%d).\n", r); 1883f43cf1b1SMichael Neumann } 1884f43cf1b1SMichael Neumann 1885f43cf1b1SMichael Neumann if (r) 1886f43cf1b1SMichael Neumann rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 1887f43cf1b1SMichael Neumann 1888926deccbSFrançois Tigeot /* Enable IRQ */ 1889f43cf1b1SMichael Neumann if (!rdev->irq.installed) { 1890f43cf1b1SMichael Neumann r = radeon_irq_kms_init(rdev); 1891f43cf1b1SMichael Neumann if (r) 1892f43cf1b1SMichael Neumann return r; 1893f43cf1b1SMichael Neumann } 1894f43cf1b1SMichael Neumann 1895926deccbSFrançois Tigeot r = r600_irq_init(rdev); 1896926deccbSFrançois Tigeot if (r) { 1897926deccbSFrançois Tigeot DRM_ERROR("radeon: IH init failed (%d).\n", r); 1898926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev); 1899926deccbSFrançois Tigeot return r; 1900926deccbSFrançois Tigeot } 1901926deccbSFrançois Tigeot r600_irq_set(rdev); 1902926deccbSFrançois Tigeot 1903926deccbSFrançois Tigeot ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1904926deccbSFrançois Tigeot r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 1905926deccbSFrançois Tigeot R600_CP_RB_RPTR, R600_CP_RB_WPTR, 1906926deccbSFrançois Tigeot 0, 0xfffff, RADEON_CP_PACKET2); 1907926deccbSFrançois Tigeot if (r) 1908926deccbSFrançois Tigeot return r; 1909926deccbSFrançois Tigeot 1910926deccbSFrançois Tigeot ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 1911926deccbSFrançois Tigeot r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 1912926deccbSFrançois Tigeot DMA_RB_RPTR, DMA_RB_WPTR, 1913926deccbSFrançois Tigeot 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 1914926deccbSFrançois Tigeot if (r) 1915926deccbSFrançois Tigeot return r; 1916926deccbSFrançois Tigeot 1917926deccbSFrançois Tigeot r = rv770_cp_load_microcode(rdev); 1918926deccbSFrançois Tigeot if (r) 1919926deccbSFrançois Tigeot return r; 1920926deccbSFrançois Tigeot r = r600_cp_resume(rdev); 1921926deccbSFrançois Tigeot if (r) 1922926deccbSFrançois Tigeot return r; 1923926deccbSFrançois Tigeot 1924926deccbSFrançois Tigeot r = r600_dma_resume(rdev); 1925926deccbSFrançois Tigeot if (r) 1926926deccbSFrançois Tigeot return r; 1927926deccbSFrançois Tigeot 1928f43cf1b1SMichael Neumann ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 1929f43cf1b1SMichael Neumann if (ring->ring_size) { 1930f43cf1b1SMichael Neumann r = radeon_ring_init(rdev, ring, ring->ring_size, 1931f43cf1b1SMichael Neumann R600_WB_UVD_RPTR_OFFSET, 1932f43cf1b1SMichael Neumann UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, 1933f43cf1b1SMichael Neumann 0, 0xfffff, RADEON_CP_PACKET2); 1934f43cf1b1SMichael Neumann if (!r) 1935f43cf1b1SMichael Neumann r = r600_uvd_init(rdev); 1936f43cf1b1SMichael Neumann 1937f43cf1b1SMichael Neumann if (r) 1938f43cf1b1SMichael Neumann DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 1939f43cf1b1SMichael Neumann } 1940f43cf1b1SMichael Neumann 1941926deccbSFrançois Tigeot r = radeon_ib_pool_init(rdev); 1942926deccbSFrançois Tigeot if (r) { 1943926deccbSFrançois Tigeot dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1944926deccbSFrançois Tigeot return r; 1945926deccbSFrançois Tigeot } 1946926deccbSFrançois Tigeot 1947926deccbSFrançois Tigeot r = r600_audio_init(rdev); 1948926deccbSFrançois Tigeot if (r) { 1949926deccbSFrançois Tigeot DRM_ERROR("radeon: audio init failed\n"); 1950926deccbSFrançois Tigeot return r; 1951926deccbSFrançois Tigeot } 1952926deccbSFrançois Tigeot 1953926deccbSFrançois Tigeot return 0; 1954926deccbSFrançois Tigeot } 1955926deccbSFrançois Tigeot 1956926deccbSFrançois Tigeot int rv770_resume(struct radeon_device *rdev) 1957926deccbSFrançois Tigeot { 1958926deccbSFrançois Tigeot int r; 1959926deccbSFrançois Tigeot 1960926deccbSFrançois Tigeot /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1961926deccbSFrançois Tigeot * posting will perform necessary task to bring back GPU into good 1962926deccbSFrançois Tigeot * shape. 1963926deccbSFrançois Tigeot */ 1964926deccbSFrançois Tigeot /* post card */ 1965926deccbSFrançois Tigeot atom_asic_init(rdev->mode_info.atom_context); 1966926deccbSFrançois Tigeot 1967f43cf1b1SMichael Neumann /* init golden registers */ 1968f43cf1b1SMichael Neumann rv770_init_golden_registers(rdev); 1969f43cf1b1SMichael Neumann 1970926deccbSFrançois Tigeot rdev->accel_working = true; 1971926deccbSFrançois Tigeot r = rv770_startup(rdev); 1972926deccbSFrançois Tigeot if (r) { 1973926deccbSFrançois Tigeot DRM_ERROR("r600 startup failed on resume\n"); 1974926deccbSFrançois Tigeot rdev->accel_working = false; 1975926deccbSFrançois Tigeot return r; 1976926deccbSFrançois Tigeot } 1977926deccbSFrançois Tigeot 1978926deccbSFrançois Tigeot return r; 1979926deccbSFrançois Tigeot 1980926deccbSFrançois Tigeot } 1981926deccbSFrançois Tigeot 1982926deccbSFrançois Tigeot int rv770_suspend(struct radeon_device *rdev) 1983926deccbSFrançois Tigeot { 1984926deccbSFrançois Tigeot r600_audio_fini(rdev); 1985*57e252bfSMichael Neumann r600_uvd_stop(rdev); 1986f43cf1b1SMichael Neumann radeon_uvd_suspend(rdev); 1987926deccbSFrançois Tigeot r700_cp_stop(rdev); 1988926deccbSFrançois Tigeot r600_dma_stop(rdev); 1989926deccbSFrançois Tigeot r600_irq_suspend(rdev); 1990926deccbSFrançois Tigeot radeon_wb_disable(rdev); 1991926deccbSFrançois Tigeot rv770_pcie_gart_disable(rdev); 1992926deccbSFrançois Tigeot 1993926deccbSFrançois Tigeot return 0; 1994926deccbSFrançois Tigeot } 1995926deccbSFrançois Tigeot 1996926deccbSFrançois Tigeot /* Plan is to move initialization in that function and use 1997926deccbSFrançois Tigeot * helper function so that radeon_device_init pretty much 1998926deccbSFrançois Tigeot * do nothing more than calling asic specific function. This 1999926deccbSFrançois Tigeot * should also allow to remove a bunch of callback function 2000926deccbSFrançois Tigeot * like vram_info. 2001926deccbSFrançois Tigeot */ 2002926deccbSFrançois Tigeot int rv770_init(struct radeon_device *rdev) 2003926deccbSFrançois Tigeot { 2004926deccbSFrançois Tigeot int r; 2005926deccbSFrançois Tigeot 2006926deccbSFrançois Tigeot /* Read BIOS */ 2007926deccbSFrançois Tigeot if (!radeon_get_bios(rdev)) { 2008926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev)) 2009926deccbSFrançois Tigeot return -EINVAL; 2010926deccbSFrançois Tigeot } 2011926deccbSFrançois Tigeot /* Must be an ATOMBIOS */ 2012926deccbSFrançois Tigeot if (!rdev->is_atom_bios) { 2013926deccbSFrançois Tigeot dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 2014926deccbSFrançois Tigeot return -EINVAL; 2015926deccbSFrançois Tigeot } 2016926deccbSFrançois Tigeot r = radeon_atombios_init(rdev); 2017926deccbSFrançois Tigeot if (r) 2018926deccbSFrançois Tigeot return r; 2019926deccbSFrançois Tigeot /* Post card if necessary */ 2020926deccbSFrançois Tigeot if (!radeon_card_posted(rdev)) { 2021926deccbSFrançois Tigeot if (!rdev->bios) { 2022926deccbSFrançois Tigeot dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2023926deccbSFrançois Tigeot return -EINVAL; 2024926deccbSFrançois Tigeot } 2025926deccbSFrançois Tigeot DRM_INFO("GPU not posted. posting now...\n"); 2026926deccbSFrançois Tigeot atom_asic_init(rdev->mode_info.atom_context); 2027926deccbSFrançois Tigeot } 2028f43cf1b1SMichael Neumann /* init golden registers */ 2029f43cf1b1SMichael Neumann rv770_init_golden_registers(rdev); 2030926deccbSFrançois Tigeot /* Initialize scratch registers */ 2031926deccbSFrançois Tigeot r600_scratch_init(rdev); 2032926deccbSFrançois Tigeot /* Initialize surface registers */ 2033926deccbSFrançois Tigeot radeon_surface_init(rdev); 2034926deccbSFrançois Tigeot /* Initialize clocks */ 2035926deccbSFrançois Tigeot radeon_get_clock_info(rdev->ddev); 2036926deccbSFrançois Tigeot /* Fence driver */ 2037926deccbSFrançois Tigeot r = radeon_fence_driver_init(rdev); 2038926deccbSFrançois Tigeot if (r) 2039926deccbSFrançois Tigeot return r; 2040926deccbSFrançois Tigeot /* initialize AGP */ 2041926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_AGP) { 2042926deccbSFrançois Tigeot r = radeon_agp_init(rdev); 2043926deccbSFrançois Tigeot if (r) 2044926deccbSFrançois Tigeot radeon_agp_disable(rdev); 2045926deccbSFrançois Tigeot } 2046926deccbSFrançois Tigeot r = rv770_mc_init(rdev); 2047926deccbSFrançois Tigeot if (r) 2048926deccbSFrançois Tigeot return r; 2049926deccbSFrançois Tigeot /* Memory manager */ 2050926deccbSFrançois Tigeot r = radeon_bo_init(rdev); 2051926deccbSFrançois Tigeot if (r) 2052926deccbSFrançois Tigeot return r; 2053926deccbSFrançois Tigeot 2054926deccbSFrançois Tigeot rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 2055926deccbSFrançois Tigeot r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 2056926deccbSFrançois Tigeot 2057926deccbSFrançois Tigeot rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 2058926deccbSFrançois Tigeot r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 2059926deccbSFrançois Tigeot 2060f43cf1b1SMichael Neumann r = radeon_uvd_init(rdev); 2061f43cf1b1SMichael Neumann if (!r) { 2062f43cf1b1SMichael Neumann rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 2063f43cf1b1SMichael Neumann r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 2064f43cf1b1SMichael Neumann 4096); 2065f43cf1b1SMichael Neumann } 2066f43cf1b1SMichael Neumann 2067926deccbSFrançois Tigeot rdev->ih.ring_obj = NULL; 2068926deccbSFrançois Tigeot r600_ih_ring_init(rdev, 64 * 1024); 2069926deccbSFrançois Tigeot 2070926deccbSFrançois Tigeot r = r600_pcie_gart_init(rdev); 2071926deccbSFrançois Tigeot if (r) 2072926deccbSFrançois Tigeot return r; 2073926deccbSFrançois Tigeot 2074926deccbSFrançois Tigeot rdev->accel_working = true; 2075926deccbSFrançois Tigeot r = rv770_startup(rdev); 2076926deccbSFrançois Tigeot if (r) { 2077926deccbSFrançois Tigeot dev_err(rdev->dev, "disabling GPU acceleration\n"); 2078926deccbSFrançois Tigeot r700_cp_fini(rdev); 2079926deccbSFrançois Tigeot r600_dma_fini(rdev); 2080926deccbSFrançois Tigeot r600_irq_fini(rdev); 2081926deccbSFrançois Tigeot radeon_wb_fini(rdev); 2082926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev); 2083926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev); 2084926deccbSFrançois Tigeot rv770_pcie_gart_fini(rdev); 2085926deccbSFrançois Tigeot rdev->accel_working = false; 2086926deccbSFrançois Tigeot } 2087926deccbSFrançois Tigeot 2088926deccbSFrançois Tigeot return 0; 2089926deccbSFrançois Tigeot } 2090926deccbSFrançois Tigeot 2091926deccbSFrançois Tigeot void rv770_fini(struct radeon_device *rdev) 2092926deccbSFrançois Tigeot { 2093926deccbSFrançois Tigeot r600_blit_fini(rdev); 2094926deccbSFrançois Tigeot r700_cp_fini(rdev); 2095926deccbSFrançois Tigeot r600_dma_fini(rdev); 2096926deccbSFrançois Tigeot r600_irq_fini(rdev); 2097926deccbSFrançois Tigeot radeon_wb_fini(rdev); 2098926deccbSFrançois Tigeot radeon_ib_pool_fini(rdev); 2099926deccbSFrançois Tigeot radeon_irq_kms_fini(rdev); 2100926deccbSFrançois Tigeot rv770_pcie_gart_fini(rdev); 2101*57e252bfSMichael Neumann r600_uvd_stop(rdev); 2102f43cf1b1SMichael Neumann radeon_uvd_fini(rdev); 2103926deccbSFrançois Tigeot r600_vram_scratch_fini(rdev); 2104926deccbSFrançois Tigeot radeon_gem_fini(rdev); 2105926deccbSFrançois Tigeot radeon_fence_driver_fini(rdev); 2106926deccbSFrançois Tigeot radeon_agp_fini(rdev); 2107926deccbSFrançois Tigeot radeon_bo_fini(rdev); 2108926deccbSFrançois Tigeot radeon_atombios_fini(rdev); 2109926deccbSFrançois Tigeot r600_fini_microcode(rdev); 21105a3b77d5SFrançois Tigeot drm_free(rdev->bios, M_DRM); 2111926deccbSFrançois Tigeot rdev->bios = NULL; 2112926deccbSFrançois Tigeot } 2113926deccbSFrançois Tigeot 2114926deccbSFrançois Tigeot static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 2115926deccbSFrançois Tigeot { 2116926deccbSFrançois Tigeot u32 link_width_cntl, lanes, speed_cntl, tmp; 2117926deccbSFrançois Tigeot u16 link_cntl2; 2118926deccbSFrançois Tigeot u32 mask; 2119926deccbSFrançois Tigeot int ret; 2120926deccbSFrançois Tigeot 2121926deccbSFrançois Tigeot if (radeon_pcie_gen2 == 0) 2122926deccbSFrançois Tigeot return; 2123926deccbSFrançois Tigeot 2124926deccbSFrançois Tigeot if (rdev->flags & RADEON_IS_IGP) 2125926deccbSFrançois Tigeot return; 2126926deccbSFrançois Tigeot 2127926deccbSFrançois Tigeot if (!(rdev->flags & RADEON_IS_PCIE)) 2128926deccbSFrançois Tigeot return; 2129926deccbSFrançois Tigeot 2130926deccbSFrançois Tigeot /* x2 cards have a special sequence */ 2131926deccbSFrançois Tigeot if (ASIC_IS_X2(rdev)) 2132926deccbSFrançois Tigeot return; 2133926deccbSFrançois Tigeot 2134926deccbSFrançois Tigeot ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 2135926deccbSFrançois Tigeot if (ret != 0) 2136926deccbSFrançois Tigeot return; 2137926deccbSFrançois Tigeot 2138926deccbSFrançois Tigeot if (!(mask & DRM_PCIE_SPEED_50)) 2139926deccbSFrançois Tigeot return; 2140926deccbSFrançois Tigeot 2141926deccbSFrançois Tigeot DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 2142926deccbSFrançois Tigeot 2143926deccbSFrançois Tigeot /* advertise upconfig capability */ 2144f43cf1b1SMichael Neumann link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2145926deccbSFrançois Tigeot link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2146f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2147f43cf1b1SMichael Neumann link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2148926deccbSFrançois Tigeot if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 2149926deccbSFrançois Tigeot lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 2150926deccbSFrançois Tigeot link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 2151926deccbSFrançois Tigeot LC_RECONFIG_ARC_MISSING_ESCAPE); 2152926deccbSFrançois Tigeot link_width_cntl |= lanes | LC_RECONFIG_NOW | 2153926deccbSFrançois Tigeot LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; 2154f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2155926deccbSFrançois Tigeot } else { 2156926deccbSFrançois Tigeot link_width_cntl |= LC_UPCONFIGURE_DIS; 2157f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2158926deccbSFrançois Tigeot } 2159926deccbSFrançois Tigeot 2160f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2161926deccbSFrançois Tigeot if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 2162926deccbSFrançois Tigeot (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 2163926deccbSFrançois Tigeot 2164926deccbSFrançois Tigeot tmp = RREG32(0x541c); 2165926deccbSFrançois Tigeot WREG32(0x541c, tmp | 0x8); 2166926deccbSFrançois Tigeot WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 2167926deccbSFrançois Tigeot link_cntl2 = RREG16(0x4088); 2168926deccbSFrançois Tigeot link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 2169926deccbSFrançois Tigeot link_cntl2 |= 0x2; 2170926deccbSFrançois Tigeot WREG16(0x4088, link_cntl2); 2171926deccbSFrançois Tigeot WREG32(MM_CFGREGS_CNTL, 0); 2172926deccbSFrançois Tigeot 2173f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2174926deccbSFrançois Tigeot speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 2175f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2176926deccbSFrançois Tigeot 2177f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2178926deccbSFrançois Tigeot speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 2179f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2180926deccbSFrançois Tigeot 2181f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2182926deccbSFrançois Tigeot speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 2183f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2184926deccbSFrançois Tigeot 2185f43cf1b1SMichael Neumann speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2186926deccbSFrançois Tigeot speed_cntl |= LC_GEN2_EN_STRAP; 2187f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2188926deccbSFrançois Tigeot 2189926deccbSFrançois Tigeot } else { 2190f43cf1b1SMichael Neumann link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2191926deccbSFrançois Tigeot /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 2192926deccbSFrançois Tigeot if (1) 2193926deccbSFrançois Tigeot link_width_cntl |= LC_UPCONFIGURE_DIS; 2194926deccbSFrançois Tigeot else 2195926deccbSFrançois Tigeot link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2196f43cf1b1SMichael Neumann WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2197926deccbSFrançois Tigeot } 2198926deccbSFrançois Tigeot } 2199