1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/firmware.h> 29 #include <drm/drmP.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include <uapi_drm/radeon_drm.h> 33 #include "rv770d.h" 34 #include "atom.h" 35 #include "avivod.h" 36 37 #define R700_PFP_UCODE_SIZE 848 38 #define R700_PM4_UCODE_SIZE 1360 39 40 static void rv770_gpu_init(struct radeon_device *rdev); 41 static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 42 43 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 44 { 45 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; 46 int r; 47 48 /* RV740 uses evergreen uvd clk programming */ 49 if (rdev->family == CHIP_RV740) 50 return evergreen_set_uvd_clocks(rdev, vclk, dclk); 51 52 /* bypass vclk and dclk with bclk */ 53 WREG32_P(CG_UPLL_FUNC_CNTL_2, 54 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 55 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 56 57 if (!vclk || !dclk) { 58 /* keep the Bypass mode, put PLL to sleep */ 59 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 60 return 0; 61 } 62 63 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 64 43663, 0x03FFFFFE, 1, 30, ~0, 65 &fb_div, &vclk_div, &dclk_div); 66 if (r) 67 return r; 68 69 fb_div |= 1; 70 vclk_div -= 1; 71 dclk_div -= 1; 72 73 /* set UPLL_FB_DIV to 0x50000 */ 74 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); 75 76 /* deassert UPLL_RESET and UPLL_SLEEP */ 77 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); 78 79 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ 80 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 81 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); 82 83 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 84 if (r) 85 return r; 86 87 /* assert PLL_RESET */ 88 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 89 90 /* set the required FB_DIV, REF_DIV, Post divder values */ 91 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); 92 WREG32_P(CG_UPLL_FUNC_CNTL_2, 93 UPLL_SW_HILEN(vclk_div >> 1) | 94 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 95 UPLL_SW_HILEN2(dclk_div >> 1) | 96 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), 97 ~UPLL_SW_MASK); 98 99 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), 100 ~UPLL_FB_DIV_MASK); 101 102 /* give the PLL some time to settle */ 103 mdelay(15); 104 105 /* deassert PLL_RESET */ 106 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 107 108 mdelay(15); 109 110 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ 111 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 112 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); 113 114 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 115 if (r) 116 return r; 117 118 /* switch VCLK and DCLK selection */ 119 WREG32_P(CG_UPLL_FUNC_CNTL_2, 120 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 121 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 122 123 mdelay(100); 124 125 return 0; 126 } 127 128 static const u32 r7xx_golden_registers[] = 129 { 130 0x8d00, 0xffffffff, 0x0e0e0074, 131 0x8d04, 0xffffffff, 0x013a2b34, 132 0x9508, 0xffffffff, 0x00000002, 133 0x8b20, 0xffffffff, 0, 134 0x88c4, 0xffffffff, 0x000000c2, 135 0x28350, 0xffffffff, 0, 136 0x9058, 0xffffffff, 0x0fffc40f, 137 0x240c, 0xffffffff, 0x00000380, 138 0x733c, 0xffffffff, 0x00000002, 139 0x2650, 0x00040000, 0, 140 0x20bc, 0x00040000, 0, 141 0x7300, 0xffffffff, 0x001000f0 142 }; 143 144 static const u32 r7xx_golden_dyn_gpr_registers[] = 145 { 146 0x8db0, 0xffffffff, 0x98989898, 147 0x8db4, 0xffffffff, 0x98989898, 148 0x8db8, 0xffffffff, 0x98989898, 149 0x8dbc, 0xffffffff, 0x98989898, 150 0x8dc0, 0xffffffff, 0x98989898, 151 0x8dc4, 0xffffffff, 0x98989898, 152 0x8dc8, 0xffffffff, 0x98989898, 153 0x8dcc, 0xffffffff, 0x98989898, 154 0x88c4, 0xffffffff, 0x00000082 155 }; 156 157 static const u32 rv770_golden_registers[] = 158 { 159 0x562c, 0xffffffff, 0, 160 0x3f90, 0xffffffff, 0, 161 0x9148, 0xffffffff, 0, 162 0x3f94, 0xffffffff, 0, 163 0x914c, 0xffffffff, 0, 164 0x9698, 0x18000000, 0x18000000 165 }; 166 167 static const u32 rv770ce_golden_registers[] = 168 { 169 0x562c, 0xffffffff, 0, 170 0x3f90, 0xffffffff, 0x00cc0000, 171 0x9148, 0xffffffff, 0x00cc0000, 172 0x3f94, 0xffffffff, 0x00cc0000, 173 0x914c, 0xffffffff, 0x00cc0000, 174 0x9b7c, 0xffffffff, 0x00fa0000, 175 0x3f8c, 0xffffffff, 0x00fa0000, 176 0x9698, 0x18000000, 0x18000000 177 }; 178 179 static const u32 rv770_mgcg_init[] = 180 { 181 0x8bcc, 0xffffffff, 0x130300f9, 182 0x5448, 0xffffffff, 0x100, 183 0x55e4, 0xffffffff, 0x100, 184 0x160c, 0xffffffff, 0x100, 185 0x5644, 0xffffffff, 0x100, 186 0xc164, 0xffffffff, 0x100, 187 0x8a18, 0xffffffff, 0x100, 188 0x897c, 0xffffffff, 0x8000100, 189 0x8b28, 0xffffffff, 0x3c000100, 190 0x9144, 0xffffffff, 0x100, 191 0x9a1c, 0xffffffff, 0x10000, 192 0x9a50, 0xffffffff, 0x100, 193 0x9a1c, 0xffffffff, 0x10001, 194 0x9a50, 0xffffffff, 0x100, 195 0x9a1c, 0xffffffff, 0x10002, 196 0x9a50, 0xffffffff, 0x100, 197 0x9a1c, 0xffffffff, 0x10003, 198 0x9a50, 0xffffffff, 0x100, 199 0x9a1c, 0xffffffff, 0x0, 200 0x9870, 0xffffffff, 0x100, 201 0x8d58, 0xffffffff, 0x100, 202 0x9500, 0xffffffff, 0x0, 203 0x9510, 0xffffffff, 0x100, 204 0x9500, 0xffffffff, 0x1, 205 0x9510, 0xffffffff, 0x100, 206 0x9500, 0xffffffff, 0x2, 207 0x9510, 0xffffffff, 0x100, 208 0x9500, 0xffffffff, 0x3, 209 0x9510, 0xffffffff, 0x100, 210 0x9500, 0xffffffff, 0x4, 211 0x9510, 0xffffffff, 0x100, 212 0x9500, 0xffffffff, 0x5, 213 0x9510, 0xffffffff, 0x100, 214 0x9500, 0xffffffff, 0x6, 215 0x9510, 0xffffffff, 0x100, 216 0x9500, 0xffffffff, 0x7, 217 0x9510, 0xffffffff, 0x100, 218 0x9500, 0xffffffff, 0x8, 219 0x9510, 0xffffffff, 0x100, 220 0x9500, 0xffffffff, 0x9, 221 0x9510, 0xffffffff, 0x100, 222 0x9500, 0xffffffff, 0x8000, 223 0x9490, 0xffffffff, 0x0, 224 0x949c, 0xffffffff, 0x100, 225 0x9490, 0xffffffff, 0x1, 226 0x949c, 0xffffffff, 0x100, 227 0x9490, 0xffffffff, 0x2, 228 0x949c, 0xffffffff, 0x100, 229 0x9490, 0xffffffff, 0x3, 230 0x949c, 0xffffffff, 0x100, 231 0x9490, 0xffffffff, 0x4, 232 0x949c, 0xffffffff, 0x100, 233 0x9490, 0xffffffff, 0x5, 234 0x949c, 0xffffffff, 0x100, 235 0x9490, 0xffffffff, 0x6, 236 0x949c, 0xffffffff, 0x100, 237 0x9490, 0xffffffff, 0x7, 238 0x949c, 0xffffffff, 0x100, 239 0x9490, 0xffffffff, 0x8, 240 0x949c, 0xffffffff, 0x100, 241 0x9490, 0xffffffff, 0x9, 242 0x949c, 0xffffffff, 0x100, 243 0x9490, 0xffffffff, 0x8000, 244 0x9604, 0xffffffff, 0x0, 245 0x9654, 0xffffffff, 0x100, 246 0x9604, 0xffffffff, 0x1, 247 0x9654, 0xffffffff, 0x100, 248 0x9604, 0xffffffff, 0x2, 249 0x9654, 0xffffffff, 0x100, 250 0x9604, 0xffffffff, 0x3, 251 0x9654, 0xffffffff, 0x100, 252 0x9604, 0xffffffff, 0x4, 253 0x9654, 0xffffffff, 0x100, 254 0x9604, 0xffffffff, 0x5, 255 0x9654, 0xffffffff, 0x100, 256 0x9604, 0xffffffff, 0x6, 257 0x9654, 0xffffffff, 0x100, 258 0x9604, 0xffffffff, 0x7, 259 0x9654, 0xffffffff, 0x100, 260 0x9604, 0xffffffff, 0x8, 261 0x9654, 0xffffffff, 0x100, 262 0x9604, 0xffffffff, 0x9, 263 0x9654, 0xffffffff, 0x100, 264 0x9604, 0xffffffff, 0x80000000, 265 0x9030, 0xffffffff, 0x100, 266 0x9034, 0xffffffff, 0x100, 267 0x9038, 0xffffffff, 0x100, 268 0x903c, 0xffffffff, 0x100, 269 0x9040, 0xffffffff, 0x100, 270 0xa200, 0xffffffff, 0x100, 271 0xa204, 0xffffffff, 0x100, 272 0xa208, 0xffffffff, 0x100, 273 0xa20c, 0xffffffff, 0x100, 274 0x971c, 0xffffffff, 0x100, 275 0x915c, 0xffffffff, 0x00020001, 276 0x9160, 0xffffffff, 0x00040003, 277 0x916c, 0xffffffff, 0x00060005, 278 0x9170, 0xffffffff, 0x00080007, 279 0x9174, 0xffffffff, 0x000a0009, 280 0x9178, 0xffffffff, 0x000c000b, 281 0x917c, 0xffffffff, 0x000e000d, 282 0x9180, 0xffffffff, 0x0010000f, 283 0x918c, 0xffffffff, 0x00120011, 284 0x9190, 0xffffffff, 0x00140013, 285 0x9194, 0xffffffff, 0x00020001, 286 0x9198, 0xffffffff, 0x00040003, 287 0x919c, 0xffffffff, 0x00060005, 288 0x91a8, 0xffffffff, 0x00080007, 289 0x91ac, 0xffffffff, 0x000a0009, 290 0x91b0, 0xffffffff, 0x000c000b, 291 0x91b4, 0xffffffff, 0x000e000d, 292 0x91b8, 0xffffffff, 0x0010000f, 293 0x91c4, 0xffffffff, 0x00120011, 294 0x91c8, 0xffffffff, 0x00140013, 295 0x91cc, 0xffffffff, 0x00020001, 296 0x91d0, 0xffffffff, 0x00040003, 297 0x91d4, 0xffffffff, 0x00060005, 298 0x91e0, 0xffffffff, 0x00080007, 299 0x91e4, 0xffffffff, 0x000a0009, 300 0x91e8, 0xffffffff, 0x000c000b, 301 0x91ec, 0xffffffff, 0x00020001, 302 0x91f0, 0xffffffff, 0x00040003, 303 0x91f4, 0xffffffff, 0x00060005, 304 0x9200, 0xffffffff, 0x00080007, 305 0x9204, 0xffffffff, 0x000a0009, 306 0x9208, 0xffffffff, 0x000c000b, 307 0x920c, 0xffffffff, 0x000e000d, 308 0x9210, 0xffffffff, 0x0010000f, 309 0x921c, 0xffffffff, 0x00120011, 310 0x9220, 0xffffffff, 0x00140013, 311 0x9224, 0xffffffff, 0x00020001, 312 0x9228, 0xffffffff, 0x00040003, 313 0x922c, 0xffffffff, 0x00060005, 314 0x9238, 0xffffffff, 0x00080007, 315 0x923c, 0xffffffff, 0x000a0009, 316 0x9240, 0xffffffff, 0x000c000b, 317 0x9244, 0xffffffff, 0x000e000d, 318 0x9248, 0xffffffff, 0x0010000f, 319 0x9254, 0xffffffff, 0x00120011, 320 0x9258, 0xffffffff, 0x00140013, 321 0x925c, 0xffffffff, 0x00020001, 322 0x9260, 0xffffffff, 0x00040003, 323 0x9264, 0xffffffff, 0x00060005, 324 0x9270, 0xffffffff, 0x00080007, 325 0x9274, 0xffffffff, 0x000a0009, 326 0x9278, 0xffffffff, 0x000c000b, 327 0x927c, 0xffffffff, 0x000e000d, 328 0x9280, 0xffffffff, 0x0010000f, 329 0x928c, 0xffffffff, 0x00120011, 330 0x9290, 0xffffffff, 0x00140013, 331 0x9294, 0xffffffff, 0x00020001, 332 0x929c, 0xffffffff, 0x00040003, 333 0x92a0, 0xffffffff, 0x00060005, 334 0x92a4, 0xffffffff, 0x00080007 335 }; 336 337 static const u32 rv710_golden_registers[] = 338 { 339 0x3f90, 0x00ff0000, 0x00fc0000, 340 0x9148, 0x00ff0000, 0x00fc0000, 341 0x3f94, 0x00ff0000, 0x00fc0000, 342 0x914c, 0x00ff0000, 0x00fc0000, 343 0xb4c, 0x00000020, 0x00000020, 344 0xa180, 0xffffffff, 0x00003f3f 345 }; 346 347 static const u32 rv710_mgcg_init[] = 348 { 349 0x8bcc, 0xffffffff, 0x13030040, 350 0x5448, 0xffffffff, 0x100, 351 0x55e4, 0xffffffff, 0x100, 352 0x160c, 0xffffffff, 0x100, 353 0x5644, 0xffffffff, 0x100, 354 0xc164, 0xffffffff, 0x100, 355 0x8a18, 0xffffffff, 0x100, 356 0x897c, 0xffffffff, 0x8000100, 357 0x8b28, 0xffffffff, 0x3c000100, 358 0x9144, 0xffffffff, 0x100, 359 0x9a1c, 0xffffffff, 0x10000, 360 0x9a50, 0xffffffff, 0x100, 361 0x9a1c, 0xffffffff, 0x0, 362 0x9870, 0xffffffff, 0x100, 363 0x8d58, 0xffffffff, 0x100, 364 0x9500, 0xffffffff, 0x0, 365 0x9510, 0xffffffff, 0x100, 366 0x9500, 0xffffffff, 0x1, 367 0x9510, 0xffffffff, 0x100, 368 0x9500, 0xffffffff, 0x8000, 369 0x9490, 0xffffffff, 0x0, 370 0x949c, 0xffffffff, 0x100, 371 0x9490, 0xffffffff, 0x1, 372 0x949c, 0xffffffff, 0x100, 373 0x9490, 0xffffffff, 0x8000, 374 0x9604, 0xffffffff, 0x0, 375 0x9654, 0xffffffff, 0x100, 376 0x9604, 0xffffffff, 0x1, 377 0x9654, 0xffffffff, 0x100, 378 0x9604, 0xffffffff, 0x80000000, 379 0x9030, 0xffffffff, 0x100, 380 0x9034, 0xffffffff, 0x100, 381 0x9038, 0xffffffff, 0x100, 382 0x903c, 0xffffffff, 0x100, 383 0x9040, 0xffffffff, 0x100, 384 0xa200, 0xffffffff, 0x100, 385 0xa204, 0xffffffff, 0x100, 386 0xa208, 0xffffffff, 0x100, 387 0xa20c, 0xffffffff, 0x100, 388 0x971c, 0xffffffff, 0x100, 389 0x915c, 0xffffffff, 0x00020001, 390 0x9174, 0xffffffff, 0x00000003, 391 0x9178, 0xffffffff, 0x00050001, 392 0x917c, 0xffffffff, 0x00030002, 393 0x918c, 0xffffffff, 0x00000004, 394 0x9190, 0xffffffff, 0x00070006, 395 0x9194, 0xffffffff, 0x00050001, 396 0x9198, 0xffffffff, 0x00030002, 397 0x91a8, 0xffffffff, 0x00000004, 398 0x91ac, 0xffffffff, 0x00070006, 399 0x91e8, 0xffffffff, 0x00000001, 400 0x9294, 0xffffffff, 0x00000001, 401 0x929c, 0xffffffff, 0x00000002, 402 0x92a0, 0xffffffff, 0x00040003, 403 0x9150, 0xffffffff, 0x4d940000 404 }; 405 406 static const u32 rv730_golden_registers[] = 407 { 408 0x3f90, 0x00ff0000, 0x00f00000, 409 0x9148, 0x00ff0000, 0x00f00000, 410 0x3f94, 0x00ff0000, 0x00f00000, 411 0x914c, 0x00ff0000, 0x00f00000, 412 0x900c, 0xffffffff, 0x003b033f, 413 0xb4c, 0x00000020, 0x00000020, 414 0xa180, 0xffffffff, 0x00003f3f 415 }; 416 417 static const u32 rv730_mgcg_init[] = 418 { 419 0x8bcc, 0xffffffff, 0x130300f9, 420 0x5448, 0xffffffff, 0x100, 421 0x55e4, 0xffffffff, 0x100, 422 0x160c, 0xffffffff, 0x100, 423 0x5644, 0xffffffff, 0x100, 424 0xc164, 0xffffffff, 0x100, 425 0x8a18, 0xffffffff, 0x100, 426 0x897c, 0xffffffff, 0x8000100, 427 0x8b28, 0xffffffff, 0x3c000100, 428 0x9144, 0xffffffff, 0x100, 429 0x9a1c, 0xffffffff, 0x10000, 430 0x9a50, 0xffffffff, 0x100, 431 0x9a1c, 0xffffffff, 0x10001, 432 0x9a50, 0xffffffff, 0x100, 433 0x9a1c, 0xffffffff, 0x0, 434 0x9870, 0xffffffff, 0x100, 435 0x8d58, 0xffffffff, 0x100, 436 0x9500, 0xffffffff, 0x0, 437 0x9510, 0xffffffff, 0x100, 438 0x9500, 0xffffffff, 0x1, 439 0x9510, 0xffffffff, 0x100, 440 0x9500, 0xffffffff, 0x2, 441 0x9510, 0xffffffff, 0x100, 442 0x9500, 0xffffffff, 0x3, 443 0x9510, 0xffffffff, 0x100, 444 0x9500, 0xffffffff, 0x4, 445 0x9510, 0xffffffff, 0x100, 446 0x9500, 0xffffffff, 0x5, 447 0x9510, 0xffffffff, 0x100, 448 0x9500, 0xffffffff, 0x6, 449 0x9510, 0xffffffff, 0x100, 450 0x9500, 0xffffffff, 0x7, 451 0x9510, 0xffffffff, 0x100, 452 0x9500, 0xffffffff, 0x8000, 453 0x9490, 0xffffffff, 0x0, 454 0x949c, 0xffffffff, 0x100, 455 0x9490, 0xffffffff, 0x1, 456 0x949c, 0xffffffff, 0x100, 457 0x9490, 0xffffffff, 0x2, 458 0x949c, 0xffffffff, 0x100, 459 0x9490, 0xffffffff, 0x3, 460 0x949c, 0xffffffff, 0x100, 461 0x9490, 0xffffffff, 0x4, 462 0x949c, 0xffffffff, 0x100, 463 0x9490, 0xffffffff, 0x5, 464 0x949c, 0xffffffff, 0x100, 465 0x9490, 0xffffffff, 0x6, 466 0x949c, 0xffffffff, 0x100, 467 0x9490, 0xffffffff, 0x7, 468 0x949c, 0xffffffff, 0x100, 469 0x9490, 0xffffffff, 0x8000, 470 0x9604, 0xffffffff, 0x0, 471 0x9654, 0xffffffff, 0x100, 472 0x9604, 0xffffffff, 0x1, 473 0x9654, 0xffffffff, 0x100, 474 0x9604, 0xffffffff, 0x2, 475 0x9654, 0xffffffff, 0x100, 476 0x9604, 0xffffffff, 0x3, 477 0x9654, 0xffffffff, 0x100, 478 0x9604, 0xffffffff, 0x4, 479 0x9654, 0xffffffff, 0x100, 480 0x9604, 0xffffffff, 0x5, 481 0x9654, 0xffffffff, 0x100, 482 0x9604, 0xffffffff, 0x6, 483 0x9654, 0xffffffff, 0x100, 484 0x9604, 0xffffffff, 0x7, 485 0x9654, 0xffffffff, 0x100, 486 0x9604, 0xffffffff, 0x80000000, 487 0x9030, 0xffffffff, 0x100, 488 0x9034, 0xffffffff, 0x100, 489 0x9038, 0xffffffff, 0x100, 490 0x903c, 0xffffffff, 0x100, 491 0x9040, 0xffffffff, 0x100, 492 0xa200, 0xffffffff, 0x100, 493 0xa204, 0xffffffff, 0x100, 494 0xa208, 0xffffffff, 0x100, 495 0xa20c, 0xffffffff, 0x100, 496 0x971c, 0xffffffff, 0x100, 497 0x915c, 0xffffffff, 0x00020001, 498 0x916c, 0xffffffff, 0x00040003, 499 0x9170, 0xffffffff, 0x00000005, 500 0x9178, 0xffffffff, 0x00050001, 501 0x917c, 0xffffffff, 0x00030002, 502 0x918c, 0xffffffff, 0x00000004, 503 0x9190, 0xffffffff, 0x00070006, 504 0x9194, 0xffffffff, 0x00050001, 505 0x9198, 0xffffffff, 0x00030002, 506 0x91a8, 0xffffffff, 0x00000004, 507 0x91ac, 0xffffffff, 0x00070006, 508 0x91b0, 0xffffffff, 0x00050001, 509 0x91b4, 0xffffffff, 0x00030002, 510 0x91c4, 0xffffffff, 0x00000004, 511 0x91c8, 0xffffffff, 0x00070006, 512 0x91cc, 0xffffffff, 0x00050001, 513 0x91d0, 0xffffffff, 0x00030002, 514 0x91e0, 0xffffffff, 0x00000004, 515 0x91e4, 0xffffffff, 0x00070006, 516 0x91e8, 0xffffffff, 0x00000001, 517 0x91ec, 0xffffffff, 0x00050001, 518 0x91f0, 0xffffffff, 0x00030002, 519 0x9200, 0xffffffff, 0x00000004, 520 0x9204, 0xffffffff, 0x00070006, 521 0x9208, 0xffffffff, 0x00050001, 522 0x920c, 0xffffffff, 0x00030002, 523 0x921c, 0xffffffff, 0x00000004, 524 0x9220, 0xffffffff, 0x00070006, 525 0x9224, 0xffffffff, 0x00050001, 526 0x9228, 0xffffffff, 0x00030002, 527 0x9238, 0xffffffff, 0x00000004, 528 0x923c, 0xffffffff, 0x00070006, 529 0x9240, 0xffffffff, 0x00050001, 530 0x9244, 0xffffffff, 0x00030002, 531 0x9254, 0xffffffff, 0x00000004, 532 0x9258, 0xffffffff, 0x00070006, 533 0x9294, 0xffffffff, 0x00000001, 534 0x929c, 0xffffffff, 0x00000002, 535 0x92a0, 0xffffffff, 0x00040003, 536 0x92a4, 0xffffffff, 0x00000005 537 }; 538 539 static const u32 rv740_golden_registers[] = 540 { 541 0x88c4, 0xffffffff, 0x00000082, 542 0x28a50, 0xfffffffc, 0x00000004, 543 0x2650, 0x00040000, 0, 544 0x20bc, 0x00040000, 0, 545 0x733c, 0xffffffff, 0x00000002, 546 0x7300, 0xffffffff, 0x001000f0, 547 0x3f90, 0x00ff0000, 0, 548 0x9148, 0x00ff0000, 0, 549 0x3f94, 0x00ff0000, 0, 550 0x914c, 0x00ff0000, 0, 551 0x240c, 0xffffffff, 0x00000380, 552 0x8a14, 0x00000007, 0x00000007, 553 0x8b24, 0xffffffff, 0x00ff0fff, 554 0x28a4c, 0xffffffff, 0x00004000, 555 0xa180, 0xffffffff, 0x00003f3f, 556 0x8d00, 0xffffffff, 0x0e0e003a, 557 0x8d04, 0xffffffff, 0x013a0e2a, 558 0x8c00, 0xffffffff, 0xe400000f, 559 0x8db0, 0xffffffff, 0x98989898, 560 0x8db4, 0xffffffff, 0x98989898, 561 0x8db8, 0xffffffff, 0x98989898, 562 0x8dbc, 0xffffffff, 0x98989898, 563 0x8dc0, 0xffffffff, 0x98989898, 564 0x8dc4, 0xffffffff, 0x98989898, 565 0x8dc8, 0xffffffff, 0x98989898, 566 0x8dcc, 0xffffffff, 0x98989898, 567 0x9058, 0xffffffff, 0x0fffc40f, 568 0x900c, 0xffffffff, 0x003b033f, 569 0x28350, 0xffffffff, 0, 570 0x8cf0, 0x1fffffff, 0x08e00420, 571 0x9508, 0xffffffff, 0x00000002, 572 0x88c4, 0xffffffff, 0x000000c2, 573 0x9698, 0x18000000, 0x18000000 574 }; 575 576 static const u32 rv740_mgcg_init[] = 577 { 578 0x8bcc, 0xffffffff, 0x13030100, 579 0x5448, 0xffffffff, 0x100, 580 0x55e4, 0xffffffff, 0x100, 581 0x160c, 0xffffffff, 0x100, 582 0x5644, 0xffffffff, 0x100, 583 0xc164, 0xffffffff, 0x100, 584 0x8a18, 0xffffffff, 0x100, 585 0x897c, 0xffffffff, 0x100, 586 0x8b28, 0xffffffff, 0x100, 587 0x9144, 0xffffffff, 0x100, 588 0x9a1c, 0xffffffff, 0x10000, 589 0x9a50, 0xffffffff, 0x100, 590 0x9a1c, 0xffffffff, 0x10001, 591 0x9a50, 0xffffffff, 0x100, 592 0x9a1c, 0xffffffff, 0x10002, 593 0x9a50, 0xffffffff, 0x100, 594 0x9a1c, 0xffffffff, 0x10003, 595 0x9a50, 0xffffffff, 0x100, 596 0x9a1c, 0xffffffff, 0x0, 597 0x9870, 0xffffffff, 0x100, 598 0x8d58, 0xffffffff, 0x100, 599 0x9500, 0xffffffff, 0x0, 600 0x9510, 0xffffffff, 0x100, 601 0x9500, 0xffffffff, 0x1, 602 0x9510, 0xffffffff, 0x100, 603 0x9500, 0xffffffff, 0x2, 604 0x9510, 0xffffffff, 0x100, 605 0x9500, 0xffffffff, 0x3, 606 0x9510, 0xffffffff, 0x100, 607 0x9500, 0xffffffff, 0x4, 608 0x9510, 0xffffffff, 0x100, 609 0x9500, 0xffffffff, 0x5, 610 0x9510, 0xffffffff, 0x100, 611 0x9500, 0xffffffff, 0x6, 612 0x9510, 0xffffffff, 0x100, 613 0x9500, 0xffffffff, 0x7, 614 0x9510, 0xffffffff, 0x100, 615 0x9500, 0xffffffff, 0x8000, 616 0x9490, 0xffffffff, 0x0, 617 0x949c, 0xffffffff, 0x100, 618 0x9490, 0xffffffff, 0x1, 619 0x949c, 0xffffffff, 0x100, 620 0x9490, 0xffffffff, 0x2, 621 0x949c, 0xffffffff, 0x100, 622 0x9490, 0xffffffff, 0x3, 623 0x949c, 0xffffffff, 0x100, 624 0x9490, 0xffffffff, 0x4, 625 0x949c, 0xffffffff, 0x100, 626 0x9490, 0xffffffff, 0x5, 627 0x949c, 0xffffffff, 0x100, 628 0x9490, 0xffffffff, 0x6, 629 0x949c, 0xffffffff, 0x100, 630 0x9490, 0xffffffff, 0x7, 631 0x949c, 0xffffffff, 0x100, 632 0x9490, 0xffffffff, 0x8000, 633 0x9604, 0xffffffff, 0x0, 634 0x9654, 0xffffffff, 0x100, 635 0x9604, 0xffffffff, 0x1, 636 0x9654, 0xffffffff, 0x100, 637 0x9604, 0xffffffff, 0x2, 638 0x9654, 0xffffffff, 0x100, 639 0x9604, 0xffffffff, 0x3, 640 0x9654, 0xffffffff, 0x100, 641 0x9604, 0xffffffff, 0x4, 642 0x9654, 0xffffffff, 0x100, 643 0x9604, 0xffffffff, 0x5, 644 0x9654, 0xffffffff, 0x100, 645 0x9604, 0xffffffff, 0x6, 646 0x9654, 0xffffffff, 0x100, 647 0x9604, 0xffffffff, 0x7, 648 0x9654, 0xffffffff, 0x100, 649 0x9604, 0xffffffff, 0x80000000, 650 0x9030, 0xffffffff, 0x100, 651 0x9034, 0xffffffff, 0x100, 652 0x9038, 0xffffffff, 0x100, 653 0x903c, 0xffffffff, 0x100, 654 0x9040, 0xffffffff, 0x100, 655 0xa200, 0xffffffff, 0x100, 656 0xa204, 0xffffffff, 0x100, 657 0xa208, 0xffffffff, 0x100, 658 0xa20c, 0xffffffff, 0x100, 659 0x971c, 0xffffffff, 0x100, 660 0x915c, 0xffffffff, 0x00020001, 661 0x9160, 0xffffffff, 0x00040003, 662 0x916c, 0xffffffff, 0x00060005, 663 0x9170, 0xffffffff, 0x00080007, 664 0x9174, 0xffffffff, 0x000a0009, 665 0x9178, 0xffffffff, 0x000c000b, 666 0x917c, 0xffffffff, 0x000e000d, 667 0x9180, 0xffffffff, 0x0010000f, 668 0x918c, 0xffffffff, 0x00120011, 669 0x9190, 0xffffffff, 0x00140013, 670 0x9194, 0xffffffff, 0x00020001, 671 0x9198, 0xffffffff, 0x00040003, 672 0x919c, 0xffffffff, 0x00060005, 673 0x91a8, 0xffffffff, 0x00080007, 674 0x91ac, 0xffffffff, 0x000a0009, 675 0x91b0, 0xffffffff, 0x000c000b, 676 0x91b4, 0xffffffff, 0x000e000d, 677 0x91b8, 0xffffffff, 0x0010000f, 678 0x91c4, 0xffffffff, 0x00120011, 679 0x91c8, 0xffffffff, 0x00140013, 680 0x91cc, 0xffffffff, 0x00020001, 681 0x91d0, 0xffffffff, 0x00040003, 682 0x91d4, 0xffffffff, 0x00060005, 683 0x91e0, 0xffffffff, 0x00080007, 684 0x91e4, 0xffffffff, 0x000a0009, 685 0x91e8, 0xffffffff, 0x000c000b, 686 0x91ec, 0xffffffff, 0x00020001, 687 0x91f0, 0xffffffff, 0x00040003, 688 0x91f4, 0xffffffff, 0x00060005, 689 0x9200, 0xffffffff, 0x00080007, 690 0x9204, 0xffffffff, 0x000a0009, 691 0x9208, 0xffffffff, 0x000c000b, 692 0x920c, 0xffffffff, 0x000e000d, 693 0x9210, 0xffffffff, 0x0010000f, 694 0x921c, 0xffffffff, 0x00120011, 695 0x9220, 0xffffffff, 0x00140013, 696 0x9224, 0xffffffff, 0x00020001, 697 0x9228, 0xffffffff, 0x00040003, 698 0x922c, 0xffffffff, 0x00060005, 699 0x9238, 0xffffffff, 0x00080007, 700 0x923c, 0xffffffff, 0x000a0009, 701 0x9240, 0xffffffff, 0x000c000b, 702 0x9244, 0xffffffff, 0x000e000d, 703 0x9248, 0xffffffff, 0x0010000f, 704 0x9254, 0xffffffff, 0x00120011, 705 0x9258, 0xffffffff, 0x00140013, 706 0x9294, 0xffffffff, 0x00020001, 707 0x929c, 0xffffffff, 0x00040003, 708 0x92a0, 0xffffffff, 0x00060005, 709 0x92a4, 0xffffffff, 0x00080007 710 }; 711 712 static void rv770_init_golden_registers(struct radeon_device *rdev) 713 { 714 switch (rdev->family) { 715 case CHIP_RV770: 716 radeon_program_register_sequence(rdev, 717 r7xx_golden_registers, 718 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 719 radeon_program_register_sequence(rdev, 720 r7xx_golden_dyn_gpr_registers, 721 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 722 if (rdev->ddev->pci_device == 0x994e) 723 radeon_program_register_sequence(rdev, 724 rv770ce_golden_registers, 725 (const u32)ARRAY_SIZE(rv770ce_golden_registers)); 726 else 727 radeon_program_register_sequence(rdev, 728 rv770_golden_registers, 729 (const u32)ARRAY_SIZE(rv770_golden_registers)); 730 radeon_program_register_sequence(rdev, 731 rv770_mgcg_init, 732 (const u32)ARRAY_SIZE(rv770_mgcg_init)); 733 break; 734 case CHIP_RV730: 735 radeon_program_register_sequence(rdev, 736 r7xx_golden_registers, 737 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 738 radeon_program_register_sequence(rdev, 739 r7xx_golden_dyn_gpr_registers, 740 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 741 radeon_program_register_sequence(rdev, 742 rv730_golden_registers, 743 (const u32)ARRAY_SIZE(rv730_golden_registers)); 744 radeon_program_register_sequence(rdev, 745 rv730_mgcg_init, 746 (const u32)ARRAY_SIZE(rv730_mgcg_init)); 747 break; 748 case CHIP_RV710: 749 radeon_program_register_sequence(rdev, 750 r7xx_golden_registers, 751 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 752 radeon_program_register_sequence(rdev, 753 r7xx_golden_dyn_gpr_registers, 754 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 755 radeon_program_register_sequence(rdev, 756 rv710_golden_registers, 757 (const u32)ARRAY_SIZE(rv710_golden_registers)); 758 radeon_program_register_sequence(rdev, 759 rv710_mgcg_init, 760 (const u32)ARRAY_SIZE(rv710_mgcg_init)); 761 break; 762 case CHIP_RV740: 763 radeon_program_register_sequence(rdev, 764 rv740_golden_registers, 765 (const u32)ARRAY_SIZE(rv740_golden_registers)); 766 radeon_program_register_sequence(rdev, 767 rv740_mgcg_init, 768 (const u32)ARRAY_SIZE(rv740_mgcg_init)); 769 break; 770 default: 771 break; 772 } 773 } 774 775 #define PCIE_BUS_CLK 10000 776 #define TCLK (PCIE_BUS_CLK / 10) 777 778 /** 779 * rv770_get_xclk - get the xclk 780 * 781 * @rdev: radeon_device pointer 782 * 783 * Returns the reference clock used by the gfx engine 784 * (r7xx-cayman). 785 */ 786 u32 rv770_get_xclk(struct radeon_device *rdev) 787 { 788 u32 reference_clock = rdev->clock.spll.reference_freq; 789 u32 tmp = RREG32(CG_CLKPIN_CNTL); 790 791 if (tmp & MUX_TCLK_TO_XCLK) 792 return TCLK; 793 794 if (tmp & XTALIN_DIVIDE) 795 return reference_clock / 4; 796 797 return reference_clock; 798 } 799 800 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 801 { 802 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 803 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 804 int i; 805 806 /* Lock the graphics update lock */ 807 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 808 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 809 810 /* update the scanout addresses */ 811 if (radeon_crtc->crtc_id) { 812 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 813 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 814 } else { 815 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 816 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 817 } 818 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 819 (u32)crtc_base); 820 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 821 (u32)crtc_base); 822 823 /* Wait for update_pending to go high. */ 824 for (i = 0; i < rdev->usec_timeout; i++) { 825 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 826 break; 827 udelay(1); 828 } 829 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 830 831 /* Unlock the lock, so double-buffering can take place inside vblank */ 832 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 833 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 834 835 /* Return current update_pending status: */ 836 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 837 } 838 839 /* get temperature in millidegrees */ 840 int rv770_get_temp(struct radeon_device *rdev) 841 { 842 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 843 ASIC_T_SHIFT; 844 int actual_temp; 845 846 if (temp & 0x400) 847 actual_temp = -256; 848 else if (temp & 0x200) 849 actual_temp = 255; 850 else if (temp & 0x100) { 851 actual_temp = temp & 0x1ff; 852 actual_temp |= ~0x1ff; 853 } else 854 actual_temp = temp & 0xff; 855 856 return (actual_temp * 1000) / 2; 857 } 858 859 void rv770_pm_misc(struct radeon_device *rdev) 860 { 861 int req_ps_idx = rdev->pm.requested_power_state_index; 862 int req_cm_idx = rdev->pm.requested_clock_mode_index; 863 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 864 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 865 866 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 867 /* 0xff01 is a flag rather then an actual voltage */ 868 if (voltage->voltage == 0xff01) 869 return; 870 if (voltage->voltage != rdev->pm.current_vddc) { 871 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 872 rdev->pm.current_vddc = voltage->voltage; 873 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 874 } 875 } 876 } 877 878 /* 879 * GART 880 */ 881 static int rv770_pcie_gart_enable(struct radeon_device *rdev) 882 { 883 u32 tmp; 884 int r, i; 885 886 if (rdev->gart.robj == NULL) { 887 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 888 return -EINVAL; 889 } 890 r = radeon_gart_table_vram_pin(rdev); 891 if (r) 892 return r; 893 radeon_gart_restore(rdev); 894 /* Setup L2 cache */ 895 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 896 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 897 EFFECTIVE_L2_QUEUE_SIZE(7)); 898 WREG32(VM_L2_CNTL2, 0); 899 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 900 /* Setup TLB control */ 901 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 902 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 903 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 904 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 905 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 906 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 907 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 908 if (rdev->family == CHIP_RV740) 909 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 910 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 911 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 912 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 913 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 914 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 915 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 916 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 917 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 918 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 919 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 920 (u32)(rdev->dummy_page.addr >> 12)); 921 for (i = 1; i < 7; i++) 922 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 923 924 r600_pcie_gart_tlb_flush(rdev); 925 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 926 (unsigned)(rdev->mc.gtt_size >> 20), 927 (unsigned long long)rdev->gart.table_addr); 928 rdev->gart.ready = true; 929 return 0; 930 } 931 932 static void rv770_pcie_gart_disable(struct radeon_device *rdev) 933 { 934 u32 tmp; 935 int i; 936 937 /* Disable all tables */ 938 for (i = 0; i < 7; i++) 939 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 940 941 /* Setup L2 cache */ 942 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 943 EFFECTIVE_L2_QUEUE_SIZE(7)); 944 WREG32(VM_L2_CNTL2, 0); 945 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 946 /* Setup TLB control */ 947 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 948 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 949 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 950 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 951 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 952 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 953 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 954 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 955 radeon_gart_table_vram_unpin(rdev); 956 } 957 958 static void rv770_pcie_gart_fini(struct radeon_device *rdev) 959 { 960 radeon_gart_fini(rdev); 961 rv770_pcie_gart_disable(rdev); 962 radeon_gart_table_vram_free(rdev); 963 } 964 965 966 static void rv770_agp_enable(struct radeon_device *rdev) 967 { 968 u32 tmp; 969 int i; 970 971 /* Setup L2 cache */ 972 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 973 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 974 EFFECTIVE_L2_QUEUE_SIZE(7)); 975 WREG32(VM_L2_CNTL2, 0); 976 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 977 /* Setup TLB control */ 978 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 979 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 980 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 981 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 982 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 983 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 984 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 985 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 986 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 987 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 988 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 989 for (i = 0; i < 7; i++) 990 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 991 } 992 993 static void rv770_mc_program(struct radeon_device *rdev) 994 { 995 struct rv515_mc_save save; 996 u32 tmp; 997 int i, j; 998 999 /* Initialize HDP */ 1000 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1001 WREG32((0x2c14 + j), 0x00000000); 1002 WREG32((0x2c18 + j), 0x00000000); 1003 WREG32((0x2c1c + j), 0x00000000); 1004 WREG32((0x2c20 + j), 0x00000000); 1005 WREG32((0x2c24 + j), 0x00000000); 1006 } 1007 /* r7xx hw bug. Read from HDP_DEBUG1 rather 1008 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL 1009 */ 1010 tmp = RREG32(HDP_DEBUG1); 1011 1012 rv515_mc_stop(rdev, &save); 1013 if (r600_mc_wait_for_idle(rdev)) { 1014 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1015 } 1016 /* Lockout access through VGA aperture*/ 1017 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1018 /* Update configuration */ 1019 if (rdev->flags & RADEON_IS_AGP) { 1020 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1021 /* VRAM before AGP */ 1022 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1023 rdev->mc.vram_start >> 12); 1024 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1025 rdev->mc.gtt_end >> 12); 1026 } else { 1027 /* VRAM after AGP */ 1028 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1029 rdev->mc.gtt_start >> 12); 1030 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1031 rdev->mc.vram_end >> 12); 1032 } 1033 } else { 1034 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1035 rdev->mc.vram_start >> 12); 1036 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1037 rdev->mc.vram_end >> 12); 1038 } 1039 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1040 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1041 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1042 WREG32(MC_VM_FB_LOCATION, tmp); 1043 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1044 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1045 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1046 if (rdev->flags & RADEON_IS_AGP) { 1047 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1048 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1049 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1050 } else { 1051 WREG32(MC_VM_AGP_BASE, 0); 1052 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1053 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1054 } 1055 if (r600_mc_wait_for_idle(rdev)) { 1056 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1057 } 1058 rv515_mc_resume(rdev, &save); 1059 /* we need to own VRAM, so turn off the VGA renderer here 1060 * to stop it overwriting our objects */ 1061 rv515_vga_render_disable(rdev); 1062 } 1063 1064 1065 /* 1066 * CP. 1067 */ 1068 void r700_cp_stop(struct radeon_device *rdev) 1069 { 1070 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1071 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1072 WREG32(SCRATCH_UMSK, 0); 1073 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1074 } 1075 1076 static int rv770_cp_load_microcode(struct radeon_device *rdev) 1077 { 1078 const __be32 *fw_data; 1079 int i; 1080 1081 if (!rdev->me_fw || !rdev->pfp_fw) 1082 return -EINVAL; 1083 1084 r700_cp_stop(rdev); 1085 WREG32(CP_RB_CNTL, 1086 #ifdef __BIG_ENDIAN 1087 BUF_SWAP_32BIT | 1088 #endif 1089 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1090 1091 /* Reset cp */ 1092 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1093 RREG32(GRBM_SOFT_RESET); 1094 mdelay(15); 1095 WREG32(GRBM_SOFT_RESET, 0); 1096 1097 fw_data = (const __be32 *)rdev->pfp_fw->data; 1098 WREG32(CP_PFP_UCODE_ADDR, 0); 1099 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 1100 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1101 WREG32(CP_PFP_UCODE_ADDR, 0); 1102 1103 fw_data = (const __be32 *)rdev->me_fw->data; 1104 WREG32(CP_ME_RAM_WADDR, 0); 1105 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 1106 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1107 1108 WREG32(CP_PFP_UCODE_ADDR, 0); 1109 WREG32(CP_ME_RAM_WADDR, 0); 1110 WREG32(CP_ME_RAM_RADDR, 0); 1111 return 0; 1112 } 1113 1114 void r700_cp_fini(struct radeon_device *rdev) 1115 { 1116 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1117 r700_cp_stop(rdev); 1118 radeon_ring_fini(rdev, ring); 1119 radeon_scratch_free(rdev, ring->rptr_save_reg); 1120 } 1121 1122 /* 1123 * Core functions 1124 */ 1125 static void rv770_gpu_init(struct radeon_device *rdev) 1126 { 1127 int i, j, num_qd_pipes; 1128 u32 ta_aux_cntl; 1129 u32 sx_debug_1; 1130 u32 smx_dc_ctl0; 1131 u32 db_debug3; 1132 u32 num_gs_verts_per_thread; 1133 u32 vgt_gs_per_es; 1134 u32 gs_prim_buffer_depth = 0; 1135 u32 sq_ms_fifo_sizes; 1136 u32 sq_config; 1137 u32 sq_thread_resource_mgmt; 1138 u32 hdp_host_path_cntl; 1139 u32 sq_dyn_gpr_size_simd_ab_0; 1140 u32 gb_tiling_config = 0; 1141 u32 cc_rb_backend_disable = 0; 1142 u32 cc_gc_shader_pipe_config = 0; 1143 u32 mc_arb_ramcfg; 1144 u32 db_debug4, tmp; 1145 u32 inactive_pipes, shader_pipe_config; 1146 u32 disabled_rb_mask; 1147 unsigned active_number; 1148 1149 /* setup chip specs */ 1150 rdev->config.rv770.tiling_group_size = 256; 1151 switch (rdev->family) { 1152 case CHIP_RV770: 1153 rdev->config.rv770.max_pipes = 4; 1154 rdev->config.rv770.max_tile_pipes = 8; 1155 rdev->config.rv770.max_simds = 10; 1156 rdev->config.rv770.max_backends = 4; 1157 rdev->config.rv770.max_gprs = 256; 1158 rdev->config.rv770.max_threads = 248; 1159 rdev->config.rv770.max_stack_entries = 512; 1160 rdev->config.rv770.max_hw_contexts = 8; 1161 rdev->config.rv770.max_gs_threads = 16 * 2; 1162 rdev->config.rv770.sx_max_export_size = 128; 1163 rdev->config.rv770.sx_max_export_pos_size = 16; 1164 rdev->config.rv770.sx_max_export_smx_size = 112; 1165 rdev->config.rv770.sq_num_cf_insts = 2; 1166 1167 rdev->config.rv770.sx_num_of_sets = 7; 1168 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 1169 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1170 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1171 break; 1172 case CHIP_RV730: 1173 rdev->config.rv770.max_pipes = 2; 1174 rdev->config.rv770.max_tile_pipes = 4; 1175 rdev->config.rv770.max_simds = 8; 1176 rdev->config.rv770.max_backends = 2; 1177 rdev->config.rv770.max_gprs = 128; 1178 rdev->config.rv770.max_threads = 248; 1179 rdev->config.rv770.max_stack_entries = 256; 1180 rdev->config.rv770.max_hw_contexts = 8; 1181 rdev->config.rv770.max_gs_threads = 16 * 2; 1182 rdev->config.rv770.sx_max_export_size = 256; 1183 rdev->config.rv770.sx_max_export_pos_size = 32; 1184 rdev->config.rv770.sx_max_export_smx_size = 224; 1185 rdev->config.rv770.sq_num_cf_insts = 2; 1186 1187 rdev->config.rv770.sx_num_of_sets = 7; 1188 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 1189 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1190 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1191 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1192 rdev->config.rv770.sx_max_export_pos_size -= 16; 1193 rdev->config.rv770.sx_max_export_smx_size += 16; 1194 } 1195 break; 1196 case CHIP_RV710: 1197 rdev->config.rv770.max_pipes = 2; 1198 rdev->config.rv770.max_tile_pipes = 2; 1199 rdev->config.rv770.max_simds = 2; 1200 rdev->config.rv770.max_backends = 1; 1201 rdev->config.rv770.max_gprs = 256; 1202 rdev->config.rv770.max_threads = 192; 1203 rdev->config.rv770.max_stack_entries = 256; 1204 rdev->config.rv770.max_hw_contexts = 4; 1205 rdev->config.rv770.max_gs_threads = 8 * 2; 1206 rdev->config.rv770.sx_max_export_size = 128; 1207 rdev->config.rv770.sx_max_export_pos_size = 16; 1208 rdev->config.rv770.sx_max_export_smx_size = 112; 1209 rdev->config.rv770.sq_num_cf_insts = 1; 1210 1211 rdev->config.rv770.sx_num_of_sets = 7; 1212 rdev->config.rv770.sc_prim_fifo_size = 0x40; 1213 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1214 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1215 break; 1216 case CHIP_RV740: 1217 rdev->config.rv770.max_pipes = 4; 1218 rdev->config.rv770.max_tile_pipes = 4; 1219 rdev->config.rv770.max_simds = 8; 1220 rdev->config.rv770.max_backends = 4; 1221 rdev->config.rv770.max_gprs = 256; 1222 rdev->config.rv770.max_threads = 248; 1223 rdev->config.rv770.max_stack_entries = 512; 1224 rdev->config.rv770.max_hw_contexts = 8; 1225 rdev->config.rv770.max_gs_threads = 16 * 2; 1226 rdev->config.rv770.sx_max_export_size = 256; 1227 rdev->config.rv770.sx_max_export_pos_size = 32; 1228 rdev->config.rv770.sx_max_export_smx_size = 224; 1229 rdev->config.rv770.sq_num_cf_insts = 2; 1230 1231 rdev->config.rv770.sx_num_of_sets = 7; 1232 rdev->config.rv770.sc_prim_fifo_size = 0x100; 1233 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1234 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1235 1236 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1237 rdev->config.rv770.sx_max_export_pos_size -= 16; 1238 rdev->config.rv770.sx_max_export_smx_size += 16; 1239 } 1240 break; 1241 default: 1242 break; 1243 } 1244 1245 /* Initialize HDP */ 1246 j = 0; 1247 for (i = 0; i < 32; i++) { 1248 WREG32((0x2c14 + j), 0x00000000); 1249 WREG32((0x2c18 + j), 0x00000000); 1250 WREG32((0x2c1c + j), 0x00000000); 1251 WREG32((0x2c20 + j), 0x00000000); 1252 WREG32((0x2c24 + j), 0x00000000); 1253 j += 0x18; 1254 } 1255 1256 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1257 1258 /* setup tiling, simd, pipe config */ 1259 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1260 1261 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 1262 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 1263 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { 1264 if (!(inactive_pipes & tmp)) { 1265 active_number++; 1266 } 1267 tmp <<= 1; 1268 } 1269 if (active_number == 1) { 1270 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); 1271 } else { 1272 WREG32(SPI_CONFIG_CNTL, 0); 1273 } 1274 1275 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1276 tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); 1277 if (tmp < rdev->config.rv770.max_backends) { 1278 rdev->config.rv770.max_backends = tmp; 1279 } 1280 1281 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1282 tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); 1283 if (tmp < rdev->config.rv770.max_pipes) { 1284 rdev->config.rv770.max_pipes = tmp; 1285 } 1286 tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); 1287 if (tmp < rdev->config.rv770.max_simds) { 1288 rdev->config.rv770.max_simds = tmp; 1289 } 1290 1291 switch (rdev->config.rv770.max_tile_pipes) { 1292 case 1: 1293 default: 1294 gb_tiling_config = PIPE_TILING(0); 1295 break; 1296 case 2: 1297 gb_tiling_config = PIPE_TILING(1); 1298 break; 1299 case 4: 1300 gb_tiling_config = PIPE_TILING(2); 1301 break; 1302 case 8: 1303 gb_tiling_config = PIPE_TILING(3); 1304 break; 1305 } 1306 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 1307 1308 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; 1309 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1310 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, 1311 R7XX_MAX_BACKENDS, disabled_rb_mask); 1312 gb_tiling_config |= tmp << 16; 1313 rdev->config.rv770.backend_map = tmp; 1314 1315 if (rdev->family == CHIP_RV770) 1316 gb_tiling_config |= BANK_TILING(1); 1317 else { 1318 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1319 gb_tiling_config |= BANK_TILING(1); 1320 else 1321 gb_tiling_config |= BANK_TILING(0); 1322 } 1323 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 1324 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1325 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 1326 gb_tiling_config |= ROW_TILING(3); 1327 gb_tiling_config |= SAMPLE_SPLIT(3); 1328 } else { 1329 gb_tiling_config |= 1330 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1331 gb_tiling_config |= 1332 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1333 } 1334 1335 gb_tiling_config |= BANK_SWAPS(1); 1336 rdev->config.rv770.tile_config = gb_tiling_config; 1337 1338 WREG32(GB_TILING_CONFIG, gb_tiling_config); 1339 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1340 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1341 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1342 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); 1343 if (rdev->family == CHIP_RV730) { 1344 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1345 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1346 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1347 } 1348 1349 WREG32(CGTS_SYS_TCC_DISABLE, 0); 1350 WREG32(CGTS_TCC_DISABLE, 0); 1351 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 1352 WREG32(CGTS_USER_TCC_DISABLE, 0); 1353 1354 1355 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1356 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 1357 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1358 1359 /* set HW defaults for 3D engine */ 1360 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1361 ROQ_IB2_START(0x2b))); 1362 1363 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 1364 1365 ta_aux_cntl = RREG32(TA_CNTL_AUX); 1366 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); 1367 1368 sx_debug_1 = RREG32(SX_DEBUG_1); 1369 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1370 WREG32(SX_DEBUG_1, sx_debug_1); 1371 1372 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1373 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 1374 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 1375 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1376 1377 if (rdev->family != CHIP_RV740) 1378 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 1379 GS_FLUSH_CTL(4) | 1380 ACK_FLUSH_CTL(3) | 1381 SYNC_FLUSH_CTL)); 1382 1383 if (rdev->family != CHIP_RV770) 1384 WREG32(SMX_SAR_CTL0, 0x00003f3f); 1385 1386 db_debug3 = RREG32(DB_DEBUG3); 1387 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 1388 switch (rdev->family) { 1389 case CHIP_RV770: 1390 case CHIP_RV740: 1391 db_debug3 |= DB_CLK_OFF_DELAY(0x1f); 1392 break; 1393 case CHIP_RV710: 1394 case CHIP_RV730: 1395 default: 1396 db_debug3 |= DB_CLK_OFF_DELAY(2); 1397 break; 1398 } 1399 WREG32(DB_DEBUG3, db_debug3); 1400 1401 if (rdev->family != CHIP_RV770) { 1402 db_debug4 = RREG32(DB_DEBUG4); 1403 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 1404 WREG32(DB_DEBUG4, db_debug4); 1405 } 1406 1407 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 1408 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 1409 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 1410 1411 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 1412 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 1413 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 1414 1415 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1416 1417 WREG32(VGT_NUM_INSTANCES, 1); 1418 1419 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1420 1421 WREG32(CP_PERFMON_CNTL, 0); 1422 1423 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 1424 DONE_FIFO_HIWATER(0xe0) | 1425 ALU_UPDATE_FIFO_HIWATER(0x8)); 1426 switch (rdev->family) { 1427 case CHIP_RV770: 1428 case CHIP_RV730: 1429 case CHIP_RV710: 1430 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 1431 break; 1432 case CHIP_RV740: 1433 default: 1434 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 1435 break; 1436 } 1437 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1438 1439 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1440 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1441 */ 1442 sq_config = RREG32(SQ_CONFIG); 1443 sq_config &= ~(PS_PRIO(3) | 1444 VS_PRIO(3) | 1445 GS_PRIO(3) | 1446 ES_PRIO(3)); 1447 sq_config |= (DX9_CONSTS | 1448 VC_ENABLE | 1449 EXPORT_SRC_C | 1450 PS_PRIO(0) | 1451 VS_PRIO(1) | 1452 GS_PRIO(2) | 1453 ES_PRIO(3)); 1454 if (rdev->family == CHIP_RV710) 1455 /* no vertex cache */ 1456 sq_config &= ~VC_ENABLE; 1457 1458 WREG32(SQ_CONFIG, sq_config); 1459 1460 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1461 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1462 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 1463 1464 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 1465 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 1466 1467 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 1468 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 1469 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 1470 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 1471 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 1472 else 1473 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 1474 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1475 1476 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1477 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1478 1479 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1480 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1481 1482 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1483 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 1484 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1485 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 1486 1487 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1488 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1489 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1490 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1491 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1492 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1493 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1494 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1495 1496 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1497 FORCE_EOV_MAX_REZ_CNT(255))); 1498 1499 if (rdev->family == CHIP_RV710) 1500 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 1501 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1502 else 1503 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 1504 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1505 1506 switch (rdev->family) { 1507 case CHIP_RV770: 1508 case CHIP_RV730: 1509 case CHIP_RV740: 1510 gs_prim_buffer_depth = 384; 1511 break; 1512 case CHIP_RV710: 1513 gs_prim_buffer_depth = 128; 1514 break; 1515 default: 1516 break; 1517 } 1518 1519 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 1520 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1521 /* Max value for this is 256 */ 1522 if (vgt_gs_per_es > 256) 1523 vgt_gs_per_es = 256; 1524 1525 WREG32(VGT_ES_PER_GS, 128); 1526 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 1527 WREG32(VGT_GS_PER_VS, 2); 1528 1529 /* more default values. 2D/3D driver should adjust as needed */ 1530 WREG32(VGT_GS_VERTEX_REUSE, 16); 1531 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1532 WREG32(VGT_STRMOUT_EN, 0); 1533 WREG32(SX_MISC, 0); 1534 WREG32(PA_SC_MODE_CNTL, 0); 1535 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 1536 WREG32(PA_SC_AA_CONFIG, 0); 1537 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 1538 WREG32(PA_SC_LINE_STIPPLE, 0); 1539 WREG32(SPI_INPUT_Z, 0); 1540 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1541 WREG32(CB_COLOR7_FRAG, 0); 1542 1543 /* clear render buffer base addresses */ 1544 WREG32(CB_COLOR0_BASE, 0); 1545 WREG32(CB_COLOR1_BASE, 0); 1546 WREG32(CB_COLOR2_BASE, 0); 1547 WREG32(CB_COLOR3_BASE, 0); 1548 WREG32(CB_COLOR4_BASE, 0); 1549 WREG32(CB_COLOR5_BASE, 0); 1550 WREG32(CB_COLOR6_BASE, 0); 1551 WREG32(CB_COLOR7_BASE, 0); 1552 1553 WREG32(TCP_CNTL, 0); 1554 1555 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1556 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1557 1558 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1559 1560 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1561 NUM_CLIP_SEQ(3))); 1562 WREG32(VC_ENHANCE, 0); 1563 } 1564 1565 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1566 { 1567 u64 size_bf, size_af; 1568 1569 if (mc->mc_vram_size > 0xE0000000) { 1570 /* leave room for at least 512M GTT */ 1571 dev_warn(rdev->dev, "limiting VRAM\n"); 1572 mc->real_vram_size = 0xE0000000; 1573 mc->mc_vram_size = 0xE0000000; 1574 } 1575 if (rdev->flags & RADEON_IS_AGP) { 1576 size_bf = mc->gtt_start; 1577 size_af = mc->mc_mask - mc->gtt_end; 1578 if (size_bf > size_af) { 1579 if (mc->mc_vram_size > size_bf) { 1580 dev_warn(rdev->dev, "limiting VRAM\n"); 1581 mc->real_vram_size = size_bf; 1582 mc->mc_vram_size = size_bf; 1583 } 1584 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1585 } else { 1586 if (mc->mc_vram_size > size_af) { 1587 dev_warn(rdev->dev, "limiting VRAM\n"); 1588 mc->real_vram_size = size_af; 1589 mc->mc_vram_size = size_af; 1590 } 1591 mc->vram_start = mc->gtt_end + 1; 1592 } 1593 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1594 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n", 1595 mc->mc_vram_size >> 20, mc->vram_start, 1596 mc->vram_end, mc->real_vram_size >> 20); 1597 } else { 1598 radeon_vram_location(rdev, &rdev->mc, 0); 1599 rdev->mc.gtt_base_align = 0; 1600 radeon_gtt_location(rdev, mc); 1601 } 1602 } 1603 1604 static int rv770_mc_init(struct radeon_device *rdev) 1605 { 1606 u32 tmp; 1607 int chansize, numchan; 1608 1609 /* Get VRAM informations */ 1610 rdev->mc.vram_is_ddr = true; 1611 tmp = RREG32(MC_ARB_RAMCFG); 1612 if (tmp & CHANSIZE_OVERRIDE) { 1613 chansize = 16; 1614 } else if (tmp & CHANSIZE_MASK) { 1615 chansize = 64; 1616 } else { 1617 chansize = 32; 1618 } 1619 tmp = RREG32(MC_SHARED_CHMAP); 1620 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1621 case 0: 1622 default: 1623 numchan = 1; 1624 break; 1625 case 1: 1626 numchan = 2; 1627 break; 1628 case 2: 1629 numchan = 4; 1630 break; 1631 case 3: 1632 numchan = 8; 1633 break; 1634 } 1635 rdev->mc.vram_width = numchan * chansize; 1636 /* Could aper size report 0 ? */ 1637 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1638 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1639 /* Setup GPU memory space */ 1640 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1641 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1642 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1643 r700_vram_gtt_location(rdev, &rdev->mc); 1644 radeon_update_bandwidth_info(rdev); 1645 1646 return 0; 1647 } 1648 1649 static int rv770_startup(struct radeon_device *rdev) 1650 { 1651 struct radeon_ring *ring; 1652 int r; 1653 1654 /* enable pcie gen2 link */ 1655 rv770_pcie_gen2_enable(rdev); 1656 1657 /* scratch needs to be initialized before MC */ 1658 r = r600_vram_scratch_init(rdev); 1659 if (r) 1660 return r; 1661 1662 rv770_mc_program(rdev); 1663 1664 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1665 r = r600_init_microcode(rdev); 1666 if (r) { 1667 DRM_ERROR("Failed to load firmware!\n"); 1668 return r; 1669 } 1670 } 1671 1672 if (rdev->flags & RADEON_IS_AGP) { 1673 rv770_agp_enable(rdev); 1674 } else { 1675 r = rv770_pcie_gart_enable(rdev); 1676 if (r) 1677 return r; 1678 } 1679 1680 rv770_gpu_init(rdev); 1681 1682 /* allocate wb buffer */ 1683 r = radeon_wb_init(rdev); 1684 if (r) 1685 return r; 1686 1687 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1688 if (r) { 1689 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1690 return r; 1691 } 1692 1693 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 1694 if (r) { 1695 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 1696 return r; 1697 } 1698 1699 r = uvd_v2_2_resume(rdev); 1700 if (!r) { 1701 r = radeon_fence_driver_start_ring(rdev, 1702 R600_RING_TYPE_UVD_INDEX); 1703 if (r) 1704 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); 1705 } 1706 1707 if (r) 1708 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 1709 1710 /* Enable IRQ */ 1711 if (!rdev->irq.installed) { 1712 r = radeon_irq_kms_init(rdev); 1713 if (r) 1714 return r; 1715 } 1716 1717 r = r600_irq_init(rdev); 1718 if (r) { 1719 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1720 radeon_irq_kms_fini(rdev); 1721 return r; 1722 } 1723 r600_irq_set(rdev); 1724 1725 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1726 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 1727 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 1728 RADEON_CP_PACKET2); 1729 if (r) 1730 return r; 1731 1732 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 1733 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 1734 DMA_RB_RPTR, DMA_RB_WPTR, 1735 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 1736 if (r) 1737 return r; 1738 1739 r = rv770_cp_load_microcode(rdev); 1740 if (r) 1741 return r; 1742 r = r600_cp_resume(rdev); 1743 if (r) 1744 return r; 1745 1746 r = r600_dma_resume(rdev); 1747 if (r) 1748 return r; 1749 1750 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 1751 if (ring->ring_size) { 1752 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 1753 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, 1754 RADEON_CP_PACKET2); 1755 if (!r) 1756 r = uvd_v1_0_init(rdev); 1757 1758 if (r) 1759 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 1760 } 1761 1762 r = radeon_ib_pool_init(rdev); 1763 if (r) { 1764 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1765 return r; 1766 } 1767 1768 r = r600_audio_init(rdev); 1769 if (r) { 1770 DRM_ERROR("radeon: audio init failed\n"); 1771 return r; 1772 } 1773 1774 return 0; 1775 } 1776 1777 int rv770_resume(struct radeon_device *rdev) 1778 { 1779 int r; 1780 1781 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1782 * posting will perform necessary task to bring back GPU into good 1783 * shape. 1784 */ 1785 /* post card */ 1786 atom_asic_init(rdev->mode_info.atom_context); 1787 1788 /* init golden registers */ 1789 rv770_init_golden_registers(rdev); 1790 1791 rdev->accel_working = true; 1792 r = rv770_startup(rdev); 1793 if (r) { 1794 DRM_ERROR("r600 startup failed on resume\n"); 1795 rdev->accel_working = false; 1796 return r; 1797 } 1798 1799 return r; 1800 1801 } 1802 1803 int rv770_suspend(struct radeon_device *rdev) 1804 { 1805 r600_audio_fini(rdev); 1806 uvd_v1_0_fini(rdev); 1807 radeon_uvd_suspend(rdev); 1808 r700_cp_stop(rdev); 1809 r600_dma_stop(rdev); 1810 r600_irq_suspend(rdev); 1811 radeon_wb_disable(rdev); 1812 rv770_pcie_gart_disable(rdev); 1813 1814 return 0; 1815 } 1816 1817 /* Plan is to move initialization in that function and use 1818 * helper function so that radeon_device_init pretty much 1819 * do nothing more than calling asic specific function. This 1820 * should also allow to remove a bunch of callback function 1821 * like vram_info. 1822 */ 1823 int rv770_init(struct radeon_device *rdev) 1824 { 1825 int r; 1826 1827 /* Read BIOS */ 1828 if (!radeon_get_bios(rdev)) { 1829 if (ASIC_IS_AVIVO(rdev)) 1830 return -EINVAL; 1831 } 1832 /* Must be an ATOMBIOS */ 1833 if (!rdev->is_atom_bios) { 1834 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1835 return -EINVAL; 1836 } 1837 r = radeon_atombios_init(rdev); 1838 if (r) 1839 return r; 1840 /* Post card if necessary */ 1841 if (!radeon_card_posted(rdev)) { 1842 if (!rdev->bios) { 1843 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1844 return -EINVAL; 1845 } 1846 DRM_INFO("GPU not posted. posting now...\n"); 1847 atom_asic_init(rdev->mode_info.atom_context); 1848 } 1849 /* init golden registers */ 1850 rv770_init_golden_registers(rdev); 1851 /* Initialize scratch registers */ 1852 r600_scratch_init(rdev); 1853 /* Initialize surface registers */ 1854 radeon_surface_init(rdev); 1855 /* Initialize clocks */ 1856 radeon_get_clock_info(rdev->ddev); 1857 /* Fence driver */ 1858 r = radeon_fence_driver_init(rdev); 1859 if (r) 1860 return r; 1861 /* initialize AGP */ 1862 if (rdev->flags & RADEON_IS_AGP) { 1863 r = radeon_agp_init(rdev); 1864 if (r) 1865 radeon_agp_disable(rdev); 1866 } 1867 r = rv770_mc_init(rdev); 1868 if (r) 1869 return r; 1870 /* Memory manager */ 1871 r = radeon_bo_init(rdev); 1872 if (r) 1873 return r; 1874 1875 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 1876 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 1877 1878 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 1879 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 1880 1881 r = radeon_uvd_init(rdev); 1882 if (!r) { 1883 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 1884 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 1885 4096); 1886 } 1887 1888 rdev->ih.ring_obj = NULL; 1889 r600_ih_ring_init(rdev, 64 * 1024); 1890 1891 r = r600_pcie_gart_init(rdev); 1892 if (r) 1893 return r; 1894 1895 rdev->accel_working = true; 1896 r = rv770_startup(rdev); 1897 if (r) { 1898 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1899 r700_cp_fini(rdev); 1900 r600_dma_fini(rdev); 1901 r600_irq_fini(rdev); 1902 radeon_wb_fini(rdev); 1903 radeon_ib_pool_fini(rdev); 1904 radeon_irq_kms_fini(rdev); 1905 rv770_pcie_gart_fini(rdev); 1906 rdev->accel_working = false; 1907 } 1908 1909 return 0; 1910 } 1911 1912 void rv770_fini(struct radeon_device *rdev) 1913 { 1914 r700_cp_fini(rdev); 1915 r600_dma_fini(rdev); 1916 r600_irq_fini(rdev); 1917 radeon_wb_fini(rdev); 1918 radeon_ib_pool_fini(rdev); 1919 radeon_irq_kms_fini(rdev); 1920 rv770_pcie_gart_fini(rdev); 1921 uvd_v1_0_fini(rdev); 1922 radeon_uvd_fini(rdev); 1923 r600_vram_scratch_fini(rdev); 1924 radeon_gem_fini(rdev); 1925 radeon_fence_driver_fini(rdev); 1926 radeon_agp_fini(rdev); 1927 radeon_bo_fini(rdev); 1928 radeon_atombios_fini(rdev); 1929 r600_fini_microcode(rdev); 1930 kfree(rdev->bios); 1931 rdev->bios = NULL; 1932 } 1933 1934 static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 1935 { 1936 u32 link_width_cntl, lanes, speed_cntl, tmp; 1937 u16 link_cntl2; 1938 u32 mask; 1939 int ret; 1940 1941 if (radeon_pcie_gen2 == 0) 1942 return; 1943 1944 if (rdev->flags & RADEON_IS_IGP) 1945 return; 1946 1947 if (!(rdev->flags & RADEON_IS_PCIE)) 1948 return; 1949 1950 /* x2 cards have a special sequence */ 1951 if (ASIC_IS_X2(rdev)) 1952 return; 1953 1954 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 1955 if (ret != 0) 1956 return; 1957 1958 if (!(mask & DRM_PCIE_SPEED_50)) 1959 return; 1960 1961 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 1962 1963 /* advertise upconfig capability */ 1964 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1965 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 1966 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1967 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1968 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 1969 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 1970 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 1971 LC_RECONFIG_ARC_MISSING_ESCAPE); 1972 link_width_cntl |= lanes | LC_RECONFIG_NOW | 1973 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; 1974 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1975 } else { 1976 link_width_cntl |= LC_UPCONFIGURE_DIS; 1977 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1978 } 1979 1980 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1981 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 1982 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 1983 1984 tmp = RREG32(0x541c); 1985 WREG32(0x541c, tmp | 0x8); 1986 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 1987 link_cntl2 = RREG16(0x4088); 1988 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 1989 link_cntl2 |= 0x2; 1990 WREG16(0x4088, link_cntl2); 1991 WREG32(MM_CFGREGS_CNTL, 0); 1992 1993 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1994 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 1995 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 1996 1997 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1998 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 1999 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2000 2001 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2002 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 2003 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2004 2005 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2006 speed_cntl |= LC_GEN2_EN_STRAP; 2007 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2008 2009 } else { 2010 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2011 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 2012 if (1) 2013 link_width_cntl |= LC_UPCONFIGURE_DIS; 2014 else 2015 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2016 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2017 } 2018 } 2019