1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/rv770d.h 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 #ifndef RV770_H 30 #define RV770_H 31 32 #define R7XX_MAX_SH_GPRS 256 33 #define R7XX_MAX_TEMP_GPRS 16 34 #define R7XX_MAX_SH_THREADS 256 35 #define R7XX_MAX_SH_STACK_ENTRIES 4096 36 #define R7XX_MAX_BACKENDS 8 37 #define R7XX_MAX_BACKENDS_MASK 0xff 38 #define R7XX_MAX_SIMDS 16 39 #define R7XX_MAX_SIMDS_MASK 0xffff 40 #define R7XX_MAX_PIPES 8 41 #define R7XX_MAX_PIPES_MASK 0xff 42 43 /* Registers */ 44 #define CB_COLOR0_BASE 0x28040 45 #define CB_COLOR1_BASE 0x28044 46 #define CB_COLOR2_BASE 0x28048 47 #define CB_COLOR3_BASE 0x2804C 48 #define CB_COLOR4_BASE 0x28050 49 #define CB_COLOR5_BASE 0x28054 50 #define CB_COLOR6_BASE 0x28058 51 #define CB_COLOR7_BASE 0x2805C 52 #define CB_COLOR7_FRAG 0x280FC 53 54 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 55 #define CC_RB_BACKEND_DISABLE 0x98F4 56 #define BACKEND_DISABLE(x) ((x) << 16) 57 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 58 59 #define CGTS_SYS_TCC_DISABLE 0x3F90 60 #define CGTS_TCC_DISABLE 0x9148 61 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 62 #define CGTS_USER_TCC_DISABLE 0x914C 63 64 #define CONFIG_MEMSIZE 0x5428 65 66 #define CP_ME_CNTL 0x86D8 67 #define CP_ME_HALT (1<<28) 68 #define CP_PFP_HALT (1<<26) 69 #define CP_ME_RAM_DATA 0xC160 70 #define CP_ME_RAM_RADDR 0xC158 71 #define CP_ME_RAM_WADDR 0xC15C 72 #define CP_MEQ_THRESHOLDS 0x8764 73 #define STQ_SPLIT(x) ((x) << 0) 74 #define CP_PERFMON_CNTL 0x87FC 75 #define CP_PFP_UCODE_ADDR 0xC150 76 #define CP_PFP_UCODE_DATA 0xC154 77 #define CP_QUEUE_THRESHOLDS 0x8760 78 #define ROQ_IB1_START(x) ((x) << 0) 79 #define ROQ_IB2_START(x) ((x) << 8) 80 #define CP_RB_CNTL 0xC104 81 #define RB_BUFSZ(x) ((x) << 0) 82 #define RB_BLKSZ(x) ((x) << 8) 83 #define RB_NO_UPDATE (1 << 27) 84 #define RB_RPTR_WR_ENA (1 << 31) 85 #define BUF_SWAP_32BIT (2 << 16) 86 #define CP_RB_RPTR 0x8700 87 #define CP_RB_RPTR_ADDR 0xC10C 88 #define CP_RB_RPTR_ADDR_HI 0xC110 89 #define CP_RB_RPTR_WR 0xC108 90 #define CP_RB_WPTR 0xC114 91 #define CP_RB_WPTR_ADDR 0xC118 92 #define CP_RB_WPTR_ADDR_HI 0xC11C 93 #define CP_RB_WPTR_DELAY 0x8704 94 #define CP_SEM_WAIT_TIMER 0x85BC 95 96 #define DB_DEBUG3 0x98B0 97 #define DB_CLK_OFF_DELAY(x) ((x) << 11) 98 #define DB_DEBUG4 0x9B8C 99 #define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 100 101 #define DCP_TILING_CONFIG 0x6CA0 102 #define PIPE_TILING(x) ((x) << 1) 103 #define BANK_TILING(x) ((x) << 4) 104 #define GROUP_SIZE(x) ((x) << 6) 105 #define ROW_TILING(x) ((x) << 8) 106 #define BANK_SWAPS(x) ((x) << 11) 107 #define SAMPLE_SPLIT(x) ((x) << 14) 108 #define BACKEND_MAP(x) ((x) << 16) 109 110 #define GB_TILING_CONFIG 0x98F0 111 #define PIPE_TILING__SHIFT 1 112 #define PIPE_TILING__MASK 0x0000000e 113 114 #define DMA_TILING_CONFIG 0x3ec8 115 #define DMA_TILING_CONFIG2 0xd0b8 116 117 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 118 #define INACTIVE_QD_PIPES(x) ((x) << 8) 119 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 120 #define INACTIVE_QD_PIPES_SHIFT 8 121 #define INACTIVE_SIMDS(x) ((x) << 16) 122 #define INACTIVE_SIMDS_MASK 0x00FF0000 123 124 #define GRBM_CNTL 0x8000 125 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 126 #define GRBM_SOFT_RESET 0x8020 127 #define SOFT_RESET_CP (1<<0) 128 #define GRBM_STATUS 0x8010 129 #define CMDFIFO_AVAIL_MASK 0x0000000F 130 #define GUI_ACTIVE (1<<31) 131 #define GRBM_STATUS2 0x8014 132 133 #define CG_CLKPIN_CNTL 0x660 134 # define MUX_TCLK_TO_XCLK (1 << 8) 135 # define XTALIN_DIVIDE (1 << 9) 136 137 #define CG_MULT_THERMAL_STATUS 0x740 138 #define ASIC_T(x) ((x) << 16) 139 #define ASIC_T_MASK 0x3FF0000 140 #define ASIC_T_SHIFT 16 141 142 #define HDP_HOST_PATH_CNTL 0x2C00 143 #define HDP_NONSURFACE_BASE 0x2C04 144 #define HDP_NONSURFACE_INFO 0x2C08 145 #define HDP_NONSURFACE_SIZE 0x2C0C 146 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 147 #define HDP_TILING_CONFIG 0x2F3C 148 #define HDP_DEBUG1 0x2F34 149 150 #define MC_SHARED_CHMAP 0x2004 151 #define NOOFCHAN_SHIFT 12 152 #define NOOFCHAN_MASK 0x00003000 153 #define MC_SHARED_CHREMAP 0x2008 154 155 #define MC_ARB_RAMCFG 0x2760 156 #define NOOFBANK_SHIFT 0 157 #define NOOFBANK_MASK 0x00000003 158 #define NOOFRANK_SHIFT 2 159 #define NOOFRANK_MASK 0x00000004 160 #define NOOFROWS_SHIFT 3 161 #define NOOFROWS_MASK 0x00000038 162 #define NOOFCOLS_SHIFT 6 163 #define NOOFCOLS_MASK 0x000000C0 164 #define CHANSIZE_SHIFT 8 165 #define CHANSIZE_MASK 0x00000100 166 #define BURSTLENGTH_SHIFT 9 167 #define BURSTLENGTH_MASK 0x00000200 168 #define CHANSIZE_OVERRIDE (1 << 11) 169 #define MC_VM_AGP_TOP 0x2028 170 #define MC_VM_AGP_BOT 0x202C 171 #define MC_VM_AGP_BASE 0x2030 172 #define MC_VM_FB_LOCATION 0x2024 173 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 174 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 175 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 176 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 177 #define ENABLE_L1_TLB (1 << 0) 178 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 179 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 180 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 181 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 182 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 183 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 184 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 185 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 186 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 187 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 188 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 189 #define MC_VM_MD_L1_TLB3_CNTL 0x2698 190 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 191 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 192 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 193 194 #define PA_CL_ENHANCE 0x8A14 195 #define CLIP_VTX_REORDER_ENA (1 << 0) 196 #define NUM_CLIP_SEQ(x) ((x) << 1) 197 #define PA_SC_AA_CONFIG 0x28C04 198 #define PA_SC_CLIPRECT_RULE 0x2820C 199 #define PA_SC_EDGERULE 0x28230 200 #define PA_SC_FIFO_SIZE 0x8BCC 201 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 202 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 203 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 204 #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 205 #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 206 #define PA_SC_LINE_STIPPLE 0x28A0C 207 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 208 #define PA_SC_MODE_CNTL 0x28A4C 209 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 210 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 211 212 #define SCRATCH_REG0 0x8500 213 #define SCRATCH_REG1 0x8504 214 #define SCRATCH_REG2 0x8508 215 #define SCRATCH_REG3 0x850C 216 #define SCRATCH_REG4 0x8510 217 #define SCRATCH_REG5 0x8514 218 #define SCRATCH_REG6 0x8518 219 #define SCRATCH_REG7 0x851C 220 #define SCRATCH_UMSK 0x8540 221 #define SCRATCH_ADDR 0x8544 222 223 #define SMX_SAR_CTL0 0xA008 224 #define SMX_DC_CTL0 0xA020 225 #define USE_HASH_FUNCTION (1 << 0) 226 #define CACHE_DEPTH(x) ((x) << 1) 227 #define FLUSH_ALL_ON_EVENT (1 << 10) 228 #define STALL_ON_EVENT (1 << 11) 229 #define SMX_EVENT_CTL 0xA02C 230 #define ES_FLUSH_CTL(x) ((x) << 0) 231 #define GS_FLUSH_CTL(x) ((x) << 3) 232 #define ACK_FLUSH_CTL(x) ((x) << 6) 233 #define SYNC_FLUSH_CTL (1 << 8) 234 235 #define SPI_CONFIG_CNTL 0x9100 236 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 237 #define DISABLE_INTERP_1 (1 << 5) 238 #define SPI_CONFIG_CNTL_1 0x913C 239 #define VTX_DONE_DELAY(x) ((x) << 0) 240 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 241 #define SPI_INPUT_Z 0x286D8 242 #define SPI_PS_IN_CONTROL_0 0x286CC 243 #define NUM_INTERP(x) ((x)<<0) 244 #define POSITION_ENA (1<<8) 245 #define POSITION_CENTROID (1<<9) 246 #define POSITION_ADDR(x) ((x)<<10) 247 #define PARAM_GEN(x) ((x)<<15) 248 #define PARAM_GEN_ADDR(x) ((x)<<19) 249 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 250 #define PERSP_GRADIENT_ENA (1<<28) 251 #define LINEAR_GRADIENT_ENA (1<<29) 252 #define POSITION_SAMPLE (1<<30) 253 #define BARYC_AT_SAMPLE_ENA (1<<31) 254 255 #define SQ_CONFIG 0x8C00 256 #define VC_ENABLE (1 << 0) 257 #define EXPORT_SRC_C (1 << 1) 258 #define DX9_CONSTS (1 << 2) 259 #define ALU_INST_PREFER_VECTOR (1 << 3) 260 #define DX10_CLAMP (1 << 4) 261 #define CLAUSE_SEQ_PRIO(x) ((x) << 8) 262 #define PS_PRIO(x) ((x) << 24) 263 #define VS_PRIO(x) ((x) << 26) 264 #define GS_PRIO(x) ((x) << 28) 265 #define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 266 #define SIMDA_RING0(x) ((x)<<0) 267 #define SIMDA_RING1(x) ((x)<<8) 268 #define SIMDB_RING0(x) ((x)<<16) 269 #define SIMDB_RING1(x) ((x)<<24) 270 #define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 271 #define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 272 #define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 273 #define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 274 #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 275 #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 276 #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 277 #define ES_PRIO(x) ((x) << 30) 278 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 279 #define NUM_PS_GPRS(x) ((x) << 0) 280 #define NUM_VS_GPRS(x) ((x) << 16) 281 #define DYN_GPR_ENABLE (1 << 27) 282 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 283 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 284 #define NUM_GS_GPRS(x) ((x) << 0) 285 #define NUM_ES_GPRS(x) ((x) << 16) 286 #define SQ_MS_FIFO_SIZES 0x8CF0 287 #define CACHE_FIFO_SIZE(x) ((x) << 0) 288 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 289 #define DONE_FIFO_HIWATER(x) ((x) << 16) 290 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 291 #define SQ_STACK_RESOURCE_MGMT_1 0x8C10 292 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 293 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 294 #define SQ_STACK_RESOURCE_MGMT_2 0x8C14 295 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 296 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 297 #define SQ_THREAD_RESOURCE_MGMT 0x8C0C 298 #define NUM_PS_THREADS(x) ((x) << 0) 299 #define NUM_VS_THREADS(x) ((x) << 8) 300 #define NUM_GS_THREADS(x) ((x) << 16) 301 #define NUM_ES_THREADS(x) ((x) << 24) 302 303 #define SX_DEBUG_1 0x9058 304 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 305 #define SX_EXPORT_BUFFER_SIZES 0x900C 306 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 307 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 308 #define SMX_BUFFER_SIZE(x) ((x) << 16) 309 #define SX_MISC 0x28350 310 311 #define TA_CNTL_AUX 0x9508 312 #define DISABLE_CUBE_WRAP (1 << 0) 313 #define DISABLE_CUBE_ANISO (1 << 1) 314 #define SYNC_GRADIENT (1 << 24) 315 #define SYNC_WALKER (1 << 25) 316 #define SYNC_ALIGNER (1 << 26) 317 #define BILINEAR_PRECISION_6_BIT (0 << 31) 318 #define BILINEAR_PRECISION_8_BIT (1 << 31) 319 320 #define TCP_CNTL 0x9610 321 #define TCP_CHAN_STEER 0x9614 322 323 #define VC_ENHANCE 0x9714 324 325 #define VGT_CACHE_INVALIDATION 0x88C4 326 #define CACHE_INVALIDATION(x) ((x)<<0) 327 #define VC_ONLY 0 328 #define TC_ONLY 1 329 #define VC_AND_TC 2 330 #define AUTO_INVLD_EN(x) ((x) << 6) 331 #define NO_AUTO 0 332 #define ES_AUTO 1 333 #define GS_AUTO 2 334 #define ES_AND_GS_AUTO 3 335 #define VGT_ES_PER_GS 0x88CC 336 #define VGT_GS_PER_ES 0x88C8 337 #define VGT_GS_PER_VS 0x88E8 338 #define VGT_GS_VERTEX_REUSE 0x88D4 339 #define VGT_NUM_INSTANCES 0x8974 340 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 341 #define DEALLOC_DIST_MASK 0x0000007F 342 #define VGT_STRMOUT_EN 0x28AB0 343 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 344 #define VTX_REUSE_DEPTH_MASK 0x000000FF 345 346 #define VM_CONTEXT0_CNTL 0x1410 347 #define ENABLE_CONTEXT (1 << 0) 348 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 349 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 350 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 351 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 352 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 353 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 354 #define VM_L2_CNTL 0x1400 355 #define ENABLE_L2_CACHE (1 << 0) 356 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 357 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 358 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 359 #define VM_L2_CNTL2 0x1404 360 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 361 #define INVALIDATE_L2_CACHE (1 << 1) 362 #define VM_L2_CNTL3 0x1408 363 #define BANK_SELECT(x) ((x) << 0) 364 #define CACHE_UPDATE_MODE(x) ((x) << 6) 365 #define VM_L2_STATUS 0x140C 366 #define L2_BUSY (1 << 0) 367 368 #define WAIT_UNTIL 0x8040 369 370 /* async DMA */ 371 #define DMA_RB_RPTR 0xd008 372 #define DMA_RB_WPTR 0xd00c 373 374 /* async DMA packets */ 375 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 376 (((t) & 0x1) << 23) | \ 377 (((s) & 0x1) << 22) | \ 378 (((n) & 0xFFFF) << 0)) 379 /* async DMA Packet types */ 380 #define DMA_PACKET_WRITE 0x2 381 #define DMA_PACKET_COPY 0x3 382 #define DMA_PACKET_INDIRECT_BUFFER 0x4 383 #define DMA_PACKET_SEMAPHORE 0x5 384 #define DMA_PACKET_FENCE 0x6 385 #define DMA_PACKET_TRAP 0x7 386 #define DMA_PACKET_CONSTANT_FILL 0xd 387 #define DMA_PACKET_NOP 0xf 388 389 390 #define SRBM_STATUS 0x0E50 391 392 /* DCE 3.2 HDMI */ 393 #define HDMI_CONTROL 0x7400 394 # define HDMI_KEEPOUT_MODE (1 << 0) 395 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 396 # define HDMI_ERROR_ACK (1 << 8) 397 # define HDMI_ERROR_MASK (1 << 9) 398 #define HDMI_STATUS 0x7404 399 # define HDMI_ACTIVE_AVMUTE (1 << 0) 400 # define HDMI_AUDIO_PACKET_ERROR (1 << 16) 401 # define HDMI_VBI_PACKET_ERROR (1 << 20) 402 #define HDMI_AUDIO_PACKET_CONTROL 0x7408 403 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 404 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 405 #define HDMI_ACR_PACKET_CONTROL 0x740c 406 # define HDMI_ACR_SEND (1 << 0) 407 # define HDMI_ACR_CONT (1 << 1) 408 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 409 # define HDMI_ACR_HW 0 410 # define HDMI_ACR_32 1 411 # define HDMI_ACR_44 2 412 # define HDMI_ACR_48 3 413 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 414 # define HDMI_ACR_AUTO_SEND (1 << 12) 415 #define HDMI_VBI_PACKET_CONTROL 0x7410 416 # define HDMI_NULL_SEND (1 << 0) 417 # define HDMI_GC_SEND (1 << 4) 418 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 419 #define HDMI_INFOFRAME_CONTROL0 0x7414 420 # define HDMI_AVI_INFO_SEND (1 << 0) 421 # define HDMI_AVI_INFO_CONT (1 << 1) 422 # define HDMI_AUDIO_INFO_SEND (1 << 4) 423 # define HDMI_AUDIO_INFO_CONT (1 << 5) 424 # define HDMI_MPEG_INFO_SEND (1 << 8) 425 # define HDMI_MPEG_INFO_CONT (1 << 9) 426 #define HDMI_INFOFRAME_CONTROL1 0x7418 427 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 428 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 429 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 430 #define HDMI_GENERIC_PACKET_CONTROL 0x741c 431 # define HDMI_GENERIC0_SEND (1 << 0) 432 # define HDMI_GENERIC0_CONT (1 << 1) 433 # define HDMI_GENERIC1_SEND (1 << 4) 434 # define HDMI_GENERIC1_CONT (1 << 5) 435 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 436 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 437 #define HDMI_GC 0x7428 438 # define HDMI_GC_AVMUTE (1 << 0) 439 #define AFMT_AUDIO_PACKET_CONTROL2 0x742c 440 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 441 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 442 # define AFMT_60958_CS_SOURCE (1 << 4) 443 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 444 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 445 #define AFMT_AVI_INFO0 0x7454 446 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 447 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 448 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 449 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 450 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 451 # define AFMT_AVI_INFO_Y_RGB 0 452 # define AFMT_AVI_INFO_Y_YCBCR422 1 453 # define AFMT_AVI_INFO_Y_YCBCR444 2 454 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 455 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 456 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 457 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 458 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 459 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 460 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 461 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 462 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 463 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 464 #define AFMT_AVI_INFO1 0x7458 465 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 466 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 467 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 468 #define AFMT_AVI_INFO2 0x745c 469 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 470 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 471 #define AFMT_AVI_INFO3 0x7460 472 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 473 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 474 #define AFMT_MPEG_INFO0 0x7464 475 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 476 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 477 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 478 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 479 #define AFMT_MPEG_INFO1 0x7468 480 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 481 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 482 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 483 #define AFMT_GENERIC0_HDR 0x746c 484 #define AFMT_GENERIC0_0 0x7470 485 #define AFMT_GENERIC0_1 0x7474 486 #define AFMT_GENERIC0_2 0x7478 487 #define AFMT_GENERIC0_3 0x747c 488 #define AFMT_GENERIC0_4 0x7480 489 #define AFMT_GENERIC0_5 0x7484 490 #define AFMT_GENERIC0_6 0x7488 491 #define AFMT_GENERIC1_HDR 0x748c 492 #define AFMT_GENERIC1_0 0x7490 493 #define AFMT_GENERIC1_1 0x7494 494 #define AFMT_GENERIC1_2 0x7498 495 #define AFMT_GENERIC1_3 0x749c 496 #define AFMT_GENERIC1_4 0x74a0 497 #define AFMT_GENERIC1_5 0x74a4 498 #define AFMT_GENERIC1_6 0x74a8 499 #define HDMI_ACR_32_0 0x74ac 500 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 501 #define HDMI_ACR_32_1 0x74b0 502 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 503 #define HDMI_ACR_44_0 0x74b4 504 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 505 #define HDMI_ACR_44_1 0x74b8 506 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 507 #define HDMI_ACR_48_0 0x74bc 508 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 509 #define HDMI_ACR_48_1 0x74c0 510 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 511 #define HDMI_ACR_STATUS_0 0x74c4 512 #define HDMI_ACR_STATUS_1 0x74c8 513 #define AFMT_AUDIO_INFO0 0x74cc 514 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 515 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 516 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 517 #define AFMT_AUDIO_INFO1 0x74d0 518 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 519 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 520 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 521 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 522 #define AFMT_60958_0 0x74d4 523 # define AFMT_60958_CS_A(x) (((x) & 1) << 0) 524 # define AFMT_60958_CS_B(x) (((x) & 1) << 1) 525 # define AFMT_60958_CS_C(x) (((x) & 1) << 2) 526 # define AFMT_60958_CS_D(x) (((x) & 3) << 3) 527 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 528 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 529 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 530 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 531 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 532 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 533 #define AFMT_60958_1 0x74d8 534 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 535 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 536 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 537 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 538 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 539 #define AFMT_AUDIO_CRC_CONTROL 0x74dc 540 # define AFMT_AUDIO_CRC_EN (1 << 0) 541 #define AFMT_RAMP_CONTROL0 0x74e0 542 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 543 # define AFMT_RAMP_DATA_SIGN (1 << 31) 544 #define AFMT_RAMP_CONTROL1 0x74e4 545 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 546 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 547 #define AFMT_RAMP_CONTROL2 0x74e8 548 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 549 #define AFMT_RAMP_CONTROL3 0x74ec 550 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 551 #define AFMT_60958_2 0x74f0 552 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 553 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 554 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 555 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 556 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 557 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 558 #define AFMT_STATUS 0x7600 559 # define AFMT_AUDIO_ENABLE (1 << 4) 560 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 561 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 562 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 563 #define AFMT_AUDIO_PACKET_CONTROL 0x7604 564 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 565 # define AFMT_AUDIO_TEST_EN (1 << 12) 566 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 567 # define AFMT_60958_CS_UPDATE (1 << 26) 568 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 569 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 570 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 571 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 572 #define AFMT_VBI_PACKET_CONTROL 0x7608 573 # define AFMT_GENERIC0_UPDATE (1 << 2) 574 #define AFMT_INFOFRAME_CONTROL0 0x760c 575 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 576 # define AFMT_AUDIO_INFO_UPDATE (1 << 7) 577 # define AFMT_MPEG_INFO_UPDATE (1 << 10) 578 #define AFMT_GENERIC0_7 0x7610 579 /* second instance starts at 0x7800 */ 580 #define HDMI_OFFSET0 (0x7400 - 0x7400) 581 #define HDMI_OFFSET1 (0x7800 - 0x7400) 582 583 /* DCE3.2 ELD audio interface */ 584 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ 585 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ 586 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ 587 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ 588 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ 589 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ 590 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ 591 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ 592 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ 593 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ 594 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ 595 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ 596 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ 597 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ 598 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 599 /* max channels minus one. 7 = 8 channels */ 600 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 601 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 602 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 603 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 604 * bit0 = 32 kHz 605 * bit1 = 44.1 kHz 606 * bit2 = 48 kHz 607 * bit3 = 88.2 kHz 608 * bit4 = 96 kHz 609 * bit5 = 176.4 kHz 610 * bit6 = 192 kHz 611 */ 612 613 #define AZ_HOT_PLUG_CONTROL 0x7300 614 # define AZ_FORCE_CODEC_WAKE (1 << 0) 615 # define PIN0_JACK_DETECTION_ENABLE (1 << 4) 616 # define PIN1_JACK_DETECTION_ENABLE (1 << 5) 617 # define PIN2_JACK_DETECTION_ENABLE (1 << 6) 618 # define PIN3_JACK_DETECTION_ENABLE (1 << 7) 619 # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 620 # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 621 # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 622 # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 623 # define CODEC_HOT_PLUG_ENABLE (1 << 12) 624 # define PIN0_AUDIO_ENABLED (1 << 24) 625 # define PIN1_AUDIO_ENABLED (1 << 25) 626 # define PIN2_AUDIO_ENABLED (1 << 26) 627 # define PIN3_AUDIO_ENABLED (1 << 27) 628 # define AUDIO_ENABLED (1 << 31) 629 630 631 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 632 #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 633 #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 634 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 635 #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 636 #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 637 638 /* PCIE link stuff */ 639 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 640 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 641 # define LC_LINK_WIDTH_SHIFT 0 642 # define LC_LINK_WIDTH_MASK 0x7 643 # define LC_LINK_WIDTH_X0 0 644 # define LC_LINK_WIDTH_X1 1 645 # define LC_LINK_WIDTH_X2 2 646 # define LC_LINK_WIDTH_X4 3 647 # define LC_LINK_WIDTH_X8 4 648 # define LC_LINK_WIDTH_X16 6 649 # define LC_LINK_WIDTH_RD_SHIFT 4 650 # define LC_LINK_WIDTH_RD_MASK 0x70 651 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 652 # define LC_RECONFIG_NOW (1 << 8) 653 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 654 # define LC_RENEGOTIATE_EN (1 << 10) 655 # define LC_SHORT_RECONFIG_EN (1 << 11) 656 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 657 # define LC_UPCONFIGURE_DIS (1 << 13) 658 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 659 # define LC_GEN2_EN_STRAP (1 << 0) 660 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 661 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 662 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 663 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 664 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 665 # define LC_CURRENT_DATA_RATE (1 << 11) 666 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 667 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 668 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 669 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 670 #define MM_CFGREGS_CNTL 0x544c 671 # define MM_WR_TO_CFG_EN (1 << 3) 672 #define LINK_CNTL2 0x88 /* F0 */ 673 # define TARGET_LINK_SPEED_MASK (0xf << 0) 674 # define SELECTABLE_DEEMPHASIS (1 << 6) 675 676 #endif 677