1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 #if 0 /* unused */ 255 static const struct si_dte_data dte_data_tahiti_le = 256 { 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271 }; 272 #endif 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1745 1746 static int si_populate_voltage_value(struct radeon_device *rdev, 1747 const struct atom_voltage_table *table, 1748 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1749 static int si_get_std_voltage_value(struct radeon_device *rdev, 1750 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1751 u16 *std_voltage); 1752 static int si_write_smc_soft_register(struct radeon_device *rdev, 1753 u16 reg_offset, u32 value); 1754 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1755 struct rv7xx_pl *pl, 1756 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1757 static int si_calculate_sclk_params(struct radeon_device *rdev, 1758 u32 engine_clock, 1759 SISLANDS_SMC_SCLK_VALUE *sclk); 1760 1761 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1762 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1763 1764 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1765 { 1766 struct si_power_info *pi = rdev->pm.dpm.priv; 1767 1768 return pi; 1769 } 1770 1771 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1772 u16 v, s32 t, u32 ileakage, u32 *leakage) 1773 { 1774 s64 kt, kv, leakage_w, i_leakage, vddc; 1775 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1776 s64 tmp; 1777 1778 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1779 vddc = div64_s64(drm_int2fixp(v), 1000); 1780 temperature = div64_s64(drm_int2fixp(t), 1000); 1781 1782 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1783 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1784 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1785 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1786 t_ref = drm_int2fixp(coeff->t_ref); 1787 1788 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1789 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1790 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1791 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1792 1793 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1794 1795 *leakage = drm_fixp2int(leakage_w * 1000); 1796 } 1797 1798 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1799 const struct ni_leakage_coeffients *coeff, 1800 u16 v, 1801 s32 t, 1802 u32 i_leakage, 1803 u32 *leakage) 1804 { 1805 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1806 } 1807 1808 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1809 const u32 fixed_kt, u16 v, 1810 u32 ileakage, u32 *leakage) 1811 { 1812 s64 kt, kv, leakage_w, i_leakage, vddc; 1813 1814 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1815 vddc = div64_s64(drm_int2fixp(v), 1000); 1816 1817 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1818 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1819 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1820 1821 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1822 1823 *leakage = drm_fixp2int(leakage_w * 1000); 1824 } 1825 1826 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1827 const struct ni_leakage_coeffients *coeff, 1828 const u32 fixed_kt, 1829 u16 v, 1830 u32 i_leakage, 1831 u32 *leakage) 1832 { 1833 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1834 } 1835 1836 1837 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1838 struct si_dte_data *dte_data) 1839 { 1840 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1841 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1842 u32 k = dte_data->k; 1843 u32 t_max = dte_data->max_t; 1844 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1845 u32 t_0 = dte_data->t0; 1846 u32 i; 1847 1848 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1849 dte_data->tdep_count = 3; 1850 1851 for (i = 0; i < k; i++) { 1852 dte_data->r[i] = 1853 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1854 (p_limit2 * (u32)100); 1855 } 1856 1857 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1858 1859 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1860 dte_data->tdep_r[i] = dte_data->r[4]; 1861 } 1862 } else { 1863 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1864 } 1865 } 1866 1867 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1868 { 1869 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1870 struct si_power_info *si_pi = si_get_pi(rdev); 1871 bool update_dte_from_pl2 = false; 1872 1873 if (rdev->family == CHIP_TAHITI) { 1874 si_pi->cac_weights = cac_weights_tahiti; 1875 si_pi->lcac_config = lcac_tahiti; 1876 si_pi->cac_override = cac_override_tahiti; 1877 si_pi->powertune_data = &powertune_data_tahiti; 1878 si_pi->dte_data = dte_data_tahiti; 1879 1880 switch (rdev->pdev->device) { 1881 case 0x6798: 1882 si_pi->dte_data.enable_dte_by_default = true; 1883 break; 1884 case 0x6799: 1885 si_pi->dte_data = dte_data_new_zealand; 1886 break; 1887 case 0x6790: 1888 case 0x6791: 1889 case 0x6792: 1890 case 0x679E: 1891 si_pi->dte_data = dte_data_aruba_pro; 1892 update_dte_from_pl2 = true; 1893 break; 1894 case 0x679B: 1895 si_pi->dte_data = dte_data_malta; 1896 update_dte_from_pl2 = true; 1897 break; 1898 case 0x679A: 1899 si_pi->dte_data = dte_data_tahiti_pro; 1900 update_dte_from_pl2 = true; 1901 break; 1902 default: 1903 if (si_pi->dte_data.enable_dte_by_default == true) 1904 DRM_ERROR("DTE is not enabled!\n"); 1905 break; 1906 } 1907 } else if (rdev->family == CHIP_PITCAIRN) { 1908 switch (rdev->pdev->device) { 1909 case 0x6810: 1910 case 0x6818: 1911 si_pi->cac_weights = cac_weights_pitcairn; 1912 si_pi->lcac_config = lcac_pitcairn; 1913 si_pi->cac_override = cac_override_pitcairn; 1914 si_pi->powertune_data = &powertune_data_pitcairn; 1915 si_pi->dte_data = dte_data_curacao_xt; 1916 update_dte_from_pl2 = true; 1917 break; 1918 case 0x6819: 1919 case 0x6811: 1920 si_pi->cac_weights = cac_weights_pitcairn; 1921 si_pi->lcac_config = lcac_pitcairn; 1922 si_pi->cac_override = cac_override_pitcairn; 1923 si_pi->powertune_data = &powertune_data_pitcairn; 1924 si_pi->dte_data = dte_data_curacao_pro; 1925 update_dte_from_pl2 = true; 1926 break; 1927 case 0x6800: 1928 case 0x6806: 1929 si_pi->cac_weights = cac_weights_pitcairn; 1930 si_pi->lcac_config = lcac_pitcairn; 1931 si_pi->cac_override = cac_override_pitcairn; 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1933 si_pi->dte_data = dte_data_neptune_xt; 1934 update_dte_from_pl2 = true; 1935 break; 1936 default: 1937 si_pi->cac_weights = cac_weights_pitcairn; 1938 si_pi->lcac_config = lcac_pitcairn; 1939 si_pi->cac_override = cac_override_pitcairn; 1940 si_pi->powertune_data = &powertune_data_pitcairn; 1941 si_pi->dte_data = dte_data_pitcairn; 1942 break; 1943 } 1944 } else if (rdev->family == CHIP_VERDE) { 1945 si_pi->lcac_config = lcac_cape_verde; 1946 si_pi->cac_override = cac_override_cape_verde; 1947 si_pi->powertune_data = &powertune_data_cape_verde; 1948 1949 switch (rdev->pdev->device) { 1950 case 0x683B: 1951 case 0x683F: 1952 case 0x6829: 1953 case 0x6835: 1954 si_pi->cac_weights = cac_weights_cape_verde_pro; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x682C: 1958 si_pi->cac_weights = cac_weights_cape_verde_pro; 1959 si_pi->dte_data = dte_data_sun_xt; 1960 break; 1961 case 0x6825: 1962 case 0x6827: 1963 si_pi->cac_weights = cac_weights_heathrow; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x6824: 1967 case 0x682D: 1968 si_pi->cac_weights = cac_weights_chelsea_xt; 1969 si_pi->dte_data = dte_data_cape_verde; 1970 break; 1971 case 0x682F: 1972 si_pi->cac_weights = cac_weights_chelsea_pro; 1973 si_pi->dte_data = dte_data_cape_verde; 1974 break; 1975 case 0x6820: 1976 si_pi->cac_weights = cac_weights_heathrow; 1977 si_pi->dte_data = dte_data_venus_xtx; 1978 break; 1979 case 0x6821: 1980 si_pi->cac_weights = cac_weights_heathrow; 1981 si_pi->dte_data = dte_data_venus_xt; 1982 break; 1983 case 0x6823: 1984 case 0x682B: 1985 case 0x6822: 1986 case 0x682A: 1987 si_pi->cac_weights = cac_weights_chelsea_pro; 1988 si_pi->dte_data = dte_data_venus_pro; 1989 break; 1990 default: 1991 si_pi->cac_weights = cac_weights_cape_verde; 1992 si_pi->dte_data = dte_data_cape_verde; 1993 break; 1994 } 1995 } else if (rdev->family == CHIP_OLAND) { 1996 switch (rdev->pdev->device) { 1997 case 0x6601: 1998 case 0x6621: 1999 case 0x6603: 2000 case 0x6605: 2001 si_pi->cac_weights = cac_weights_mars_pro; 2002 si_pi->lcac_config = lcac_mars_pro; 2003 si_pi->cac_override = cac_override_oland; 2004 si_pi->powertune_data = &powertune_data_mars_pro; 2005 si_pi->dte_data = dte_data_mars_pro; 2006 update_dte_from_pl2 = true; 2007 break; 2008 case 0x6600: 2009 case 0x6606: 2010 case 0x6620: 2011 case 0x6604: 2012 si_pi->cac_weights = cac_weights_mars_xt; 2013 si_pi->lcac_config = lcac_mars_pro; 2014 si_pi->cac_override = cac_override_oland; 2015 si_pi->powertune_data = &powertune_data_mars_pro; 2016 si_pi->dte_data = dte_data_mars_pro; 2017 update_dte_from_pl2 = true; 2018 break; 2019 case 0x6611: 2020 case 0x6613: 2021 case 0x6608: 2022 si_pi->cac_weights = cac_weights_oland_pro; 2023 si_pi->lcac_config = lcac_mars_pro; 2024 si_pi->cac_override = cac_override_oland; 2025 si_pi->powertune_data = &powertune_data_mars_pro; 2026 si_pi->dte_data = dte_data_mars_pro; 2027 update_dte_from_pl2 = true; 2028 break; 2029 case 0x6610: 2030 si_pi->cac_weights = cac_weights_oland_xt; 2031 si_pi->lcac_config = lcac_mars_pro; 2032 si_pi->cac_override = cac_override_oland; 2033 si_pi->powertune_data = &powertune_data_mars_pro; 2034 si_pi->dte_data = dte_data_mars_pro; 2035 update_dte_from_pl2 = true; 2036 break; 2037 default: 2038 si_pi->cac_weights = cac_weights_oland; 2039 si_pi->lcac_config = lcac_oland; 2040 si_pi->cac_override = cac_override_oland; 2041 si_pi->powertune_data = &powertune_data_oland; 2042 si_pi->dte_data = dte_data_oland; 2043 break; 2044 } 2045 } else if (rdev->family == CHIP_HAINAN) { 2046 si_pi->cac_weights = cac_weights_hainan; 2047 si_pi->lcac_config = lcac_oland; 2048 si_pi->cac_override = cac_override_oland; 2049 si_pi->powertune_data = &powertune_data_hainan; 2050 si_pi->dte_data = dte_data_sun_xt; 2051 update_dte_from_pl2 = true; 2052 } else { 2053 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2054 return; 2055 } 2056 2057 ni_pi->enable_power_containment = false; 2058 ni_pi->enable_cac = false; 2059 ni_pi->enable_sq_ramping = false; 2060 si_pi->enable_dte = false; 2061 2062 if (si_pi->powertune_data->enable_powertune_by_default) { 2063 ni_pi->enable_power_containment= true; 2064 ni_pi->enable_cac = true; 2065 if (si_pi->dte_data.enable_dte_by_default) { 2066 si_pi->enable_dte = true; 2067 if (update_dte_from_pl2) 2068 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2069 2070 } 2071 ni_pi->enable_sq_ramping = true; 2072 } 2073 2074 ni_pi->driver_calculate_cac_leakage = true; 2075 ni_pi->cac_configuration_required = true; 2076 2077 if (ni_pi->cac_configuration_required) { 2078 ni_pi->support_cac_long_term_average = true; 2079 si_pi->dyn_powertune_data.l2_lta_window_size = 2080 si_pi->powertune_data->l2_lta_window_size_default; 2081 si_pi->dyn_powertune_data.lts_truncate = 2082 si_pi->powertune_data->lts_truncate_default; 2083 } else { 2084 ni_pi->support_cac_long_term_average = false; 2085 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2086 si_pi->dyn_powertune_data.lts_truncate = 0; 2087 } 2088 2089 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2090 } 2091 2092 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2093 { 2094 return 1; 2095 } 2096 2097 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2098 { 2099 u32 xclk; 2100 u32 wintime; 2101 u32 cac_window; 2102 u32 cac_window_size; 2103 2104 xclk = radeon_get_xclk(rdev); 2105 2106 if (xclk == 0) 2107 return 0; 2108 2109 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2110 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2111 2112 wintime = (cac_window_size * 100) / xclk; 2113 2114 return wintime; 2115 } 2116 2117 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2118 { 2119 return power_in_watts; 2120 } 2121 2122 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2123 bool adjust_polarity, 2124 u32 tdp_adjustment, 2125 u32 *tdp_limit, 2126 u32 *near_tdp_limit) 2127 { 2128 u32 adjustment_delta, max_tdp_limit; 2129 2130 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2131 return -EINVAL; 2132 2133 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2134 2135 if (adjust_polarity) { 2136 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2138 } else { 2139 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2140 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2141 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2142 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2143 else 2144 *near_tdp_limit = 0; 2145 } 2146 2147 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2148 return -EINVAL; 2149 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2150 return -EINVAL; 2151 2152 return 0; 2153 } 2154 2155 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2156 struct radeon_ps *radeon_state) 2157 { 2158 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2159 struct si_power_info *si_pi = si_get_pi(rdev); 2160 2161 if (ni_pi->enable_power_containment) { 2162 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2163 PP_SIslands_PAPMParameters *papm_parm; 2164 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2165 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2166 u32 tdp_limit; 2167 u32 near_tdp_limit; 2168 int ret; 2169 2170 if (scaling_factor == 0) 2171 return -EINVAL; 2172 2173 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2174 2175 ret = si_calculate_adjusted_tdp_limits(rdev, 2176 false, /* ??? */ 2177 rdev->pm.dpm.tdp_adjustment, 2178 &tdp_limit, 2179 &near_tdp_limit); 2180 if (ret) 2181 return ret; 2182 2183 smc_table->dpm2Params.TDPLimit = 2184 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2185 smc_table->dpm2Params.NearTDPLimit = 2186 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2187 smc_table->dpm2Params.SafePowerLimit = 2188 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2189 2190 ret = si_copy_bytes_to_smc(rdev, 2191 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2192 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2193 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2194 sizeof(u32) * 3, 2195 si_pi->sram_end); 2196 if (ret) 2197 return ret; 2198 2199 if (si_pi->enable_ppm) { 2200 papm_parm = &si_pi->papm_parm; 2201 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2202 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2203 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2204 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2205 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2206 papm_parm->PlatformPowerLimit = 0xffffffff; 2207 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2208 2209 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2210 (u8 *)papm_parm, 2211 sizeof(PP_SIslands_PAPMParameters), 2212 si_pi->sram_end); 2213 if (ret) 2214 return ret; 2215 } 2216 } 2217 return 0; 2218 } 2219 2220 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2221 struct radeon_ps *radeon_state) 2222 { 2223 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2224 struct si_power_info *si_pi = si_get_pi(rdev); 2225 2226 if (ni_pi->enable_power_containment) { 2227 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2228 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2229 int ret; 2230 2231 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2232 2233 smc_table->dpm2Params.NearTDPLimit = 2234 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2235 smc_table->dpm2Params.SafePowerLimit = 2236 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2237 2238 ret = si_copy_bytes_to_smc(rdev, 2239 (si_pi->state_table_start + 2240 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2241 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2242 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2243 sizeof(u32) * 2, 2244 si_pi->sram_end); 2245 if (ret) 2246 return ret; 2247 } 2248 2249 return 0; 2250 } 2251 2252 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2253 const u16 prev_std_vddc, 2254 const u16 curr_std_vddc) 2255 { 2256 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2257 u64 prev_vddc = (u64)prev_std_vddc; 2258 u64 curr_vddc = (u64)curr_std_vddc; 2259 u64 pwr_efficiency_ratio, n, d; 2260 2261 if ((prev_vddc == 0) || (curr_vddc == 0)) 2262 return 0; 2263 2264 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2265 d = prev_vddc * prev_vddc; 2266 pwr_efficiency_ratio = div64_u64(n, d); 2267 2268 if (pwr_efficiency_ratio > (u64)0xFFFF) 2269 return 0; 2270 2271 return (u16)pwr_efficiency_ratio; 2272 } 2273 2274 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2275 struct radeon_ps *radeon_state) 2276 { 2277 struct si_power_info *si_pi = si_get_pi(rdev); 2278 2279 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2280 radeon_state->vclk && radeon_state->dclk) 2281 return true; 2282 2283 return false; 2284 } 2285 2286 static int si_populate_power_containment_values(struct radeon_device *rdev, 2287 struct radeon_ps *radeon_state, 2288 SISLANDS_SMC_SWSTATE *smc_state) 2289 { 2290 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2291 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2292 struct ni_ps *state = ni_get_ps(radeon_state); 2293 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2294 u32 prev_sclk; 2295 u32 max_sclk; 2296 u32 min_sclk; 2297 u16 prev_std_vddc; 2298 u16 curr_std_vddc; 2299 int i; 2300 u16 pwr_efficiency_ratio; 2301 u8 max_ps_percent; 2302 bool disable_uvd_power_tune; 2303 int ret; 2304 2305 if (ni_pi->enable_power_containment == false) 2306 return 0; 2307 2308 if (state->performance_level_count == 0) 2309 return -EINVAL; 2310 2311 if (smc_state->levelCount != state->performance_level_count) 2312 return -EINVAL; 2313 2314 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2315 2316 smc_state->levels[0].dpm2.MaxPS = 0; 2317 smc_state->levels[0].dpm2.NearTDPDec = 0; 2318 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2319 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2320 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2321 2322 for (i = 1; i < state->performance_level_count; i++) { 2323 prev_sclk = state->performance_levels[i-1].sclk; 2324 max_sclk = state->performance_levels[i].sclk; 2325 if (i == 1) 2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2327 else 2328 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2329 2330 if (prev_sclk > max_sclk) 2331 return -EINVAL; 2332 2333 if ((max_ps_percent == 0) || 2334 (prev_sclk == max_sclk) || 2335 disable_uvd_power_tune) { 2336 min_sclk = max_sclk; 2337 } else if (i == 1) { 2338 min_sclk = prev_sclk; 2339 } else { 2340 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2341 } 2342 2343 if (min_sclk < state->performance_levels[0].sclk) 2344 min_sclk = state->performance_levels[0].sclk; 2345 2346 if (min_sclk == 0) 2347 return -EINVAL; 2348 2349 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2350 state->performance_levels[i-1].vddc, &vddc); 2351 if (ret) 2352 return ret; 2353 2354 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2359 state->performance_levels[i].vddc, &vddc); 2360 if (ret) 2361 return ret; 2362 2363 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2364 if (ret) 2365 return ret; 2366 2367 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2368 prev_std_vddc, curr_std_vddc); 2369 2370 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2371 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2372 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2373 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2374 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2375 } 2376 2377 return 0; 2378 } 2379 2380 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2381 struct radeon_ps *radeon_state, 2382 SISLANDS_SMC_SWSTATE *smc_state) 2383 { 2384 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2385 struct ni_ps *state = ni_get_ps(radeon_state); 2386 u32 sq_power_throttle, sq_power_throttle2; 2387 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2388 int i; 2389 2390 if (state->performance_level_count == 0) 2391 return -EINVAL; 2392 2393 if (smc_state->levelCount != state->performance_level_count) 2394 return -EINVAL; 2395 2396 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2397 return -EINVAL; 2398 2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2403 enable_sq_ramping = false; 2404 2405 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2406 enable_sq_ramping = false; 2407 2408 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2409 enable_sq_ramping = false; 2410 2411 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2412 enable_sq_ramping = false; 2413 2414 for (i = 0; i < state->performance_level_count; i++) { 2415 sq_power_throttle = 0; 2416 sq_power_throttle2 = 0; 2417 2418 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2419 enable_sq_ramping) { 2420 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2421 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2422 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2423 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2424 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2425 } else { 2426 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2427 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2428 } 2429 2430 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2431 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2432 } 2433 2434 return 0; 2435 } 2436 2437 static int si_enable_power_containment(struct radeon_device *rdev, 2438 struct radeon_ps *radeon_new_state, 2439 bool enable) 2440 { 2441 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2442 PPSMC_Result smc_result; 2443 int ret = 0; 2444 2445 if (ni_pi->enable_power_containment) { 2446 if (enable) { 2447 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2448 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2449 if (smc_result != PPSMC_Result_OK) { 2450 ret = -EINVAL; 2451 ni_pi->pc_enabled = false; 2452 } else { 2453 ni_pi->pc_enabled = true; 2454 } 2455 } 2456 } else { 2457 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2458 if (smc_result != PPSMC_Result_OK) 2459 ret = -EINVAL; 2460 ni_pi->pc_enabled = false; 2461 } 2462 } 2463 2464 return ret; 2465 } 2466 2467 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2468 { 2469 struct si_power_info *si_pi = si_get_pi(rdev); 2470 int ret = 0; 2471 struct si_dte_data *dte_data = &si_pi->dte_data; 2472 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2473 u32 table_size; 2474 u8 tdep_count; 2475 u32 i; 2476 2477 if (dte_data == NULL) 2478 si_pi->enable_dte = false; 2479 2480 if (si_pi->enable_dte == false) 2481 return 0; 2482 2483 if (dte_data->k <= 0) 2484 return -EINVAL; 2485 2486 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2487 if (dte_tables == NULL) { 2488 si_pi->enable_dte = false; 2489 return -ENOMEM; 2490 } 2491 2492 table_size = dte_data->k; 2493 2494 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2495 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2496 2497 tdep_count = dte_data->tdep_count; 2498 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2499 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2500 2501 dte_tables->K = cpu_to_be32(table_size); 2502 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2503 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2504 dte_tables->WindowSize = dte_data->window_size; 2505 dte_tables->temp_select = dte_data->temp_select; 2506 dte_tables->DTE_mode = dte_data->dte_mode; 2507 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2508 2509 if (tdep_count > 0) 2510 table_size--; 2511 2512 for (i = 0; i < table_size; i++) { 2513 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2514 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2515 } 2516 2517 dte_tables->Tdep_count = tdep_count; 2518 2519 for (i = 0; i < (u32)tdep_count; i++) { 2520 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2521 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2522 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2523 } 2524 2525 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2526 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2527 kfree(dte_tables); 2528 2529 return ret; 2530 } 2531 2532 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2533 u16 *max, u16 *min) 2534 { 2535 struct si_power_info *si_pi = si_get_pi(rdev); 2536 struct radeon_cac_leakage_table *table = 2537 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2538 u32 i; 2539 u32 v0_loadline; 2540 2541 2542 if (table == NULL) 2543 return -EINVAL; 2544 2545 *max = 0; 2546 *min = 0xFFFF; 2547 2548 for (i = 0; i < table->count; i++) { 2549 if (table->entries[i].vddc > *max) 2550 *max = table->entries[i].vddc; 2551 if (table->entries[i].vddc < *min) 2552 *min = table->entries[i].vddc; 2553 } 2554 2555 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2556 return -EINVAL; 2557 2558 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2559 2560 if (v0_loadline > 0xFFFFUL) 2561 return -EINVAL; 2562 2563 *min = (u16)v0_loadline; 2564 2565 if ((*min > *max) || (*max == 0) || (*min == 0)) 2566 return -EINVAL; 2567 2568 return 0; 2569 } 2570 2571 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2572 { 2573 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2574 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2575 } 2576 2577 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2578 PP_SIslands_CacConfig *cac_tables, 2579 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2580 u16 t0, u16 t_step) 2581 { 2582 struct si_power_info *si_pi = si_get_pi(rdev); 2583 u32 leakage; 2584 unsigned int i, j; 2585 s32 t; 2586 u32 smc_leakage; 2587 u32 scaling_factor; 2588 u16 voltage; 2589 2590 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2591 2592 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2593 t = (1000 * (i * t_step + t0)); 2594 2595 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2596 voltage = vddc_max - (vddc_step * j); 2597 2598 si_calculate_leakage_for_v_and_t(rdev, 2599 &si_pi->powertune_data->leakage_coefficients, 2600 voltage, 2601 t, 2602 si_pi->dyn_powertune_data.cac_leakage, 2603 &leakage); 2604 2605 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2606 2607 if (smc_leakage > 0xFFFF) 2608 smc_leakage = 0xFFFF; 2609 2610 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2611 cpu_to_be16((u16)smc_leakage); 2612 } 2613 } 2614 return 0; 2615 } 2616 2617 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2618 PP_SIslands_CacConfig *cac_tables, 2619 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2620 { 2621 struct si_power_info *si_pi = si_get_pi(rdev); 2622 u32 leakage; 2623 unsigned int i, j; 2624 u32 smc_leakage; 2625 u32 scaling_factor; 2626 u16 voltage; 2627 2628 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2629 2630 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2631 voltage = vddc_max - (vddc_step * j); 2632 2633 si_calculate_leakage_for_v(rdev, 2634 &si_pi->powertune_data->leakage_coefficients, 2635 si_pi->powertune_data->fixed_kt, 2636 voltage, 2637 si_pi->dyn_powertune_data.cac_leakage, 2638 &leakage); 2639 2640 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2641 2642 if (smc_leakage > 0xFFFF) 2643 smc_leakage = 0xFFFF; 2644 2645 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2646 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2647 cpu_to_be16((u16)smc_leakage); 2648 } 2649 return 0; 2650 } 2651 2652 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2653 { 2654 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2655 struct si_power_info *si_pi = si_get_pi(rdev); 2656 PP_SIslands_CacConfig *cac_tables = NULL; 2657 u16 vddc_max, vddc_min, vddc_step; 2658 u16 t0, t_step; 2659 u32 load_line_slope, reg; 2660 int ret = 0; 2661 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2662 2663 if (ni_pi->enable_cac == false) 2664 return 0; 2665 2666 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2667 if (!cac_tables) 2668 return -ENOMEM; 2669 2670 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2671 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2672 WREG32(CG_CAC_CTRL, reg); 2673 2674 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2675 si_pi->dyn_powertune_data.dc_pwr_value = 2676 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2677 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2678 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2679 2680 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2681 2682 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2683 if (ret) 2684 goto done_free; 2685 2686 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2687 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2688 t_step = 4; 2689 t0 = 60; 2690 2691 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2692 ret = si_init_dte_leakage_table(rdev, cac_tables, 2693 vddc_max, vddc_min, vddc_step, 2694 t0, t_step); 2695 else 2696 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2697 vddc_max, vddc_min, vddc_step); 2698 if (ret) 2699 goto done_free; 2700 2701 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2702 2703 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2704 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2705 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2706 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2707 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2708 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2709 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2710 cac_tables->calculation_repeats = cpu_to_be32(2); 2711 cac_tables->dc_cac = cpu_to_be32(0); 2712 cac_tables->log2_PG_LKG_SCALE = 12; 2713 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2714 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2715 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2716 2717 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2718 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2719 2720 if (ret) 2721 goto done_free; 2722 2723 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2724 2725 done_free: 2726 if (ret) { 2727 ni_pi->enable_cac = false; 2728 ni_pi->enable_power_containment = false; 2729 } 2730 2731 kfree(cac_tables); 2732 2733 return 0; 2734 } 2735 2736 static int si_program_cac_config_registers(struct radeon_device *rdev, 2737 const struct si_cac_config_reg *cac_config_regs) 2738 { 2739 const struct si_cac_config_reg *config_regs = cac_config_regs; 2740 u32 data = 0, offset; 2741 2742 if (!config_regs) 2743 return -EINVAL; 2744 2745 while (config_regs->offset != 0xFFFFFFFF) { 2746 switch (config_regs->type) { 2747 case SISLANDS_CACCONFIG_CGIND: 2748 offset = SMC_CG_IND_START + config_regs->offset; 2749 if (offset < SMC_CG_IND_END) 2750 data = RREG32_SMC(offset); 2751 break; 2752 default: 2753 data = RREG32(config_regs->offset << 2); 2754 break; 2755 } 2756 2757 data &= ~config_regs->mask; 2758 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2759 2760 switch (config_regs->type) { 2761 case SISLANDS_CACCONFIG_CGIND: 2762 offset = SMC_CG_IND_START + config_regs->offset; 2763 if (offset < SMC_CG_IND_END) 2764 WREG32_SMC(offset, data); 2765 break; 2766 default: 2767 WREG32(config_regs->offset << 2, data); 2768 break; 2769 } 2770 config_regs++; 2771 } 2772 return 0; 2773 } 2774 2775 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2776 { 2777 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2778 struct si_power_info *si_pi = si_get_pi(rdev); 2779 int ret; 2780 2781 if ((ni_pi->enable_cac == false) || 2782 (ni_pi->cac_configuration_required == false)) 2783 return 0; 2784 2785 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2786 if (ret) 2787 return ret; 2788 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2789 if (ret) 2790 return ret; 2791 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2792 if (ret) 2793 return ret; 2794 2795 return 0; 2796 } 2797 2798 static int si_enable_smc_cac(struct radeon_device *rdev, 2799 struct radeon_ps *radeon_new_state, 2800 bool enable) 2801 { 2802 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2803 struct si_power_info *si_pi = si_get_pi(rdev); 2804 PPSMC_Result smc_result; 2805 int ret = 0; 2806 2807 if (ni_pi->enable_cac) { 2808 if (enable) { 2809 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2810 if (ni_pi->support_cac_long_term_average) { 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2812 if (smc_result != PPSMC_Result_OK) 2813 ni_pi->support_cac_long_term_average = false; 2814 } 2815 2816 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2817 if (smc_result != PPSMC_Result_OK) { 2818 ret = -EINVAL; 2819 ni_pi->cac_enabled = false; 2820 } else { 2821 ni_pi->cac_enabled = true; 2822 } 2823 2824 if (si_pi->enable_dte) { 2825 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2826 if (smc_result != PPSMC_Result_OK) 2827 ret = -EINVAL; 2828 } 2829 } 2830 } else if (ni_pi->cac_enabled) { 2831 if (si_pi->enable_dte) 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2833 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2835 2836 ni_pi->cac_enabled = false; 2837 2838 if (ni_pi->support_cac_long_term_average) 2839 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2840 } 2841 } 2842 return ret; 2843 } 2844 2845 static int si_init_smc_spll_table(struct radeon_device *rdev) 2846 { 2847 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2848 struct si_power_info *si_pi = si_get_pi(rdev); 2849 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2850 SISLANDS_SMC_SCLK_VALUE sclk_params; 2851 u32 fb_div, p_div; 2852 u32 clk_s, clk_v; 2853 u32 sclk = 0; 2854 int ret = 0; 2855 u32 tmp; 2856 int i; 2857 2858 if (si_pi->spll_table_start == 0) 2859 return -EINVAL; 2860 2861 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2862 if (spll_table == NULL) 2863 return -ENOMEM; 2864 2865 for (i = 0; i < 256; i++) { 2866 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2867 if (ret) 2868 break; 2869 2870 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2871 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2872 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2873 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2874 2875 fb_div &= ~0x00001FFF; 2876 fb_div >>= 1; 2877 clk_v >>= 6; 2878 2879 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2880 ret = -EINVAL; 2881 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2882 ret = -EINVAL; 2883 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2884 ret = -EINVAL; 2885 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2886 ret = -EINVAL; 2887 2888 if (ret) 2889 break; 2890 2891 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2892 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2893 spll_table->freq[i] = cpu_to_be32(tmp); 2894 2895 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2896 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2897 spll_table->ss[i] = cpu_to_be32(tmp); 2898 2899 sclk += 512; 2900 } 2901 2902 2903 if (!ret) 2904 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2905 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2906 si_pi->sram_end); 2907 2908 if (ret) 2909 ni_pi->enable_power_containment = false; 2910 2911 kfree(spll_table); 2912 2913 return ret; 2914 } 2915 2916 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2917 u16 vce_voltage) 2918 { 2919 u16 highest_leakage = 0; 2920 struct si_power_info *si_pi = si_get_pi(rdev); 2921 int i; 2922 2923 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2924 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2925 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2926 } 2927 2928 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2929 return highest_leakage; 2930 2931 return vce_voltage; 2932 } 2933 2934 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2935 u32 evclk, u32 ecclk, u16 *voltage) 2936 { 2937 u32 i; 2938 int ret = -EINVAL; 2939 struct radeon_vce_clock_voltage_dependency_table *table = 2940 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2941 2942 if (((evclk == 0) && (ecclk == 0)) || 2943 (table && (table->count == 0))) { 2944 *voltage = 0; 2945 return 0; 2946 } 2947 2948 for (i = 0; i < table->count; i++) { 2949 if ((evclk <= table->entries[i].evclk) && 2950 (ecclk <= table->entries[i].ecclk)) { 2951 *voltage = table->entries[i].v; 2952 ret = 0; 2953 break; 2954 } 2955 } 2956 2957 /* if no match return the highest voltage */ 2958 if (ret) 2959 *voltage = table->entries[table->count - 1].v; 2960 2961 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2962 2963 return ret; 2964 } 2965 2966 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2967 struct radeon_ps *rps) 2968 { 2969 struct ni_ps *ps = ni_get_ps(rps); 2970 struct radeon_clock_and_voltage_limits *max_limits; 2971 bool disable_mclk_switching = false; 2972 bool disable_sclk_switching = false; 2973 u32 mclk, sclk; 2974 u16 vddc, vddci, min_vce_voltage = 0; 2975 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2976 u32 max_sclk = 0, max_mclk = 0; 2977 int i; 2978 2979 if (rdev->family == CHIP_HAINAN) { 2980 if ((rdev->pdev->revision == 0x81) || 2981 (rdev->pdev->revision == 0x83) || 2982 (rdev->pdev->revision == 0xC3) || 2983 (rdev->pdev->device == 0x6664) || 2984 (rdev->pdev->device == 0x6665) || 2985 (rdev->pdev->device == 0x6667)) { 2986 max_sclk = 75000; 2987 } 2988 } else if (rdev->family == CHIP_OLAND) { 2989 if ((rdev->pdev->revision == 0xC7) || 2990 (rdev->pdev->revision == 0x80) || 2991 (rdev->pdev->revision == 0x81) || 2992 (rdev->pdev->revision == 0x83) || 2993 (rdev->pdev->revision == 0x87) || 2994 (rdev->pdev->device == 0x6604) || 2995 (rdev->pdev->device == 0x6605)) { 2996 max_sclk = 75000; 2997 } 2998 } 2999 3000 if (rps->vce_active) { 3001 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3002 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3003 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3004 &min_vce_voltage); 3005 } else { 3006 rps->evclk = 0; 3007 rps->ecclk = 0; 3008 } 3009 3010 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3011 ni_dpm_vblank_too_short(rdev)) 3012 disable_mclk_switching = true; 3013 3014 if (rps->vclk || rps->dclk) { 3015 disable_mclk_switching = true; 3016 disable_sclk_switching = true; 3017 } 3018 3019 if (rdev->pm.dpm.ac_power) 3020 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3021 else 3022 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3023 3024 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3025 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3026 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3027 } 3028 if (rdev->pm.dpm.ac_power == false) { 3029 for (i = 0; i < ps->performance_level_count; i++) { 3030 if (ps->performance_levels[i].mclk > max_limits->mclk) 3031 ps->performance_levels[i].mclk = max_limits->mclk; 3032 if (ps->performance_levels[i].sclk > max_limits->sclk) 3033 ps->performance_levels[i].sclk = max_limits->sclk; 3034 if (ps->performance_levels[i].vddc > max_limits->vddc) 3035 ps->performance_levels[i].vddc = max_limits->vddc; 3036 if (ps->performance_levels[i].vddci > max_limits->vddci) 3037 ps->performance_levels[i].vddci = max_limits->vddci; 3038 } 3039 } 3040 3041 /* limit clocks to max supported clocks based on voltage dependency tables */ 3042 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3043 &max_sclk_vddc); 3044 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3045 &max_mclk_vddci); 3046 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3047 &max_mclk_vddc); 3048 3049 for (i = 0; i < ps->performance_level_count; i++) { 3050 if (max_sclk_vddc) { 3051 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3052 ps->performance_levels[i].sclk = max_sclk_vddc; 3053 } 3054 if (max_mclk_vddci) { 3055 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3056 ps->performance_levels[i].mclk = max_mclk_vddci; 3057 } 3058 if (max_mclk_vddc) { 3059 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3060 ps->performance_levels[i].mclk = max_mclk_vddc; 3061 } 3062 if (max_mclk) { 3063 if (ps->performance_levels[i].mclk > max_mclk) 3064 ps->performance_levels[i].mclk = max_mclk; 3065 } 3066 if (max_sclk) { 3067 if (ps->performance_levels[i].sclk > max_sclk) 3068 ps->performance_levels[i].sclk = max_sclk; 3069 } 3070 } 3071 3072 /* XXX validate the min clocks required for display */ 3073 3074 if (disable_mclk_switching) { 3075 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3076 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3077 } else { 3078 mclk = ps->performance_levels[0].mclk; 3079 vddci = ps->performance_levels[0].vddci; 3080 } 3081 3082 if (disable_sclk_switching) { 3083 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3084 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3085 } else { 3086 sclk = ps->performance_levels[0].sclk; 3087 vddc = ps->performance_levels[0].vddc; 3088 } 3089 3090 if (rps->vce_active) { 3091 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3092 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3093 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3094 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3095 } 3096 3097 /* adjusted low state */ 3098 ps->performance_levels[0].sclk = sclk; 3099 ps->performance_levels[0].mclk = mclk; 3100 ps->performance_levels[0].vddc = vddc; 3101 ps->performance_levels[0].vddci = vddci; 3102 3103 if (disable_sclk_switching) { 3104 sclk = ps->performance_levels[0].sclk; 3105 for (i = 1; i < ps->performance_level_count; i++) { 3106 if (sclk < ps->performance_levels[i].sclk) 3107 sclk = ps->performance_levels[i].sclk; 3108 } 3109 for (i = 0; i < ps->performance_level_count; i++) { 3110 ps->performance_levels[i].sclk = sclk; 3111 ps->performance_levels[i].vddc = vddc; 3112 } 3113 } else { 3114 for (i = 1; i < ps->performance_level_count; i++) { 3115 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3116 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3117 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3118 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3119 } 3120 } 3121 3122 if (disable_mclk_switching) { 3123 mclk = ps->performance_levels[0].mclk; 3124 for (i = 1; i < ps->performance_level_count; i++) { 3125 if (mclk < ps->performance_levels[i].mclk) 3126 mclk = ps->performance_levels[i].mclk; 3127 } 3128 for (i = 0; i < ps->performance_level_count; i++) { 3129 ps->performance_levels[i].mclk = mclk; 3130 ps->performance_levels[i].vddci = vddci; 3131 } 3132 } else { 3133 for (i = 1; i < ps->performance_level_count; i++) { 3134 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3135 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3136 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3137 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3138 } 3139 } 3140 3141 for (i = 0; i < ps->performance_level_count; i++) 3142 btc_adjust_clock_combinations(rdev, max_limits, 3143 &ps->performance_levels[i]); 3144 3145 for (i = 0; i < ps->performance_level_count; i++) { 3146 if (ps->performance_levels[i].vddc < min_vce_voltage) 3147 ps->performance_levels[i].vddc = min_vce_voltage; 3148 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3149 ps->performance_levels[i].sclk, 3150 max_limits->vddc, &ps->performance_levels[i].vddc); 3151 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3152 ps->performance_levels[i].mclk, 3153 max_limits->vddci, &ps->performance_levels[i].vddci); 3154 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3155 ps->performance_levels[i].mclk, 3156 max_limits->vddc, &ps->performance_levels[i].vddc); 3157 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3158 rdev->clock.current_dispclk, 3159 max_limits->vddc, &ps->performance_levels[i].vddc); 3160 } 3161 3162 for (i = 0; i < ps->performance_level_count; i++) { 3163 btc_apply_voltage_delta_rules(rdev, 3164 max_limits->vddc, max_limits->vddci, 3165 &ps->performance_levels[i].vddc, 3166 &ps->performance_levels[i].vddci); 3167 } 3168 3169 ps->dc_compatible = true; 3170 for (i = 0; i < ps->performance_level_count; i++) { 3171 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3172 ps->dc_compatible = false; 3173 } 3174 } 3175 3176 #if 0 3177 static int si_read_smc_soft_register(struct radeon_device *rdev, 3178 u16 reg_offset, u32 *value) 3179 { 3180 struct si_power_info *si_pi = si_get_pi(rdev); 3181 3182 return si_read_smc_sram_dword(rdev, 3183 si_pi->soft_regs_start + reg_offset, value, 3184 si_pi->sram_end); 3185 } 3186 #endif 3187 3188 static int si_write_smc_soft_register(struct radeon_device *rdev, 3189 u16 reg_offset, u32 value) 3190 { 3191 struct si_power_info *si_pi = si_get_pi(rdev); 3192 3193 return si_write_smc_sram_dword(rdev, 3194 si_pi->soft_regs_start + reg_offset, 3195 value, si_pi->sram_end); 3196 } 3197 3198 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3199 { 3200 bool ret = false; 3201 u32 tmp, width, row, column, bank, density; 3202 bool is_memory_gddr5, is_special; 3203 3204 tmp = RREG32(MC_SEQ_MISC0); 3205 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3206 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3207 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3208 3209 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3210 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3211 3212 tmp = RREG32(MC_ARB_RAMCFG); 3213 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3214 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3215 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3216 3217 density = (1 << (row + column - 20 + bank)) * width; 3218 3219 if ((rdev->pdev->device == 0x6819) && 3220 is_memory_gddr5 && is_special && (density == 0x400)) 3221 ret = true; 3222 3223 return ret; 3224 } 3225 3226 static void si_get_leakage_vddc(struct radeon_device *rdev) 3227 { 3228 struct si_power_info *si_pi = si_get_pi(rdev); 3229 u16 vddc, count = 0; 3230 int i, ret; 3231 3232 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3233 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3234 3235 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3236 si_pi->leakage_voltage.entries[count].voltage = vddc; 3237 si_pi->leakage_voltage.entries[count].leakage_index = 3238 SISLANDS_LEAKAGE_INDEX0 + i; 3239 count++; 3240 } 3241 } 3242 si_pi->leakage_voltage.count = count; 3243 } 3244 3245 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3246 u32 index, u16 *leakage_voltage) 3247 { 3248 struct si_power_info *si_pi = si_get_pi(rdev); 3249 int i; 3250 3251 if (leakage_voltage == NULL) 3252 return -EINVAL; 3253 3254 if ((index & 0xff00) != 0xff00) 3255 return -EINVAL; 3256 3257 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3258 return -EINVAL; 3259 3260 if (index < SISLANDS_LEAKAGE_INDEX0) 3261 return -EINVAL; 3262 3263 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3264 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3265 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3266 return 0; 3267 } 3268 } 3269 return -EAGAIN; 3270 } 3271 3272 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3273 { 3274 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3275 bool want_thermal_protection; 3276 enum radeon_dpm_event_src dpm_event_src; 3277 3278 switch (sources) { 3279 case 0: 3280 default: 3281 want_thermal_protection = false; 3282 break; 3283 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3284 want_thermal_protection = true; 3285 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3286 break; 3287 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3288 want_thermal_protection = true; 3289 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3290 break; 3291 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3292 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3293 want_thermal_protection = true; 3294 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3295 break; 3296 } 3297 3298 if (want_thermal_protection) { 3299 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3300 if (pi->thermal_protection) 3301 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3302 } else { 3303 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3304 } 3305 } 3306 3307 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3308 enum radeon_dpm_auto_throttle_src source, 3309 bool enable) 3310 { 3311 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3312 3313 if (enable) { 3314 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3315 pi->active_auto_throttle_sources |= 1 << source; 3316 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3317 } 3318 } else { 3319 if (pi->active_auto_throttle_sources & (1 << source)) { 3320 pi->active_auto_throttle_sources &= ~(1 << source); 3321 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3322 } 3323 } 3324 } 3325 3326 static void si_start_dpm(struct radeon_device *rdev) 3327 { 3328 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3329 } 3330 3331 static void si_stop_dpm(struct radeon_device *rdev) 3332 { 3333 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3334 } 3335 3336 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3337 { 3338 if (enable) 3339 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3340 else 3341 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3342 3343 } 3344 3345 #if 0 3346 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3347 u32 thermal_level) 3348 { 3349 PPSMC_Result ret; 3350 3351 if (thermal_level == 0) { 3352 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3353 if (ret == PPSMC_Result_OK) 3354 return 0; 3355 else 3356 return -EINVAL; 3357 } 3358 return 0; 3359 } 3360 3361 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3362 { 3363 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3364 } 3365 #endif 3366 3367 #if 0 3368 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3369 { 3370 if (ac_power) 3371 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3372 0 : -EINVAL; 3373 3374 return 0; 3375 } 3376 #endif 3377 3378 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3379 PPSMC_Msg msg, u32 parameter) 3380 { 3381 WREG32(SMC_SCRATCH0, parameter); 3382 return si_send_msg_to_smc(rdev, msg); 3383 } 3384 3385 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3386 { 3387 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3388 return -EINVAL; 3389 3390 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3391 0 : -EINVAL; 3392 } 3393 3394 int si_dpm_force_performance_level(struct radeon_device *rdev, 3395 enum radeon_dpm_forced_level level) 3396 { 3397 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3398 struct ni_ps *ps = ni_get_ps(rps); 3399 u32 levels = ps->performance_level_count; 3400 3401 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3402 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3403 return -EINVAL; 3404 3405 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3406 return -EINVAL; 3407 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3408 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3409 return -EINVAL; 3410 3411 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3412 return -EINVAL; 3413 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3414 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3415 return -EINVAL; 3416 3417 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3418 return -EINVAL; 3419 } 3420 3421 rdev->pm.dpm.forced_level = level; 3422 3423 return 0; 3424 } 3425 3426 #if 0 3427 static int si_set_boot_state(struct radeon_device *rdev) 3428 { 3429 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3430 0 : -EINVAL; 3431 } 3432 #endif 3433 3434 static int si_set_sw_state(struct radeon_device *rdev) 3435 { 3436 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3437 0 : -EINVAL; 3438 } 3439 3440 static int si_halt_smc(struct radeon_device *rdev) 3441 { 3442 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3443 return -EINVAL; 3444 3445 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3446 0 : -EINVAL; 3447 } 3448 3449 static int si_resume_smc(struct radeon_device *rdev) 3450 { 3451 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3452 return -EINVAL; 3453 3454 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3455 0 : -EINVAL; 3456 } 3457 3458 static void si_dpm_start_smc(struct radeon_device *rdev) 3459 { 3460 si_program_jump_on_start(rdev); 3461 si_start_smc(rdev); 3462 si_start_smc_clock(rdev); 3463 } 3464 3465 static void si_dpm_stop_smc(struct radeon_device *rdev) 3466 { 3467 si_reset_smc(rdev); 3468 si_stop_smc_clock(rdev); 3469 } 3470 3471 static int si_process_firmware_header(struct radeon_device *rdev) 3472 { 3473 struct si_power_info *si_pi = si_get_pi(rdev); 3474 u32 tmp; 3475 int ret; 3476 3477 ret = si_read_smc_sram_dword(rdev, 3478 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3479 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3480 &tmp, si_pi->sram_end); 3481 if (ret) 3482 return ret; 3483 3484 si_pi->state_table_start = tmp; 3485 3486 ret = si_read_smc_sram_dword(rdev, 3487 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3488 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3489 &tmp, si_pi->sram_end); 3490 if (ret) 3491 return ret; 3492 3493 si_pi->soft_regs_start = tmp; 3494 3495 ret = si_read_smc_sram_dword(rdev, 3496 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3497 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3498 &tmp, si_pi->sram_end); 3499 if (ret) 3500 return ret; 3501 3502 si_pi->mc_reg_table_start = tmp; 3503 3504 ret = si_read_smc_sram_dword(rdev, 3505 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3506 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3507 &tmp, si_pi->sram_end); 3508 if (ret) 3509 return ret; 3510 3511 si_pi->fan_table_start = tmp; 3512 3513 ret = si_read_smc_sram_dword(rdev, 3514 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3515 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3516 &tmp, si_pi->sram_end); 3517 if (ret) 3518 return ret; 3519 3520 si_pi->arb_table_start = tmp; 3521 3522 ret = si_read_smc_sram_dword(rdev, 3523 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3524 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3525 &tmp, si_pi->sram_end); 3526 if (ret) 3527 return ret; 3528 3529 si_pi->cac_table_start = tmp; 3530 3531 ret = si_read_smc_sram_dword(rdev, 3532 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3533 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3534 &tmp, si_pi->sram_end); 3535 if (ret) 3536 return ret; 3537 3538 si_pi->dte_table_start = tmp; 3539 3540 ret = si_read_smc_sram_dword(rdev, 3541 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3542 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3543 &tmp, si_pi->sram_end); 3544 if (ret) 3545 return ret; 3546 3547 si_pi->spll_table_start = tmp; 3548 3549 ret = si_read_smc_sram_dword(rdev, 3550 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3551 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3552 &tmp, si_pi->sram_end); 3553 if (ret) 3554 return ret; 3555 3556 si_pi->papm_cfg_table_start = tmp; 3557 3558 return ret; 3559 } 3560 3561 static void si_read_clock_registers(struct radeon_device *rdev) 3562 { 3563 struct si_power_info *si_pi = si_get_pi(rdev); 3564 3565 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3566 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3567 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3568 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3569 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3570 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3571 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3572 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3573 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3574 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3575 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3576 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3577 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3578 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3579 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3580 } 3581 3582 static void si_enable_thermal_protection(struct radeon_device *rdev, 3583 bool enable) 3584 { 3585 if (enable) 3586 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3587 else 3588 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3589 } 3590 3591 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3592 { 3593 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3594 } 3595 3596 #if 0 3597 static int si_enter_ulp_state(struct radeon_device *rdev) 3598 { 3599 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3600 3601 udelay(25000); 3602 3603 return 0; 3604 } 3605 3606 static int si_exit_ulp_state(struct radeon_device *rdev) 3607 { 3608 int i; 3609 3610 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3611 3612 udelay(7000); 3613 3614 for (i = 0; i < rdev->usec_timeout; i++) { 3615 if (RREG32(SMC_RESP_0) == 1) 3616 break; 3617 udelay(1000); 3618 } 3619 3620 return 0; 3621 } 3622 #endif 3623 3624 static int si_notify_smc_display_change(struct radeon_device *rdev, 3625 bool has_display) 3626 { 3627 PPSMC_Msg msg = has_display ? 3628 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3629 3630 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3631 0 : -EINVAL; 3632 } 3633 3634 static void si_program_response_times(struct radeon_device *rdev) 3635 { 3636 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3637 u32 vddc_dly, acpi_dly, vbi_dly; 3638 u32 reference_clock; 3639 3640 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3641 3642 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3643 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3644 3645 if (voltage_response_time == 0) 3646 voltage_response_time = 1000; 3647 3648 acpi_delay_time = 15000; 3649 vbi_time_out = 100000; 3650 3651 reference_clock = radeon_get_xclk(rdev); 3652 3653 vddc_dly = (voltage_response_time * reference_clock) / 100; 3654 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3655 vbi_dly = (vbi_time_out * reference_clock) / 100; 3656 3657 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3658 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3659 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3660 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3661 } 3662 3663 static void si_program_ds_registers(struct radeon_device *rdev) 3664 { 3665 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3666 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3667 3668 if (eg_pi->sclk_deep_sleep) { 3669 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3670 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3671 ~AUTOSCALE_ON_SS_CLEAR); 3672 } 3673 } 3674 3675 static void si_program_display_gap(struct radeon_device *rdev) 3676 { 3677 u32 tmp, pipe; 3678 int i; 3679 3680 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3681 if (rdev->pm.dpm.new_active_crtc_count > 0) 3682 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3683 else 3684 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3685 3686 if (rdev->pm.dpm.new_active_crtc_count > 1) 3687 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3688 else 3689 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3690 3691 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3692 3693 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3694 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3695 3696 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3697 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3698 /* find the first active crtc */ 3699 for (i = 0; i < rdev->num_crtc; i++) { 3700 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3701 break; 3702 } 3703 if (i == rdev->num_crtc) 3704 pipe = 0; 3705 else 3706 pipe = i; 3707 3708 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3709 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3710 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3711 } 3712 3713 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3714 * This can be a problem on PowerXpress systems or if you want to use the card 3715 * for offscreen rendering or compute if there are no crtcs enabled. 3716 */ 3717 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3718 } 3719 3720 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3721 { 3722 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3723 3724 if (enable) { 3725 if (pi->sclk_ss) 3726 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3727 } else { 3728 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3729 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3730 } 3731 } 3732 3733 static void si_setup_bsp(struct radeon_device *rdev) 3734 { 3735 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3736 u32 xclk = radeon_get_xclk(rdev); 3737 3738 r600_calculate_u_and_p(pi->asi, 3739 xclk, 3740 16, 3741 &pi->bsp, 3742 &pi->bsu); 3743 3744 r600_calculate_u_and_p(pi->pasi, 3745 xclk, 3746 16, 3747 &pi->pbsp, 3748 &pi->pbsu); 3749 3750 3751 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3752 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3753 3754 WREG32(CG_BSP, pi->dsp); 3755 } 3756 3757 static void si_program_git(struct radeon_device *rdev) 3758 { 3759 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3760 } 3761 3762 static void si_program_tp(struct radeon_device *rdev) 3763 { 3764 int i; 3765 enum r600_td td = R600_TD_DFLT; 3766 3767 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3768 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3769 3770 if (td == R600_TD_AUTO) 3771 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3772 else 3773 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3774 3775 if (td == R600_TD_UP) 3776 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3777 3778 if (td == R600_TD_DOWN) 3779 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3780 } 3781 3782 static void si_program_tpp(struct radeon_device *rdev) 3783 { 3784 WREG32(CG_TPC, R600_TPC_DFLT); 3785 } 3786 3787 static void si_program_sstp(struct radeon_device *rdev) 3788 { 3789 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3790 } 3791 3792 static void si_enable_display_gap(struct radeon_device *rdev) 3793 { 3794 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3795 3796 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3797 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3798 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3799 3800 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3801 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3802 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3803 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3804 } 3805 3806 static void si_program_vc(struct radeon_device *rdev) 3807 { 3808 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3809 3810 WREG32(CG_FTV, pi->vrc); 3811 } 3812 3813 static void si_clear_vc(struct radeon_device *rdev) 3814 { 3815 WREG32(CG_FTV, 0); 3816 } 3817 3818 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3819 { 3820 u8 mc_para_index; 3821 3822 if (memory_clock < 10000) 3823 mc_para_index = 0; 3824 else if (memory_clock >= 80000) 3825 mc_para_index = 0x0f; 3826 else 3827 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3828 return mc_para_index; 3829 } 3830 3831 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3832 { 3833 u8 mc_para_index; 3834 3835 if (strobe_mode) { 3836 if (memory_clock < 12500) 3837 mc_para_index = 0x00; 3838 else if (memory_clock > 47500) 3839 mc_para_index = 0x0f; 3840 else 3841 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3842 } else { 3843 if (memory_clock < 65000) 3844 mc_para_index = 0x00; 3845 else if (memory_clock > 135000) 3846 mc_para_index = 0x0f; 3847 else 3848 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3849 } 3850 return mc_para_index; 3851 } 3852 3853 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3854 { 3855 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3856 bool strobe_mode = false; 3857 u8 result = 0; 3858 3859 if (mclk <= pi->mclk_strobe_mode_threshold) 3860 strobe_mode = true; 3861 3862 if (pi->mem_gddr5) 3863 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3864 else 3865 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3866 3867 if (strobe_mode) 3868 result |= SISLANDS_SMC_STROBE_ENABLE; 3869 3870 return result; 3871 } 3872 3873 static int si_upload_firmware(struct radeon_device *rdev) 3874 { 3875 struct si_power_info *si_pi = si_get_pi(rdev); 3876 int ret; 3877 3878 si_reset_smc(rdev); 3879 si_stop_smc_clock(rdev); 3880 3881 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3882 3883 return ret; 3884 } 3885 3886 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3887 const struct atom_voltage_table *table, 3888 const struct radeon_phase_shedding_limits_table *limits) 3889 { 3890 u32 data, num_bits, num_levels; 3891 3892 if ((table == NULL) || (limits == NULL)) 3893 return false; 3894 3895 data = table->mask_low; 3896 3897 num_bits = hweight32(data); 3898 3899 if (num_bits == 0) 3900 return false; 3901 3902 num_levels = (1 << num_bits); 3903 3904 if (table->count != num_levels) 3905 return false; 3906 3907 if (limits->count != (num_levels - 1)) 3908 return false; 3909 3910 return true; 3911 } 3912 3913 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3914 u32 max_voltage_steps, 3915 struct atom_voltage_table *voltage_table) 3916 { 3917 unsigned int i, diff; 3918 3919 if (voltage_table->count <= max_voltage_steps) 3920 return; 3921 3922 diff = voltage_table->count - max_voltage_steps; 3923 3924 for (i= 0; i < max_voltage_steps; i++) 3925 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3926 3927 voltage_table->count = max_voltage_steps; 3928 } 3929 3930 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3931 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3932 struct atom_voltage_table *voltage_table) 3933 { 3934 u32 i; 3935 3936 if (voltage_dependency_table == NULL) 3937 return -EINVAL; 3938 3939 voltage_table->mask_low = 0; 3940 voltage_table->phase_delay = 0; 3941 3942 voltage_table->count = voltage_dependency_table->count; 3943 for (i = 0; i < voltage_table->count; i++) { 3944 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3945 voltage_table->entries[i].smio_low = 0; 3946 } 3947 3948 return 0; 3949 } 3950 3951 static int si_construct_voltage_tables(struct radeon_device *rdev) 3952 { 3953 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3954 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3955 struct si_power_info *si_pi = si_get_pi(rdev); 3956 int ret; 3957 3958 if (pi->voltage_control) { 3959 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3960 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3961 if (ret) 3962 return ret; 3963 3964 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3965 si_trim_voltage_table_to_fit_state_table(rdev, 3966 SISLANDS_MAX_NO_VREG_STEPS, 3967 &eg_pi->vddc_voltage_table); 3968 } else if (si_pi->voltage_control_svi2) { 3969 ret = si_get_svi2_voltage_table(rdev, 3970 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3971 &eg_pi->vddc_voltage_table); 3972 if (ret) 3973 return ret; 3974 } else { 3975 return -EINVAL; 3976 } 3977 3978 if (eg_pi->vddci_control) { 3979 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3980 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3981 if (ret) 3982 return ret; 3983 3984 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3985 si_trim_voltage_table_to_fit_state_table(rdev, 3986 SISLANDS_MAX_NO_VREG_STEPS, 3987 &eg_pi->vddci_voltage_table); 3988 } 3989 if (si_pi->vddci_control_svi2) { 3990 ret = si_get_svi2_voltage_table(rdev, 3991 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3992 &eg_pi->vddci_voltage_table); 3993 if (ret) 3994 return ret; 3995 } 3996 3997 if (pi->mvdd_control) { 3998 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3999 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4000 4001 if (ret) { 4002 pi->mvdd_control = false; 4003 return ret; 4004 } 4005 4006 if (si_pi->mvdd_voltage_table.count == 0) { 4007 pi->mvdd_control = false; 4008 return -EINVAL; 4009 } 4010 4011 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4012 si_trim_voltage_table_to_fit_state_table(rdev, 4013 SISLANDS_MAX_NO_VREG_STEPS, 4014 &si_pi->mvdd_voltage_table); 4015 } 4016 4017 if (si_pi->vddc_phase_shed_control) { 4018 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4019 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4020 if (ret) 4021 si_pi->vddc_phase_shed_control = false; 4022 4023 if ((si_pi->vddc_phase_shed_table.count == 0) || 4024 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4025 si_pi->vddc_phase_shed_control = false; 4026 } 4027 4028 return 0; 4029 } 4030 4031 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4032 const struct atom_voltage_table *voltage_table, 4033 SISLANDS_SMC_STATETABLE *table) 4034 { 4035 unsigned int i; 4036 4037 for (i = 0; i < voltage_table->count; i++) 4038 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4039 } 4040 4041 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4042 SISLANDS_SMC_STATETABLE *table) 4043 { 4044 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4045 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4046 struct si_power_info *si_pi = si_get_pi(rdev); 4047 u8 i; 4048 4049 if (si_pi->voltage_control_svi2) { 4050 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4051 si_pi->svc_gpio_id); 4052 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4053 si_pi->svd_gpio_id); 4054 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4055 2); 4056 } else { 4057 if (eg_pi->vddc_voltage_table.count) { 4058 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4059 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4060 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4061 4062 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4063 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4064 table->maxVDDCIndexInPPTable = i; 4065 break; 4066 } 4067 } 4068 } 4069 4070 if (eg_pi->vddci_voltage_table.count) { 4071 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4072 4073 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4074 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4075 } 4076 4077 4078 if (si_pi->mvdd_voltage_table.count) { 4079 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4080 4081 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4082 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4083 } 4084 4085 if (si_pi->vddc_phase_shed_control) { 4086 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4087 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4088 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4089 4090 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4091 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4092 4093 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4094 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4095 } else { 4096 si_pi->vddc_phase_shed_control = false; 4097 } 4098 } 4099 } 4100 4101 return 0; 4102 } 4103 4104 static int si_populate_voltage_value(struct radeon_device *rdev, 4105 const struct atom_voltage_table *table, 4106 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4107 { 4108 unsigned int i; 4109 4110 for (i = 0; i < table->count; i++) { 4111 if (value <= table->entries[i].value) { 4112 voltage->index = (u8)i; 4113 voltage->value = cpu_to_be16(table->entries[i].value); 4114 break; 4115 } 4116 } 4117 4118 if (i >= table->count) 4119 return -EINVAL; 4120 4121 return 0; 4122 } 4123 4124 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4125 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4126 { 4127 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4128 struct si_power_info *si_pi = si_get_pi(rdev); 4129 4130 if (pi->mvdd_control) { 4131 if (mclk <= pi->mvdd_split_frequency) 4132 voltage->index = 0; 4133 else 4134 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4135 4136 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4137 } 4138 return 0; 4139 } 4140 4141 static int si_get_std_voltage_value(struct radeon_device *rdev, 4142 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4143 u16 *std_voltage) 4144 { 4145 u16 v_index; 4146 bool voltage_found = false; 4147 *std_voltage = be16_to_cpu(voltage->value); 4148 4149 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4150 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4151 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4152 return -EINVAL; 4153 4154 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4155 if (be16_to_cpu(voltage->value) == 4156 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4157 voltage_found = true; 4158 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4159 *std_voltage = 4160 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4161 else 4162 *std_voltage = 4163 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4164 break; 4165 } 4166 } 4167 4168 if (!voltage_found) { 4169 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4170 if (be16_to_cpu(voltage->value) <= 4171 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4172 voltage_found = true; 4173 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4174 *std_voltage = 4175 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4176 else 4177 *std_voltage = 4178 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4179 break; 4180 } 4181 } 4182 } 4183 } else { 4184 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4185 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4186 } 4187 } 4188 4189 return 0; 4190 } 4191 4192 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4193 u16 value, u8 index, 4194 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4195 { 4196 voltage->index = index; 4197 voltage->value = cpu_to_be16(value); 4198 4199 return 0; 4200 } 4201 4202 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4203 const struct radeon_phase_shedding_limits_table *limits, 4204 u16 voltage, u32 sclk, u32 mclk, 4205 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4206 { 4207 unsigned int i; 4208 4209 for (i = 0; i < limits->count; i++) { 4210 if ((voltage <= limits->entries[i].voltage) && 4211 (sclk <= limits->entries[i].sclk) && 4212 (mclk <= limits->entries[i].mclk)) 4213 break; 4214 } 4215 4216 smc_voltage->phase_settings = (u8)i; 4217 4218 return 0; 4219 } 4220 4221 static int si_init_arb_table_index(struct radeon_device *rdev) 4222 { 4223 struct si_power_info *si_pi = si_get_pi(rdev); 4224 u32 tmp; 4225 int ret; 4226 4227 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4228 if (ret) 4229 return ret; 4230 4231 tmp &= 0x00FFFFFF; 4232 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4233 4234 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4235 } 4236 4237 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4238 { 4239 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4240 } 4241 4242 static int si_reset_to_default(struct radeon_device *rdev) 4243 { 4244 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4245 0 : -EINVAL; 4246 } 4247 4248 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4249 { 4250 struct si_power_info *si_pi = si_get_pi(rdev); 4251 u32 tmp; 4252 int ret; 4253 4254 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4255 &tmp, si_pi->sram_end); 4256 if (ret) 4257 return ret; 4258 4259 tmp = (tmp >> 24) & 0xff; 4260 4261 if (tmp == MC_CG_ARB_FREQ_F0) 4262 return 0; 4263 4264 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4265 } 4266 4267 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4268 u32 engine_clock) 4269 { 4270 u32 dram_rows; 4271 u32 dram_refresh_rate; 4272 u32 mc_arb_rfsh_rate; 4273 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4274 4275 if (tmp >= 4) 4276 dram_rows = 16384; 4277 else 4278 dram_rows = 1 << (tmp + 10); 4279 4280 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4281 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4282 4283 return mc_arb_rfsh_rate; 4284 } 4285 4286 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4287 struct rv7xx_pl *pl, 4288 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4289 { 4290 u32 dram_timing; 4291 u32 dram_timing2; 4292 u32 burst_time; 4293 4294 arb_regs->mc_arb_rfsh_rate = 4295 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4296 4297 radeon_atom_set_engine_dram_timings(rdev, 4298 pl->sclk, 4299 pl->mclk); 4300 4301 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4302 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4303 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4304 4305 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4306 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4307 arb_regs->mc_arb_burst_time = (u8)burst_time; 4308 4309 return 0; 4310 } 4311 4312 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4313 struct radeon_ps *radeon_state, 4314 unsigned int first_arb_set) 4315 { 4316 struct si_power_info *si_pi = si_get_pi(rdev); 4317 struct ni_ps *state = ni_get_ps(radeon_state); 4318 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4319 int i, ret = 0; 4320 4321 for (i = 0; i < state->performance_level_count; i++) { 4322 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4323 if (ret) 4324 break; 4325 ret = si_copy_bytes_to_smc(rdev, 4326 si_pi->arb_table_start + 4327 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4328 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4329 (u8 *)&arb_regs, 4330 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4331 si_pi->sram_end); 4332 if (ret) 4333 break; 4334 } 4335 4336 return ret; 4337 } 4338 4339 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4340 struct radeon_ps *radeon_new_state) 4341 { 4342 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4343 SISLANDS_DRIVER_STATE_ARB_INDEX); 4344 } 4345 4346 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4347 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4348 { 4349 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4350 struct si_power_info *si_pi = si_get_pi(rdev); 4351 4352 if (pi->mvdd_control) 4353 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4354 si_pi->mvdd_bootup_value, voltage); 4355 4356 return 0; 4357 } 4358 4359 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4360 struct radeon_ps *radeon_initial_state, 4361 SISLANDS_SMC_STATETABLE *table) 4362 { 4363 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4364 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4365 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4366 struct si_power_info *si_pi = si_get_pi(rdev); 4367 u32 reg; 4368 int ret; 4369 4370 table->initialState.levels[0].mclk.vDLL_CNTL = 4371 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4372 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4373 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4374 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4375 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4376 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4377 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4378 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4379 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4380 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4381 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4382 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4383 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4384 table->initialState.levels[0].mclk.vMPLL_SS = 4385 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4386 table->initialState.levels[0].mclk.vMPLL_SS2 = 4387 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4388 4389 table->initialState.levels[0].mclk.mclk_value = 4390 cpu_to_be32(initial_state->performance_levels[0].mclk); 4391 4392 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4393 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4394 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4395 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4396 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4397 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4398 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4399 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4400 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4401 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4402 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4403 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4404 4405 table->initialState.levels[0].sclk.sclk_value = 4406 cpu_to_be32(initial_state->performance_levels[0].sclk); 4407 4408 table->initialState.levels[0].arbRefreshState = 4409 SISLANDS_INITIAL_STATE_ARB_INDEX; 4410 4411 table->initialState.levels[0].ACIndex = 0; 4412 4413 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4414 initial_state->performance_levels[0].vddc, 4415 &table->initialState.levels[0].vddc); 4416 4417 if (!ret) { 4418 u16 std_vddc; 4419 4420 ret = si_get_std_voltage_value(rdev, 4421 &table->initialState.levels[0].vddc, 4422 &std_vddc); 4423 if (!ret) 4424 si_populate_std_voltage_value(rdev, std_vddc, 4425 table->initialState.levels[0].vddc.index, 4426 &table->initialState.levels[0].std_vddc); 4427 } 4428 4429 if (eg_pi->vddci_control) 4430 si_populate_voltage_value(rdev, 4431 &eg_pi->vddci_voltage_table, 4432 initial_state->performance_levels[0].vddci, 4433 &table->initialState.levels[0].vddci); 4434 4435 if (si_pi->vddc_phase_shed_control) 4436 si_populate_phase_shedding_value(rdev, 4437 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4438 initial_state->performance_levels[0].vddc, 4439 initial_state->performance_levels[0].sclk, 4440 initial_state->performance_levels[0].mclk, 4441 &table->initialState.levels[0].vddc); 4442 4443 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4444 4445 reg = CG_R(0xffff) | CG_L(0); 4446 table->initialState.levels[0].aT = cpu_to_be32(reg); 4447 4448 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4449 4450 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4451 4452 if (pi->mem_gddr5) { 4453 table->initialState.levels[0].strobeMode = 4454 si_get_strobe_mode_settings(rdev, 4455 initial_state->performance_levels[0].mclk); 4456 4457 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4458 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4459 else 4460 table->initialState.levels[0].mcFlags = 0; 4461 } 4462 4463 table->initialState.levelCount = 1; 4464 4465 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4466 4467 table->initialState.levels[0].dpm2.MaxPS = 0; 4468 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4469 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4470 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4471 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4472 4473 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4474 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4475 4476 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4477 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4478 4479 return 0; 4480 } 4481 4482 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4483 SISLANDS_SMC_STATETABLE *table) 4484 { 4485 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4486 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4487 struct si_power_info *si_pi = si_get_pi(rdev); 4488 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4489 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4490 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4491 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4492 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4493 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4494 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4495 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4496 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4497 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4498 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4499 u32 reg; 4500 int ret; 4501 4502 table->ACPIState = table->initialState; 4503 4504 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4505 4506 if (pi->acpi_vddc) { 4507 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4508 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4509 if (!ret) { 4510 u16 std_vddc; 4511 4512 ret = si_get_std_voltage_value(rdev, 4513 &table->ACPIState.levels[0].vddc, &std_vddc); 4514 if (!ret) 4515 si_populate_std_voltage_value(rdev, std_vddc, 4516 table->ACPIState.levels[0].vddc.index, 4517 &table->ACPIState.levels[0].std_vddc); 4518 } 4519 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4520 4521 if (si_pi->vddc_phase_shed_control) { 4522 si_populate_phase_shedding_value(rdev, 4523 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4524 pi->acpi_vddc, 4525 0, 4526 0, 4527 &table->ACPIState.levels[0].vddc); 4528 } 4529 } else { 4530 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4531 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4532 if (!ret) { 4533 u16 std_vddc; 4534 4535 ret = si_get_std_voltage_value(rdev, 4536 &table->ACPIState.levels[0].vddc, &std_vddc); 4537 4538 if (!ret) 4539 si_populate_std_voltage_value(rdev, std_vddc, 4540 table->ACPIState.levels[0].vddc.index, 4541 &table->ACPIState.levels[0].std_vddc); 4542 } 4543 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4544 si_pi->sys_pcie_mask, 4545 si_pi->boot_pcie_gen, 4546 RADEON_PCIE_GEN1); 4547 4548 if (si_pi->vddc_phase_shed_control) 4549 si_populate_phase_shedding_value(rdev, 4550 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4551 pi->min_vddc_in_table, 4552 0, 4553 0, 4554 &table->ACPIState.levels[0].vddc); 4555 } 4556 4557 if (pi->acpi_vddc) { 4558 if (eg_pi->acpi_vddci) 4559 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4560 eg_pi->acpi_vddci, 4561 &table->ACPIState.levels[0].vddci); 4562 } 4563 4564 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4565 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4566 4567 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4568 4569 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4570 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4571 4572 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4573 cpu_to_be32(dll_cntl); 4574 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4575 cpu_to_be32(mclk_pwrmgt_cntl); 4576 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4577 cpu_to_be32(mpll_ad_func_cntl); 4578 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4579 cpu_to_be32(mpll_dq_func_cntl); 4580 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4581 cpu_to_be32(mpll_func_cntl); 4582 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4583 cpu_to_be32(mpll_func_cntl_1); 4584 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4585 cpu_to_be32(mpll_func_cntl_2); 4586 table->ACPIState.levels[0].mclk.vMPLL_SS = 4587 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4588 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4589 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4590 4591 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4592 cpu_to_be32(spll_func_cntl); 4593 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4594 cpu_to_be32(spll_func_cntl_2); 4595 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4596 cpu_to_be32(spll_func_cntl_3); 4597 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4598 cpu_to_be32(spll_func_cntl_4); 4599 4600 table->ACPIState.levels[0].mclk.mclk_value = 0; 4601 table->ACPIState.levels[0].sclk.sclk_value = 0; 4602 4603 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4604 4605 if (eg_pi->dynamic_ac_timing) 4606 table->ACPIState.levels[0].ACIndex = 0; 4607 4608 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4609 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4610 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4611 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4612 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4613 4614 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4615 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4616 4617 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4618 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4619 4620 return 0; 4621 } 4622 4623 static int si_populate_ulv_state(struct radeon_device *rdev, 4624 SISLANDS_SMC_SWSTATE *state) 4625 { 4626 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4627 struct si_power_info *si_pi = si_get_pi(rdev); 4628 struct si_ulv_param *ulv = &si_pi->ulv; 4629 u32 sclk_in_sr = 1350; /* ??? */ 4630 int ret; 4631 4632 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4633 &state->levels[0]); 4634 if (!ret) { 4635 if (eg_pi->sclk_deep_sleep) { 4636 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4637 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4638 else 4639 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4640 } 4641 if (ulv->one_pcie_lane_in_ulv) 4642 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4643 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4644 state->levels[0].ACIndex = 1; 4645 state->levels[0].std_vddc = state->levels[0].vddc; 4646 state->levelCount = 1; 4647 4648 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4649 } 4650 4651 return ret; 4652 } 4653 4654 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4655 { 4656 struct si_power_info *si_pi = si_get_pi(rdev); 4657 struct si_ulv_param *ulv = &si_pi->ulv; 4658 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4659 int ret; 4660 4661 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4662 &arb_regs); 4663 if (ret) 4664 return ret; 4665 4666 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4667 ulv->volt_change_delay); 4668 4669 ret = si_copy_bytes_to_smc(rdev, 4670 si_pi->arb_table_start + 4671 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4672 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4673 (u8 *)&arb_regs, 4674 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4675 si_pi->sram_end); 4676 4677 return ret; 4678 } 4679 4680 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4681 { 4682 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4683 4684 pi->mvdd_split_frequency = 30000; 4685 } 4686 4687 static int si_init_smc_table(struct radeon_device *rdev) 4688 { 4689 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4690 struct si_power_info *si_pi = si_get_pi(rdev); 4691 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4692 const struct si_ulv_param *ulv = &si_pi->ulv; 4693 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4694 int ret; 4695 u32 lane_width; 4696 u32 vr_hot_gpio; 4697 4698 si_populate_smc_voltage_tables(rdev, table); 4699 4700 switch (rdev->pm.int_thermal_type) { 4701 case THERMAL_TYPE_SI: 4702 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4703 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4704 break; 4705 case THERMAL_TYPE_NONE: 4706 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4707 break; 4708 default: 4709 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4710 break; 4711 } 4712 4713 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4714 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4715 4716 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4717 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4718 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4719 } 4720 4721 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4722 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4723 4724 if (pi->mem_gddr5) 4725 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4726 4727 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4728 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4729 4730 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4731 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4732 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4733 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4734 vr_hot_gpio); 4735 } 4736 4737 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4738 if (ret) 4739 return ret; 4740 4741 ret = si_populate_smc_acpi_state(rdev, table); 4742 if (ret) 4743 return ret; 4744 4745 table->driverState = table->initialState; 4746 4747 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4748 SISLANDS_INITIAL_STATE_ARB_INDEX); 4749 if (ret) 4750 return ret; 4751 4752 if (ulv->supported && ulv->pl.vddc) { 4753 ret = si_populate_ulv_state(rdev, &table->ULVState); 4754 if (ret) 4755 return ret; 4756 4757 ret = si_program_ulv_memory_timing_parameters(rdev); 4758 if (ret) 4759 return ret; 4760 4761 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4762 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4763 4764 lane_width = radeon_get_pcie_lanes(rdev); 4765 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4766 } else { 4767 table->ULVState = table->initialState; 4768 } 4769 4770 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4771 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4772 si_pi->sram_end); 4773 } 4774 4775 static int si_calculate_sclk_params(struct radeon_device *rdev, 4776 u32 engine_clock, 4777 SISLANDS_SMC_SCLK_VALUE *sclk) 4778 { 4779 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4780 struct si_power_info *si_pi = si_get_pi(rdev); 4781 struct atom_clock_dividers dividers; 4782 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4783 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4784 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4785 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4786 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4787 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4788 u64 tmp; 4789 u32 reference_clock = rdev->clock.spll.reference_freq; 4790 u32 reference_divider; 4791 u32 fbdiv; 4792 int ret; 4793 4794 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4795 engine_clock, false, ÷rs); 4796 if (ret) 4797 return ret; 4798 4799 reference_divider = 1 + dividers.ref_div; 4800 4801 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4802 do_div(tmp, reference_clock); 4803 fbdiv = (u32) tmp; 4804 4805 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4806 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4807 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4808 4809 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4810 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4811 4812 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4813 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4814 spll_func_cntl_3 |= SPLL_DITHEN; 4815 4816 if (pi->sclk_ss) { 4817 struct radeon_atom_ss ss; 4818 u32 vco_freq = engine_clock * dividers.post_div; 4819 4820 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4821 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4822 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4823 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4824 4825 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4826 cg_spll_spread_spectrum |= CLK_S(clk_s); 4827 cg_spll_spread_spectrum |= SSEN; 4828 4829 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4830 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4831 } 4832 } 4833 4834 sclk->sclk_value = engine_clock; 4835 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4836 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4837 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4838 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4839 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4840 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4841 4842 return 0; 4843 } 4844 4845 static int si_populate_sclk_value(struct radeon_device *rdev, 4846 u32 engine_clock, 4847 SISLANDS_SMC_SCLK_VALUE *sclk) 4848 { 4849 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4850 int ret; 4851 4852 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4853 if (!ret) { 4854 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4855 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4856 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4857 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4858 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4859 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4860 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4861 } 4862 4863 return ret; 4864 } 4865 4866 static int si_populate_mclk_value(struct radeon_device *rdev, 4867 u32 engine_clock, 4868 u32 memory_clock, 4869 SISLANDS_SMC_MCLK_VALUE *mclk, 4870 bool strobe_mode, 4871 bool dll_state_on) 4872 { 4873 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4874 struct si_power_info *si_pi = si_get_pi(rdev); 4875 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4876 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4877 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4878 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4879 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4880 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4881 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4882 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4883 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4884 struct atom_mpll_param mpll_param; 4885 int ret; 4886 4887 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4888 if (ret) 4889 return ret; 4890 4891 mpll_func_cntl &= ~BWCTRL_MASK; 4892 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4893 4894 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4895 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4896 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4897 4898 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4899 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4900 4901 if (pi->mem_gddr5) { 4902 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4903 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4904 YCLK_POST_DIV(mpll_param.post_div); 4905 } 4906 4907 if (pi->mclk_ss) { 4908 struct radeon_atom_ss ss; 4909 u32 freq_nom; 4910 u32 tmp; 4911 u32 reference_clock = rdev->clock.mpll.reference_freq; 4912 4913 if (pi->mem_gddr5) 4914 freq_nom = memory_clock * 4; 4915 else 4916 freq_nom = memory_clock * 2; 4917 4918 tmp = freq_nom / reference_clock; 4919 tmp = tmp * tmp; 4920 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4921 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4922 u32 clks = reference_clock * 5 / ss.rate; 4923 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4924 4925 mpll_ss1 &= ~CLKV_MASK; 4926 mpll_ss1 |= CLKV(clkv); 4927 4928 mpll_ss2 &= ~CLKS_MASK; 4929 mpll_ss2 |= CLKS(clks); 4930 } 4931 } 4932 4933 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4934 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4935 4936 if (dll_state_on) 4937 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4938 else 4939 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4940 4941 mclk->mclk_value = cpu_to_be32(memory_clock); 4942 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4943 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4944 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4945 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4946 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4947 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4948 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4949 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4950 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4951 4952 return 0; 4953 } 4954 4955 static void si_populate_smc_sp(struct radeon_device *rdev, 4956 struct radeon_ps *radeon_state, 4957 SISLANDS_SMC_SWSTATE *smc_state) 4958 { 4959 struct ni_ps *ps = ni_get_ps(radeon_state); 4960 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4961 int i; 4962 4963 for (i = 0; i < ps->performance_level_count - 1; i++) 4964 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4965 4966 smc_state->levels[ps->performance_level_count - 1].bSP = 4967 cpu_to_be32(pi->psp); 4968 } 4969 4970 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4971 struct rv7xx_pl *pl, 4972 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4973 { 4974 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4975 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4976 struct si_power_info *si_pi = si_get_pi(rdev); 4977 int ret; 4978 bool dll_state_on; 4979 u16 std_vddc; 4980 bool gmc_pg = false; 4981 4982 if (eg_pi->pcie_performance_request && 4983 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4984 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4985 else 4986 level->gen2PCIE = (u8)pl->pcie_gen; 4987 4988 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4989 if (ret) 4990 return ret; 4991 4992 level->mcFlags = 0; 4993 4994 if (pi->mclk_stutter_mode_threshold && 4995 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4996 !eg_pi->uvd_enabled && 4997 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4998 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4999 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5000 5001 if (gmc_pg) 5002 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5003 } 5004 5005 if (pi->mem_gddr5) { 5006 if (pl->mclk > pi->mclk_edc_enable_threshold) 5007 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5008 5009 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5010 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5011 5012 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5013 5014 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5015 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5016 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5017 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5018 else 5019 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5020 } else { 5021 dll_state_on = false; 5022 } 5023 } else { 5024 level->strobeMode = si_get_strobe_mode_settings(rdev, 5025 pl->mclk); 5026 5027 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5028 } 5029 5030 ret = si_populate_mclk_value(rdev, 5031 pl->sclk, 5032 pl->mclk, 5033 &level->mclk, 5034 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5035 if (ret) 5036 return ret; 5037 5038 ret = si_populate_voltage_value(rdev, 5039 &eg_pi->vddc_voltage_table, 5040 pl->vddc, &level->vddc); 5041 if (ret) 5042 return ret; 5043 5044 5045 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5046 if (ret) 5047 return ret; 5048 5049 ret = si_populate_std_voltage_value(rdev, std_vddc, 5050 level->vddc.index, &level->std_vddc); 5051 if (ret) 5052 return ret; 5053 5054 if (eg_pi->vddci_control) { 5055 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5056 pl->vddci, &level->vddci); 5057 if (ret) 5058 return ret; 5059 } 5060 5061 if (si_pi->vddc_phase_shed_control) { 5062 ret = si_populate_phase_shedding_value(rdev, 5063 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5064 pl->vddc, 5065 pl->sclk, 5066 pl->mclk, 5067 &level->vddc); 5068 if (ret) 5069 return ret; 5070 } 5071 5072 level->MaxPoweredUpCU = si_pi->max_cu; 5073 5074 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5075 5076 return ret; 5077 } 5078 5079 static int si_populate_smc_t(struct radeon_device *rdev, 5080 struct radeon_ps *radeon_state, 5081 SISLANDS_SMC_SWSTATE *smc_state) 5082 { 5083 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5084 struct ni_ps *state = ni_get_ps(radeon_state); 5085 u32 a_t; 5086 u32 t_l, t_h; 5087 u32 high_bsp; 5088 int i, ret; 5089 5090 if (state->performance_level_count >= 9) 5091 return -EINVAL; 5092 5093 if (state->performance_level_count < 2) { 5094 a_t = CG_R(0xffff) | CG_L(0); 5095 smc_state->levels[0].aT = cpu_to_be32(a_t); 5096 return 0; 5097 } 5098 5099 smc_state->levels[0].aT = cpu_to_be32(0); 5100 5101 for (i = 0; i <= state->performance_level_count - 2; i++) { 5102 ret = r600_calculate_at( 5103 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5104 100 * R600_AH_DFLT, 5105 state->performance_levels[i + 1].sclk, 5106 state->performance_levels[i].sclk, 5107 &t_l, 5108 &t_h); 5109 5110 if (ret) { 5111 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5112 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5113 } 5114 5115 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5116 a_t |= CG_R(t_l * pi->bsp / 20000); 5117 smc_state->levels[i].aT = cpu_to_be32(a_t); 5118 5119 high_bsp = (i == state->performance_level_count - 2) ? 5120 pi->pbsp : pi->bsp; 5121 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5122 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5123 } 5124 5125 return 0; 5126 } 5127 5128 static int si_disable_ulv(struct radeon_device *rdev) 5129 { 5130 struct si_power_info *si_pi = si_get_pi(rdev); 5131 struct si_ulv_param *ulv = &si_pi->ulv; 5132 5133 if (ulv->supported) 5134 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5135 0 : -EINVAL; 5136 5137 return 0; 5138 } 5139 5140 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5141 struct radeon_ps *radeon_state) 5142 { 5143 const struct si_power_info *si_pi = si_get_pi(rdev); 5144 const struct si_ulv_param *ulv = &si_pi->ulv; 5145 const struct ni_ps *state = ni_get_ps(radeon_state); 5146 int i; 5147 5148 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5149 return false; 5150 5151 /* XXX validate against display requirements! */ 5152 5153 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5154 if (rdev->clock.current_dispclk <= 5155 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5156 if (ulv->pl.vddc < 5157 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5158 return false; 5159 } 5160 } 5161 5162 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5163 return false; 5164 5165 return true; 5166 } 5167 5168 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5169 struct radeon_ps *radeon_new_state) 5170 { 5171 const struct si_power_info *si_pi = si_get_pi(rdev); 5172 const struct si_ulv_param *ulv = &si_pi->ulv; 5173 5174 if (ulv->supported) { 5175 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5176 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5177 0 : -EINVAL; 5178 } 5179 return 0; 5180 } 5181 5182 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5183 struct radeon_ps *radeon_state, 5184 SISLANDS_SMC_SWSTATE *smc_state) 5185 { 5186 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5187 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5188 struct si_power_info *si_pi = si_get_pi(rdev); 5189 struct ni_ps *state = ni_get_ps(radeon_state); 5190 int i, ret; 5191 u32 threshold; 5192 u32 sclk_in_sr = 1350; /* ??? */ 5193 5194 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5195 return -EINVAL; 5196 5197 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5198 5199 if (radeon_state->vclk && radeon_state->dclk) { 5200 eg_pi->uvd_enabled = true; 5201 if (eg_pi->smu_uvd_hs) 5202 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5203 } else { 5204 eg_pi->uvd_enabled = false; 5205 } 5206 5207 if (state->dc_compatible) 5208 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5209 5210 smc_state->levelCount = 0; 5211 for (i = 0; i < state->performance_level_count; i++) { 5212 if (eg_pi->sclk_deep_sleep) { 5213 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5214 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5215 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5216 else 5217 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5218 } 5219 } 5220 5221 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5222 &smc_state->levels[i]); 5223 smc_state->levels[i].arbRefreshState = 5224 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5225 5226 if (ret) 5227 return ret; 5228 5229 if (ni_pi->enable_power_containment) 5230 smc_state->levels[i].displayWatermark = 5231 (state->performance_levels[i].sclk < threshold) ? 5232 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5233 else 5234 smc_state->levels[i].displayWatermark = (i < 2) ? 5235 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5236 5237 if (eg_pi->dynamic_ac_timing) 5238 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5239 else 5240 smc_state->levels[i].ACIndex = 0; 5241 5242 smc_state->levelCount++; 5243 } 5244 5245 si_write_smc_soft_register(rdev, 5246 SI_SMC_SOFT_REGISTER_watermark_threshold, 5247 threshold / 512); 5248 5249 si_populate_smc_sp(rdev, radeon_state, smc_state); 5250 5251 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5252 if (ret) 5253 ni_pi->enable_power_containment = false; 5254 5255 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5256 if (ret) 5257 ni_pi->enable_sq_ramping = false; 5258 5259 return si_populate_smc_t(rdev, radeon_state, smc_state); 5260 } 5261 5262 static int si_upload_sw_state(struct radeon_device *rdev, 5263 struct radeon_ps *radeon_new_state) 5264 { 5265 struct si_power_info *si_pi = si_get_pi(rdev); 5266 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5267 int ret; 5268 u32 address = si_pi->state_table_start + 5269 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5270 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5271 ((new_state->performance_level_count - 1) * 5272 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5273 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5274 5275 memset(smc_state, 0, state_size); 5276 5277 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5278 if (ret) 5279 return ret; 5280 5281 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5282 state_size, si_pi->sram_end); 5283 5284 return ret; 5285 } 5286 5287 static int si_upload_ulv_state(struct radeon_device *rdev) 5288 { 5289 struct si_power_info *si_pi = si_get_pi(rdev); 5290 struct si_ulv_param *ulv = &si_pi->ulv; 5291 int ret = 0; 5292 5293 if (ulv->supported && ulv->pl.vddc) { 5294 u32 address = si_pi->state_table_start + 5295 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5296 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5297 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5298 5299 memset(smc_state, 0, state_size); 5300 5301 ret = si_populate_ulv_state(rdev, smc_state); 5302 if (!ret) 5303 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5304 state_size, si_pi->sram_end); 5305 } 5306 5307 return ret; 5308 } 5309 5310 static int si_upload_smc_data(struct radeon_device *rdev) 5311 { 5312 struct radeon_crtc *radeon_crtc = NULL; 5313 int i; 5314 5315 if (rdev->pm.dpm.new_active_crtc_count == 0) 5316 return 0; 5317 5318 for (i = 0; i < rdev->num_crtc; i++) { 5319 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5320 radeon_crtc = rdev->mode_info.crtcs[i]; 5321 break; 5322 } 5323 } 5324 5325 if (radeon_crtc == NULL) 5326 return 0; 5327 5328 if (radeon_crtc->line_time <= 0) 5329 return 0; 5330 5331 if (si_write_smc_soft_register(rdev, 5332 SI_SMC_SOFT_REGISTER_crtc_index, 5333 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5334 return 0; 5335 5336 if (si_write_smc_soft_register(rdev, 5337 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5338 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5339 return 0; 5340 5341 if (si_write_smc_soft_register(rdev, 5342 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5343 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5344 return 0; 5345 5346 return 0; 5347 } 5348 5349 static int si_set_mc_special_registers(struct radeon_device *rdev, 5350 struct si_mc_reg_table *table) 5351 { 5352 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5353 u8 i, j, k; 5354 u32 temp_reg; 5355 5356 for (i = 0, j = table->last; i < table->last; i++) { 5357 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5358 return -EINVAL; 5359 switch (table->mc_reg_address[i].s1 << 2) { 5360 case MC_SEQ_MISC1: 5361 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5362 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5363 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5364 for (k = 0; k < table->num_entries; k++) 5365 table->mc_reg_table_entry[k].mc_data[j] = 5366 ((temp_reg & 0xffff0000)) | 5367 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5368 j++; 5369 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5370 return -EINVAL; 5371 5372 temp_reg = RREG32(MC_PMG_CMD_MRS); 5373 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5374 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5375 for (k = 0; k < table->num_entries; k++) { 5376 table->mc_reg_table_entry[k].mc_data[j] = 5377 (temp_reg & 0xffff0000) | 5378 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5379 if (!pi->mem_gddr5) 5380 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5381 } 5382 j++; 5383 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5384 return -EINVAL; 5385 5386 if (!pi->mem_gddr5) { 5387 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5388 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5389 for (k = 0; k < table->num_entries; k++) 5390 table->mc_reg_table_entry[k].mc_data[j] = 5391 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5392 j++; 5393 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5394 return -EINVAL; 5395 } 5396 break; 5397 case MC_SEQ_RESERVE_M: 5398 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5399 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5400 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5401 for(k = 0; k < table->num_entries; k++) 5402 table->mc_reg_table_entry[k].mc_data[j] = 5403 (temp_reg & 0xffff0000) | 5404 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5405 j++; 5406 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5407 return -EINVAL; 5408 break; 5409 default: 5410 break; 5411 } 5412 } 5413 5414 table->last = j; 5415 5416 return 0; 5417 } 5418 5419 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5420 { 5421 bool result = true; 5422 5423 switch (in_reg) { 5424 case MC_SEQ_RAS_TIMING >> 2: 5425 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5426 break; 5427 case MC_SEQ_CAS_TIMING >> 2: 5428 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5429 break; 5430 case MC_SEQ_MISC_TIMING >> 2: 5431 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5432 break; 5433 case MC_SEQ_MISC_TIMING2 >> 2: 5434 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5435 break; 5436 case MC_SEQ_RD_CTL_D0 >> 2: 5437 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5438 break; 5439 case MC_SEQ_RD_CTL_D1 >> 2: 5440 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5441 break; 5442 case MC_SEQ_WR_CTL_D0 >> 2: 5443 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5444 break; 5445 case MC_SEQ_WR_CTL_D1 >> 2: 5446 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5447 break; 5448 case MC_PMG_CMD_EMRS >> 2: 5449 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5450 break; 5451 case MC_PMG_CMD_MRS >> 2: 5452 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5453 break; 5454 case MC_PMG_CMD_MRS1 >> 2: 5455 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5456 break; 5457 case MC_SEQ_PMG_TIMING >> 2: 5458 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5459 break; 5460 case MC_PMG_CMD_MRS2 >> 2: 5461 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5462 break; 5463 case MC_SEQ_WR_CTL_2 >> 2: 5464 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5465 break; 5466 default: 5467 result = false; 5468 break; 5469 } 5470 5471 return result; 5472 } 5473 5474 static void si_set_valid_flag(struct si_mc_reg_table *table) 5475 { 5476 u8 i, j; 5477 5478 for (i = 0; i < table->last; i++) { 5479 for (j = 1; j < table->num_entries; j++) { 5480 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5481 table->valid_flag |= 1 << i; 5482 break; 5483 } 5484 } 5485 } 5486 } 5487 5488 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5489 { 5490 u32 i; 5491 u16 address; 5492 5493 for (i = 0; i < table->last; i++) 5494 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5495 address : table->mc_reg_address[i].s1; 5496 5497 } 5498 5499 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5500 struct si_mc_reg_table *si_table) 5501 { 5502 u8 i, j; 5503 5504 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5505 return -EINVAL; 5506 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5507 return -EINVAL; 5508 5509 for (i = 0; i < table->last; i++) 5510 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5511 si_table->last = table->last; 5512 5513 for (i = 0; i < table->num_entries; i++) { 5514 si_table->mc_reg_table_entry[i].mclk_max = 5515 table->mc_reg_table_entry[i].mclk_max; 5516 for (j = 0; j < table->last; j++) { 5517 si_table->mc_reg_table_entry[i].mc_data[j] = 5518 table->mc_reg_table_entry[i].mc_data[j]; 5519 } 5520 } 5521 si_table->num_entries = table->num_entries; 5522 5523 return 0; 5524 } 5525 5526 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5527 { 5528 struct si_power_info *si_pi = si_get_pi(rdev); 5529 struct atom_mc_reg_table *table; 5530 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5531 u8 module_index = rv770_get_memory_module_index(rdev); 5532 int ret; 5533 5534 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5535 if (!table) 5536 return -ENOMEM; 5537 5538 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5539 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5540 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5541 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5542 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5543 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5544 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5545 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5546 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5547 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5548 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5549 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5550 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5551 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5552 5553 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5554 if (ret) 5555 goto init_mc_done; 5556 5557 ret = si_copy_vbios_mc_reg_table(table, si_table); 5558 if (ret) 5559 goto init_mc_done; 5560 5561 si_set_s0_mc_reg_index(si_table); 5562 5563 ret = si_set_mc_special_registers(rdev, si_table); 5564 if (ret) 5565 goto init_mc_done; 5566 5567 si_set_valid_flag(si_table); 5568 5569 init_mc_done: 5570 kfree(table); 5571 5572 return ret; 5573 5574 } 5575 5576 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5577 SMC_SIslands_MCRegisters *mc_reg_table) 5578 { 5579 struct si_power_info *si_pi = si_get_pi(rdev); 5580 u32 i, j; 5581 5582 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5583 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5584 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5585 break; 5586 mc_reg_table->address[i].s0 = 5587 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5588 mc_reg_table->address[i].s1 = 5589 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5590 i++; 5591 } 5592 } 5593 mc_reg_table->last = (u8)i; 5594 } 5595 5596 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5597 SMC_SIslands_MCRegisterSet *data, 5598 u32 num_entries, u32 valid_flag) 5599 { 5600 u32 i, j; 5601 5602 for(i = 0, j = 0; j < num_entries; j++) { 5603 if (valid_flag & (1 << j)) { 5604 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5605 i++; 5606 } 5607 } 5608 } 5609 5610 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5611 struct rv7xx_pl *pl, 5612 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5613 { 5614 struct si_power_info *si_pi = si_get_pi(rdev); 5615 u32 i = 0; 5616 5617 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5618 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5619 break; 5620 } 5621 5622 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5623 --i; 5624 5625 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5626 mc_reg_table_data, si_pi->mc_reg_table.last, 5627 si_pi->mc_reg_table.valid_flag); 5628 } 5629 5630 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5631 struct radeon_ps *radeon_state, 5632 SMC_SIslands_MCRegisters *mc_reg_table) 5633 { 5634 struct ni_ps *state = ni_get_ps(radeon_state); 5635 int i; 5636 5637 for (i = 0; i < state->performance_level_count; i++) { 5638 si_convert_mc_reg_table_entry_to_smc(rdev, 5639 &state->performance_levels[i], 5640 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5641 } 5642 } 5643 5644 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5645 struct radeon_ps *radeon_boot_state) 5646 { 5647 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5648 struct si_power_info *si_pi = si_get_pi(rdev); 5649 struct si_ulv_param *ulv = &si_pi->ulv; 5650 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5651 5652 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5653 5654 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5655 5656 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5657 5658 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5659 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5660 5661 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5662 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5663 si_pi->mc_reg_table.last, 5664 si_pi->mc_reg_table.valid_flag); 5665 5666 if (ulv->supported && ulv->pl.vddc != 0) 5667 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5668 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5669 else 5670 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5671 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5672 si_pi->mc_reg_table.last, 5673 si_pi->mc_reg_table.valid_flag); 5674 5675 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5676 5677 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5678 (u8 *)smc_mc_reg_table, 5679 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5680 } 5681 5682 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5683 struct radeon_ps *radeon_new_state) 5684 { 5685 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5686 struct si_power_info *si_pi = si_get_pi(rdev); 5687 u32 address = si_pi->mc_reg_table_start + 5688 offsetof(SMC_SIslands_MCRegisters, 5689 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5690 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5691 5692 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5693 5694 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5695 5696 5697 return si_copy_bytes_to_smc(rdev, address, 5698 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5699 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5700 si_pi->sram_end); 5701 5702 } 5703 5704 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5705 { 5706 if (enable) 5707 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5708 else 5709 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5710 } 5711 5712 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5713 struct radeon_ps *radeon_state) 5714 { 5715 struct ni_ps *state = ni_get_ps(radeon_state); 5716 int i; 5717 u16 pcie_speed, max_speed = 0; 5718 5719 for (i = 0; i < state->performance_level_count; i++) { 5720 pcie_speed = state->performance_levels[i].pcie_gen; 5721 if (max_speed < pcie_speed) 5722 max_speed = pcie_speed; 5723 } 5724 return max_speed; 5725 } 5726 5727 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5728 { 5729 u32 speed_cntl; 5730 5731 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5732 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5733 5734 return (u16)speed_cntl; 5735 } 5736 5737 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5738 struct radeon_ps *radeon_new_state, 5739 struct radeon_ps *radeon_current_state) 5740 { 5741 struct si_power_info *si_pi = si_get_pi(rdev); 5742 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5743 enum radeon_pcie_gen current_link_speed; 5744 5745 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5746 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5747 else 5748 current_link_speed = si_pi->force_pcie_gen; 5749 5750 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5751 si_pi->pspp_notify_required = false; 5752 if (target_link_speed > current_link_speed) { 5753 switch (target_link_speed) { 5754 #if defined(CONFIG_ACPI) 5755 case RADEON_PCIE_GEN3: 5756 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5757 break; 5758 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5759 if (current_link_speed == RADEON_PCIE_GEN2) 5760 break; 5761 case RADEON_PCIE_GEN2: 5762 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5763 break; 5764 #endif 5765 default: 5766 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5767 break; 5768 } 5769 } else { 5770 if (target_link_speed < current_link_speed) 5771 si_pi->pspp_notify_required = true; 5772 } 5773 } 5774 5775 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5776 struct radeon_ps *radeon_new_state, 5777 struct radeon_ps *radeon_current_state) 5778 { 5779 struct si_power_info *si_pi = si_get_pi(rdev); 5780 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5781 u8 request; 5782 5783 if (si_pi->pspp_notify_required) { 5784 if (target_link_speed == RADEON_PCIE_GEN3) 5785 request = PCIE_PERF_REQ_PECI_GEN3; 5786 else if (target_link_speed == RADEON_PCIE_GEN2) 5787 request = PCIE_PERF_REQ_PECI_GEN2; 5788 else 5789 request = PCIE_PERF_REQ_PECI_GEN1; 5790 5791 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5792 (si_get_current_pcie_speed(rdev) > 0)) 5793 return; 5794 5795 #if defined(CONFIG_ACPI) 5796 radeon_acpi_pcie_performance_request(rdev, request, false); 5797 #endif 5798 } 5799 } 5800 5801 #if 0 5802 static int si_ds_request(struct radeon_device *rdev, 5803 bool ds_status_on, u32 count_write) 5804 { 5805 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5806 5807 if (eg_pi->sclk_deep_sleep) { 5808 if (ds_status_on) 5809 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5810 PPSMC_Result_OK) ? 5811 0 : -EINVAL; 5812 else 5813 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5814 PPSMC_Result_OK) ? 0 : -EINVAL; 5815 } 5816 return 0; 5817 } 5818 #endif 5819 5820 static void si_set_max_cu_value(struct radeon_device *rdev) 5821 { 5822 struct si_power_info *si_pi = si_get_pi(rdev); 5823 5824 if (rdev->family == CHIP_VERDE) { 5825 switch (rdev->pdev->device) { 5826 case 0x6820: 5827 case 0x6825: 5828 case 0x6821: 5829 case 0x6823: 5830 case 0x6827: 5831 si_pi->max_cu = 10; 5832 break; 5833 case 0x682D: 5834 case 0x6824: 5835 case 0x682F: 5836 case 0x6826: 5837 si_pi->max_cu = 8; 5838 break; 5839 case 0x6828: 5840 case 0x6830: 5841 case 0x6831: 5842 case 0x6838: 5843 case 0x6839: 5844 case 0x683D: 5845 si_pi->max_cu = 10; 5846 break; 5847 case 0x683B: 5848 case 0x683F: 5849 case 0x6829: 5850 si_pi->max_cu = 8; 5851 break; 5852 default: 5853 si_pi->max_cu = 0; 5854 break; 5855 } 5856 } else { 5857 si_pi->max_cu = 0; 5858 } 5859 } 5860 5861 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5862 struct radeon_clock_voltage_dependency_table *table) 5863 { 5864 u32 i; 5865 int j; 5866 u16 leakage_voltage; 5867 5868 if (table) { 5869 for (i = 0; i < table->count; i++) { 5870 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5871 table->entries[i].v, 5872 &leakage_voltage)) { 5873 case 0: 5874 table->entries[i].v = leakage_voltage; 5875 break; 5876 case -EAGAIN: 5877 return -EINVAL; 5878 case -EINVAL: 5879 default: 5880 break; 5881 } 5882 } 5883 5884 for (j = (table->count - 2); j >= 0; j--) { 5885 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5886 table->entries[j].v : table->entries[j + 1].v; 5887 } 5888 } 5889 return 0; 5890 } 5891 5892 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5893 { 5894 int ret = 0; 5895 5896 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5897 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5898 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5899 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5900 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5901 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5902 return ret; 5903 } 5904 5905 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5906 struct radeon_ps *radeon_new_state, 5907 struct radeon_ps *radeon_current_state) 5908 { 5909 u32 lane_width; 5910 u32 new_lane_width = 5911 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5912 u32 current_lane_width = 5913 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5914 5915 if (new_lane_width != current_lane_width) { 5916 radeon_set_pcie_lanes(rdev, new_lane_width); 5917 lane_width = radeon_get_pcie_lanes(rdev); 5918 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5919 } 5920 } 5921 5922 static void si_set_vce_clock(struct radeon_device *rdev, 5923 struct radeon_ps *new_rps, 5924 struct radeon_ps *old_rps) 5925 { 5926 if ((old_rps->evclk != new_rps->evclk) || 5927 (old_rps->ecclk != new_rps->ecclk)) { 5928 /* turn the clocks on when encoding, off otherwise */ 5929 if (new_rps->evclk || new_rps->ecclk) 5930 vce_v1_0_enable_mgcg(rdev, false); 5931 else 5932 vce_v1_0_enable_mgcg(rdev, true); 5933 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5934 } 5935 } 5936 5937 void si_dpm_setup_asic(struct radeon_device *rdev) 5938 { 5939 int r; 5940 5941 r = si_mc_load_microcode(rdev); 5942 if (r) 5943 DRM_ERROR("Failed to load MC firmware!\n"); 5944 rv770_get_memory_type(rdev); 5945 si_read_clock_registers(rdev); 5946 si_enable_acpi_power_management(rdev); 5947 } 5948 5949 static int si_thermal_enable_alert(struct radeon_device *rdev, 5950 bool enable) 5951 { 5952 u32 thermal_int = RREG32(CG_THERMAL_INT); 5953 5954 if (enable) { 5955 PPSMC_Result result; 5956 5957 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5958 WREG32(CG_THERMAL_INT, thermal_int); 5959 rdev->irq.dpm_thermal = false; 5960 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5961 if (result != PPSMC_Result_OK) { 5962 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5963 return -EINVAL; 5964 } 5965 } else { 5966 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5967 WREG32(CG_THERMAL_INT, thermal_int); 5968 rdev->irq.dpm_thermal = true; 5969 } 5970 5971 return 0; 5972 } 5973 5974 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5975 int min_temp, int max_temp) 5976 { 5977 int low_temp = 0 * 1000; 5978 int high_temp = 255 * 1000; 5979 5980 if (low_temp < min_temp) 5981 low_temp = min_temp; 5982 if (high_temp > max_temp) 5983 high_temp = max_temp; 5984 if (high_temp < low_temp) { 5985 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5986 return -EINVAL; 5987 } 5988 5989 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5990 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5991 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5992 5993 rdev->pm.dpm.thermal.min_temp = low_temp; 5994 rdev->pm.dpm.thermal.max_temp = high_temp; 5995 5996 return 0; 5997 } 5998 5999 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6000 { 6001 struct si_power_info *si_pi = si_get_pi(rdev); 6002 u32 tmp; 6003 6004 if (si_pi->fan_ctrl_is_in_default_mode) { 6005 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6006 si_pi->fan_ctrl_default_mode = tmp; 6007 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6008 si_pi->t_min = tmp; 6009 si_pi->fan_ctrl_is_in_default_mode = false; 6010 } 6011 6012 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6013 tmp |= TMIN(0); 6014 WREG32(CG_FDO_CTRL2, tmp); 6015 6016 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6017 tmp |= FDO_PWM_MODE(mode); 6018 WREG32(CG_FDO_CTRL2, tmp); 6019 } 6020 6021 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6022 { 6023 struct si_power_info *si_pi = si_get_pi(rdev); 6024 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6025 u32 duty100; 6026 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6027 u16 fdo_min, slope1, slope2; 6028 u32 reference_clock, tmp; 6029 int ret; 6030 u64 tmp64; 6031 6032 if (!si_pi->fan_table_start) { 6033 rdev->pm.dpm.fan.ucode_fan_control = false; 6034 return 0; 6035 } 6036 6037 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6038 6039 if (duty100 == 0) { 6040 rdev->pm.dpm.fan.ucode_fan_control = false; 6041 return 0; 6042 } 6043 6044 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6045 do_div(tmp64, 10000); 6046 fdo_min = (u16)tmp64; 6047 6048 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6049 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6050 6051 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6052 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6053 6054 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6055 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6056 6057 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6058 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6059 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6060 6061 fan_table.slope1 = cpu_to_be16(slope1); 6062 fan_table.slope2 = cpu_to_be16(slope2); 6063 6064 fan_table.fdo_min = cpu_to_be16(fdo_min); 6065 6066 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6067 6068 fan_table.hys_up = cpu_to_be16(1); 6069 6070 fan_table.hys_slope = cpu_to_be16(1); 6071 6072 fan_table.temp_resp_lim = cpu_to_be16(5); 6073 6074 reference_clock = radeon_get_xclk(rdev); 6075 6076 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6077 reference_clock) / 1600); 6078 6079 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6080 6081 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6082 fan_table.temp_src = (uint8_t)tmp; 6083 6084 ret = si_copy_bytes_to_smc(rdev, 6085 si_pi->fan_table_start, 6086 (u8 *)(&fan_table), 6087 sizeof(fan_table), 6088 si_pi->sram_end); 6089 6090 if (ret) { 6091 DRM_ERROR("Failed to load fan table to the SMC."); 6092 rdev->pm.dpm.fan.ucode_fan_control = false; 6093 } 6094 6095 return 0; 6096 } 6097 6098 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6099 { 6100 struct si_power_info *si_pi = si_get_pi(rdev); 6101 PPSMC_Result ret; 6102 6103 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6104 if (ret == PPSMC_Result_OK) { 6105 si_pi->fan_is_controlled_by_smc = true; 6106 return 0; 6107 } else { 6108 return -EINVAL; 6109 } 6110 } 6111 6112 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6113 { 6114 struct si_power_info *si_pi = si_get_pi(rdev); 6115 PPSMC_Result ret; 6116 6117 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6118 6119 if (ret == PPSMC_Result_OK) { 6120 si_pi->fan_is_controlled_by_smc = false; 6121 return 0; 6122 } else { 6123 return -EINVAL; 6124 } 6125 } 6126 6127 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6128 u32 *speed) 6129 { 6130 u32 duty, duty100; 6131 u64 tmp64; 6132 6133 if (rdev->pm.no_fan) 6134 return -ENOENT; 6135 6136 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6137 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6138 6139 if (duty100 == 0) 6140 return -EINVAL; 6141 6142 tmp64 = (u64)duty * 100; 6143 do_div(tmp64, duty100); 6144 *speed = (u32)tmp64; 6145 6146 if (*speed > 100) 6147 *speed = 100; 6148 6149 return 0; 6150 } 6151 6152 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6153 u32 speed) 6154 { 6155 struct si_power_info *si_pi = si_get_pi(rdev); 6156 u32 tmp; 6157 u32 duty, duty100; 6158 u64 tmp64; 6159 6160 if (rdev->pm.no_fan) 6161 return -ENOENT; 6162 6163 if (si_pi->fan_is_controlled_by_smc) 6164 return -EINVAL; 6165 6166 if (speed > 100) 6167 return -EINVAL; 6168 6169 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6170 6171 if (duty100 == 0) 6172 return -EINVAL; 6173 6174 tmp64 = (u64)speed * duty100; 6175 do_div(tmp64, 100); 6176 duty = (u32)tmp64; 6177 6178 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6179 tmp |= FDO_STATIC_DUTY(duty); 6180 WREG32(CG_FDO_CTRL0, tmp); 6181 6182 return 0; 6183 } 6184 6185 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6186 { 6187 if (mode) { 6188 /* stop auto-manage */ 6189 if (rdev->pm.dpm.fan.ucode_fan_control) 6190 si_fan_ctrl_stop_smc_fan_control(rdev); 6191 si_fan_ctrl_set_static_mode(rdev, mode); 6192 } else { 6193 /* restart auto-manage */ 6194 if (rdev->pm.dpm.fan.ucode_fan_control) 6195 si_thermal_start_smc_fan_control(rdev); 6196 else 6197 si_fan_ctrl_set_default_mode(rdev); 6198 } 6199 } 6200 6201 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6202 { 6203 struct si_power_info *si_pi = si_get_pi(rdev); 6204 u32 tmp; 6205 6206 if (si_pi->fan_is_controlled_by_smc) 6207 return 0; 6208 6209 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6210 return (tmp >> FDO_PWM_MODE_SHIFT); 6211 } 6212 6213 #if 0 6214 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6215 u32 *speed) 6216 { 6217 u32 tach_period; 6218 u32 xclk = radeon_get_xclk(rdev); 6219 6220 if (rdev->pm.no_fan) 6221 return -ENOENT; 6222 6223 if (rdev->pm.fan_pulses_per_revolution == 0) 6224 return -ENOENT; 6225 6226 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6227 if (tach_period == 0) 6228 return -ENOENT; 6229 6230 *speed = 60 * xclk * 10000 / tach_period; 6231 6232 return 0; 6233 } 6234 6235 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6236 u32 speed) 6237 { 6238 u32 tach_period, tmp; 6239 u32 xclk = radeon_get_xclk(rdev); 6240 6241 if (rdev->pm.no_fan) 6242 return -ENOENT; 6243 6244 if (rdev->pm.fan_pulses_per_revolution == 0) 6245 return -ENOENT; 6246 6247 if ((speed < rdev->pm.fan_min_rpm) || 6248 (speed > rdev->pm.fan_max_rpm)) 6249 return -EINVAL; 6250 6251 if (rdev->pm.dpm.fan.ucode_fan_control) 6252 si_fan_ctrl_stop_smc_fan_control(rdev); 6253 6254 tach_period = 60 * xclk * 10000 / (8 * speed); 6255 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6256 tmp |= TARGET_PERIOD(tach_period); 6257 WREG32(CG_TACH_CTRL, tmp); 6258 6259 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6260 6261 return 0; 6262 } 6263 #endif 6264 6265 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6266 { 6267 struct si_power_info *si_pi = si_get_pi(rdev); 6268 u32 tmp; 6269 6270 if (!si_pi->fan_ctrl_is_in_default_mode) { 6271 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6272 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6273 WREG32(CG_FDO_CTRL2, tmp); 6274 6275 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6276 tmp |= TMIN(si_pi->t_min); 6277 WREG32(CG_FDO_CTRL2, tmp); 6278 si_pi->fan_ctrl_is_in_default_mode = true; 6279 } 6280 } 6281 6282 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6283 { 6284 if (rdev->pm.dpm.fan.ucode_fan_control) { 6285 si_fan_ctrl_start_smc_fan_control(rdev); 6286 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6287 } 6288 } 6289 6290 static void si_thermal_initialize(struct radeon_device *rdev) 6291 { 6292 u32 tmp; 6293 6294 if (rdev->pm.fan_pulses_per_revolution) { 6295 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6296 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6297 WREG32(CG_TACH_CTRL, tmp); 6298 } 6299 6300 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6301 tmp |= TACH_PWM_RESP_RATE(0x28); 6302 WREG32(CG_FDO_CTRL2, tmp); 6303 } 6304 6305 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6306 { 6307 int ret; 6308 6309 si_thermal_initialize(rdev); 6310 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6311 if (ret) 6312 return ret; 6313 ret = si_thermal_enable_alert(rdev, true); 6314 if (ret) 6315 return ret; 6316 if (rdev->pm.dpm.fan.ucode_fan_control) { 6317 ret = si_halt_smc(rdev); 6318 if (ret) 6319 return ret; 6320 ret = si_thermal_setup_fan_table(rdev); 6321 if (ret) 6322 return ret; 6323 ret = si_resume_smc(rdev); 6324 if (ret) 6325 return ret; 6326 si_thermal_start_smc_fan_control(rdev); 6327 } 6328 6329 return 0; 6330 } 6331 6332 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6333 { 6334 if (!rdev->pm.no_fan) { 6335 si_fan_ctrl_set_default_mode(rdev); 6336 si_fan_ctrl_stop_smc_fan_control(rdev); 6337 } 6338 } 6339 6340 int si_dpm_enable(struct radeon_device *rdev) 6341 { 6342 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6343 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6344 struct si_power_info *si_pi = si_get_pi(rdev); 6345 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6346 int ret; 6347 6348 if (si_is_smc_running(rdev)) 6349 return -EINVAL; 6350 if (pi->voltage_control || si_pi->voltage_control_svi2) 6351 si_enable_voltage_control(rdev, true); 6352 if (pi->mvdd_control) 6353 si_get_mvdd_configuration(rdev); 6354 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6355 ret = si_construct_voltage_tables(rdev); 6356 if (ret) { 6357 DRM_ERROR("si_construct_voltage_tables failed\n"); 6358 return ret; 6359 } 6360 } 6361 if (eg_pi->dynamic_ac_timing) { 6362 ret = si_initialize_mc_reg_table(rdev); 6363 if (ret) 6364 eg_pi->dynamic_ac_timing = false; 6365 } 6366 if (pi->dynamic_ss) 6367 si_enable_spread_spectrum(rdev, true); 6368 if (pi->thermal_protection) 6369 si_enable_thermal_protection(rdev, true); 6370 si_setup_bsp(rdev); 6371 si_program_git(rdev); 6372 si_program_tp(rdev); 6373 si_program_tpp(rdev); 6374 si_program_sstp(rdev); 6375 si_enable_display_gap(rdev); 6376 si_program_vc(rdev); 6377 ret = si_upload_firmware(rdev); 6378 if (ret) { 6379 DRM_ERROR("si_upload_firmware failed\n"); 6380 return ret; 6381 } 6382 ret = si_process_firmware_header(rdev); 6383 if (ret) { 6384 DRM_ERROR("si_process_firmware_header failed\n"); 6385 return ret; 6386 } 6387 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6388 if (ret) { 6389 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6390 return ret; 6391 } 6392 ret = si_init_smc_table(rdev); 6393 if (ret) { 6394 DRM_ERROR("si_init_smc_table failed\n"); 6395 return ret; 6396 } 6397 ret = si_init_smc_spll_table(rdev); 6398 if (ret) { 6399 DRM_ERROR("si_init_smc_spll_table failed\n"); 6400 return ret; 6401 } 6402 ret = si_init_arb_table_index(rdev); 6403 if (ret) { 6404 DRM_ERROR("si_init_arb_table_index failed\n"); 6405 return ret; 6406 } 6407 if (eg_pi->dynamic_ac_timing) { 6408 ret = si_populate_mc_reg_table(rdev, boot_ps); 6409 if (ret) { 6410 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6411 return ret; 6412 } 6413 } 6414 ret = si_initialize_smc_cac_tables(rdev); 6415 if (ret) { 6416 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6417 return ret; 6418 } 6419 ret = si_initialize_hardware_cac_manager(rdev); 6420 if (ret) { 6421 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6422 return ret; 6423 } 6424 ret = si_initialize_smc_dte_tables(rdev); 6425 if (ret) { 6426 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6427 return ret; 6428 } 6429 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6430 if (ret) { 6431 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6432 return ret; 6433 } 6434 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6435 if (ret) { 6436 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6437 return ret; 6438 } 6439 si_program_response_times(rdev); 6440 si_program_ds_registers(rdev); 6441 si_dpm_start_smc(rdev); 6442 ret = si_notify_smc_display_change(rdev, false); 6443 if (ret) { 6444 DRM_ERROR("si_notify_smc_display_change failed\n"); 6445 return ret; 6446 } 6447 si_enable_sclk_control(rdev, true); 6448 si_start_dpm(rdev); 6449 6450 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6451 6452 si_thermal_start_thermal_controller(rdev); 6453 6454 ni_update_current_ps(rdev, boot_ps); 6455 6456 return 0; 6457 } 6458 6459 static int si_set_temperature_range(struct radeon_device *rdev) 6460 { 6461 int ret; 6462 6463 ret = si_thermal_enable_alert(rdev, false); 6464 if (ret) 6465 return ret; 6466 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6467 if (ret) 6468 return ret; 6469 ret = si_thermal_enable_alert(rdev, true); 6470 if (ret) 6471 return ret; 6472 6473 return ret; 6474 } 6475 6476 int si_dpm_late_enable(struct radeon_device *rdev) 6477 { 6478 int ret; 6479 6480 ret = si_set_temperature_range(rdev); 6481 if (ret) 6482 return ret; 6483 6484 return ret; 6485 } 6486 6487 void si_dpm_disable(struct radeon_device *rdev) 6488 { 6489 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6490 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6491 6492 if (!si_is_smc_running(rdev)) 6493 return; 6494 si_thermal_stop_thermal_controller(rdev); 6495 si_disable_ulv(rdev); 6496 si_clear_vc(rdev); 6497 if (pi->thermal_protection) 6498 si_enable_thermal_protection(rdev, false); 6499 si_enable_power_containment(rdev, boot_ps, false); 6500 si_enable_smc_cac(rdev, boot_ps, false); 6501 si_enable_spread_spectrum(rdev, false); 6502 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6503 si_stop_dpm(rdev); 6504 si_reset_to_default(rdev); 6505 si_dpm_stop_smc(rdev); 6506 si_force_switch_to_arb_f0(rdev); 6507 6508 ni_update_current_ps(rdev, boot_ps); 6509 } 6510 6511 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6512 { 6513 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6514 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6515 struct radeon_ps *new_ps = &requested_ps; 6516 6517 ni_update_requested_ps(rdev, new_ps); 6518 6519 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6520 6521 return 0; 6522 } 6523 6524 static int si_power_control_set_level(struct radeon_device *rdev) 6525 { 6526 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6527 int ret; 6528 6529 ret = si_restrict_performance_levels_before_switch(rdev); 6530 if (ret) 6531 return ret; 6532 ret = si_halt_smc(rdev); 6533 if (ret) 6534 return ret; 6535 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6536 if (ret) 6537 return ret; 6538 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6539 if (ret) 6540 return ret; 6541 ret = si_resume_smc(rdev); 6542 if (ret) 6543 return ret; 6544 ret = si_set_sw_state(rdev); 6545 if (ret) 6546 return ret; 6547 return 0; 6548 } 6549 6550 int si_dpm_set_power_state(struct radeon_device *rdev) 6551 { 6552 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6553 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6554 struct radeon_ps *old_ps = &eg_pi->current_rps; 6555 int ret; 6556 6557 ret = si_disable_ulv(rdev); 6558 if (ret) { 6559 DRM_ERROR("si_disable_ulv failed\n"); 6560 return ret; 6561 } 6562 ret = si_restrict_performance_levels_before_switch(rdev); 6563 if (ret) { 6564 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6565 return ret; 6566 } 6567 if (eg_pi->pcie_performance_request) 6568 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6569 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6570 ret = si_enable_power_containment(rdev, new_ps, false); 6571 if (ret) { 6572 DRM_ERROR("si_enable_power_containment failed\n"); 6573 return ret; 6574 } 6575 ret = si_enable_smc_cac(rdev, new_ps, false); 6576 if (ret) { 6577 DRM_ERROR("si_enable_smc_cac failed\n"); 6578 return ret; 6579 } 6580 ret = si_halt_smc(rdev); 6581 if (ret) { 6582 DRM_ERROR("si_halt_smc failed\n"); 6583 return ret; 6584 } 6585 ret = si_upload_sw_state(rdev, new_ps); 6586 if (ret) { 6587 DRM_ERROR("si_upload_sw_state failed\n"); 6588 return ret; 6589 } 6590 ret = si_upload_smc_data(rdev); 6591 if (ret) { 6592 DRM_ERROR("si_upload_smc_data failed\n"); 6593 return ret; 6594 } 6595 ret = si_upload_ulv_state(rdev); 6596 if (ret) { 6597 DRM_ERROR("si_upload_ulv_state failed\n"); 6598 return ret; 6599 } 6600 if (eg_pi->dynamic_ac_timing) { 6601 ret = si_upload_mc_reg_table(rdev, new_ps); 6602 if (ret) { 6603 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6604 return ret; 6605 } 6606 } 6607 ret = si_program_memory_timing_parameters(rdev, new_ps); 6608 if (ret) { 6609 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6610 return ret; 6611 } 6612 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6613 6614 ret = si_resume_smc(rdev); 6615 if (ret) { 6616 DRM_ERROR("si_resume_smc failed\n"); 6617 return ret; 6618 } 6619 ret = si_set_sw_state(rdev); 6620 if (ret) { 6621 DRM_ERROR("si_set_sw_state failed\n"); 6622 return ret; 6623 } 6624 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6625 si_set_vce_clock(rdev, new_ps, old_ps); 6626 if (eg_pi->pcie_performance_request) 6627 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6628 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6629 if (ret) { 6630 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6631 return ret; 6632 } 6633 ret = si_enable_smc_cac(rdev, new_ps, true); 6634 if (ret) { 6635 DRM_ERROR("si_enable_smc_cac failed\n"); 6636 return ret; 6637 } 6638 ret = si_enable_power_containment(rdev, new_ps, true); 6639 if (ret) { 6640 DRM_ERROR("si_enable_power_containment failed\n"); 6641 return ret; 6642 } 6643 6644 ret = si_power_control_set_level(rdev); 6645 if (ret) { 6646 DRM_ERROR("si_power_control_set_level failed\n"); 6647 return ret; 6648 } 6649 6650 return 0; 6651 } 6652 6653 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6654 { 6655 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6656 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6657 6658 ni_update_current_ps(rdev, new_ps); 6659 } 6660 6661 #if 0 6662 void si_dpm_reset_asic(struct radeon_device *rdev) 6663 { 6664 si_restrict_performance_levels_before_switch(rdev); 6665 si_disable_ulv(rdev); 6666 si_set_boot_state(rdev); 6667 } 6668 #endif 6669 6670 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6671 { 6672 si_program_display_gap(rdev); 6673 } 6674 6675 union power_info { 6676 struct _ATOM_POWERPLAY_INFO info; 6677 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6678 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6679 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6680 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6681 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6682 }; 6683 6684 union pplib_clock_info { 6685 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6686 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6687 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6688 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6689 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6690 }; 6691 6692 union pplib_power_state { 6693 struct _ATOM_PPLIB_STATE v1; 6694 struct _ATOM_PPLIB_STATE_V2 v2; 6695 }; 6696 6697 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6698 struct radeon_ps *rps, 6699 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6700 u8 table_rev) 6701 { 6702 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6703 rps->class = le16_to_cpu(non_clock_info->usClassification); 6704 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6705 6706 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6707 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6708 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6709 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6710 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6711 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6712 } else { 6713 rps->vclk = 0; 6714 rps->dclk = 0; 6715 } 6716 6717 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6718 rdev->pm.dpm.boot_ps = rps; 6719 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6720 rdev->pm.dpm.uvd_ps = rps; 6721 } 6722 6723 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6724 struct radeon_ps *rps, int index, 6725 union pplib_clock_info *clock_info) 6726 { 6727 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6728 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6729 struct si_power_info *si_pi = si_get_pi(rdev); 6730 struct ni_ps *ps = ni_get_ps(rps); 6731 u16 leakage_voltage; 6732 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6733 int ret; 6734 6735 ps->performance_level_count = index + 1; 6736 6737 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6738 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6739 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6740 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6741 6742 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6743 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6744 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6745 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6746 si_pi->sys_pcie_mask, 6747 si_pi->boot_pcie_gen, 6748 clock_info->si.ucPCIEGen); 6749 6750 /* patch up vddc if necessary */ 6751 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6752 &leakage_voltage); 6753 if (ret == 0) 6754 pl->vddc = leakage_voltage; 6755 6756 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6757 pi->acpi_vddc = pl->vddc; 6758 eg_pi->acpi_vddci = pl->vddci; 6759 si_pi->acpi_pcie_gen = pl->pcie_gen; 6760 } 6761 6762 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6763 index == 0) { 6764 /* XXX disable for A0 tahiti */ 6765 si_pi->ulv.supported = false; 6766 si_pi->ulv.pl = *pl; 6767 si_pi->ulv.one_pcie_lane_in_ulv = false; 6768 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6769 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6770 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6771 } 6772 6773 if (pi->min_vddc_in_table > pl->vddc) 6774 pi->min_vddc_in_table = pl->vddc; 6775 6776 if (pi->max_vddc_in_table < pl->vddc) 6777 pi->max_vddc_in_table = pl->vddc; 6778 6779 /* patch up boot state */ 6780 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6781 u16 vddc, vddci, mvdd; 6782 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6783 pl->mclk = rdev->clock.default_mclk; 6784 pl->sclk = rdev->clock.default_sclk; 6785 pl->vddc = vddc; 6786 pl->vddci = vddci; 6787 si_pi->mvdd_bootup_value = mvdd; 6788 } 6789 6790 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6791 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6792 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6793 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6794 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6795 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6796 } 6797 } 6798 6799 static int si_parse_power_table(struct radeon_device *rdev) 6800 { 6801 struct radeon_mode_info *mode_info = &rdev->mode_info; 6802 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6803 union pplib_power_state *power_state; 6804 int i, j, k, non_clock_array_index, clock_array_index; 6805 union pplib_clock_info *clock_info; 6806 struct _StateArray *state_array; 6807 struct _ClockInfoArray *clock_info_array; 6808 struct _NonClockInfoArray *non_clock_info_array; 6809 union power_info *power_info; 6810 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6811 u16 data_offset; 6812 u8 frev, crev; 6813 u8 *power_state_offset; 6814 struct ni_ps *ps; 6815 6816 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6817 &frev, &crev, &data_offset)) 6818 return -EINVAL; 6819 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6820 6821 state_array = (struct _StateArray *) 6822 (mode_info->atom_context->bios + data_offset + 6823 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6824 clock_info_array = (struct _ClockInfoArray *) 6825 (mode_info->atom_context->bios + data_offset + 6826 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6827 non_clock_info_array = (struct _NonClockInfoArray *) 6828 (mode_info->atom_context->bios + data_offset + 6829 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6830 6831 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6832 state_array->ucNumEntries, GFP_KERNEL); 6833 if (!rdev->pm.dpm.ps) 6834 return -ENOMEM; 6835 power_state_offset = (u8 *)state_array->states; 6836 for (i = 0; i < state_array->ucNumEntries; i++) { 6837 u8 *idx; 6838 power_state = (union pplib_power_state *)power_state_offset; 6839 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6840 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6841 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6842 if (!rdev->pm.power_state[i].clock_info) 6843 return -EINVAL; 6844 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6845 if (ps == NULL) { 6846 kfree(rdev->pm.dpm.ps); 6847 return -ENOMEM; 6848 } 6849 rdev->pm.dpm.ps[i].ps_priv = ps; 6850 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6851 non_clock_info, 6852 non_clock_info_array->ucEntrySize); 6853 k = 0; 6854 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6855 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6856 clock_array_index = idx[j]; 6857 if (clock_array_index >= clock_info_array->ucNumEntries) 6858 continue; 6859 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6860 break; 6861 clock_info = (union pplib_clock_info *) 6862 ((u8 *)&clock_info_array->clockInfo[0] + 6863 (clock_array_index * clock_info_array->ucEntrySize)); 6864 si_parse_pplib_clock_info(rdev, 6865 &rdev->pm.dpm.ps[i], k, 6866 clock_info); 6867 k++; 6868 } 6869 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6870 } 6871 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6872 6873 /* fill in the vce power states */ 6874 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6875 u32 sclk, mclk; 6876 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6877 clock_info = (union pplib_clock_info *) 6878 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6879 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6880 sclk |= clock_info->si.ucEngineClockHigh << 16; 6881 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6882 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6883 rdev->pm.dpm.vce_states[i].sclk = sclk; 6884 rdev->pm.dpm.vce_states[i].mclk = mclk; 6885 } 6886 6887 return 0; 6888 } 6889 6890 int si_dpm_init(struct radeon_device *rdev) 6891 { 6892 struct rv7xx_power_info *pi; 6893 struct evergreen_power_info *eg_pi; 6894 struct ni_power_info *ni_pi; 6895 struct si_power_info *si_pi; 6896 struct atom_clock_dividers dividers; 6897 int ret; 6898 u32 mask; 6899 6900 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6901 if (si_pi == NULL) 6902 return -ENOMEM; 6903 rdev->pm.dpm.priv = si_pi; 6904 ni_pi = &si_pi->ni; 6905 eg_pi = &ni_pi->eg; 6906 pi = &eg_pi->rv7xx; 6907 6908 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6909 if (ret) 6910 si_pi->sys_pcie_mask = 0; 6911 else 6912 si_pi->sys_pcie_mask = mask; 6913 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6914 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6915 6916 si_set_max_cu_value(rdev); 6917 6918 rv770_get_max_vddc(rdev); 6919 si_get_leakage_vddc(rdev); 6920 si_patch_dependency_tables_based_on_leakage(rdev); 6921 6922 pi->acpi_vddc = 0; 6923 eg_pi->acpi_vddci = 0; 6924 pi->min_vddc_in_table = 0; 6925 pi->max_vddc_in_table = 0; 6926 6927 ret = r600_get_platform_caps(rdev); 6928 if (ret) 6929 return ret; 6930 6931 ret = r600_parse_extended_power_table(rdev); 6932 if (ret) 6933 return ret; 6934 6935 ret = si_parse_power_table(rdev); 6936 if (ret) 6937 return ret; 6938 6939 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6940 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6941 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6942 r600_free_extended_power_table(rdev); 6943 return -ENOMEM; 6944 } 6945 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6946 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6947 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6948 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6949 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6953 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6954 6955 if (rdev->pm.dpm.voltage_response_time == 0) 6956 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6957 if (rdev->pm.dpm.backbias_response_time == 0) 6958 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6959 6960 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6961 0, false, ÷rs); 6962 if (ret) 6963 pi->ref_div = dividers.ref_div + 1; 6964 else 6965 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6966 6967 eg_pi->smu_uvd_hs = false; 6968 6969 pi->mclk_strobe_mode_threshold = 40000; 6970 if (si_is_special_1gb_platform(rdev)) 6971 pi->mclk_stutter_mode_threshold = 0; 6972 else 6973 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6974 pi->mclk_edc_enable_threshold = 40000; 6975 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6976 6977 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6978 6979 pi->voltage_control = 6980 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6981 VOLTAGE_OBJ_GPIO_LUT); 6982 if (!pi->voltage_control) { 6983 si_pi->voltage_control_svi2 = 6984 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6985 VOLTAGE_OBJ_SVID2); 6986 if (si_pi->voltage_control_svi2) 6987 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6988 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6989 } 6990 6991 pi->mvdd_control = 6992 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6993 VOLTAGE_OBJ_GPIO_LUT); 6994 6995 eg_pi->vddci_control = 6996 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6997 VOLTAGE_OBJ_GPIO_LUT); 6998 if (!eg_pi->vddci_control) 6999 si_pi->vddci_control_svi2 = 7000 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7001 VOLTAGE_OBJ_SVID2); 7002 7003 si_pi->vddc_phase_shed_control = 7004 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7005 VOLTAGE_OBJ_PHASE_LUT); 7006 7007 rv770_get_engine_memory_ss(rdev); 7008 7009 pi->asi = RV770_ASI_DFLT; 7010 pi->pasi = CYPRESS_HASI_DFLT; 7011 pi->vrc = SISLANDS_VRC_DFLT; 7012 7013 pi->gfx_clock_gating = true; 7014 7015 eg_pi->sclk_deep_sleep = true; 7016 si_pi->sclk_deep_sleep_above_low = false; 7017 7018 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7019 pi->thermal_protection = true; 7020 else 7021 pi->thermal_protection = false; 7022 7023 eg_pi->dynamic_ac_timing = true; 7024 7025 eg_pi->light_sleep = true; 7026 #if defined(CONFIG_ACPI) 7027 eg_pi->pcie_performance_request = 7028 radeon_acpi_is_pcie_performance_request_supported(rdev); 7029 #else 7030 eg_pi->pcie_performance_request = false; 7031 #endif 7032 7033 si_pi->sram_end = SMC_RAM_END; 7034 7035 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7036 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7037 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7038 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7039 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7040 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7041 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7042 7043 si_initialize_powertune_defaults(rdev); 7044 7045 /* make sure dc limits are valid */ 7046 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7047 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7048 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7049 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7050 7051 si_pi->fan_ctrl_is_in_default_mode = true; 7052 7053 return 0; 7054 } 7055 7056 void si_dpm_fini(struct radeon_device *rdev) 7057 { 7058 int i; 7059 7060 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7061 kfree(rdev->pm.dpm.ps[i].ps_priv); 7062 } 7063 kfree(rdev->pm.dpm.ps); 7064 kfree(rdev->pm.dpm.priv); 7065 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7066 r600_free_extended_power_table(rdev); 7067 } 7068 7069 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7070 struct seq_file *m) 7071 { 7072 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7073 struct radeon_ps *rps = &eg_pi->current_rps; 7074 struct ni_ps *ps = ni_get_ps(rps); 7075 struct rv7xx_pl *pl; 7076 u32 current_index = 7077 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7078 CURRENT_STATE_INDEX_SHIFT; 7079 7080 if (current_index >= ps->performance_level_count) { 7081 seq_printf(m, "invalid dpm profile %d\n", current_index); 7082 } else { 7083 pl = &ps->performance_levels[current_index]; 7084 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7085 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7086 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7087 } 7088 } 7089 7090 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7091 { 7092 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7093 struct radeon_ps *rps = &eg_pi->current_rps; 7094 struct ni_ps *ps = ni_get_ps(rps); 7095 struct rv7xx_pl *pl; 7096 u32 current_index = 7097 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7098 CURRENT_STATE_INDEX_SHIFT; 7099 7100 if (current_index >= ps->performance_level_count) { 7101 return 0; 7102 } else { 7103 pl = &ps->performance_levels[current_index]; 7104 return pl->sclk; 7105 } 7106 } 7107 7108 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7109 { 7110 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7111 struct radeon_ps *rps = &eg_pi->current_rps; 7112 struct ni_ps *ps = ni_get_ps(rps); 7113 struct rv7xx_pl *pl; 7114 u32 current_index = 7115 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7116 CURRENT_STATE_INDEX_SHIFT; 7117 7118 if (current_index >= ps->performance_level_count) { 7119 return 0; 7120 } else { 7121 pl = &ps->performance_levels[current_index]; 7122 return pl->mclk; 7123 } 7124 } 7125