1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 #if 0 /* unused */ 255 static const struct si_dte_data dte_data_tahiti_le = 256 { 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271 }; 272 #endif 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 static int si_populate_voltage_value(struct radeon_device *rdev, 1745 const struct atom_voltage_table *table, 1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1747 static int si_get_std_voltage_value(struct radeon_device *rdev, 1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1749 u16 *std_voltage); 1750 static int si_write_smc_soft_register(struct radeon_device *rdev, 1751 u16 reg_offset, u32 value); 1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1753 struct rv7xx_pl *pl, 1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1755 static int si_calculate_sclk_params(struct radeon_device *rdev, 1756 u32 engine_clock, 1757 SISLANDS_SMC_SCLK_VALUE *sclk); 1758 1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1760 { 1761 struct si_power_info *pi = rdev->pm.dpm.priv; 1762 1763 return pi; 1764 } 1765 1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1767 u16 v, s32 t, u32 ileakage, u32 *leakage) 1768 { 1769 s64 kt, kv, leakage_w, i_leakage, vddc; 1770 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1771 s64 tmp; 1772 1773 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1774 vddc = div64_s64(drm_int2fixp(v), 1000); 1775 temperature = div64_s64(drm_int2fixp(t), 1000); 1776 1777 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1778 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1779 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1780 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1781 t_ref = drm_int2fixp(coeff->t_ref); 1782 1783 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1784 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1785 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1786 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1787 1788 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1789 1790 *leakage = drm_fixp2int(leakage_w * 1000); 1791 } 1792 1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1794 const struct ni_leakage_coeffients *coeff, 1795 u16 v, 1796 s32 t, 1797 u32 i_leakage, 1798 u32 *leakage) 1799 { 1800 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1801 } 1802 1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1804 const u32 fixed_kt, u16 v, 1805 u32 ileakage, u32 *leakage) 1806 { 1807 s64 kt, kv, leakage_w, i_leakage, vddc; 1808 1809 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1810 vddc = div64_s64(drm_int2fixp(v), 1000); 1811 1812 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1813 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1814 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1815 1816 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1817 1818 *leakage = drm_fixp2int(leakage_w * 1000); 1819 } 1820 1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1822 const struct ni_leakage_coeffients *coeff, 1823 const u32 fixed_kt, 1824 u16 v, 1825 u32 i_leakage, 1826 u32 *leakage) 1827 { 1828 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1829 } 1830 1831 1832 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1833 struct si_dte_data *dte_data) 1834 { 1835 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1836 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1837 u32 k = dte_data->k; 1838 u32 t_max = dte_data->max_t; 1839 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1840 u32 t_0 = dte_data->t0; 1841 u32 i; 1842 1843 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1844 dte_data->tdep_count = 3; 1845 1846 for (i = 0; i < k; i++) { 1847 dte_data->r[i] = 1848 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1849 (p_limit2 * (u32)100); 1850 } 1851 1852 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1853 1854 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1855 dte_data->tdep_r[i] = dte_data->r[4]; 1856 } 1857 } else { 1858 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1859 } 1860 } 1861 1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1863 { 1864 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1865 struct si_power_info *si_pi = si_get_pi(rdev); 1866 bool update_dte_from_pl2 = false; 1867 1868 if (rdev->family == CHIP_TAHITI) { 1869 si_pi->cac_weights = cac_weights_tahiti; 1870 si_pi->lcac_config = lcac_tahiti; 1871 si_pi->cac_override = cac_override_tahiti; 1872 si_pi->powertune_data = &powertune_data_tahiti; 1873 si_pi->dte_data = dte_data_tahiti; 1874 1875 switch (rdev->pdev->device) { 1876 case 0x6798: 1877 si_pi->dte_data.enable_dte_by_default = true; 1878 break; 1879 case 0x6799: 1880 si_pi->dte_data = dte_data_new_zealand; 1881 break; 1882 case 0x6790: 1883 case 0x6791: 1884 case 0x6792: 1885 case 0x679E: 1886 si_pi->dte_data = dte_data_aruba_pro; 1887 update_dte_from_pl2 = true; 1888 break; 1889 case 0x679B: 1890 si_pi->dte_data = dte_data_malta; 1891 update_dte_from_pl2 = true; 1892 break; 1893 case 0x679A: 1894 si_pi->dte_data = dte_data_tahiti_pro; 1895 update_dte_from_pl2 = true; 1896 break; 1897 default: 1898 if (si_pi->dte_data.enable_dte_by_default == true) 1899 DRM_ERROR("DTE is not enabled!\n"); 1900 break; 1901 } 1902 } else if (rdev->family == CHIP_PITCAIRN) { 1903 switch (rdev->pdev->device) { 1904 case 0x6810: 1905 case 0x6818: 1906 si_pi->cac_weights = cac_weights_pitcairn; 1907 si_pi->lcac_config = lcac_pitcairn; 1908 si_pi->cac_override = cac_override_pitcairn; 1909 si_pi->powertune_data = &powertune_data_pitcairn; 1910 si_pi->dte_data = dte_data_curacao_xt; 1911 update_dte_from_pl2 = true; 1912 break; 1913 case 0x6819: 1914 case 0x6811: 1915 si_pi->cac_weights = cac_weights_pitcairn; 1916 si_pi->lcac_config = lcac_pitcairn; 1917 si_pi->cac_override = cac_override_pitcairn; 1918 si_pi->powertune_data = &powertune_data_pitcairn; 1919 si_pi->dte_data = dte_data_curacao_pro; 1920 update_dte_from_pl2 = true; 1921 break; 1922 case 0x6800: 1923 case 0x6806: 1924 si_pi->cac_weights = cac_weights_pitcairn; 1925 si_pi->lcac_config = lcac_pitcairn; 1926 si_pi->cac_override = cac_override_pitcairn; 1927 si_pi->powertune_data = &powertune_data_pitcairn; 1928 si_pi->dte_data = dte_data_neptune_xt; 1929 update_dte_from_pl2 = true; 1930 break; 1931 default: 1932 si_pi->cac_weights = cac_weights_pitcairn; 1933 si_pi->lcac_config = lcac_pitcairn; 1934 si_pi->cac_override = cac_override_pitcairn; 1935 si_pi->powertune_data = &powertune_data_pitcairn; 1936 si_pi->dte_data = dte_data_pitcairn; 1937 break; 1938 } 1939 } else if (rdev->family == CHIP_VERDE) { 1940 si_pi->lcac_config = lcac_cape_verde; 1941 si_pi->cac_override = cac_override_cape_verde; 1942 si_pi->powertune_data = &powertune_data_cape_verde; 1943 1944 switch (rdev->pdev->device) { 1945 case 0x683B: 1946 case 0x683F: 1947 case 0x6829: 1948 case 0x6835: 1949 si_pi->cac_weights = cac_weights_cape_verde_pro; 1950 si_pi->dte_data = dte_data_cape_verde; 1951 break; 1952 case 0x682C: 1953 si_pi->cac_weights = cac_weights_cape_verde_pro; 1954 si_pi->dte_data = dte_data_sun_xt; 1955 break; 1956 case 0x6825: 1957 case 0x6827: 1958 si_pi->cac_weights = cac_weights_heathrow; 1959 si_pi->dte_data = dte_data_cape_verde; 1960 break; 1961 case 0x6824: 1962 case 0x682D: 1963 si_pi->cac_weights = cac_weights_chelsea_xt; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x682F: 1967 si_pi->cac_weights = cac_weights_chelsea_pro; 1968 si_pi->dte_data = dte_data_cape_verde; 1969 break; 1970 case 0x6820: 1971 si_pi->cac_weights = cac_weights_heathrow; 1972 si_pi->dte_data = dte_data_venus_xtx; 1973 break; 1974 case 0x6821: 1975 si_pi->cac_weights = cac_weights_heathrow; 1976 si_pi->dte_data = dte_data_venus_xt; 1977 break; 1978 case 0x6823: 1979 case 0x682B: 1980 case 0x6822: 1981 case 0x682A: 1982 si_pi->cac_weights = cac_weights_chelsea_pro; 1983 si_pi->dte_data = dte_data_venus_pro; 1984 break; 1985 default: 1986 si_pi->cac_weights = cac_weights_cape_verde; 1987 si_pi->dte_data = dte_data_cape_verde; 1988 break; 1989 } 1990 } else if (rdev->family == CHIP_OLAND) { 1991 switch (rdev->pdev->device) { 1992 case 0x6601: 1993 case 0x6621: 1994 case 0x6603: 1995 case 0x6605: 1996 si_pi->cac_weights = cac_weights_mars_pro; 1997 si_pi->lcac_config = lcac_mars_pro; 1998 si_pi->cac_override = cac_override_oland; 1999 si_pi->powertune_data = &powertune_data_mars_pro; 2000 si_pi->dte_data = dte_data_mars_pro; 2001 update_dte_from_pl2 = true; 2002 break; 2003 case 0x6600: 2004 case 0x6606: 2005 case 0x6620: 2006 case 0x6604: 2007 si_pi->cac_weights = cac_weights_mars_xt; 2008 si_pi->lcac_config = lcac_mars_pro; 2009 si_pi->cac_override = cac_override_oland; 2010 si_pi->powertune_data = &powertune_data_mars_pro; 2011 si_pi->dte_data = dte_data_mars_pro; 2012 update_dte_from_pl2 = true; 2013 break; 2014 case 0x6611: 2015 case 0x6613: 2016 case 0x6608: 2017 si_pi->cac_weights = cac_weights_oland_pro; 2018 si_pi->lcac_config = lcac_mars_pro; 2019 si_pi->cac_override = cac_override_oland; 2020 si_pi->powertune_data = &powertune_data_mars_pro; 2021 si_pi->dte_data = dte_data_mars_pro; 2022 update_dte_from_pl2 = true; 2023 break; 2024 case 0x6610: 2025 si_pi->cac_weights = cac_weights_oland_xt; 2026 si_pi->lcac_config = lcac_mars_pro; 2027 si_pi->cac_override = cac_override_oland; 2028 si_pi->powertune_data = &powertune_data_mars_pro; 2029 si_pi->dte_data = dte_data_mars_pro; 2030 update_dte_from_pl2 = true; 2031 break; 2032 default: 2033 si_pi->cac_weights = cac_weights_oland; 2034 si_pi->lcac_config = lcac_oland; 2035 si_pi->cac_override = cac_override_oland; 2036 si_pi->powertune_data = &powertune_data_oland; 2037 si_pi->dte_data = dte_data_oland; 2038 break; 2039 } 2040 } else if (rdev->family == CHIP_HAINAN) { 2041 si_pi->cac_weights = cac_weights_hainan; 2042 si_pi->lcac_config = lcac_oland; 2043 si_pi->cac_override = cac_override_oland; 2044 si_pi->powertune_data = &powertune_data_hainan; 2045 si_pi->dte_data = dte_data_sun_xt; 2046 update_dte_from_pl2 = true; 2047 } else { 2048 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2049 return; 2050 } 2051 2052 ni_pi->enable_power_containment = false; 2053 ni_pi->enable_cac = false; 2054 ni_pi->enable_sq_ramping = false; 2055 si_pi->enable_dte = false; 2056 2057 if (si_pi->powertune_data->enable_powertune_by_default) { 2058 ni_pi->enable_power_containment= true; 2059 ni_pi->enable_cac = true; 2060 if (si_pi->dte_data.enable_dte_by_default) { 2061 si_pi->enable_dte = true; 2062 if (update_dte_from_pl2) 2063 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2064 2065 } 2066 ni_pi->enable_sq_ramping = true; 2067 } 2068 2069 ni_pi->driver_calculate_cac_leakage = true; 2070 ni_pi->cac_configuration_required = true; 2071 2072 if (ni_pi->cac_configuration_required) { 2073 ni_pi->support_cac_long_term_average = true; 2074 si_pi->dyn_powertune_data.l2_lta_window_size = 2075 si_pi->powertune_data->l2_lta_window_size_default; 2076 si_pi->dyn_powertune_data.lts_truncate = 2077 si_pi->powertune_data->lts_truncate_default; 2078 } else { 2079 ni_pi->support_cac_long_term_average = false; 2080 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2081 si_pi->dyn_powertune_data.lts_truncate = 0; 2082 } 2083 2084 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2085 } 2086 2087 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2088 { 2089 return 1; 2090 } 2091 2092 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2093 { 2094 u32 xclk; 2095 u32 wintime; 2096 u32 cac_window; 2097 u32 cac_window_size; 2098 2099 xclk = radeon_get_xclk(rdev); 2100 2101 if (xclk == 0) 2102 return 0; 2103 2104 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2105 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2106 2107 wintime = (cac_window_size * 100) / xclk; 2108 2109 return wintime; 2110 } 2111 2112 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2113 { 2114 return power_in_watts; 2115 } 2116 2117 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2118 bool adjust_polarity, 2119 u32 tdp_adjustment, 2120 u32 *tdp_limit, 2121 u32 *near_tdp_limit) 2122 { 2123 u32 adjustment_delta, max_tdp_limit; 2124 2125 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2126 return -EINVAL; 2127 2128 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2129 2130 if (adjust_polarity) { 2131 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2132 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2133 } else { 2134 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2135 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2136 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2138 else 2139 *near_tdp_limit = 0; 2140 } 2141 2142 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2143 return -EINVAL; 2144 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2145 return -EINVAL; 2146 2147 return 0; 2148 } 2149 2150 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2151 struct radeon_ps *radeon_state) 2152 { 2153 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2154 struct si_power_info *si_pi = si_get_pi(rdev); 2155 2156 if (ni_pi->enable_power_containment) { 2157 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2158 PP_SIslands_PAPMParameters *papm_parm; 2159 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2160 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2161 u32 tdp_limit; 2162 u32 near_tdp_limit; 2163 int ret; 2164 2165 if (scaling_factor == 0) 2166 return -EINVAL; 2167 2168 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2169 2170 ret = si_calculate_adjusted_tdp_limits(rdev, 2171 false, /* ??? */ 2172 rdev->pm.dpm.tdp_adjustment, 2173 &tdp_limit, 2174 &near_tdp_limit); 2175 if (ret) 2176 return ret; 2177 2178 smc_table->dpm2Params.TDPLimit = 2179 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2180 smc_table->dpm2Params.NearTDPLimit = 2181 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2182 smc_table->dpm2Params.SafePowerLimit = 2183 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2184 2185 ret = si_copy_bytes_to_smc(rdev, 2186 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2187 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2188 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2189 sizeof(u32) * 3, 2190 si_pi->sram_end); 2191 if (ret) 2192 return ret; 2193 2194 if (si_pi->enable_ppm) { 2195 papm_parm = &si_pi->papm_parm; 2196 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2197 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2198 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2199 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2200 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2201 papm_parm->PlatformPowerLimit = 0xffffffff; 2202 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2203 2204 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2205 (u8 *)papm_parm, 2206 sizeof(PP_SIslands_PAPMParameters), 2207 si_pi->sram_end); 2208 if (ret) 2209 return ret; 2210 } 2211 } 2212 return 0; 2213 } 2214 2215 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2216 struct radeon_ps *radeon_state) 2217 { 2218 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2219 struct si_power_info *si_pi = si_get_pi(rdev); 2220 2221 if (ni_pi->enable_power_containment) { 2222 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2223 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2224 int ret; 2225 2226 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2227 2228 smc_table->dpm2Params.NearTDPLimit = 2229 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2230 smc_table->dpm2Params.SafePowerLimit = 2231 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2232 2233 ret = si_copy_bytes_to_smc(rdev, 2234 (si_pi->state_table_start + 2235 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2236 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2237 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2238 sizeof(u32) * 2, 2239 si_pi->sram_end); 2240 if (ret) 2241 return ret; 2242 } 2243 2244 return 0; 2245 } 2246 2247 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2248 const u16 prev_std_vddc, 2249 const u16 curr_std_vddc) 2250 { 2251 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2252 u64 prev_vddc = (u64)prev_std_vddc; 2253 u64 curr_vddc = (u64)curr_std_vddc; 2254 u64 pwr_efficiency_ratio, n, d; 2255 2256 if ((prev_vddc == 0) || (curr_vddc == 0)) 2257 return 0; 2258 2259 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2260 d = prev_vddc * prev_vddc; 2261 pwr_efficiency_ratio = div64_u64(n, d); 2262 2263 if (pwr_efficiency_ratio > (u64)0xFFFF) 2264 return 0; 2265 2266 return (u16)pwr_efficiency_ratio; 2267 } 2268 2269 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2270 struct radeon_ps *radeon_state) 2271 { 2272 struct si_power_info *si_pi = si_get_pi(rdev); 2273 2274 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2275 radeon_state->vclk && radeon_state->dclk) 2276 return true; 2277 2278 return false; 2279 } 2280 2281 static int si_populate_power_containment_values(struct radeon_device *rdev, 2282 struct radeon_ps *radeon_state, 2283 SISLANDS_SMC_SWSTATE *smc_state) 2284 { 2285 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2286 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2287 struct ni_ps *state = ni_get_ps(radeon_state); 2288 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2289 u32 prev_sclk; 2290 u32 max_sclk; 2291 u32 min_sclk; 2292 u16 prev_std_vddc; 2293 u16 curr_std_vddc; 2294 int i; 2295 u16 pwr_efficiency_ratio; 2296 u8 max_ps_percent; 2297 bool disable_uvd_power_tune; 2298 int ret; 2299 2300 if (ni_pi->enable_power_containment == false) 2301 return 0; 2302 2303 if (state->performance_level_count == 0) 2304 return -EINVAL; 2305 2306 if (smc_state->levelCount != state->performance_level_count) 2307 return -EINVAL; 2308 2309 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2310 2311 smc_state->levels[0].dpm2.MaxPS = 0; 2312 smc_state->levels[0].dpm2.NearTDPDec = 0; 2313 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2314 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2315 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2316 2317 for (i = 1; i < state->performance_level_count; i++) { 2318 prev_sclk = state->performance_levels[i-1].sclk; 2319 max_sclk = state->performance_levels[i].sclk; 2320 if (i == 1) 2321 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2322 else 2323 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2324 2325 if (prev_sclk > max_sclk) 2326 return -EINVAL; 2327 2328 if ((max_ps_percent == 0) || 2329 (prev_sclk == max_sclk) || 2330 disable_uvd_power_tune) { 2331 min_sclk = max_sclk; 2332 } else if (i == 1) { 2333 min_sclk = prev_sclk; 2334 } else { 2335 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2336 } 2337 2338 if (min_sclk < state->performance_levels[0].sclk) 2339 min_sclk = state->performance_levels[0].sclk; 2340 2341 if (min_sclk == 0) 2342 return -EINVAL; 2343 2344 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2345 state->performance_levels[i-1].vddc, &vddc); 2346 if (ret) 2347 return ret; 2348 2349 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2350 if (ret) 2351 return ret; 2352 2353 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2354 state->performance_levels[i].vddc, &vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2359 if (ret) 2360 return ret; 2361 2362 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2363 prev_std_vddc, curr_std_vddc); 2364 2365 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2366 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2367 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2368 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2369 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2370 } 2371 2372 return 0; 2373 } 2374 2375 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2376 struct radeon_ps *radeon_state, 2377 SISLANDS_SMC_SWSTATE *smc_state) 2378 { 2379 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2380 struct ni_ps *state = ni_get_ps(radeon_state); 2381 u32 sq_power_throttle, sq_power_throttle2; 2382 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2383 int i; 2384 2385 if (state->performance_level_count == 0) 2386 return -EINVAL; 2387 2388 if (smc_state->levelCount != state->performance_level_count) 2389 return -EINVAL; 2390 2391 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2392 return -EINVAL; 2393 2394 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2395 enable_sq_ramping = false; 2396 2397 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2398 enable_sq_ramping = false; 2399 2400 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2401 enable_sq_ramping = false; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 for (i = 0; i < state->performance_level_count; i++) { 2410 sq_power_throttle = 0; 2411 sq_power_throttle2 = 0; 2412 2413 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2414 enable_sq_ramping) { 2415 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2416 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2417 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2418 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2419 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2420 } else { 2421 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2422 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2423 } 2424 2425 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2426 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2427 } 2428 2429 return 0; 2430 } 2431 2432 static int si_enable_power_containment(struct radeon_device *rdev, 2433 struct radeon_ps *radeon_new_state, 2434 bool enable) 2435 { 2436 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2437 PPSMC_Result smc_result; 2438 int ret = 0; 2439 2440 if (ni_pi->enable_power_containment) { 2441 if (enable) { 2442 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2443 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2444 if (smc_result != PPSMC_Result_OK) { 2445 ret = -EINVAL; 2446 ni_pi->pc_enabled = false; 2447 } else { 2448 ni_pi->pc_enabled = true; 2449 } 2450 } 2451 } else { 2452 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2453 if (smc_result != PPSMC_Result_OK) 2454 ret = -EINVAL; 2455 ni_pi->pc_enabled = false; 2456 } 2457 } 2458 2459 return ret; 2460 } 2461 2462 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2463 { 2464 struct si_power_info *si_pi = si_get_pi(rdev); 2465 int ret = 0; 2466 struct si_dte_data *dte_data = &si_pi->dte_data; 2467 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2468 u32 table_size; 2469 u8 tdep_count; 2470 u32 i; 2471 2472 if (dte_data == NULL) 2473 si_pi->enable_dte = false; 2474 2475 if (si_pi->enable_dte == false) 2476 return 0; 2477 2478 if (dte_data->k <= 0) 2479 return -EINVAL; 2480 2481 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2482 if (dte_tables == NULL) { 2483 si_pi->enable_dte = false; 2484 return -ENOMEM; 2485 } 2486 2487 table_size = dte_data->k; 2488 2489 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2490 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2491 2492 tdep_count = dte_data->tdep_count; 2493 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2494 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2495 2496 dte_tables->K = cpu_to_be32(table_size); 2497 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2498 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2499 dte_tables->WindowSize = dte_data->window_size; 2500 dte_tables->temp_select = dte_data->temp_select; 2501 dte_tables->DTE_mode = dte_data->dte_mode; 2502 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2503 2504 if (tdep_count > 0) 2505 table_size--; 2506 2507 for (i = 0; i < table_size; i++) { 2508 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2509 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2510 } 2511 2512 dte_tables->Tdep_count = tdep_count; 2513 2514 for (i = 0; i < (u32)tdep_count; i++) { 2515 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2516 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2517 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2518 } 2519 2520 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2521 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2522 kfree(dte_tables); 2523 2524 return ret; 2525 } 2526 2527 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2528 u16 *max, u16 *min) 2529 { 2530 struct si_power_info *si_pi = si_get_pi(rdev); 2531 struct radeon_cac_leakage_table *table = 2532 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2533 u32 i; 2534 u32 v0_loadline; 2535 2536 2537 if (table == NULL) 2538 return -EINVAL; 2539 2540 *max = 0; 2541 *min = 0xFFFF; 2542 2543 for (i = 0; i < table->count; i++) { 2544 if (table->entries[i].vddc > *max) 2545 *max = table->entries[i].vddc; 2546 if (table->entries[i].vddc < *min) 2547 *min = table->entries[i].vddc; 2548 } 2549 2550 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2551 return -EINVAL; 2552 2553 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2554 2555 if (v0_loadline > 0xFFFFUL) 2556 return -EINVAL; 2557 2558 *min = (u16)v0_loadline; 2559 2560 if ((*min > *max) || (*max == 0) || (*min == 0)) 2561 return -EINVAL; 2562 2563 return 0; 2564 } 2565 2566 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2567 { 2568 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2569 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2570 } 2571 2572 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2573 PP_SIslands_CacConfig *cac_tables, 2574 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2575 u16 t0, u16 t_step) 2576 { 2577 struct si_power_info *si_pi = si_get_pi(rdev); 2578 u32 leakage; 2579 unsigned int i, j; 2580 s32 t; 2581 u32 smc_leakage; 2582 u32 scaling_factor; 2583 u16 voltage; 2584 2585 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2586 2587 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2588 t = (1000 * (i * t_step + t0)); 2589 2590 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2591 voltage = vddc_max - (vddc_step * j); 2592 2593 si_calculate_leakage_for_v_and_t(rdev, 2594 &si_pi->powertune_data->leakage_coefficients, 2595 voltage, 2596 t, 2597 si_pi->dyn_powertune_data.cac_leakage, 2598 &leakage); 2599 2600 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2601 2602 if (smc_leakage > 0xFFFF) 2603 smc_leakage = 0xFFFF; 2604 2605 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2606 cpu_to_be16((u16)smc_leakage); 2607 } 2608 } 2609 return 0; 2610 } 2611 2612 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2613 PP_SIslands_CacConfig *cac_tables, 2614 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2615 { 2616 struct si_power_info *si_pi = si_get_pi(rdev); 2617 u32 leakage; 2618 unsigned int i, j; 2619 u32 smc_leakage; 2620 u32 scaling_factor; 2621 u16 voltage; 2622 2623 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2624 2625 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2626 voltage = vddc_max - (vddc_step * j); 2627 2628 si_calculate_leakage_for_v(rdev, 2629 &si_pi->powertune_data->leakage_coefficients, 2630 si_pi->powertune_data->fixed_kt, 2631 voltage, 2632 si_pi->dyn_powertune_data.cac_leakage, 2633 &leakage); 2634 2635 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2636 2637 if (smc_leakage > 0xFFFF) 2638 smc_leakage = 0xFFFF; 2639 2640 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2641 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2642 cpu_to_be16((u16)smc_leakage); 2643 } 2644 return 0; 2645 } 2646 2647 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2648 { 2649 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2650 struct si_power_info *si_pi = si_get_pi(rdev); 2651 PP_SIslands_CacConfig *cac_tables = NULL; 2652 u16 vddc_max, vddc_min, vddc_step; 2653 u16 t0, t_step; 2654 u32 load_line_slope, reg; 2655 int ret = 0; 2656 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2657 2658 if (ni_pi->enable_cac == false) 2659 return 0; 2660 2661 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2662 if (!cac_tables) 2663 return -ENOMEM; 2664 2665 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2666 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2667 WREG32(CG_CAC_CTRL, reg); 2668 2669 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2670 si_pi->dyn_powertune_data.dc_pwr_value = 2671 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2672 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2673 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2674 2675 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2676 2677 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2678 if (ret) 2679 goto done_free; 2680 2681 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2682 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2683 t_step = 4; 2684 t0 = 60; 2685 2686 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2687 ret = si_init_dte_leakage_table(rdev, cac_tables, 2688 vddc_max, vddc_min, vddc_step, 2689 t0, t_step); 2690 else 2691 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2692 vddc_max, vddc_min, vddc_step); 2693 if (ret) 2694 goto done_free; 2695 2696 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2697 2698 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2699 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2700 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2701 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2702 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2703 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2704 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2705 cac_tables->calculation_repeats = cpu_to_be32(2); 2706 cac_tables->dc_cac = cpu_to_be32(0); 2707 cac_tables->log2_PG_LKG_SCALE = 12; 2708 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2709 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2710 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2711 2712 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2713 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2714 2715 if (ret) 2716 goto done_free; 2717 2718 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2719 2720 done_free: 2721 if (ret) { 2722 ni_pi->enable_cac = false; 2723 ni_pi->enable_power_containment = false; 2724 } 2725 2726 kfree(cac_tables); 2727 2728 return 0; 2729 } 2730 2731 static int si_program_cac_config_registers(struct radeon_device *rdev, 2732 const struct si_cac_config_reg *cac_config_regs) 2733 { 2734 const struct si_cac_config_reg *config_regs = cac_config_regs; 2735 u32 data = 0, offset; 2736 2737 if (!config_regs) 2738 return -EINVAL; 2739 2740 while (config_regs->offset != 0xFFFFFFFF) { 2741 switch (config_regs->type) { 2742 case SISLANDS_CACCONFIG_CGIND: 2743 offset = SMC_CG_IND_START + config_regs->offset; 2744 if (offset < SMC_CG_IND_END) 2745 data = RREG32_SMC(offset); 2746 break; 2747 default: 2748 data = RREG32(config_regs->offset << 2); 2749 break; 2750 } 2751 2752 data &= ~config_regs->mask; 2753 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2754 2755 switch (config_regs->type) { 2756 case SISLANDS_CACCONFIG_CGIND: 2757 offset = SMC_CG_IND_START + config_regs->offset; 2758 if (offset < SMC_CG_IND_END) 2759 WREG32_SMC(offset, data); 2760 break; 2761 default: 2762 WREG32(config_regs->offset << 2, data); 2763 break; 2764 } 2765 config_regs++; 2766 } 2767 return 0; 2768 } 2769 2770 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2771 { 2772 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2773 struct si_power_info *si_pi = si_get_pi(rdev); 2774 int ret; 2775 2776 if ((ni_pi->enable_cac == false) || 2777 (ni_pi->cac_configuration_required == false)) 2778 return 0; 2779 2780 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2781 if (ret) 2782 return ret; 2783 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2784 if (ret) 2785 return ret; 2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2787 if (ret) 2788 return ret; 2789 2790 return 0; 2791 } 2792 2793 static int si_enable_smc_cac(struct radeon_device *rdev, 2794 struct radeon_ps *radeon_new_state, 2795 bool enable) 2796 { 2797 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2798 struct si_power_info *si_pi = si_get_pi(rdev); 2799 PPSMC_Result smc_result; 2800 int ret = 0; 2801 2802 if (ni_pi->enable_cac) { 2803 if (enable) { 2804 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2805 if (ni_pi->support_cac_long_term_average) { 2806 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2807 if (smc_result != PPSMC_Result_OK) 2808 ni_pi->support_cac_long_term_average = false; 2809 } 2810 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2812 if (smc_result != PPSMC_Result_OK) { 2813 ret = -EINVAL; 2814 ni_pi->cac_enabled = false; 2815 } else { 2816 ni_pi->cac_enabled = true; 2817 } 2818 2819 if (si_pi->enable_dte) { 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2821 if (smc_result != PPSMC_Result_OK) 2822 ret = -EINVAL; 2823 } 2824 } 2825 } else if (ni_pi->cac_enabled) { 2826 if (si_pi->enable_dte) 2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2828 2829 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2830 2831 ni_pi->cac_enabled = false; 2832 2833 if (ni_pi->support_cac_long_term_average) 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2835 } 2836 } 2837 return ret; 2838 } 2839 2840 static int si_init_smc_spll_table(struct radeon_device *rdev) 2841 { 2842 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2843 struct si_power_info *si_pi = si_get_pi(rdev); 2844 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2845 SISLANDS_SMC_SCLK_VALUE sclk_params; 2846 u32 fb_div, p_div; 2847 u32 clk_s, clk_v; 2848 u32 sclk = 0; 2849 int ret = 0; 2850 u32 tmp; 2851 int i; 2852 2853 if (si_pi->spll_table_start == 0) 2854 return -EINVAL; 2855 2856 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2857 if (spll_table == NULL) 2858 return -ENOMEM; 2859 2860 for (i = 0; i < 256; i++) { 2861 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2862 if (ret) 2863 break; 2864 2865 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2866 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2867 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2868 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2869 2870 fb_div &= ~0x00001FFF; 2871 fb_div >>= 1; 2872 clk_v >>= 6; 2873 2874 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2875 ret = -EINVAL; 2876 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2877 ret = -EINVAL; 2878 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2879 ret = -EINVAL; 2880 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2881 ret = -EINVAL; 2882 2883 if (ret) 2884 break; 2885 2886 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2887 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2888 spll_table->freq[i] = cpu_to_be32(tmp); 2889 2890 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2891 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2892 spll_table->ss[i] = cpu_to_be32(tmp); 2893 2894 sclk += 512; 2895 } 2896 2897 2898 if (!ret) 2899 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2900 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2901 si_pi->sram_end); 2902 2903 if (ret) 2904 ni_pi->enable_power_containment = false; 2905 2906 kfree(spll_table); 2907 2908 return ret; 2909 } 2910 2911 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2912 struct radeon_ps *rps) 2913 { 2914 struct ni_ps *ps = ni_get_ps(rps); 2915 struct radeon_clock_and_voltage_limits *max_limits; 2916 bool disable_mclk_switching = false; 2917 bool disable_sclk_switching = false; 2918 u32 mclk, sclk; 2919 u16 vddc, vddci; 2920 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2921 int i; 2922 2923 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2924 ni_dpm_vblank_too_short(rdev)) 2925 disable_mclk_switching = true; 2926 2927 if (rps->vclk || rps->dclk) { 2928 disable_mclk_switching = true; 2929 disable_sclk_switching = true; 2930 } 2931 2932 if (rdev->pm.dpm.ac_power) 2933 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2934 else 2935 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2936 2937 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2938 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2939 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2940 } 2941 if (rdev->pm.dpm.ac_power == false) { 2942 for (i = 0; i < ps->performance_level_count; i++) { 2943 if (ps->performance_levels[i].mclk > max_limits->mclk) 2944 ps->performance_levels[i].mclk = max_limits->mclk; 2945 if (ps->performance_levels[i].sclk > max_limits->sclk) 2946 ps->performance_levels[i].sclk = max_limits->sclk; 2947 if (ps->performance_levels[i].vddc > max_limits->vddc) 2948 ps->performance_levels[i].vddc = max_limits->vddc; 2949 if (ps->performance_levels[i].vddci > max_limits->vddci) 2950 ps->performance_levels[i].vddci = max_limits->vddci; 2951 } 2952 } 2953 2954 /* limit clocks to max supported clocks based on voltage dependency tables */ 2955 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2956 &max_sclk_vddc); 2957 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2958 &max_mclk_vddci); 2959 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2960 &max_mclk_vddc); 2961 2962 for (i = 0; i < ps->performance_level_count; i++) { 2963 if (max_sclk_vddc) { 2964 if (ps->performance_levels[i].sclk > max_sclk_vddc) 2965 ps->performance_levels[i].sclk = max_sclk_vddc; 2966 } 2967 if (max_mclk_vddci) { 2968 if (ps->performance_levels[i].mclk > max_mclk_vddci) 2969 ps->performance_levels[i].mclk = max_mclk_vddci; 2970 } 2971 if (max_mclk_vddc) { 2972 if (ps->performance_levels[i].mclk > max_mclk_vddc) 2973 ps->performance_levels[i].mclk = max_mclk_vddc; 2974 } 2975 } 2976 2977 /* XXX validate the min clocks required for display */ 2978 2979 if (disable_mclk_switching) { 2980 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2981 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2982 } else { 2983 mclk = ps->performance_levels[0].mclk; 2984 vddci = ps->performance_levels[0].vddci; 2985 } 2986 2987 if (disable_sclk_switching) { 2988 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2989 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2990 } else { 2991 sclk = ps->performance_levels[0].sclk; 2992 vddc = ps->performance_levels[0].vddc; 2993 } 2994 2995 /* adjusted low state */ 2996 ps->performance_levels[0].sclk = sclk; 2997 ps->performance_levels[0].mclk = mclk; 2998 ps->performance_levels[0].vddc = vddc; 2999 ps->performance_levels[0].vddci = vddci; 3000 3001 if (disable_sclk_switching) { 3002 sclk = ps->performance_levels[0].sclk; 3003 for (i = 1; i < ps->performance_level_count; i++) { 3004 if (sclk < ps->performance_levels[i].sclk) 3005 sclk = ps->performance_levels[i].sclk; 3006 } 3007 for (i = 0; i < ps->performance_level_count; i++) { 3008 ps->performance_levels[i].sclk = sclk; 3009 ps->performance_levels[i].vddc = vddc; 3010 } 3011 } else { 3012 for (i = 1; i < ps->performance_level_count; i++) { 3013 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3014 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3015 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3016 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3017 } 3018 } 3019 3020 if (disable_mclk_switching) { 3021 mclk = ps->performance_levels[0].mclk; 3022 for (i = 1; i < ps->performance_level_count; i++) { 3023 if (mclk < ps->performance_levels[i].mclk) 3024 mclk = ps->performance_levels[i].mclk; 3025 } 3026 for (i = 0; i < ps->performance_level_count; i++) { 3027 ps->performance_levels[i].mclk = mclk; 3028 ps->performance_levels[i].vddci = vddci; 3029 } 3030 } else { 3031 for (i = 1; i < ps->performance_level_count; i++) { 3032 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3033 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3034 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3035 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3036 } 3037 } 3038 3039 for (i = 0; i < ps->performance_level_count; i++) 3040 btc_adjust_clock_combinations(rdev, max_limits, 3041 &ps->performance_levels[i]); 3042 3043 for (i = 0; i < ps->performance_level_count; i++) { 3044 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3045 ps->performance_levels[i].sclk, 3046 max_limits->vddc, &ps->performance_levels[i].vddc); 3047 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3048 ps->performance_levels[i].mclk, 3049 max_limits->vddci, &ps->performance_levels[i].vddci); 3050 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3051 ps->performance_levels[i].mclk, 3052 max_limits->vddc, &ps->performance_levels[i].vddc); 3053 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3054 rdev->clock.current_dispclk, 3055 max_limits->vddc, &ps->performance_levels[i].vddc); 3056 } 3057 3058 for (i = 0; i < ps->performance_level_count; i++) { 3059 btc_apply_voltage_delta_rules(rdev, 3060 max_limits->vddc, max_limits->vddci, 3061 &ps->performance_levels[i].vddc, 3062 &ps->performance_levels[i].vddci); 3063 } 3064 3065 ps->dc_compatible = true; 3066 for (i = 0; i < ps->performance_level_count; i++) { 3067 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3068 ps->dc_compatible = false; 3069 } 3070 3071 } 3072 3073 #if 0 3074 static int si_read_smc_soft_register(struct radeon_device *rdev, 3075 u16 reg_offset, u32 *value) 3076 { 3077 struct si_power_info *si_pi = si_get_pi(rdev); 3078 3079 return si_read_smc_sram_dword(rdev, 3080 si_pi->soft_regs_start + reg_offset, value, 3081 si_pi->sram_end); 3082 } 3083 #endif 3084 3085 static int si_write_smc_soft_register(struct radeon_device *rdev, 3086 u16 reg_offset, u32 value) 3087 { 3088 struct si_power_info *si_pi = si_get_pi(rdev); 3089 3090 return si_write_smc_sram_dword(rdev, 3091 si_pi->soft_regs_start + reg_offset, 3092 value, si_pi->sram_end); 3093 } 3094 3095 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3096 { 3097 bool ret = false; 3098 u32 tmp, width, row, column, bank, density; 3099 bool is_memory_gddr5, is_special; 3100 3101 tmp = RREG32(MC_SEQ_MISC0); 3102 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3103 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3104 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3105 3106 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3107 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3108 3109 tmp = RREG32(MC_ARB_RAMCFG); 3110 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3111 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3112 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3113 3114 density = (1 << (row + column - 20 + bank)) * width; 3115 3116 if ((rdev->pdev->device == 0x6819) && 3117 is_memory_gddr5 && is_special && (density == 0x400)) 3118 ret = true; 3119 3120 return ret; 3121 } 3122 3123 static void si_get_leakage_vddc(struct radeon_device *rdev) 3124 { 3125 struct si_power_info *si_pi = si_get_pi(rdev); 3126 u16 vddc, count = 0; 3127 int i, ret; 3128 3129 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3130 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3131 3132 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3133 si_pi->leakage_voltage.entries[count].voltage = vddc; 3134 si_pi->leakage_voltage.entries[count].leakage_index = 3135 SISLANDS_LEAKAGE_INDEX0 + i; 3136 count++; 3137 } 3138 } 3139 si_pi->leakage_voltage.count = count; 3140 } 3141 3142 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3143 u32 index, u16 *leakage_voltage) 3144 { 3145 struct si_power_info *si_pi = si_get_pi(rdev); 3146 int i; 3147 3148 if (leakage_voltage == NULL) 3149 return -EINVAL; 3150 3151 if ((index & 0xff00) != 0xff00) 3152 return -EINVAL; 3153 3154 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3155 return -EINVAL; 3156 3157 if (index < SISLANDS_LEAKAGE_INDEX0) 3158 return -EINVAL; 3159 3160 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3161 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3162 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3163 return 0; 3164 } 3165 } 3166 return -EAGAIN; 3167 } 3168 3169 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3170 { 3171 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3172 bool want_thermal_protection; 3173 enum radeon_dpm_event_src dpm_event_src; 3174 3175 switch (sources) { 3176 case 0: 3177 default: 3178 want_thermal_protection = false; 3179 break; 3180 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3181 want_thermal_protection = true; 3182 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3183 break; 3184 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3185 want_thermal_protection = true; 3186 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3187 break; 3188 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3189 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3190 want_thermal_protection = true; 3191 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3192 break; 3193 } 3194 3195 if (want_thermal_protection) { 3196 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3197 if (pi->thermal_protection) 3198 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3199 } else { 3200 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3201 } 3202 } 3203 3204 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3205 enum radeon_dpm_auto_throttle_src source, 3206 bool enable) 3207 { 3208 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3209 3210 if (enable) { 3211 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3212 pi->active_auto_throttle_sources |= 1 << source; 3213 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3214 } 3215 } else { 3216 if (pi->active_auto_throttle_sources & (1 << source)) { 3217 pi->active_auto_throttle_sources &= ~(1 << source); 3218 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3219 } 3220 } 3221 } 3222 3223 static void si_start_dpm(struct radeon_device *rdev) 3224 { 3225 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3226 } 3227 3228 static void si_stop_dpm(struct radeon_device *rdev) 3229 { 3230 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3231 } 3232 3233 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3234 { 3235 if (enable) 3236 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3237 else 3238 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3239 3240 } 3241 3242 #if 0 3243 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3244 u32 thermal_level) 3245 { 3246 PPSMC_Result ret; 3247 3248 if (thermal_level == 0) { 3249 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3250 if (ret == PPSMC_Result_OK) 3251 return 0; 3252 else 3253 return -EINVAL; 3254 } 3255 return 0; 3256 } 3257 3258 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3259 { 3260 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3261 } 3262 #endif 3263 3264 #if 0 3265 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3266 { 3267 if (ac_power) 3268 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3269 0 : -EINVAL; 3270 3271 return 0; 3272 } 3273 #endif 3274 3275 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3276 PPSMC_Msg msg, u32 parameter) 3277 { 3278 WREG32(SMC_SCRATCH0, parameter); 3279 return si_send_msg_to_smc(rdev, msg); 3280 } 3281 3282 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3283 { 3284 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3285 return -EINVAL; 3286 3287 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3288 0 : -EINVAL; 3289 } 3290 3291 int si_dpm_force_performance_level(struct radeon_device *rdev, 3292 enum radeon_dpm_forced_level level) 3293 { 3294 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3295 struct ni_ps *ps = ni_get_ps(rps); 3296 u32 levels = ps->performance_level_count; 3297 3298 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3299 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3300 return -EINVAL; 3301 3302 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3303 return -EINVAL; 3304 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3305 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3306 return -EINVAL; 3307 3308 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3309 return -EINVAL; 3310 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3311 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3312 return -EINVAL; 3313 3314 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3315 return -EINVAL; 3316 } 3317 3318 rdev->pm.dpm.forced_level = level; 3319 3320 return 0; 3321 } 3322 3323 #if 0 3324 static int si_set_boot_state(struct radeon_device *rdev) 3325 { 3326 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3327 0 : -EINVAL; 3328 } 3329 #endif 3330 3331 static int si_set_sw_state(struct radeon_device *rdev) 3332 { 3333 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3334 0 : -EINVAL; 3335 } 3336 3337 static int si_halt_smc(struct radeon_device *rdev) 3338 { 3339 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3340 return -EINVAL; 3341 3342 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3343 0 : -EINVAL; 3344 } 3345 3346 static int si_resume_smc(struct radeon_device *rdev) 3347 { 3348 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3349 return -EINVAL; 3350 3351 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3352 0 : -EINVAL; 3353 } 3354 3355 static void si_dpm_start_smc(struct radeon_device *rdev) 3356 { 3357 si_program_jump_on_start(rdev); 3358 si_start_smc(rdev); 3359 si_start_smc_clock(rdev); 3360 } 3361 3362 static void si_dpm_stop_smc(struct radeon_device *rdev) 3363 { 3364 si_reset_smc(rdev); 3365 si_stop_smc_clock(rdev); 3366 } 3367 3368 static int si_process_firmware_header(struct radeon_device *rdev) 3369 { 3370 struct si_power_info *si_pi = si_get_pi(rdev); 3371 u32 tmp; 3372 int ret; 3373 3374 ret = si_read_smc_sram_dword(rdev, 3375 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3376 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3377 &tmp, si_pi->sram_end); 3378 if (ret) 3379 return ret; 3380 3381 si_pi->state_table_start = tmp; 3382 3383 ret = si_read_smc_sram_dword(rdev, 3384 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3385 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3386 &tmp, si_pi->sram_end); 3387 if (ret) 3388 return ret; 3389 3390 si_pi->soft_regs_start = tmp; 3391 3392 ret = si_read_smc_sram_dword(rdev, 3393 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3394 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3395 &tmp, si_pi->sram_end); 3396 if (ret) 3397 return ret; 3398 3399 si_pi->mc_reg_table_start = tmp; 3400 3401 ret = si_read_smc_sram_dword(rdev, 3402 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3403 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3404 &tmp, si_pi->sram_end); 3405 if (ret) 3406 return ret; 3407 3408 si_pi->arb_table_start = tmp; 3409 3410 ret = si_read_smc_sram_dword(rdev, 3411 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3412 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3413 &tmp, si_pi->sram_end); 3414 if (ret) 3415 return ret; 3416 3417 si_pi->cac_table_start = tmp; 3418 3419 ret = si_read_smc_sram_dword(rdev, 3420 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3421 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3422 &tmp, si_pi->sram_end); 3423 if (ret) 3424 return ret; 3425 3426 si_pi->dte_table_start = tmp; 3427 3428 ret = si_read_smc_sram_dword(rdev, 3429 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3430 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3431 &tmp, si_pi->sram_end); 3432 if (ret) 3433 return ret; 3434 3435 si_pi->spll_table_start = tmp; 3436 3437 ret = si_read_smc_sram_dword(rdev, 3438 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3439 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3440 &tmp, si_pi->sram_end); 3441 if (ret) 3442 return ret; 3443 3444 si_pi->papm_cfg_table_start = tmp; 3445 3446 return ret; 3447 } 3448 3449 static void si_read_clock_registers(struct radeon_device *rdev) 3450 { 3451 struct si_power_info *si_pi = si_get_pi(rdev); 3452 3453 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3454 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3455 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3456 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3457 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3458 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3459 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3460 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3461 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3462 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3463 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3464 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3465 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3466 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3467 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3468 } 3469 3470 static void si_enable_thermal_protection(struct radeon_device *rdev, 3471 bool enable) 3472 { 3473 if (enable) 3474 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3475 else 3476 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3477 } 3478 3479 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3480 { 3481 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3482 } 3483 3484 #if 0 3485 static int si_enter_ulp_state(struct radeon_device *rdev) 3486 { 3487 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3488 3489 udelay(25000); 3490 3491 return 0; 3492 } 3493 3494 static int si_exit_ulp_state(struct radeon_device *rdev) 3495 { 3496 int i; 3497 3498 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3499 3500 udelay(7000); 3501 3502 for (i = 0; i < rdev->usec_timeout; i++) { 3503 if (RREG32(SMC_RESP_0) == 1) 3504 break; 3505 udelay(1000); 3506 } 3507 3508 return 0; 3509 } 3510 #endif 3511 3512 static int si_notify_smc_display_change(struct radeon_device *rdev, 3513 bool has_display) 3514 { 3515 PPSMC_Msg msg = has_display ? 3516 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3517 3518 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3519 0 : -EINVAL; 3520 } 3521 3522 static void si_program_response_times(struct radeon_device *rdev) 3523 { 3524 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3525 u32 vddc_dly, acpi_dly, vbi_dly; 3526 u32 reference_clock; 3527 3528 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3529 3530 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3531 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3532 3533 if (voltage_response_time == 0) 3534 voltage_response_time = 1000; 3535 3536 acpi_delay_time = 15000; 3537 vbi_time_out = 100000; 3538 3539 reference_clock = radeon_get_xclk(rdev); 3540 3541 vddc_dly = (voltage_response_time * reference_clock) / 100; 3542 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3543 vbi_dly = (vbi_time_out * reference_clock) / 100; 3544 3545 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3546 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3547 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3548 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3549 } 3550 3551 static void si_program_ds_registers(struct radeon_device *rdev) 3552 { 3553 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3554 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3555 3556 if (eg_pi->sclk_deep_sleep) { 3557 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3558 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3559 ~AUTOSCALE_ON_SS_CLEAR); 3560 } 3561 } 3562 3563 static void si_program_display_gap(struct radeon_device *rdev) 3564 { 3565 u32 tmp, pipe; 3566 int i; 3567 3568 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3569 if (rdev->pm.dpm.new_active_crtc_count > 0) 3570 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3571 else 3572 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3573 3574 if (rdev->pm.dpm.new_active_crtc_count > 1) 3575 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3576 else 3577 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3578 3579 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3580 3581 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3582 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3583 3584 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3585 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3586 /* find the first active crtc */ 3587 for (i = 0; i < rdev->num_crtc; i++) { 3588 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3589 break; 3590 } 3591 if (i == rdev->num_crtc) 3592 pipe = 0; 3593 else 3594 pipe = i; 3595 3596 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3597 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3598 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3599 } 3600 3601 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3602 * This can be a problem on PowerXpress systems or if you want to use the card 3603 * for offscreen rendering or compute if there are no crtcs enabled. 3604 */ 3605 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3606 } 3607 3608 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3609 { 3610 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3611 3612 if (enable) { 3613 if (pi->sclk_ss) 3614 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3615 } else { 3616 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3617 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3618 } 3619 } 3620 3621 static void si_setup_bsp(struct radeon_device *rdev) 3622 { 3623 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3624 u32 xclk = radeon_get_xclk(rdev); 3625 3626 r600_calculate_u_and_p(pi->asi, 3627 xclk, 3628 16, 3629 &pi->bsp, 3630 &pi->bsu); 3631 3632 r600_calculate_u_and_p(pi->pasi, 3633 xclk, 3634 16, 3635 &pi->pbsp, 3636 &pi->pbsu); 3637 3638 3639 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3640 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3641 3642 WREG32(CG_BSP, pi->dsp); 3643 } 3644 3645 static void si_program_git(struct radeon_device *rdev) 3646 { 3647 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3648 } 3649 3650 static void si_program_tp(struct radeon_device *rdev) 3651 { 3652 int i; 3653 enum r600_td td = R600_TD_DFLT; 3654 3655 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3656 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3657 3658 if (td == R600_TD_AUTO) 3659 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3660 else 3661 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3662 3663 if (td == R600_TD_UP) 3664 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3665 3666 if (td == R600_TD_DOWN) 3667 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3668 } 3669 3670 static void si_program_tpp(struct radeon_device *rdev) 3671 { 3672 WREG32(CG_TPC, R600_TPC_DFLT); 3673 } 3674 3675 static void si_program_sstp(struct radeon_device *rdev) 3676 { 3677 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3678 } 3679 3680 static void si_enable_display_gap(struct radeon_device *rdev) 3681 { 3682 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3683 3684 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3685 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3686 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3687 3688 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3689 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3690 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3691 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3692 } 3693 3694 static void si_program_vc(struct radeon_device *rdev) 3695 { 3696 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3697 3698 WREG32(CG_FTV, pi->vrc); 3699 } 3700 3701 static void si_clear_vc(struct radeon_device *rdev) 3702 { 3703 WREG32(CG_FTV, 0); 3704 } 3705 3706 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3707 { 3708 u8 mc_para_index; 3709 3710 if (memory_clock < 10000) 3711 mc_para_index = 0; 3712 else if (memory_clock >= 80000) 3713 mc_para_index = 0x0f; 3714 else 3715 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3716 return mc_para_index; 3717 } 3718 3719 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3720 { 3721 u8 mc_para_index; 3722 3723 if (strobe_mode) { 3724 if (memory_clock < 12500) 3725 mc_para_index = 0x00; 3726 else if (memory_clock > 47500) 3727 mc_para_index = 0x0f; 3728 else 3729 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3730 } else { 3731 if (memory_clock < 65000) 3732 mc_para_index = 0x00; 3733 else if (memory_clock > 135000) 3734 mc_para_index = 0x0f; 3735 else 3736 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3737 } 3738 return mc_para_index; 3739 } 3740 3741 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3742 { 3743 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3744 bool strobe_mode = false; 3745 u8 result = 0; 3746 3747 if (mclk <= pi->mclk_strobe_mode_threshold) 3748 strobe_mode = true; 3749 3750 if (pi->mem_gddr5) 3751 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3752 else 3753 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3754 3755 if (strobe_mode) 3756 result |= SISLANDS_SMC_STROBE_ENABLE; 3757 3758 return result; 3759 } 3760 3761 static int si_upload_firmware(struct radeon_device *rdev) 3762 { 3763 struct si_power_info *si_pi = si_get_pi(rdev); 3764 int ret; 3765 3766 si_reset_smc(rdev); 3767 si_stop_smc_clock(rdev); 3768 3769 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3770 3771 return ret; 3772 } 3773 3774 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3775 const struct atom_voltage_table *table, 3776 const struct radeon_phase_shedding_limits_table *limits) 3777 { 3778 u32 data, num_bits, num_levels; 3779 3780 if ((table == NULL) || (limits == NULL)) 3781 return false; 3782 3783 data = table->mask_low; 3784 3785 num_bits = hweight32(data); 3786 3787 if (num_bits == 0) 3788 return false; 3789 3790 num_levels = (1 << num_bits); 3791 3792 if (table->count != num_levels) 3793 return false; 3794 3795 if (limits->count != (num_levels - 1)) 3796 return false; 3797 3798 return true; 3799 } 3800 3801 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3802 u32 max_voltage_steps, 3803 struct atom_voltage_table *voltage_table) 3804 { 3805 unsigned int i, diff; 3806 3807 if (voltage_table->count <= max_voltage_steps) 3808 return; 3809 3810 diff = voltage_table->count - max_voltage_steps; 3811 3812 for (i= 0; i < max_voltage_steps; i++) 3813 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3814 3815 voltage_table->count = max_voltage_steps; 3816 } 3817 3818 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3819 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3820 struct atom_voltage_table *voltage_table) 3821 { 3822 u32 i; 3823 3824 if (voltage_dependency_table == NULL) 3825 return -EINVAL; 3826 3827 voltage_table->mask_low = 0; 3828 voltage_table->phase_delay = 0; 3829 3830 voltage_table->count = voltage_dependency_table->count; 3831 for (i = 0; i < voltage_table->count; i++) { 3832 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3833 voltage_table->entries[i].smio_low = 0; 3834 } 3835 3836 return 0; 3837 } 3838 3839 static int si_construct_voltage_tables(struct radeon_device *rdev) 3840 { 3841 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3842 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3843 struct si_power_info *si_pi = si_get_pi(rdev); 3844 int ret; 3845 3846 if (pi->voltage_control) { 3847 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3848 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3849 if (ret) 3850 return ret; 3851 3852 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3853 si_trim_voltage_table_to_fit_state_table(rdev, 3854 SISLANDS_MAX_NO_VREG_STEPS, 3855 &eg_pi->vddc_voltage_table); 3856 } else if (si_pi->voltage_control_svi2) { 3857 ret = si_get_svi2_voltage_table(rdev, 3858 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3859 &eg_pi->vddc_voltage_table); 3860 if (ret) 3861 return ret; 3862 } else { 3863 return -EINVAL; 3864 } 3865 3866 if (eg_pi->vddci_control) { 3867 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3868 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3869 if (ret) 3870 return ret; 3871 3872 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3873 si_trim_voltage_table_to_fit_state_table(rdev, 3874 SISLANDS_MAX_NO_VREG_STEPS, 3875 &eg_pi->vddci_voltage_table); 3876 } 3877 if (si_pi->vddci_control_svi2) { 3878 ret = si_get_svi2_voltage_table(rdev, 3879 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3880 &eg_pi->vddci_voltage_table); 3881 if (ret) 3882 return ret; 3883 } 3884 3885 if (pi->mvdd_control) { 3886 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3887 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3888 3889 if (ret) { 3890 pi->mvdd_control = false; 3891 return ret; 3892 } 3893 3894 if (si_pi->mvdd_voltage_table.count == 0) { 3895 pi->mvdd_control = false; 3896 return -EINVAL; 3897 } 3898 3899 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3900 si_trim_voltage_table_to_fit_state_table(rdev, 3901 SISLANDS_MAX_NO_VREG_STEPS, 3902 &si_pi->mvdd_voltage_table); 3903 } 3904 3905 if (si_pi->vddc_phase_shed_control) { 3906 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3907 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3908 if (ret) 3909 si_pi->vddc_phase_shed_control = false; 3910 3911 if ((si_pi->vddc_phase_shed_table.count == 0) || 3912 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3913 si_pi->vddc_phase_shed_control = false; 3914 } 3915 3916 return 0; 3917 } 3918 3919 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3920 const struct atom_voltage_table *voltage_table, 3921 SISLANDS_SMC_STATETABLE *table) 3922 { 3923 unsigned int i; 3924 3925 for (i = 0; i < voltage_table->count; i++) 3926 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3927 } 3928 3929 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3930 SISLANDS_SMC_STATETABLE *table) 3931 { 3932 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3933 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3934 struct si_power_info *si_pi = si_get_pi(rdev); 3935 u8 i; 3936 3937 if (si_pi->voltage_control_svi2) { 3938 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 3939 si_pi->svc_gpio_id); 3940 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 3941 si_pi->svd_gpio_id); 3942 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 3943 2); 3944 } else { 3945 if (eg_pi->vddc_voltage_table.count) { 3946 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3947 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3948 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3949 3950 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3951 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3952 table->maxVDDCIndexInPPTable = i; 3953 break; 3954 } 3955 } 3956 } 3957 3958 if (eg_pi->vddci_voltage_table.count) { 3959 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3960 3961 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3962 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3963 } 3964 3965 3966 if (si_pi->mvdd_voltage_table.count) { 3967 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3968 3969 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3970 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3971 } 3972 3973 if (si_pi->vddc_phase_shed_control) { 3974 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3975 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3976 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3977 3978 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3979 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3980 3981 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3982 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3983 } else { 3984 si_pi->vddc_phase_shed_control = false; 3985 } 3986 } 3987 } 3988 3989 return 0; 3990 } 3991 3992 static int si_populate_voltage_value(struct radeon_device *rdev, 3993 const struct atom_voltage_table *table, 3994 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3995 { 3996 unsigned int i; 3997 3998 for (i = 0; i < table->count; i++) { 3999 if (value <= table->entries[i].value) { 4000 voltage->index = (u8)i; 4001 voltage->value = cpu_to_be16(table->entries[i].value); 4002 break; 4003 } 4004 } 4005 4006 if (i >= table->count) 4007 return -EINVAL; 4008 4009 return 0; 4010 } 4011 4012 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4013 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4014 { 4015 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4016 struct si_power_info *si_pi = si_get_pi(rdev); 4017 4018 if (pi->mvdd_control) { 4019 if (mclk <= pi->mvdd_split_frequency) 4020 voltage->index = 0; 4021 else 4022 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4023 4024 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4025 } 4026 return 0; 4027 } 4028 4029 static int si_get_std_voltage_value(struct radeon_device *rdev, 4030 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4031 u16 *std_voltage) 4032 { 4033 u16 v_index; 4034 bool voltage_found = false; 4035 *std_voltage = be16_to_cpu(voltage->value); 4036 4037 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4038 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4039 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4040 return -EINVAL; 4041 4042 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4043 if (be16_to_cpu(voltage->value) == 4044 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4045 voltage_found = true; 4046 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4047 *std_voltage = 4048 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4049 else 4050 *std_voltage = 4051 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4052 break; 4053 } 4054 } 4055 4056 if (!voltage_found) { 4057 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4058 if (be16_to_cpu(voltage->value) <= 4059 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4060 voltage_found = true; 4061 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4062 *std_voltage = 4063 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4064 else 4065 *std_voltage = 4066 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4067 break; 4068 } 4069 } 4070 } 4071 } else { 4072 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4073 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4074 } 4075 } 4076 4077 return 0; 4078 } 4079 4080 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4081 u16 value, u8 index, 4082 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4083 { 4084 voltage->index = index; 4085 voltage->value = cpu_to_be16(value); 4086 4087 return 0; 4088 } 4089 4090 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4091 const struct radeon_phase_shedding_limits_table *limits, 4092 u16 voltage, u32 sclk, u32 mclk, 4093 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4094 { 4095 unsigned int i; 4096 4097 for (i = 0; i < limits->count; i++) { 4098 if ((voltage <= limits->entries[i].voltage) && 4099 (sclk <= limits->entries[i].sclk) && 4100 (mclk <= limits->entries[i].mclk)) 4101 break; 4102 } 4103 4104 smc_voltage->phase_settings = (u8)i; 4105 4106 return 0; 4107 } 4108 4109 static int si_init_arb_table_index(struct radeon_device *rdev) 4110 { 4111 struct si_power_info *si_pi = si_get_pi(rdev); 4112 u32 tmp; 4113 int ret; 4114 4115 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4116 if (ret) 4117 return ret; 4118 4119 tmp &= 0x00FFFFFF; 4120 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4121 4122 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4123 } 4124 4125 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4126 { 4127 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4128 } 4129 4130 static int si_reset_to_default(struct radeon_device *rdev) 4131 { 4132 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4133 0 : -EINVAL; 4134 } 4135 4136 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4137 { 4138 struct si_power_info *si_pi = si_get_pi(rdev); 4139 u32 tmp; 4140 int ret; 4141 4142 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4143 &tmp, si_pi->sram_end); 4144 if (ret) 4145 return ret; 4146 4147 tmp = (tmp >> 24) & 0xff; 4148 4149 if (tmp == MC_CG_ARB_FREQ_F0) 4150 return 0; 4151 4152 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4153 } 4154 4155 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4156 u32 engine_clock) 4157 { 4158 u32 dram_rows; 4159 u32 dram_refresh_rate; 4160 u32 mc_arb_rfsh_rate; 4161 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4162 4163 if (tmp >= 4) 4164 dram_rows = 16384; 4165 else 4166 dram_rows = 1 << (tmp + 10); 4167 4168 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4169 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4170 4171 return mc_arb_rfsh_rate; 4172 } 4173 4174 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4175 struct rv7xx_pl *pl, 4176 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4177 { 4178 u32 dram_timing; 4179 u32 dram_timing2; 4180 u32 burst_time; 4181 4182 arb_regs->mc_arb_rfsh_rate = 4183 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4184 4185 radeon_atom_set_engine_dram_timings(rdev, 4186 pl->sclk, 4187 pl->mclk); 4188 4189 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4190 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4191 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4192 4193 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4194 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4195 arb_regs->mc_arb_burst_time = (u8)burst_time; 4196 4197 return 0; 4198 } 4199 4200 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4201 struct radeon_ps *radeon_state, 4202 unsigned int first_arb_set) 4203 { 4204 struct si_power_info *si_pi = si_get_pi(rdev); 4205 struct ni_ps *state = ni_get_ps(radeon_state); 4206 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4207 int i, ret = 0; 4208 4209 for (i = 0; i < state->performance_level_count; i++) { 4210 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4211 if (ret) 4212 break; 4213 ret = si_copy_bytes_to_smc(rdev, 4214 si_pi->arb_table_start + 4215 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4216 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4217 (u8 *)&arb_regs, 4218 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4219 si_pi->sram_end); 4220 if (ret) 4221 break; 4222 } 4223 4224 return ret; 4225 } 4226 4227 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4228 struct radeon_ps *radeon_new_state) 4229 { 4230 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4231 SISLANDS_DRIVER_STATE_ARB_INDEX); 4232 } 4233 4234 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4235 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4236 { 4237 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4238 struct si_power_info *si_pi = si_get_pi(rdev); 4239 4240 if (pi->mvdd_control) 4241 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4242 si_pi->mvdd_bootup_value, voltage); 4243 4244 return 0; 4245 } 4246 4247 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4248 struct radeon_ps *radeon_initial_state, 4249 SISLANDS_SMC_STATETABLE *table) 4250 { 4251 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4252 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4253 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4254 struct si_power_info *si_pi = si_get_pi(rdev); 4255 u32 reg; 4256 int ret; 4257 4258 table->initialState.levels[0].mclk.vDLL_CNTL = 4259 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4260 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4261 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4262 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4263 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4264 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4265 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4266 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4267 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4268 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4269 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4270 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4271 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4272 table->initialState.levels[0].mclk.vMPLL_SS = 4273 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4274 table->initialState.levels[0].mclk.vMPLL_SS2 = 4275 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4276 4277 table->initialState.levels[0].mclk.mclk_value = 4278 cpu_to_be32(initial_state->performance_levels[0].mclk); 4279 4280 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4281 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4282 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4283 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4284 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4285 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4286 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4287 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4288 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4289 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4290 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4291 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4292 4293 table->initialState.levels[0].sclk.sclk_value = 4294 cpu_to_be32(initial_state->performance_levels[0].sclk); 4295 4296 table->initialState.levels[0].arbRefreshState = 4297 SISLANDS_INITIAL_STATE_ARB_INDEX; 4298 4299 table->initialState.levels[0].ACIndex = 0; 4300 4301 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4302 initial_state->performance_levels[0].vddc, 4303 &table->initialState.levels[0].vddc); 4304 4305 if (!ret) { 4306 u16 std_vddc; 4307 4308 ret = si_get_std_voltage_value(rdev, 4309 &table->initialState.levels[0].vddc, 4310 &std_vddc); 4311 if (!ret) 4312 si_populate_std_voltage_value(rdev, std_vddc, 4313 table->initialState.levels[0].vddc.index, 4314 &table->initialState.levels[0].std_vddc); 4315 } 4316 4317 if (eg_pi->vddci_control) 4318 si_populate_voltage_value(rdev, 4319 &eg_pi->vddci_voltage_table, 4320 initial_state->performance_levels[0].vddci, 4321 &table->initialState.levels[0].vddci); 4322 4323 if (si_pi->vddc_phase_shed_control) 4324 si_populate_phase_shedding_value(rdev, 4325 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4326 initial_state->performance_levels[0].vddc, 4327 initial_state->performance_levels[0].sclk, 4328 initial_state->performance_levels[0].mclk, 4329 &table->initialState.levels[0].vddc); 4330 4331 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4332 4333 reg = CG_R(0xffff) | CG_L(0); 4334 table->initialState.levels[0].aT = cpu_to_be32(reg); 4335 4336 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4337 4338 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4339 4340 if (pi->mem_gddr5) { 4341 table->initialState.levels[0].strobeMode = 4342 si_get_strobe_mode_settings(rdev, 4343 initial_state->performance_levels[0].mclk); 4344 4345 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4346 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4347 else 4348 table->initialState.levels[0].mcFlags = 0; 4349 } 4350 4351 table->initialState.levelCount = 1; 4352 4353 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4354 4355 table->initialState.levels[0].dpm2.MaxPS = 0; 4356 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4357 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4358 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4359 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4360 4361 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4362 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4363 4364 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4365 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4366 4367 return 0; 4368 } 4369 4370 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4371 SISLANDS_SMC_STATETABLE *table) 4372 { 4373 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4374 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4375 struct si_power_info *si_pi = si_get_pi(rdev); 4376 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4377 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4378 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4379 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4380 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4381 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4382 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4383 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4384 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4385 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4386 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4387 u32 reg; 4388 int ret; 4389 4390 table->ACPIState = table->initialState; 4391 4392 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4393 4394 if (pi->acpi_vddc) { 4395 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4396 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4397 if (!ret) { 4398 u16 std_vddc; 4399 4400 ret = si_get_std_voltage_value(rdev, 4401 &table->ACPIState.levels[0].vddc, &std_vddc); 4402 if (!ret) 4403 si_populate_std_voltage_value(rdev, std_vddc, 4404 table->ACPIState.levels[0].vddc.index, 4405 &table->ACPIState.levels[0].std_vddc); 4406 } 4407 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4408 4409 if (si_pi->vddc_phase_shed_control) { 4410 si_populate_phase_shedding_value(rdev, 4411 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4412 pi->acpi_vddc, 4413 0, 4414 0, 4415 &table->ACPIState.levels[0].vddc); 4416 } 4417 } else { 4418 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4419 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4420 if (!ret) { 4421 u16 std_vddc; 4422 4423 ret = si_get_std_voltage_value(rdev, 4424 &table->ACPIState.levels[0].vddc, &std_vddc); 4425 4426 if (!ret) 4427 si_populate_std_voltage_value(rdev, std_vddc, 4428 table->ACPIState.levels[0].vddc.index, 4429 &table->ACPIState.levels[0].std_vddc); 4430 } 4431 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4432 si_pi->sys_pcie_mask, 4433 si_pi->boot_pcie_gen, 4434 RADEON_PCIE_GEN1); 4435 4436 if (si_pi->vddc_phase_shed_control) 4437 si_populate_phase_shedding_value(rdev, 4438 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4439 pi->min_vddc_in_table, 4440 0, 4441 0, 4442 &table->ACPIState.levels[0].vddc); 4443 } 4444 4445 if (pi->acpi_vddc) { 4446 if (eg_pi->acpi_vddci) 4447 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4448 eg_pi->acpi_vddci, 4449 &table->ACPIState.levels[0].vddci); 4450 } 4451 4452 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4453 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4454 4455 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4456 4457 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4458 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4459 4460 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4461 cpu_to_be32(dll_cntl); 4462 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4463 cpu_to_be32(mclk_pwrmgt_cntl); 4464 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4465 cpu_to_be32(mpll_ad_func_cntl); 4466 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4467 cpu_to_be32(mpll_dq_func_cntl); 4468 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4469 cpu_to_be32(mpll_func_cntl); 4470 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4471 cpu_to_be32(mpll_func_cntl_1); 4472 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4473 cpu_to_be32(mpll_func_cntl_2); 4474 table->ACPIState.levels[0].mclk.vMPLL_SS = 4475 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4476 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4477 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4478 4479 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4480 cpu_to_be32(spll_func_cntl); 4481 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4482 cpu_to_be32(spll_func_cntl_2); 4483 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4484 cpu_to_be32(spll_func_cntl_3); 4485 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4486 cpu_to_be32(spll_func_cntl_4); 4487 4488 table->ACPIState.levels[0].mclk.mclk_value = 0; 4489 table->ACPIState.levels[0].sclk.sclk_value = 0; 4490 4491 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4492 4493 if (eg_pi->dynamic_ac_timing) 4494 table->ACPIState.levels[0].ACIndex = 0; 4495 4496 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4497 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4498 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4499 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4500 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4501 4502 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4503 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4504 4505 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4506 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4507 4508 return 0; 4509 } 4510 4511 static int si_populate_ulv_state(struct radeon_device *rdev, 4512 SISLANDS_SMC_SWSTATE *state) 4513 { 4514 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4515 struct si_power_info *si_pi = si_get_pi(rdev); 4516 struct si_ulv_param *ulv = &si_pi->ulv; 4517 u32 sclk_in_sr = 1350; /* ??? */ 4518 int ret; 4519 4520 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4521 &state->levels[0]); 4522 if (!ret) { 4523 if (eg_pi->sclk_deep_sleep) { 4524 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4525 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4526 else 4527 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4528 } 4529 if (ulv->one_pcie_lane_in_ulv) 4530 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4531 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4532 state->levels[0].ACIndex = 1; 4533 state->levels[0].std_vddc = state->levels[0].vddc; 4534 state->levelCount = 1; 4535 4536 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4537 } 4538 4539 return ret; 4540 } 4541 4542 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4543 { 4544 struct si_power_info *si_pi = si_get_pi(rdev); 4545 struct si_ulv_param *ulv = &si_pi->ulv; 4546 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4547 int ret; 4548 4549 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4550 &arb_regs); 4551 if (ret) 4552 return ret; 4553 4554 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4555 ulv->volt_change_delay); 4556 4557 ret = si_copy_bytes_to_smc(rdev, 4558 si_pi->arb_table_start + 4559 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4560 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4561 (u8 *)&arb_regs, 4562 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4563 si_pi->sram_end); 4564 4565 return ret; 4566 } 4567 4568 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4569 { 4570 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4571 4572 pi->mvdd_split_frequency = 30000; 4573 } 4574 4575 static int si_init_smc_table(struct radeon_device *rdev) 4576 { 4577 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4578 struct si_power_info *si_pi = si_get_pi(rdev); 4579 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4580 const struct si_ulv_param *ulv = &si_pi->ulv; 4581 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4582 int ret; 4583 u32 lane_width; 4584 u32 vr_hot_gpio; 4585 4586 si_populate_smc_voltage_tables(rdev, table); 4587 4588 switch (rdev->pm.int_thermal_type) { 4589 case THERMAL_TYPE_SI: 4590 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4591 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4592 break; 4593 case THERMAL_TYPE_NONE: 4594 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4595 break; 4596 default: 4597 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4598 break; 4599 } 4600 4601 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4602 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4603 4604 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4605 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4606 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4607 } 4608 4609 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4610 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4611 4612 if (pi->mem_gddr5) 4613 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4614 4615 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4616 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4617 4618 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4619 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4620 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4621 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4622 vr_hot_gpio); 4623 } 4624 4625 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4626 if (ret) 4627 return ret; 4628 4629 ret = si_populate_smc_acpi_state(rdev, table); 4630 if (ret) 4631 return ret; 4632 4633 table->driverState = table->initialState; 4634 4635 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4636 SISLANDS_INITIAL_STATE_ARB_INDEX); 4637 if (ret) 4638 return ret; 4639 4640 if (ulv->supported && ulv->pl.vddc) { 4641 ret = si_populate_ulv_state(rdev, &table->ULVState); 4642 if (ret) 4643 return ret; 4644 4645 ret = si_program_ulv_memory_timing_parameters(rdev); 4646 if (ret) 4647 return ret; 4648 4649 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4650 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4651 4652 lane_width = radeon_get_pcie_lanes(rdev); 4653 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4654 } else { 4655 table->ULVState = table->initialState; 4656 } 4657 4658 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4659 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4660 si_pi->sram_end); 4661 } 4662 4663 static int si_calculate_sclk_params(struct radeon_device *rdev, 4664 u32 engine_clock, 4665 SISLANDS_SMC_SCLK_VALUE *sclk) 4666 { 4667 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4668 struct si_power_info *si_pi = si_get_pi(rdev); 4669 struct atom_clock_dividers dividers; 4670 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4671 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4672 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4673 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4674 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4675 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4676 u64 tmp; 4677 u32 reference_clock = rdev->clock.spll.reference_freq; 4678 u32 reference_divider; 4679 u32 fbdiv; 4680 int ret; 4681 4682 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4683 engine_clock, false, ÷rs); 4684 if (ret) 4685 return ret; 4686 4687 reference_divider = 1 + dividers.ref_div; 4688 4689 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4690 do_div(tmp, reference_clock); 4691 fbdiv = (u32) tmp; 4692 4693 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4694 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4695 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4696 4697 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4698 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4699 4700 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4701 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4702 spll_func_cntl_3 |= SPLL_DITHEN; 4703 4704 if (pi->sclk_ss) { 4705 struct radeon_atom_ss ss; 4706 u32 vco_freq = engine_clock * dividers.post_div; 4707 4708 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4709 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4710 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4711 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4712 4713 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4714 cg_spll_spread_spectrum |= CLK_S(clk_s); 4715 cg_spll_spread_spectrum |= SSEN; 4716 4717 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4718 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4719 } 4720 } 4721 4722 sclk->sclk_value = engine_clock; 4723 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4724 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4725 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4726 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4727 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4728 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4729 4730 return 0; 4731 } 4732 4733 static int si_populate_sclk_value(struct radeon_device *rdev, 4734 u32 engine_clock, 4735 SISLANDS_SMC_SCLK_VALUE *sclk) 4736 { 4737 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4738 int ret; 4739 4740 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4741 if (!ret) { 4742 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4743 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4744 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4745 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4746 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4747 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4748 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4749 } 4750 4751 return ret; 4752 } 4753 4754 static int si_populate_mclk_value(struct radeon_device *rdev, 4755 u32 engine_clock, 4756 u32 memory_clock, 4757 SISLANDS_SMC_MCLK_VALUE *mclk, 4758 bool strobe_mode, 4759 bool dll_state_on) 4760 { 4761 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4762 struct si_power_info *si_pi = si_get_pi(rdev); 4763 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4764 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4765 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4766 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4767 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4768 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4769 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4770 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4771 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4772 struct atom_mpll_param mpll_param; 4773 int ret; 4774 4775 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4776 if (ret) 4777 return ret; 4778 4779 mpll_func_cntl &= ~BWCTRL_MASK; 4780 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4781 4782 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4783 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4784 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4785 4786 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4787 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4788 4789 if (pi->mem_gddr5) { 4790 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4791 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4792 YCLK_POST_DIV(mpll_param.post_div); 4793 } 4794 4795 if (pi->mclk_ss) { 4796 struct radeon_atom_ss ss; 4797 u32 freq_nom; 4798 u32 tmp; 4799 u32 reference_clock = rdev->clock.mpll.reference_freq; 4800 4801 if (pi->mem_gddr5) 4802 freq_nom = memory_clock * 4; 4803 else 4804 freq_nom = memory_clock * 2; 4805 4806 tmp = freq_nom / reference_clock; 4807 tmp = tmp * tmp; 4808 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4809 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4810 u32 clks = reference_clock * 5 / ss.rate; 4811 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4812 4813 mpll_ss1 &= ~CLKV_MASK; 4814 mpll_ss1 |= CLKV(clkv); 4815 4816 mpll_ss2 &= ~CLKS_MASK; 4817 mpll_ss2 |= CLKS(clks); 4818 } 4819 } 4820 4821 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4822 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4823 4824 if (dll_state_on) 4825 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4826 else 4827 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4828 4829 mclk->mclk_value = cpu_to_be32(memory_clock); 4830 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4831 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4832 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4833 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4834 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4835 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4836 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4837 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4838 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4839 4840 return 0; 4841 } 4842 4843 static void si_populate_smc_sp(struct radeon_device *rdev, 4844 struct radeon_ps *radeon_state, 4845 SISLANDS_SMC_SWSTATE *smc_state) 4846 { 4847 struct ni_ps *ps = ni_get_ps(radeon_state); 4848 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4849 int i; 4850 4851 for (i = 0; i < ps->performance_level_count - 1; i++) 4852 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4853 4854 smc_state->levels[ps->performance_level_count - 1].bSP = 4855 cpu_to_be32(pi->psp); 4856 } 4857 4858 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4859 struct rv7xx_pl *pl, 4860 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4861 { 4862 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4863 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4864 struct si_power_info *si_pi = si_get_pi(rdev); 4865 int ret; 4866 bool dll_state_on; 4867 u16 std_vddc; 4868 bool gmc_pg = false; 4869 4870 if (eg_pi->pcie_performance_request && 4871 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4872 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4873 else 4874 level->gen2PCIE = (u8)pl->pcie_gen; 4875 4876 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4877 if (ret) 4878 return ret; 4879 4880 level->mcFlags = 0; 4881 4882 if (pi->mclk_stutter_mode_threshold && 4883 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4884 !eg_pi->uvd_enabled && 4885 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4886 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4887 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4888 4889 if (gmc_pg) 4890 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4891 } 4892 4893 if (pi->mem_gddr5) { 4894 if (pl->mclk > pi->mclk_edc_enable_threshold) 4895 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4896 4897 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4898 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4899 4900 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4901 4902 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4903 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4904 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4905 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4906 else 4907 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4908 } else { 4909 dll_state_on = false; 4910 } 4911 } else { 4912 level->strobeMode = si_get_strobe_mode_settings(rdev, 4913 pl->mclk); 4914 4915 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4916 } 4917 4918 ret = si_populate_mclk_value(rdev, 4919 pl->sclk, 4920 pl->mclk, 4921 &level->mclk, 4922 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4923 if (ret) 4924 return ret; 4925 4926 ret = si_populate_voltage_value(rdev, 4927 &eg_pi->vddc_voltage_table, 4928 pl->vddc, &level->vddc); 4929 if (ret) 4930 return ret; 4931 4932 4933 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4934 if (ret) 4935 return ret; 4936 4937 ret = si_populate_std_voltage_value(rdev, std_vddc, 4938 level->vddc.index, &level->std_vddc); 4939 if (ret) 4940 return ret; 4941 4942 if (eg_pi->vddci_control) { 4943 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4944 pl->vddci, &level->vddci); 4945 if (ret) 4946 return ret; 4947 } 4948 4949 if (si_pi->vddc_phase_shed_control) { 4950 ret = si_populate_phase_shedding_value(rdev, 4951 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4952 pl->vddc, 4953 pl->sclk, 4954 pl->mclk, 4955 &level->vddc); 4956 if (ret) 4957 return ret; 4958 } 4959 4960 level->MaxPoweredUpCU = si_pi->max_cu; 4961 4962 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4963 4964 return ret; 4965 } 4966 4967 static int si_populate_smc_t(struct radeon_device *rdev, 4968 struct radeon_ps *radeon_state, 4969 SISLANDS_SMC_SWSTATE *smc_state) 4970 { 4971 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4972 struct ni_ps *state = ni_get_ps(radeon_state); 4973 u32 a_t; 4974 u32 t_l, t_h; 4975 u32 high_bsp; 4976 int i, ret; 4977 4978 if (state->performance_level_count >= 9) 4979 return -EINVAL; 4980 4981 if (state->performance_level_count < 2) { 4982 a_t = CG_R(0xffff) | CG_L(0); 4983 smc_state->levels[0].aT = cpu_to_be32(a_t); 4984 return 0; 4985 } 4986 4987 smc_state->levels[0].aT = cpu_to_be32(0); 4988 4989 for (i = 0; i <= state->performance_level_count - 2; i++) { 4990 ret = r600_calculate_at( 4991 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4992 100 * R600_AH_DFLT, 4993 state->performance_levels[i + 1].sclk, 4994 state->performance_levels[i].sclk, 4995 &t_l, 4996 &t_h); 4997 4998 if (ret) { 4999 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5000 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5001 } 5002 5003 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5004 a_t |= CG_R(t_l * pi->bsp / 20000); 5005 smc_state->levels[i].aT = cpu_to_be32(a_t); 5006 5007 high_bsp = (i == state->performance_level_count - 2) ? 5008 pi->pbsp : pi->bsp; 5009 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5010 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5011 } 5012 5013 return 0; 5014 } 5015 5016 static int si_disable_ulv(struct radeon_device *rdev) 5017 { 5018 struct si_power_info *si_pi = si_get_pi(rdev); 5019 struct si_ulv_param *ulv = &si_pi->ulv; 5020 5021 if (ulv->supported) 5022 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5023 0 : -EINVAL; 5024 5025 return 0; 5026 } 5027 5028 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5029 struct radeon_ps *radeon_state) 5030 { 5031 const struct si_power_info *si_pi = si_get_pi(rdev); 5032 const struct si_ulv_param *ulv = &si_pi->ulv; 5033 const struct ni_ps *state = ni_get_ps(radeon_state); 5034 int i; 5035 5036 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5037 return false; 5038 5039 /* XXX validate against display requirements! */ 5040 5041 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5042 if (rdev->clock.current_dispclk <= 5043 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5044 if (ulv->pl.vddc < 5045 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5046 return false; 5047 } 5048 } 5049 5050 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5051 return false; 5052 5053 return true; 5054 } 5055 5056 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5057 struct radeon_ps *radeon_new_state) 5058 { 5059 const struct si_power_info *si_pi = si_get_pi(rdev); 5060 const struct si_ulv_param *ulv = &si_pi->ulv; 5061 5062 if (ulv->supported) { 5063 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5064 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5065 0 : -EINVAL; 5066 } 5067 return 0; 5068 } 5069 5070 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5071 struct radeon_ps *radeon_state, 5072 SISLANDS_SMC_SWSTATE *smc_state) 5073 { 5074 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5075 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5076 struct si_power_info *si_pi = si_get_pi(rdev); 5077 struct ni_ps *state = ni_get_ps(radeon_state); 5078 int i, ret; 5079 u32 threshold; 5080 u32 sclk_in_sr = 1350; /* ??? */ 5081 5082 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5083 return -EINVAL; 5084 5085 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5086 5087 if (radeon_state->vclk && radeon_state->dclk) { 5088 eg_pi->uvd_enabled = true; 5089 if (eg_pi->smu_uvd_hs) 5090 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5091 } else { 5092 eg_pi->uvd_enabled = false; 5093 } 5094 5095 if (state->dc_compatible) 5096 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5097 5098 smc_state->levelCount = 0; 5099 for (i = 0; i < state->performance_level_count; i++) { 5100 if (eg_pi->sclk_deep_sleep) { 5101 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5102 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5103 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5104 else 5105 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5106 } 5107 } 5108 5109 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5110 &smc_state->levels[i]); 5111 smc_state->levels[i].arbRefreshState = 5112 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5113 5114 if (ret) 5115 return ret; 5116 5117 if (ni_pi->enable_power_containment) 5118 smc_state->levels[i].displayWatermark = 5119 (state->performance_levels[i].sclk < threshold) ? 5120 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5121 else 5122 smc_state->levels[i].displayWatermark = (i < 2) ? 5123 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5124 5125 if (eg_pi->dynamic_ac_timing) 5126 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5127 else 5128 smc_state->levels[i].ACIndex = 0; 5129 5130 smc_state->levelCount++; 5131 } 5132 5133 si_write_smc_soft_register(rdev, 5134 SI_SMC_SOFT_REGISTER_watermark_threshold, 5135 threshold / 512); 5136 5137 si_populate_smc_sp(rdev, radeon_state, smc_state); 5138 5139 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5140 if (ret) 5141 ni_pi->enable_power_containment = false; 5142 5143 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5144 if (ret) 5145 ni_pi->enable_sq_ramping = false; 5146 5147 return si_populate_smc_t(rdev, radeon_state, smc_state); 5148 } 5149 5150 static int si_upload_sw_state(struct radeon_device *rdev, 5151 struct radeon_ps *radeon_new_state) 5152 { 5153 struct si_power_info *si_pi = si_get_pi(rdev); 5154 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5155 int ret; 5156 u32 address = si_pi->state_table_start + 5157 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5158 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5159 ((new_state->performance_level_count - 1) * 5160 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5161 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5162 5163 memset(smc_state, 0, state_size); 5164 5165 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5166 if (ret) 5167 return ret; 5168 5169 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5170 state_size, si_pi->sram_end); 5171 5172 return ret; 5173 } 5174 5175 static int si_upload_ulv_state(struct radeon_device *rdev) 5176 { 5177 struct si_power_info *si_pi = si_get_pi(rdev); 5178 struct si_ulv_param *ulv = &si_pi->ulv; 5179 int ret = 0; 5180 5181 if (ulv->supported && ulv->pl.vddc) { 5182 u32 address = si_pi->state_table_start + 5183 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5184 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5185 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5186 5187 memset(smc_state, 0, state_size); 5188 5189 ret = si_populate_ulv_state(rdev, smc_state); 5190 if (!ret) 5191 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5192 state_size, si_pi->sram_end); 5193 } 5194 5195 return ret; 5196 } 5197 5198 static int si_upload_smc_data(struct radeon_device *rdev) 5199 { 5200 struct radeon_crtc *radeon_crtc = NULL; 5201 int i; 5202 5203 if (rdev->pm.dpm.new_active_crtc_count == 0) 5204 return 0; 5205 5206 for (i = 0; i < rdev->num_crtc; i++) { 5207 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5208 radeon_crtc = rdev->mode_info.crtcs[i]; 5209 break; 5210 } 5211 } 5212 5213 if (radeon_crtc == NULL) 5214 return 0; 5215 5216 if (radeon_crtc->line_time <= 0) 5217 return 0; 5218 5219 if (si_write_smc_soft_register(rdev, 5220 SI_SMC_SOFT_REGISTER_crtc_index, 5221 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5222 return 0; 5223 5224 if (si_write_smc_soft_register(rdev, 5225 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5226 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5227 return 0; 5228 5229 if (si_write_smc_soft_register(rdev, 5230 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5231 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5232 return 0; 5233 5234 return 0; 5235 } 5236 5237 static int si_set_mc_special_registers(struct radeon_device *rdev, 5238 struct si_mc_reg_table *table) 5239 { 5240 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5241 u8 i, j, k; 5242 u32 temp_reg; 5243 5244 for (i = 0, j = table->last; i < table->last; i++) { 5245 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5246 return -EINVAL; 5247 switch (table->mc_reg_address[i].s1 << 2) { 5248 case MC_SEQ_MISC1: 5249 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5250 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5251 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5252 for (k = 0; k < table->num_entries; k++) 5253 table->mc_reg_table_entry[k].mc_data[j] = 5254 ((temp_reg & 0xffff0000)) | 5255 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5256 j++; 5257 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5258 return -EINVAL; 5259 5260 temp_reg = RREG32(MC_PMG_CMD_MRS); 5261 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5262 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5263 for (k = 0; k < table->num_entries; k++) { 5264 table->mc_reg_table_entry[k].mc_data[j] = 5265 (temp_reg & 0xffff0000) | 5266 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5267 if (!pi->mem_gddr5) 5268 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5269 } 5270 j++; 5271 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5272 return -EINVAL; 5273 5274 if (!pi->mem_gddr5) { 5275 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5276 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5277 for (k = 0; k < table->num_entries; k++) 5278 table->mc_reg_table_entry[k].mc_data[j] = 5279 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5280 j++; 5281 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5282 return -EINVAL; 5283 } 5284 break; 5285 case MC_SEQ_RESERVE_M: 5286 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5287 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5288 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5289 for(k = 0; k < table->num_entries; k++) 5290 table->mc_reg_table_entry[k].mc_data[j] = 5291 (temp_reg & 0xffff0000) | 5292 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5293 j++; 5294 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5295 return -EINVAL; 5296 break; 5297 default: 5298 break; 5299 } 5300 } 5301 5302 table->last = j; 5303 5304 return 0; 5305 } 5306 5307 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5308 { 5309 bool result = true; 5310 5311 switch (in_reg) { 5312 case MC_SEQ_RAS_TIMING >> 2: 5313 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5314 break; 5315 case MC_SEQ_CAS_TIMING >> 2: 5316 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5317 break; 5318 case MC_SEQ_MISC_TIMING >> 2: 5319 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5320 break; 5321 case MC_SEQ_MISC_TIMING2 >> 2: 5322 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5323 break; 5324 case MC_SEQ_RD_CTL_D0 >> 2: 5325 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5326 break; 5327 case MC_SEQ_RD_CTL_D1 >> 2: 5328 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5329 break; 5330 case MC_SEQ_WR_CTL_D0 >> 2: 5331 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5332 break; 5333 case MC_SEQ_WR_CTL_D1 >> 2: 5334 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5335 break; 5336 case MC_PMG_CMD_EMRS >> 2: 5337 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5338 break; 5339 case MC_PMG_CMD_MRS >> 2: 5340 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5341 break; 5342 case MC_PMG_CMD_MRS1 >> 2: 5343 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5344 break; 5345 case MC_SEQ_PMG_TIMING >> 2: 5346 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5347 break; 5348 case MC_PMG_CMD_MRS2 >> 2: 5349 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5350 break; 5351 case MC_SEQ_WR_CTL_2 >> 2: 5352 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5353 break; 5354 default: 5355 result = false; 5356 break; 5357 } 5358 5359 return result; 5360 } 5361 5362 static void si_set_valid_flag(struct si_mc_reg_table *table) 5363 { 5364 u8 i, j; 5365 5366 for (i = 0; i < table->last; i++) { 5367 for (j = 1; j < table->num_entries; j++) { 5368 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5369 table->valid_flag |= 1 << i; 5370 break; 5371 } 5372 } 5373 } 5374 } 5375 5376 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5377 { 5378 u32 i; 5379 u16 address; 5380 5381 for (i = 0; i < table->last; i++) 5382 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5383 address : table->mc_reg_address[i].s1; 5384 5385 } 5386 5387 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5388 struct si_mc_reg_table *si_table) 5389 { 5390 u8 i, j; 5391 5392 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5393 return -EINVAL; 5394 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5395 return -EINVAL; 5396 5397 for (i = 0; i < table->last; i++) 5398 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5399 si_table->last = table->last; 5400 5401 for (i = 0; i < table->num_entries; i++) { 5402 si_table->mc_reg_table_entry[i].mclk_max = 5403 table->mc_reg_table_entry[i].mclk_max; 5404 for (j = 0; j < table->last; j++) { 5405 si_table->mc_reg_table_entry[i].mc_data[j] = 5406 table->mc_reg_table_entry[i].mc_data[j]; 5407 } 5408 } 5409 si_table->num_entries = table->num_entries; 5410 5411 return 0; 5412 } 5413 5414 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5415 { 5416 struct si_power_info *si_pi = si_get_pi(rdev); 5417 struct atom_mc_reg_table *table; 5418 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5419 u8 module_index = rv770_get_memory_module_index(rdev); 5420 int ret; 5421 5422 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5423 if (!table) 5424 return -ENOMEM; 5425 5426 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5427 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5428 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5429 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5430 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5431 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5432 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5433 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5434 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5435 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5436 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5437 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5438 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5439 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5440 5441 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5442 if (ret) 5443 goto init_mc_done; 5444 5445 ret = si_copy_vbios_mc_reg_table(table, si_table); 5446 if (ret) 5447 goto init_mc_done; 5448 5449 si_set_s0_mc_reg_index(si_table); 5450 5451 ret = si_set_mc_special_registers(rdev, si_table); 5452 if (ret) 5453 goto init_mc_done; 5454 5455 si_set_valid_flag(si_table); 5456 5457 init_mc_done: 5458 kfree(table); 5459 5460 return ret; 5461 5462 } 5463 5464 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5465 SMC_SIslands_MCRegisters *mc_reg_table) 5466 { 5467 struct si_power_info *si_pi = si_get_pi(rdev); 5468 u32 i, j; 5469 5470 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5471 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5472 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5473 break; 5474 mc_reg_table->address[i].s0 = 5475 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5476 mc_reg_table->address[i].s1 = 5477 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5478 i++; 5479 } 5480 } 5481 mc_reg_table->last = (u8)i; 5482 } 5483 5484 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5485 SMC_SIslands_MCRegisterSet *data, 5486 u32 num_entries, u32 valid_flag) 5487 { 5488 u32 i, j; 5489 5490 for(i = 0, j = 0; j < num_entries; j++) { 5491 if (valid_flag & (1 << j)) { 5492 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5493 i++; 5494 } 5495 } 5496 } 5497 5498 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5499 struct rv7xx_pl *pl, 5500 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5501 { 5502 struct si_power_info *si_pi = si_get_pi(rdev); 5503 u32 i = 0; 5504 5505 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5506 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5507 break; 5508 } 5509 5510 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5511 --i; 5512 5513 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5514 mc_reg_table_data, si_pi->mc_reg_table.last, 5515 si_pi->mc_reg_table.valid_flag); 5516 } 5517 5518 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5519 struct radeon_ps *radeon_state, 5520 SMC_SIslands_MCRegisters *mc_reg_table) 5521 { 5522 struct ni_ps *state = ni_get_ps(radeon_state); 5523 int i; 5524 5525 for (i = 0; i < state->performance_level_count; i++) { 5526 si_convert_mc_reg_table_entry_to_smc(rdev, 5527 &state->performance_levels[i], 5528 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5529 } 5530 } 5531 5532 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5533 struct radeon_ps *radeon_boot_state) 5534 { 5535 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5536 struct si_power_info *si_pi = si_get_pi(rdev); 5537 struct si_ulv_param *ulv = &si_pi->ulv; 5538 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5539 5540 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5541 5542 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5543 5544 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5545 5546 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5547 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5548 5549 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5550 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5551 si_pi->mc_reg_table.last, 5552 si_pi->mc_reg_table.valid_flag); 5553 5554 if (ulv->supported && ulv->pl.vddc != 0) 5555 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5556 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5557 else 5558 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5559 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5560 si_pi->mc_reg_table.last, 5561 si_pi->mc_reg_table.valid_flag); 5562 5563 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5564 5565 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5566 (u8 *)smc_mc_reg_table, 5567 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5568 } 5569 5570 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5571 struct radeon_ps *radeon_new_state) 5572 { 5573 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5574 struct si_power_info *si_pi = si_get_pi(rdev); 5575 u32 address = si_pi->mc_reg_table_start + 5576 offsetof(SMC_SIslands_MCRegisters, 5577 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5578 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5579 5580 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5581 5582 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5583 5584 5585 return si_copy_bytes_to_smc(rdev, address, 5586 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5587 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5588 si_pi->sram_end); 5589 5590 } 5591 5592 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5593 { 5594 if (enable) 5595 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5596 else 5597 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5598 } 5599 5600 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5601 struct radeon_ps *radeon_state) 5602 { 5603 struct ni_ps *state = ni_get_ps(radeon_state); 5604 int i; 5605 u16 pcie_speed, max_speed = 0; 5606 5607 for (i = 0; i < state->performance_level_count; i++) { 5608 pcie_speed = state->performance_levels[i].pcie_gen; 5609 if (max_speed < pcie_speed) 5610 max_speed = pcie_speed; 5611 } 5612 return max_speed; 5613 } 5614 5615 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5616 { 5617 u32 speed_cntl; 5618 5619 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5620 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5621 5622 return (u16)speed_cntl; 5623 } 5624 5625 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5626 struct radeon_ps *radeon_new_state, 5627 struct radeon_ps *radeon_current_state) 5628 { 5629 struct si_power_info *si_pi = si_get_pi(rdev); 5630 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5631 enum radeon_pcie_gen current_link_speed; 5632 5633 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5634 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5635 else 5636 current_link_speed = si_pi->force_pcie_gen; 5637 5638 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5639 si_pi->pspp_notify_required = false; 5640 if (target_link_speed > current_link_speed) { 5641 switch (target_link_speed) { 5642 #if defined(CONFIG_ACPI) 5643 case RADEON_PCIE_GEN3: 5644 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5645 break; 5646 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5647 if (current_link_speed == RADEON_PCIE_GEN2) 5648 break; 5649 case RADEON_PCIE_GEN2: 5650 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5651 break; 5652 #endif 5653 default: 5654 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5655 break; 5656 } 5657 } else { 5658 if (target_link_speed < current_link_speed) 5659 si_pi->pspp_notify_required = true; 5660 } 5661 } 5662 5663 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5664 struct radeon_ps *radeon_new_state, 5665 struct radeon_ps *radeon_current_state) 5666 { 5667 struct si_power_info *si_pi = si_get_pi(rdev); 5668 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5669 u8 request; 5670 5671 if (si_pi->pspp_notify_required) { 5672 if (target_link_speed == RADEON_PCIE_GEN3) 5673 request = PCIE_PERF_REQ_PECI_GEN3; 5674 else if (target_link_speed == RADEON_PCIE_GEN2) 5675 request = PCIE_PERF_REQ_PECI_GEN2; 5676 else 5677 request = PCIE_PERF_REQ_PECI_GEN1; 5678 5679 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5680 (si_get_current_pcie_speed(rdev) > 0)) 5681 return; 5682 5683 #if defined(CONFIG_ACPI) 5684 radeon_acpi_pcie_performance_request(rdev, request, false); 5685 #endif 5686 } 5687 } 5688 5689 #if 0 5690 static int si_ds_request(struct radeon_device *rdev, 5691 bool ds_status_on, u32 count_write) 5692 { 5693 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5694 5695 if (eg_pi->sclk_deep_sleep) { 5696 if (ds_status_on) 5697 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5698 PPSMC_Result_OK) ? 5699 0 : -EINVAL; 5700 else 5701 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5702 PPSMC_Result_OK) ? 0 : -EINVAL; 5703 } 5704 return 0; 5705 } 5706 #endif 5707 5708 static void si_set_max_cu_value(struct radeon_device *rdev) 5709 { 5710 struct si_power_info *si_pi = si_get_pi(rdev); 5711 5712 if (rdev->family == CHIP_VERDE) { 5713 switch (rdev->pdev->device) { 5714 case 0x6820: 5715 case 0x6825: 5716 case 0x6821: 5717 case 0x6823: 5718 case 0x6827: 5719 si_pi->max_cu = 10; 5720 break; 5721 case 0x682D: 5722 case 0x6824: 5723 case 0x682F: 5724 case 0x6826: 5725 si_pi->max_cu = 8; 5726 break; 5727 case 0x6828: 5728 case 0x6830: 5729 case 0x6831: 5730 case 0x6838: 5731 case 0x6839: 5732 case 0x683D: 5733 si_pi->max_cu = 10; 5734 break; 5735 case 0x683B: 5736 case 0x683F: 5737 case 0x6829: 5738 si_pi->max_cu = 8; 5739 break; 5740 default: 5741 si_pi->max_cu = 0; 5742 break; 5743 } 5744 } else { 5745 si_pi->max_cu = 0; 5746 } 5747 } 5748 5749 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5750 struct radeon_clock_voltage_dependency_table *table) 5751 { 5752 u32 i; 5753 int j; 5754 u16 leakage_voltage; 5755 5756 if (table) { 5757 for (i = 0; i < table->count; i++) { 5758 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5759 table->entries[i].v, 5760 &leakage_voltage)) { 5761 case 0: 5762 table->entries[i].v = leakage_voltage; 5763 break; 5764 case -EAGAIN: 5765 return -EINVAL; 5766 case -EINVAL: 5767 default: 5768 break; 5769 } 5770 } 5771 5772 for (j = (table->count - 2); j >= 0; j--) { 5773 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5774 table->entries[j].v : table->entries[j + 1].v; 5775 } 5776 } 5777 return 0; 5778 } 5779 5780 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5781 { 5782 int ret = 0; 5783 5784 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5785 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5786 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5787 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5788 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5789 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5790 return ret; 5791 } 5792 5793 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5794 struct radeon_ps *radeon_new_state, 5795 struct radeon_ps *radeon_current_state) 5796 { 5797 u32 lane_width; 5798 u32 new_lane_width = 5799 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5800 u32 current_lane_width = 5801 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5802 5803 if (new_lane_width != current_lane_width) { 5804 radeon_set_pcie_lanes(rdev, new_lane_width); 5805 lane_width = radeon_get_pcie_lanes(rdev); 5806 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5807 } 5808 } 5809 5810 void si_dpm_setup_asic(struct radeon_device *rdev) 5811 { 5812 int r; 5813 5814 r = si_mc_load_microcode(rdev); 5815 if (r) 5816 DRM_ERROR("Failed to load MC firmware!\n"); 5817 rv770_get_memory_type(rdev); 5818 si_read_clock_registers(rdev); 5819 si_enable_acpi_power_management(rdev); 5820 } 5821 5822 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5823 int min_temp, int max_temp) 5824 { 5825 int low_temp = 0 * 1000; 5826 int high_temp = 255 * 1000; 5827 5828 if (low_temp < min_temp) 5829 low_temp = min_temp; 5830 if (high_temp > max_temp) 5831 high_temp = max_temp; 5832 if (high_temp < low_temp) { 5833 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5834 return -EINVAL; 5835 } 5836 5837 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5838 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5839 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5840 5841 rdev->pm.dpm.thermal.min_temp = low_temp; 5842 rdev->pm.dpm.thermal.max_temp = high_temp; 5843 5844 return 0; 5845 } 5846 5847 int si_dpm_enable(struct radeon_device *rdev) 5848 { 5849 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5850 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5851 struct si_power_info *si_pi = si_get_pi(rdev); 5852 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5853 int ret; 5854 5855 if (si_is_smc_running(rdev)) 5856 return -EINVAL; 5857 if (pi->voltage_control || si_pi->voltage_control_svi2) 5858 si_enable_voltage_control(rdev, true); 5859 if (pi->mvdd_control) 5860 si_get_mvdd_configuration(rdev); 5861 if (pi->voltage_control || si_pi->voltage_control_svi2) { 5862 ret = si_construct_voltage_tables(rdev); 5863 if (ret) { 5864 DRM_ERROR("si_construct_voltage_tables failed\n"); 5865 return ret; 5866 } 5867 } 5868 if (eg_pi->dynamic_ac_timing) { 5869 ret = si_initialize_mc_reg_table(rdev); 5870 if (ret) 5871 eg_pi->dynamic_ac_timing = false; 5872 } 5873 if (pi->dynamic_ss) 5874 si_enable_spread_spectrum(rdev, true); 5875 if (pi->thermal_protection) 5876 si_enable_thermal_protection(rdev, true); 5877 si_setup_bsp(rdev); 5878 si_program_git(rdev); 5879 si_program_tp(rdev); 5880 si_program_tpp(rdev); 5881 si_program_sstp(rdev); 5882 si_enable_display_gap(rdev); 5883 si_program_vc(rdev); 5884 ret = si_upload_firmware(rdev); 5885 if (ret) { 5886 DRM_ERROR("si_upload_firmware failed\n"); 5887 return ret; 5888 } 5889 ret = si_process_firmware_header(rdev); 5890 if (ret) { 5891 DRM_ERROR("si_process_firmware_header failed\n"); 5892 return ret; 5893 } 5894 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5895 if (ret) { 5896 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5897 return ret; 5898 } 5899 ret = si_init_smc_table(rdev); 5900 if (ret) { 5901 DRM_ERROR("si_init_smc_table failed\n"); 5902 return ret; 5903 } 5904 ret = si_init_smc_spll_table(rdev); 5905 if (ret) { 5906 DRM_ERROR("si_init_smc_spll_table failed\n"); 5907 return ret; 5908 } 5909 ret = si_init_arb_table_index(rdev); 5910 if (ret) { 5911 DRM_ERROR("si_init_arb_table_index failed\n"); 5912 return ret; 5913 } 5914 if (eg_pi->dynamic_ac_timing) { 5915 ret = si_populate_mc_reg_table(rdev, boot_ps); 5916 if (ret) { 5917 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5918 return ret; 5919 } 5920 } 5921 ret = si_initialize_smc_cac_tables(rdev); 5922 if (ret) { 5923 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5924 return ret; 5925 } 5926 ret = si_initialize_hardware_cac_manager(rdev); 5927 if (ret) { 5928 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5929 return ret; 5930 } 5931 ret = si_initialize_smc_dte_tables(rdev); 5932 if (ret) { 5933 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5934 return ret; 5935 } 5936 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5937 if (ret) { 5938 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5939 return ret; 5940 } 5941 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5942 if (ret) { 5943 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5944 return ret; 5945 } 5946 si_program_response_times(rdev); 5947 si_program_ds_registers(rdev); 5948 si_dpm_start_smc(rdev); 5949 ret = si_notify_smc_display_change(rdev, false); 5950 if (ret) { 5951 DRM_ERROR("si_notify_smc_display_change failed\n"); 5952 return ret; 5953 } 5954 si_enable_sclk_control(rdev, true); 5955 si_start_dpm(rdev); 5956 5957 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5958 5959 ni_update_current_ps(rdev, boot_ps); 5960 5961 return 0; 5962 } 5963 5964 int si_dpm_late_enable(struct radeon_device *rdev) 5965 { 5966 int ret; 5967 5968 if (rdev->irq.installed && 5969 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5970 PPSMC_Result result; 5971 5972 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5973 if (ret) 5974 return ret; 5975 rdev->irq.dpm_thermal = true; 5976 radeon_irq_set(rdev); 5977 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5978 5979 if (result != PPSMC_Result_OK) 5980 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5981 } 5982 5983 return 0; 5984 } 5985 5986 void si_dpm_disable(struct radeon_device *rdev) 5987 { 5988 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5989 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5990 5991 if (!si_is_smc_running(rdev)) 5992 return; 5993 si_disable_ulv(rdev); 5994 si_clear_vc(rdev); 5995 if (pi->thermal_protection) 5996 si_enable_thermal_protection(rdev, false); 5997 si_enable_power_containment(rdev, boot_ps, false); 5998 si_enable_smc_cac(rdev, boot_ps, false); 5999 si_enable_spread_spectrum(rdev, false); 6000 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6001 si_stop_dpm(rdev); 6002 si_reset_to_default(rdev); 6003 si_dpm_stop_smc(rdev); 6004 si_force_switch_to_arb_f0(rdev); 6005 6006 ni_update_current_ps(rdev, boot_ps); 6007 } 6008 6009 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6010 { 6011 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6012 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6013 struct radeon_ps *new_ps = &requested_ps; 6014 6015 ni_update_requested_ps(rdev, new_ps); 6016 6017 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6018 6019 return 0; 6020 } 6021 6022 static int si_power_control_set_level(struct radeon_device *rdev) 6023 { 6024 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6025 int ret; 6026 6027 ret = si_restrict_performance_levels_before_switch(rdev); 6028 if (ret) 6029 return ret; 6030 ret = si_halt_smc(rdev); 6031 if (ret) 6032 return ret; 6033 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6034 if (ret) 6035 return ret; 6036 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6037 if (ret) 6038 return ret; 6039 ret = si_resume_smc(rdev); 6040 if (ret) 6041 return ret; 6042 ret = si_set_sw_state(rdev); 6043 if (ret) 6044 return ret; 6045 return 0; 6046 } 6047 6048 int si_dpm_set_power_state(struct radeon_device *rdev) 6049 { 6050 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6051 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6052 struct radeon_ps *old_ps = &eg_pi->current_rps; 6053 int ret; 6054 6055 ret = si_disable_ulv(rdev); 6056 if (ret) { 6057 DRM_ERROR("si_disable_ulv failed\n"); 6058 return ret; 6059 } 6060 ret = si_restrict_performance_levels_before_switch(rdev); 6061 if (ret) { 6062 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6063 return ret; 6064 } 6065 if (eg_pi->pcie_performance_request) 6066 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6067 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6068 ret = si_enable_power_containment(rdev, new_ps, false); 6069 if (ret) { 6070 DRM_ERROR("si_enable_power_containment failed\n"); 6071 return ret; 6072 } 6073 ret = si_enable_smc_cac(rdev, new_ps, false); 6074 if (ret) { 6075 DRM_ERROR("si_enable_smc_cac failed\n"); 6076 return ret; 6077 } 6078 ret = si_halt_smc(rdev); 6079 if (ret) { 6080 DRM_ERROR("si_halt_smc failed\n"); 6081 return ret; 6082 } 6083 ret = si_upload_sw_state(rdev, new_ps); 6084 if (ret) { 6085 DRM_ERROR("si_upload_sw_state failed\n"); 6086 return ret; 6087 } 6088 ret = si_upload_smc_data(rdev); 6089 if (ret) { 6090 DRM_ERROR("si_upload_smc_data failed\n"); 6091 return ret; 6092 } 6093 ret = si_upload_ulv_state(rdev); 6094 if (ret) { 6095 DRM_ERROR("si_upload_ulv_state failed\n"); 6096 return ret; 6097 } 6098 if (eg_pi->dynamic_ac_timing) { 6099 ret = si_upload_mc_reg_table(rdev, new_ps); 6100 if (ret) { 6101 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6102 return ret; 6103 } 6104 } 6105 ret = si_program_memory_timing_parameters(rdev, new_ps); 6106 if (ret) { 6107 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6108 return ret; 6109 } 6110 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6111 6112 ret = si_resume_smc(rdev); 6113 if (ret) { 6114 DRM_ERROR("si_resume_smc failed\n"); 6115 return ret; 6116 } 6117 ret = si_set_sw_state(rdev); 6118 if (ret) { 6119 DRM_ERROR("si_set_sw_state failed\n"); 6120 return ret; 6121 } 6122 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6123 if (eg_pi->pcie_performance_request) 6124 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6125 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6126 if (ret) { 6127 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6128 return ret; 6129 } 6130 ret = si_enable_smc_cac(rdev, new_ps, true); 6131 if (ret) { 6132 DRM_ERROR("si_enable_smc_cac failed\n"); 6133 return ret; 6134 } 6135 ret = si_enable_power_containment(rdev, new_ps, true); 6136 if (ret) { 6137 DRM_ERROR("si_enable_power_containment failed\n"); 6138 return ret; 6139 } 6140 6141 ret = si_power_control_set_level(rdev); 6142 if (ret) { 6143 DRM_ERROR("si_power_control_set_level failed\n"); 6144 return ret; 6145 } 6146 6147 return 0; 6148 } 6149 6150 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6151 { 6152 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6153 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6154 6155 ni_update_current_ps(rdev, new_ps); 6156 } 6157 6158 #if 0 6159 void si_dpm_reset_asic(struct radeon_device *rdev) 6160 { 6161 si_restrict_performance_levels_before_switch(rdev); 6162 si_disable_ulv(rdev); 6163 si_set_boot_state(rdev); 6164 } 6165 #endif 6166 6167 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6168 { 6169 si_program_display_gap(rdev); 6170 } 6171 6172 union power_info { 6173 struct _ATOM_POWERPLAY_INFO info; 6174 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6175 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6176 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6177 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6178 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6179 }; 6180 6181 union pplib_clock_info { 6182 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6183 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6184 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6185 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6186 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6187 }; 6188 6189 union pplib_power_state { 6190 struct _ATOM_PPLIB_STATE v1; 6191 struct _ATOM_PPLIB_STATE_V2 v2; 6192 }; 6193 6194 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6195 struct radeon_ps *rps, 6196 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6197 u8 table_rev) 6198 { 6199 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6200 rps->class = le16_to_cpu(non_clock_info->usClassification); 6201 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6202 6203 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6204 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6205 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6206 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6207 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6208 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6209 } else { 6210 rps->vclk = 0; 6211 rps->dclk = 0; 6212 } 6213 6214 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6215 rdev->pm.dpm.boot_ps = rps; 6216 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6217 rdev->pm.dpm.uvd_ps = rps; 6218 } 6219 6220 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6221 struct radeon_ps *rps, int index, 6222 union pplib_clock_info *clock_info) 6223 { 6224 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6225 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6226 struct si_power_info *si_pi = si_get_pi(rdev); 6227 struct ni_ps *ps = ni_get_ps(rps); 6228 u16 leakage_voltage; 6229 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6230 int ret; 6231 6232 ps->performance_level_count = index + 1; 6233 6234 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6235 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6236 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6237 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6238 6239 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6240 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6241 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6242 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6243 si_pi->sys_pcie_mask, 6244 si_pi->boot_pcie_gen, 6245 clock_info->si.ucPCIEGen); 6246 6247 /* patch up vddc if necessary */ 6248 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6249 &leakage_voltage); 6250 if (ret == 0) 6251 pl->vddc = leakage_voltage; 6252 6253 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6254 pi->acpi_vddc = pl->vddc; 6255 eg_pi->acpi_vddci = pl->vddci; 6256 si_pi->acpi_pcie_gen = pl->pcie_gen; 6257 } 6258 6259 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6260 index == 0) { 6261 /* XXX disable for A0 tahiti */ 6262 si_pi->ulv.supported = false; 6263 si_pi->ulv.pl = *pl; 6264 si_pi->ulv.one_pcie_lane_in_ulv = false; 6265 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6266 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6267 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6268 } 6269 6270 if (pi->min_vddc_in_table > pl->vddc) 6271 pi->min_vddc_in_table = pl->vddc; 6272 6273 if (pi->max_vddc_in_table < pl->vddc) 6274 pi->max_vddc_in_table = pl->vddc; 6275 6276 /* patch up boot state */ 6277 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6278 u16 vddc, vddci, mvdd; 6279 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6280 pl->mclk = rdev->clock.default_mclk; 6281 pl->sclk = rdev->clock.default_sclk; 6282 pl->vddc = vddc; 6283 pl->vddci = vddci; 6284 si_pi->mvdd_bootup_value = mvdd; 6285 } 6286 6287 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6288 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6289 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6290 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6291 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6292 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6293 } 6294 } 6295 6296 static int si_parse_power_table(struct radeon_device *rdev) 6297 { 6298 struct radeon_mode_info *mode_info = &rdev->mode_info; 6299 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6300 union pplib_power_state *power_state; 6301 int i, j, k, non_clock_array_index, clock_array_index; 6302 union pplib_clock_info *clock_info; 6303 struct _StateArray *state_array; 6304 struct _ClockInfoArray *clock_info_array; 6305 struct _NonClockInfoArray *non_clock_info_array; 6306 union power_info *power_info; 6307 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6308 u16 data_offset; 6309 u8 frev, crev; 6310 u8 *power_state_offset; 6311 struct ni_ps *ps; 6312 6313 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6314 &frev, &crev, &data_offset)) 6315 return -EINVAL; 6316 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6317 6318 state_array = (struct _StateArray *) 6319 (mode_info->atom_context->bios + data_offset + 6320 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6321 clock_info_array = (struct _ClockInfoArray *) 6322 (mode_info->atom_context->bios + data_offset + 6323 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6324 non_clock_info_array = (struct _NonClockInfoArray *) 6325 (mode_info->atom_context->bios + data_offset + 6326 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6327 6328 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6329 state_array->ucNumEntries, GFP_KERNEL); 6330 if (!rdev->pm.dpm.ps) 6331 return -ENOMEM; 6332 power_state_offset = (u8 *)state_array->states; 6333 for (i = 0; i < state_array->ucNumEntries; i++) { 6334 u8 *idx; 6335 power_state = (union pplib_power_state *)power_state_offset; 6336 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6337 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6338 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6339 if (!rdev->pm.power_state[i].clock_info) 6340 return -EINVAL; 6341 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6342 if (ps == NULL) { 6343 kfree(rdev->pm.dpm.ps); 6344 return -ENOMEM; 6345 } 6346 rdev->pm.dpm.ps[i].ps_priv = ps; 6347 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6348 non_clock_info, 6349 non_clock_info_array->ucEntrySize); 6350 k = 0; 6351 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6352 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6353 clock_array_index = idx[j]; 6354 if (clock_array_index >= clock_info_array->ucNumEntries) 6355 continue; 6356 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6357 break; 6358 clock_info = (union pplib_clock_info *) 6359 ((u8 *)&clock_info_array->clockInfo[0] + 6360 (clock_array_index * clock_info_array->ucEntrySize)); 6361 si_parse_pplib_clock_info(rdev, 6362 &rdev->pm.dpm.ps[i], k, 6363 clock_info); 6364 k++; 6365 } 6366 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6367 } 6368 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6369 return 0; 6370 } 6371 6372 int si_dpm_init(struct radeon_device *rdev) 6373 { 6374 struct rv7xx_power_info *pi; 6375 struct evergreen_power_info *eg_pi; 6376 struct ni_power_info *ni_pi; 6377 struct si_power_info *si_pi; 6378 struct atom_clock_dividers dividers; 6379 int ret; 6380 u32 mask; 6381 6382 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6383 if (si_pi == NULL) 6384 return -ENOMEM; 6385 rdev->pm.dpm.priv = si_pi; 6386 ni_pi = &si_pi->ni; 6387 eg_pi = &ni_pi->eg; 6388 pi = &eg_pi->rv7xx; 6389 6390 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6391 if (ret) 6392 si_pi->sys_pcie_mask = 0; 6393 else 6394 si_pi->sys_pcie_mask = mask; 6395 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6396 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6397 6398 si_set_max_cu_value(rdev); 6399 6400 rv770_get_max_vddc(rdev); 6401 si_get_leakage_vddc(rdev); 6402 si_patch_dependency_tables_based_on_leakage(rdev); 6403 6404 pi->acpi_vddc = 0; 6405 eg_pi->acpi_vddci = 0; 6406 pi->min_vddc_in_table = 0; 6407 pi->max_vddc_in_table = 0; 6408 6409 ret = r600_get_platform_caps(rdev); 6410 if (ret) 6411 return ret; 6412 6413 ret = si_parse_power_table(rdev); 6414 if (ret) 6415 return ret; 6416 ret = r600_parse_extended_power_table(rdev); 6417 if (ret) 6418 return ret; 6419 6420 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6421 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6422 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6423 r600_free_extended_power_table(rdev); 6424 return -ENOMEM; 6425 } 6426 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6427 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6428 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6429 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6430 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6431 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6432 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6433 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6434 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6435 6436 if (rdev->pm.dpm.voltage_response_time == 0) 6437 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6438 if (rdev->pm.dpm.backbias_response_time == 0) 6439 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6440 6441 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6442 0, false, ÷rs); 6443 if (ret) 6444 pi->ref_div = dividers.ref_div + 1; 6445 else 6446 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6447 6448 eg_pi->smu_uvd_hs = false; 6449 6450 pi->mclk_strobe_mode_threshold = 40000; 6451 if (si_is_special_1gb_platform(rdev)) 6452 pi->mclk_stutter_mode_threshold = 0; 6453 else 6454 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6455 pi->mclk_edc_enable_threshold = 40000; 6456 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6457 6458 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6459 6460 pi->voltage_control = 6461 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6462 VOLTAGE_OBJ_GPIO_LUT); 6463 if (!pi->voltage_control) { 6464 si_pi->voltage_control_svi2 = 6465 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6466 VOLTAGE_OBJ_SVID2); 6467 if (si_pi->voltage_control_svi2) 6468 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6469 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6470 } 6471 6472 pi->mvdd_control = 6473 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6474 VOLTAGE_OBJ_GPIO_LUT); 6475 6476 eg_pi->vddci_control = 6477 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6478 VOLTAGE_OBJ_GPIO_LUT); 6479 if (!eg_pi->vddci_control) 6480 si_pi->vddci_control_svi2 = 6481 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6482 VOLTAGE_OBJ_SVID2); 6483 6484 si_pi->vddc_phase_shed_control = 6485 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6486 VOLTAGE_OBJ_PHASE_LUT); 6487 6488 rv770_get_engine_memory_ss(rdev); 6489 6490 pi->asi = RV770_ASI_DFLT; 6491 pi->pasi = CYPRESS_HASI_DFLT; 6492 pi->vrc = SISLANDS_VRC_DFLT; 6493 6494 pi->gfx_clock_gating = true; 6495 6496 eg_pi->sclk_deep_sleep = true; 6497 si_pi->sclk_deep_sleep_above_low = false; 6498 6499 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6500 pi->thermal_protection = true; 6501 else 6502 pi->thermal_protection = false; 6503 6504 eg_pi->dynamic_ac_timing = true; 6505 6506 eg_pi->light_sleep = true; 6507 #if defined(CONFIG_ACPI) 6508 eg_pi->pcie_performance_request = 6509 radeon_acpi_is_pcie_performance_request_supported(rdev); 6510 #else 6511 eg_pi->pcie_performance_request = false; 6512 #endif 6513 6514 si_pi->sram_end = SMC_RAM_END; 6515 6516 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6517 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6518 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6519 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6520 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6521 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6522 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6523 6524 si_initialize_powertune_defaults(rdev); 6525 6526 /* make sure dc limits are valid */ 6527 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6528 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6529 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6530 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6531 6532 return 0; 6533 } 6534 6535 void si_dpm_fini(struct radeon_device *rdev) 6536 { 6537 int i; 6538 6539 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6540 kfree(rdev->pm.dpm.ps[i].ps_priv); 6541 } 6542 kfree(rdev->pm.dpm.ps); 6543 kfree(rdev->pm.dpm.priv); 6544 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6545 r600_free_extended_power_table(rdev); 6546 } 6547 6548 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6549 struct seq_file *m) 6550 { 6551 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6552 struct radeon_ps *rps = &eg_pi->current_rps; 6553 struct ni_ps *ps = ni_get_ps(rps); 6554 struct rv7xx_pl *pl; 6555 u32 current_index = 6556 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6557 CURRENT_STATE_INDEX_SHIFT; 6558 6559 if (current_index >= ps->performance_level_count) { 6560 seq_printf(m, "invalid dpm profile %d\n", current_index); 6561 } else { 6562 pl = &ps->performance_levels[current_index]; 6563 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6564 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6565 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6566 } 6567 } 6568