1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 static const struct si_dte_data dte_data_tahiti_le = 255 { 256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 258 0x5, 259 0xAFC8, 260 0x64, 261 0x32, 262 1, 263 0, 264 0x10, 265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 268 85, 269 true 270 }; 271 272 static const struct si_dte_data dte_data_tahiti_pro = 273 { 274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 275 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 276 5, 277 45000, 278 100, 279 0xA, 280 1, 281 0, 282 0x10, 283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 286 90, 287 true 288 }; 289 290 static const struct si_dte_data dte_data_new_zealand = 291 { 292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 294 0x5, 295 0xAFC8, 296 0x69, 297 0x32, 298 1, 299 0, 300 0x10, 301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 304 85, 305 true 306 }; 307 308 static const struct si_dte_data dte_data_aruba_pro = 309 { 310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 311 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 312 5, 313 45000, 314 100, 315 0xA, 316 1, 317 0, 318 0x10, 319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 322 90, 323 true 324 }; 325 326 static const struct si_dte_data dte_data_malta = 327 { 328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 329 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 330 5, 331 45000, 332 100, 333 0xA, 334 1, 335 0, 336 0x10, 337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 340 90, 341 true 342 }; 343 344 struct si_cac_config_reg cac_weights_pitcairn[] = 345 { 346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 406 { 0xFFFFFFFF } 407 }; 408 409 static const struct si_cac_config_reg lcac_pitcairn[] = 410 { 411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0xFFFFFFFF } 498 }; 499 500 static const struct si_cac_config_reg cac_override_pitcairn[] = 501 { 502 { 0xFFFFFFFF } 503 }; 504 505 static const struct si_powertune_data powertune_data_pitcairn = 506 { 507 ((1 << 16) | 27027), 508 5, 509 0, 510 6, 511 100, 512 { 513 51600000UL, 514 1800000UL, 515 7194395UL, 516 309631529UL, 517 -1270850L, 518 4513710L, 519 100 520 }, 521 117830498UL, 522 12, 523 { 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0 532 }, 533 true 534 }; 535 536 static const struct si_dte_data dte_data_pitcairn = 537 { 538 { 0, 0, 0, 0, 0 }, 539 { 0, 0, 0, 0, 0 }, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 0, 551 false 552 }; 553 554 static const struct si_dte_data dte_data_curacao_xt = 555 { 556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 557 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 558 5, 559 45000, 560 100, 561 0xA, 562 1, 563 0, 564 0x10, 565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 568 90, 569 true 570 }; 571 572 static const struct si_dte_data dte_data_curacao_pro = 573 { 574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 575 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 576 5, 577 45000, 578 100, 579 0xA, 580 1, 581 0, 582 0x10, 583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 586 90, 587 true 588 }; 589 590 static const struct si_dte_data dte_data_neptune_xt = 591 { 592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 593 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 594 5, 595 45000, 596 100, 597 0xA, 598 1, 599 0, 600 0x10, 601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 604 90, 605 true 606 }; 607 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 609 { 610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 670 { 0xFFFFFFFF } 671 }; 672 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 674 { 675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 735 { 0xFFFFFFFF } 736 }; 737 738 static const struct si_cac_config_reg cac_weights_heathrow[] = 739 { 740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 800 { 0xFFFFFFFF } 801 }; 802 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 804 { 805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 865 { 0xFFFFFFFF } 866 }; 867 868 static const struct si_cac_config_reg cac_weights_cape_verde[] = 869 { 870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 930 { 0xFFFFFFFF } 931 }; 932 933 static const struct si_cac_config_reg lcac_cape_verde[] = 934 { 935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0xFFFFFFFF } 990 }; 991 992 static const struct si_cac_config_reg cac_override_cape_verde[] = 993 { 994 { 0xFFFFFFFF } 995 }; 996 997 static const struct si_powertune_data powertune_data_cape_verde = 998 { 999 ((1 << 16) | 0x6993), 1000 5, 1001 0, 1002 7, 1003 105, 1004 { 1005 0UL, 1006 0UL, 1007 7194395UL, 1008 309631529UL, 1009 -1270850L, 1010 4513710L, 1011 100 1012 }, 1013 117830498UL, 1014 12, 1015 { 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0 1024 }, 1025 true 1026 }; 1027 1028 static const struct si_dte_data dte_data_cape_verde = 1029 { 1030 { 0, 0, 0, 0, 0 }, 1031 { 0, 0, 0, 0, 0 }, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 0, 1043 false 1044 }; 1045 1046 static const struct si_dte_data dte_data_venus_xtx = 1047 { 1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1050 5, 1051 55000, 1052 0x69, 1053 0xA, 1054 1, 1055 0, 1056 0x3, 1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 90, 1061 true 1062 }; 1063 1064 static const struct si_dte_data dte_data_venus_xt = 1065 { 1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1068 5, 1069 55000, 1070 0x69, 1071 0xA, 1072 1, 1073 0, 1074 0x3, 1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 90, 1079 true 1080 }; 1081 1082 static const struct si_dte_data dte_data_venus_pro = 1083 { 1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1086 5, 1087 55000, 1088 0x69, 1089 0xA, 1090 1, 1091 0, 1092 0x3, 1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 90, 1097 true 1098 }; 1099 1100 struct si_cac_config_reg cac_weights_oland[] = 1101 { 1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1162 { 0xFFFFFFFF } 1163 }; 1164 1165 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1166 { 1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1227 { 0xFFFFFFFF } 1228 }; 1229 1230 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1231 { 1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1292 { 0xFFFFFFFF } 1293 }; 1294 1295 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1296 { 1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1357 { 0xFFFFFFFF } 1358 }; 1359 1360 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1361 { 1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1422 { 0xFFFFFFFF } 1423 }; 1424 1425 static const struct si_cac_config_reg lcac_oland[] = 1426 { 1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0xFFFFFFFF } 1470 }; 1471 1472 static const struct si_cac_config_reg lcac_mars_pro[] = 1473 { 1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0xFFFFFFFF } 1517 }; 1518 1519 static const struct si_cac_config_reg cac_override_oland[] = 1520 { 1521 { 0xFFFFFFFF } 1522 }; 1523 1524 static const struct si_powertune_data powertune_data_oland = 1525 { 1526 ((1 << 16) | 0x6993), 1527 5, 1528 0, 1529 7, 1530 105, 1531 { 1532 0UL, 1533 0UL, 1534 7194395UL, 1535 309631529UL, 1536 -1270850L, 1537 4513710L, 1538 100 1539 }, 1540 117830498UL, 1541 12, 1542 { 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0 1551 }, 1552 true 1553 }; 1554 1555 static const struct si_powertune_data powertune_data_mars_pro = 1556 { 1557 ((1 << 16) | 0x6993), 1558 5, 1559 0, 1560 7, 1561 105, 1562 { 1563 0UL, 1564 0UL, 1565 7194395UL, 1566 309631529UL, 1567 -1270850L, 1568 4513710L, 1569 100 1570 }, 1571 117830498UL, 1572 12, 1573 { 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0 1582 }, 1583 true 1584 }; 1585 1586 static const struct si_dte_data dte_data_oland = 1587 { 1588 { 0, 0, 0, 0, 0 }, 1589 { 0, 0, 0, 0, 0 }, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 0, 1601 false 1602 }; 1603 1604 static const struct si_dte_data dte_data_mars_pro = 1605 { 1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1607 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1608 5, 1609 55000, 1610 105, 1611 0xA, 1612 1, 1613 0, 1614 0x10, 1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1618 90, 1619 true 1620 }; 1621 1622 static const struct si_dte_data dte_data_sun_xt = 1623 { 1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1625 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1626 5, 1627 55000, 1628 105, 1629 0xA, 1630 1, 1631 0, 1632 0x10, 1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1636 90, 1637 true 1638 }; 1639 1640 1641 static const struct si_cac_config_reg cac_weights_hainan[] = 1642 { 1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1703 { 0xFFFFFFFF } 1704 }; 1705 1706 static const struct si_powertune_data powertune_data_hainan = 1707 { 1708 ((1 << 16) | 0x6993), 1709 5, 1710 0, 1711 9, 1712 105, 1713 { 1714 0UL, 1715 0UL, 1716 7194395UL, 1717 309631529UL, 1718 -1270850L, 1719 4513710L, 1720 100 1721 }, 1722 117830498UL, 1723 12, 1724 { 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0 1733 }, 1734 true 1735 }; 1736 1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1741 1742 static int si_populate_voltage_value(struct radeon_device *rdev, 1743 const struct atom_voltage_table *table, 1744 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1745 static int si_get_std_voltage_value(struct radeon_device *rdev, 1746 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1747 u16 *std_voltage); 1748 static int si_write_smc_soft_register(struct radeon_device *rdev, 1749 u16 reg_offset, u32 value); 1750 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1751 struct rv7xx_pl *pl, 1752 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1753 static int si_calculate_sclk_params(struct radeon_device *rdev, 1754 u32 engine_clock, 1755 SISLANDS_SMC_SCLK_VALUE *sclk); 1756 1757 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1758 { 1759 struct si_power_info *pi = rdev->pm.dpm.priv; 1760 1761 return pi; 1762 } 1763 1764 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1765 u16 v, s32 t, u32 ileakage, u32 *leakage) 1766 { 1767 s64 kt, kv, leakage_w, i_leakage, vddc; 1768 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1769 s64 tmp; 1770 1771 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1772 vddc = div64_s64(drm_int2fixp(v), 1000); 1773 temperature = div64_s64(drm_int2fixp(t), 1000); 1774 1775 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1776 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1777 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1778 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1779 t_ref = drm_int2fixp(coeff->t_ref); 1780 1781 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1782 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1783 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1784 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1785 1786 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1787 1788 *leakage = drm_fixp2int(leakage_w * 1000); 1789 } 1790 1791 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1792 const struct ni_leakage_coeffients *coeff, 1793 u16 v, 1794 s32 t, 1795 u32 i_leakage, 1796 u32 *leakage) 1797 { 1798 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1799 } 1800 1801 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1802 const u32 fixed_kt, u16 v, 1803 u32 ileakage, u32 *leakage) 1804 { 1805 s64 kt, kv, leakage_w, i_leakage, vddc; 1806 1807 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1808 vddc = div64_s64(drm_int2fixp(v), 1000); 1809 1810 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1811 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1812 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1813 1814 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1815 1816 *leakage = drm_fixp2int(leakage_w * 1000); 1817 } 1818 1819 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1820 const struct ni_leakage_coeffients *coeff, 1821 const u32 fixed_kt, 1822 u16 v, 1823 u32 i_leakage, 1824 u32 *leakage) 1825 { 1826 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1827 } 1828 1829 1830 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1831 struct si_dte_data *dte_data) 1832 { 1833 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1834 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1835 u32 k = dte_data->k; 1836 u32 t_max = dte_data->max_t; 1837 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1838 u32 t_0 = dte_data->t0; 1839 u32 i; 1840 1841 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1842 dte_data->tdep_count = 3; 1843 1844 for (i = 0; i < k; i++) { 1845 dte_data->r[i] = 1846 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1847 (p_limit2 * (u32)100); 1848 } 1849 1850 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1851 1852 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1853 dte_data->tdep_r[i] = dte_data->r[4]; 1854 } 1855 } else { 1856 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1857 } 1858 } 1859 1860 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1861 { 1862 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1863 struct si_power_info *si_pi = si_get_pi(rdev); 1864 bool update_dte_from_pl2 = false; 1865 1866 if (rdev->family == CHIP_TAHITI) { 1867 si_pi->cac_weights = cac_weights_tahiti; 1868 si_pi->lcac_config = lcac_tahiti; 1869 si_pi->cac_override = cac_override_tahiti; 1870 si_pi->powertune_data = &powertune_data_tahiti; 1871 si_pi->dte_data = dte_data_tahiti; 1872 1873 switch (rdev->pdev->device) { 1874 case 0x6798: 1875 si_pi->dte_data.enable_dte_by_default = true; 1876 break; 1877 case 0x6799: 1878 si_pi->dte_data = dte_data_new_zealand; 1879 break; 1880 case 0x6790: 1881 case 0x6791: 1882 case 0x6792: 1883 case 0x679E: 1884 si_pi->dte_data = dte_data_aruba_pro; 1885 update_dte_from_pl2 = true; 1886 break; 1887 case 0x679B: 1888 si_pi->dte_data = dte_data_malta; 1889 update_dte_from_pl2 = true; 1890 break; 1891 case 0x679A: 1892 si_pi->dte_data = dte_data_tahiti_pro; 1893 update_dte_from_pl2 = true; 1894 break; 1895 default: 1896 if (si_pi->dte_data.enable_dte_by_default == true) 1897 DRM_ERROR("DTE is not enabled!\n"); 1898 break; 1899 } 1900 } else if (rdev->family == CHIP_PITCAIRN) { 1901 switch (rdev->pdev->device) { 1902 case 0x6810: 1903 case 0x6818: 1904 si_pi->cac_weights = cac_weights_pitcairn; 1905 si_pi->lcac_config = lcac_pitcairn; 1906 si_pi->cac_override = cac_override_pitcairn; 1907 si_pi->powertune_data = &powertune_data_pitcairn; 1908 si_pi->dte_data = dte_data_curacao_xt; 1909 update_dte_from_pl2 = true; 1910 break; 1911 case 0x6819: 1912 case 0x6811: 1913 si_pi->cac_weights = cac_weights_pitcairn; 1914 si_pi->lcac_config = lcac_pitcairn; 1915 si_pi->cac_override = cac_override_pitcairn; 1916 si_pi->powertune_data = &powertune_data_pitcairn; 1917 si_pi->dte_data = dte_data_curacao_pro; 1918 update_dte_from_pl2 = true; 1919 break; 1920 case 0x6800: 1921 case 0x6806: 1922 si_pi->cac_weights = cac_weights_pitcairn; 1923 si_pi->lcac_config = lcac_pitcairn; 1924 si_pi->cac_override = cac_override_pitcairn; 1925 si_pi->powertune_data = &powertune_data_pitcairn; 1926 si_pi->dte_data = dte_data_neptune_xt; 1927 update_dte_from_pl2 = true; 1928 break; 1929 default: 1930 si_pi->cac_weights = cac_weights_pitcairn; 1931 si_pi->lcac_config = lcac_pitcairn; 1932 si_pi->cac_override = cac_override_pitcairn; 1933 si_pi->powertune_data = &powertune_data_pitcairn; 1934 si_pi->dte_data = dte_data_pitcairn; 1935 break; 1936 } 1937 } else if (rdev->family == CHIP_VERDE) { 1938 si_pi->lcac_config = lcac_cape_verde; 1939 si_pi->cac_override = cac_override_cape_verde; 1940 si_pi->powertune_data = &powertune_data_cape_verde; 1941 1942 switch (rdev->pdev->device) { 1943 case 0x683B: 1944 case 0x683F: 1945 case 0x6829: 1946 case 0x6835: 1947 si_pi->cac_weights = cac_weights_cape_verde_pro; 1948 si_pi->dte_data = dte_data_cape_verde; 1949 break; 1950 case 0x682C: 1951 si_pi->cac_weights = cac_weights_cape_verde_pro; 1952 si_pi->dte_data = dte_data_sun_xt; 1953 break; 1954 case 0x6825: 1955 case 0x6827: 1956 si_pi->cac_weights = cac_weights_heathrow; 1957 si_pi->dte_data = dte_data_cape_verde; 1958 break; 1959 case 0x6824: 1960 case 0x682D: 1961 si_pi->cac_weights = cac_weights_chelsea_xt; 1962 si_pi->dte_data = dte_data_cape_verde; 1963 break; 1964 case 0x682F: 1965 si_pi->cac_weights = cac_weights_chelsea_pro; 1966 si_pi->dte_data = dte_data_cape_verde; 1967 break; 1968 case 0x6820: 1969 si_pi->cac_weights = cac_weights_heathrow; 1970 si_pi->dte_data = dte_data_venus_xtx; 1971 break; 1972 case 0x6821: 1973 si_pi->cac_weights = cac_weights_heathrow; 1974 si_pi->dte_data = dte_data_venus_xt; 1975 break; 1976 case 0x6823: 1977 case 0x682B: 1978 case 0x6822: 1979 case 0x682A: 1980 si_pi->cac_weights = cac_weights_chelsea_pro; 1981 si_pi->dte_data = dte_data_venus_pro; 1982 break; 1983 default: 1984 si_pi->cac_weights = cac_weights_cape_verde; 1985 si_pi->dte_data = dte_data_cape_verde; 1986 break; 1987 } 1988 } else if (rdev->family == CHIP_OLAND) { 1989 switch (rdev->pdev->device) { 1990 case 0x6601: 1991 case 0x6621: 1992 case 0x6603: 1993 case 0x6605: 1994 si_pi->cac_weights = cac_weights_mars_pro; 1995 si_pi->lcac_config = lcac_mars_pro; 1996 si_pi->cac_override = cac_override_oland; 1997 si_pi->powertune_data = &powertune_data_mars_pro; 1998 si_pi->dte_data = dte_data_mars_pro; 1999 update_dte_from_pl2 = true; 2000 break; 2001 case 0x6600: 2002 case 0x6606: 2003 case 0x6620: 2004 case 0x6604: 2005 si_pi->cac_weights = cac_weights_mars_xt; 2006 si_pi->lcac_config = lcac_mars_pro; 2007 si_pi->cac_override = cac_override_oland; 2008 si_pi->powertune_data = &powertune_data_mars_pro; 2009 si_pi->dte_data = dte_data_mars_pro; 2010 update_dte_from_pl2 = true; 2011 break; 2012 case 0x6611: 2013 case 0x6613: 2014 case 0x6608: 2015 si_pi->cac_weights = cac_weights_oland_pro; 2016 si_pi->lcac_config = lcac_mars_pro; 2017 si_pi->cac_override = cac_override_oland; 2018 si_pi->powertune_data = &powertune_data_mars_pro; 2019 si_pi->dte_data = dte_data_mars_pro; 2020 update_dte_from_pl2 = true; 2021 break; 2022 case 0x6610: 2023 si_pi->cac_weights = cac_weights_oland_xt; 2024 si_pi->lcac_config = lcac_mars_pro; 2025 si_pi->cac_override = cac_override_oland; 2026 si_pi->powertune_data = &powertune_data_mars_pro; 2027 si_pi->dte_data = dte_data_mars_pro; 2028 update_dte_from_pl2 = true; 2029 break; 2030 default: 2031 si_pi->cac_weights = cac_weights_oland; 2032 si_pi->lcac_config = lcac_oland; 2033 si_pi->cac_override = cac_override_oland; 2034 si_pi->powertune_data = &powertune_data_oland; 2035 si_pi->dte_data = dte_data_oland; 2036 break; 2037 } 2038 } else if (rdev->family == CHIP_HAINAN) { 2039 si_pi->cac_weights = cac_weights_hainan; 2040 si_pi->lcac_config = lcac_oland; 2041 si_pi->cac_override = cac_override_oland; 2042 si_pi->powertune_data = &powertune_data_hainan; 2043 si_pi->dte_data = dte_data_sun_xt; 2044 update_dte_from_pl2 = true; 2045 } else { 2046 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2047 return; 2048 } 2049 2050 ni_pi->enable_power_containment = false; 2051 ni_pi->enable_cac = false; 2052 ni_pi->enable_sq_ramping = false; 2053 si_pi->enable_dte = false; 2054 2055 if (si_pi->powertune_data->enable_powertune_by_default) { 2056 ni_pi->enable_power_containment= true; 2057 ni_pi->enable_cac = true; 2058 if (si_pi->dte_data.enable_dte_by_default) { 2059 si_pi->enable_dte = true; 2060 if (update_dte_from_pl2) 2061 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2062 2063 } 2064 ni_pi->enable_sq_ramping = true; 2065 } 2066 2067 ni_pi->driver_calculate_cac_leakage = true; 2068 ni_pi->cac_configuration_required = true; 2069 2070 if (ni_pi->cac_configuration_required) { 2071 ni_pi->support_cac_long_term_average = true; 2072 si_pi->dyn_powertune_data.l2_lta_window_size = 2073 si_pi->powertune_data->l2_lta_window_size_default; 2074 si_pi->dyn_powertune_data.lts_truncate = 2075 si_pi->powertune_data->lts_truncate_default; 2076 } else { 2077 ni_pi->support_cac_long_term_average = false; 2078 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2079 si_pi->dyn_powertune_data.lts_truncate = 0; 2080 } 2081 2082 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2083 } 2084 2085 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2086 { 2087 return 1; 2088 } 2089 2090 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2091 { 2092 u32 xclk; 2093 u32 wintime; 2094 u32 cac_window; 2095 u32 cac_window_size; 2096 2097 xclk = radeon_get_xclk(rdev); 2098 2099 if (xclk == 0) 2100 return 0; 2101 2102 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2103 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2104 2105 wintime = (cac_window_size * 100) / xclk; 2106 2107 return wintime; 2108 } 2109 2110 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2111 { 2112 return power_in_watts; 2113 } 2114 2115 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2116 bool adjust_polarity, 2117 u32 tdp_adjustment, 2118 u32 *tdp_limit, 2119 u32 *near_tdp_limit) 2120 { 2121 u32 adjustment_delta, max_tdp_limit; 2122 2123 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2124 return -EINVAL; 2125 2126 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2127 2128 if (adjust_polarity) { 2129 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2130 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2131 } else { 2132 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2133 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2134 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2135 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2136 else 2137 *near_tdp_limit = 0; 2138 } 2139 2140 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2141 return -EINVAL; 2142 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2143 return -EINVAL; 2144 2145 return 0; 2146 } 2147 2148 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2149 struct radeon_ps *radeon_state) 2150 { 2151 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2152 struct si_power_info *si_pi = si_get_pi(rdev); 2153 2154 if (ni_pi->enable_power_containment) { 2155 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2156 PP_SIslands_PAPMParameters *papm_parm; 2157 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2158 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2159 u32 tdp_limit; 2160 u32 near_tdp_limit; 2161 int ret; 2162 2163 if (scaling_factor == 0) 2164 return -EINVAL; 2165 2166 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2167 2168 ret = si_calculate_adjusted_tdp_limits(rdev, 2169 false, /* ??? */ 2170 rdev->pm.dpm.tdp_adjustment, 2171 &tdp_limit, 2172 &near_tdp_limit); 2173 if (ret) 2174 return ret; 2175 2176 smc_table->dpm2Params.TDPLimit = 2177 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2178 smc_table->dpm2Params.NearTDPLimit = 2179 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2180 smc_table->dpm2Params.SafePowerLimit = 2181 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2182 2183 ret = si_copy_bytes_to_smc(rdev, 2184 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2185 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2186 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2187 sizeof(u32) * 3, 2188 si_pi->sram_end); 2189 if (ret) 2190 return ret; 2191 2192 if (si_pi->enable_ppm) { 2193 papm_parm = &si_pi->papm_parm; 2194 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2195 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2196 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2197 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2198 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2199 papm_parm->PlatformPowerLimit = 0xffffffff; 2200 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2201 2202 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2203 (u8 *)papm_parm, 2204 sizeof(PP_SIslands_PAPMParameters), 2205 si_pi->sram_end); 2206 if (ret) 2207 return ret; 2208 } 2209 } 2210 return 0; 2211 } 2212 2213 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2214 struct radeon_ps *radeon_state) 2215 { 2216 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2217 struct si_power_info *si_pi = si_get_pi(rdev); 2218 2219 if (ni_pi->enable_power_containment) { 2220 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2221 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2222 int ret; 2223 2224 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2225 2226 smc_table->dpm2Params.NearTDPLimit = 2227 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2228 smc_table->dpm2Params.SafePowerLimit = 2229 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2230 2231 ret = si_copy_bytes_to_smc(rdev, 2232 (si_pi->state_table_start + 2233 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2234 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2235 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2236 sizeof(u32) * 2, 2237 si_pi->sram_end); 2238 if (ret) 2239 return ret; 2240 } 2241 2242 return 0; 2243 } 2244 2245 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2246 const u16 prev_std_vddc, 2247 const u16 curr_std_vddc) 2248 { 2249 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2250 u64 prev_vddc = (u64)prev_std_vddc; 2251 u64 curr_vddc = (u64)curr_std_vddc; 2252 u64 pwr_efficiency_ratio, n, d; 2253 2254 if ((prev_vddc == 0) || (curr_vddc == 0)) 2255 return 0; 2256 2257 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2258 d = prev_vddc * prev_vddc; 2259 pwr_efficiency_ratio = div64_u64(n, d); 2260 2261 if (pwr_efficiency_ratio > (u64)0xFFFF) 2262 return 0; 2263 2264 return (u16)pwr_efficiency_ratio; 2265 } 2266 2267 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2268 struct radeon_ps *radeon_state) 2269 { 2270 struct si_power_info *si_pi = si_get_pi(rdev); 2271 2272 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2273 radeon_state->vclk && radeon_state->dclk) 2274 return true; 2275 2276 return false; 2277 } 2278 2279 static int si_populate_power_containment_values(struct radeon_device *rdev, 2280 struct radeon_ps *radeon_state, 2281 SISLANDS_SMC_SWSTATE *smc_state) 2282 { 2283 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2284 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2285 struct ni_ps *state = ni_get_ps(radeon_state); 2286 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2287 u32 prev_sclk; 2288 u32 max_sclk; 2289 u32 min_sclk; 2290 u16 prev_std_vddc; 2291 u16 curr_std_vddc; 2292 int i; 2293 u16 pwr_efficiency_ratio; 2294 u8 max_ps_percent; 2295 bool disable_uvd_power_tune; 2296 int ret; 2297 2298 if (ni_pi->enable_power_containment == false) 2299 return 0; 2300 2301 if (state->performance_level_count == 0) 2302 return -EINVAL; 2303 2304 if (smc_state->levelCount != state->performance_level_count) 2305 return -EINVAL; 2306 2307 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2308 2309 smc_state->levels[0].dpm2.MaxPS = 0; 2310 smc_state->levels[0].dpm2.NearTDPDec = 0; 2311 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2312 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2313 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2314 2315 for (i = 1; i < state->performance_level_count; i++) { 2316 prev_sclk = state->performance_levels[i-1].sclk; 2317 max_sclk = state->performance_levels[i].sclk; 2318 if (i == 1) 2319 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2320 else 2321 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2322 2323 if (prev_sclk > max_sclk) 2324 return -EINVAL; 2325 2326 if ((max_ps_percent == 0) || 2327 (prev_sclk == max_sclk) || 2328 disable_uvd_power_tune) { 2329 min_sclk = max_sclk; 2330 } else if (i == 1) { 2331 min_sclk = prev_sclk; 2332 } else { 2333 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2334 } 2335 2336 if (min_sclk < state->performance_levels[0].sclk) 2337 min_sclk = state->performance_levels[0].sclk; 2338 2339 if (min_sclk == 0) 2340 return -EINVAL; 2341 2342 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2343 state->performance_levels[i-1].vddc, &vddc); 2344 if (ret) 2345 return ret; 2346 2347 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2348 if (ret) 2349 return ret; 2350 2351 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2352 state->performance_levels[i].vddc, &vddc); 2353 if (ret) 2354 return ret; 2355 2356 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2357 if (ret) 2358 return ret; 2359 2360 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2361 prev_std_vddc, curr_std_vddc); 2362 2363 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2364 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2365 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2366 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2367 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2368 } 2369 2370 return 0; 2371 } 2372 2373 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2374 struct radeon_ps *radeon_state, 2375 SISLANDS_SMC_SWSTATE *smc_state) 2376 { 2377 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2378 struct ni_ps *state = ni_get_ps(radeon_state); 2379 u32 sq_power_throttle, sq_power_throttle2; 2380 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2381 int i; 2382 2383 if (state->performance_level_count == 0) 2384 return -EINVAL; 2385 2386 if (smc_state->levelCount != state->performance_level_count) 2387 return -EINVAL; 2388 2389 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2390 return -EINVAL; 2391 2392 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2393 enable_sq_ramping = false; 2394 2395 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2396 enable_sq_ramping = false; 2397 2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2399 enable_sq_ramping = false; 2400 2401 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2402 enable_sq_ramping = false; 2403 2404 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2405 enable_sq_ramping = false; 2406 2407 for (i = 0; i < state->performance_level_count; i++) { 2408 sq_power_throttle = 0; 2409 sq_power_throttle2 = 0; 2410 2411 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2412 enable_sq_ramping) { 2413 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2414 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2415 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2416 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2417 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2418 } else { 2419 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2420 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2421 } 2422 2423 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2424 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2425 } 2426 2427 return 0; 2428 } 2429 2430 static int si_enable_power_containment(struct radeon_device *rdev, 2431 struct radeon_ps *radeon_new_state, 2432 bool enable) 2433 { 2434 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2435 PPSMC_Result smc_result; 2436 int ret = 0; 2437 2438 if (ni_pi->enable_power_containment) { 2439 if (enable) { 2440 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2441 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2442 if (smc_result != PPSMC_Result_OK) { 2443 ret = -EINVAL; 2444 ni_pi->pc_enabled = false; 2445 } else { 2446 ni_pi->pc_enabled = true; 2447 } 2448 } 2449 } else { 2450 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2451 if (smc_result != PPSMC_Result_OK) 2452 ret = -EINVAL; 2453 ni_pi->pc_enabled = false; 2454 } 2455 } 2456 2457 return ret; 2458 } 2459 2460 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2461 { 2462 struct si_power_info *si_pi = si_get_pi(rdev); 2463 int ret = 0; 2464 struct si_dte_data *dte_data = &si_pi->dte_data; 2465 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2466 u32 table_size; 2467 u8 tdep_count; 2468 u32 i; 2469 2470 if (dte_data == NULL) 2471 si_pi->enable_dte = false; 2472 2473 if (si_pi->enable_dte == false) 2474 return 0; 2475 2476 if (dte_data->k <= 0) 2477 return -EINVAL; 2478 2479 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2480 if (dte_tables == NULL) { 2481 si_pi->enable_dte = false; 2482 return -ENOMEM; 2483 } 2484 2485 table_size = dte_data->k; 2486 2487 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2488 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2489 2490 tdep_count = dte_data->tdep_count; 2491 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2492 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2493 2494 dte_tables->K = cpu_to_be32(table_size); 2495 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2496 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2497 dte_tables->WindowSize = dte_data->window_size; 2498 dte_tables->temp_select = dte_data->temp_select; 2499 dte_tables->DTE_mode = dte_data->dte_mode; 2500 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2501 2502 if (tdep_count > 0) 2503 table_size--; 2504 2505 for (i = 0; i < table_size; i++) { 2506 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2507 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2508 } 2509 2510 dte_tables->Tdep_count = tdep_count; 2511 2512 for (i = 0; i < (u32)tdep_count; i++) { 2513 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2514 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2515 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2516 } 2517 2518 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2519 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2520 kfree(dte_tables); 2521 2522 return ret; 2523 } 2524 2525 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2526 u16 *max, u16 *min) 2527 { 2528 struct si_power_info *si_pi = si_get_pi(rdev); 2529 struct radeon_cac_leakage_table *table = 2530 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2531 u32 i; 2532 u32 v0_loadline; 2533 2534 2535 if (table == NULL) 2536 return -EINVAL; 2537 2538 *max = 0; 2539 *min = 0xFFFF; 2540 2541 for (i = 0; i < table->count; i++) { 2542 if (table->entries[i].vddc > *max) 2543 *max = table->entries[i].vddc; 2544 if (table->entries[i].vddc < *min) 2545 *min = table->entries[i].vddc; 2546 } 2547 2548 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2549 return -EINVAL; 2550 2551 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2552 2553 if (v0_loadline > 0xFFFFUL) 2554 return -EINVAL; 2555 2556 *min = (u16)v0_loadline; 2557 2558 if ((*min > *max) || (*max == 0) || (*min == 0)) 2559 return -EINVAL; 2560 2561 return 0; 2562 } 2563 2564 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2565 { 2566 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2567 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2568 } 2569 2570 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2571 PP_SIslands_CacConfig *cac_tables, 2572 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2573 u16 t0, u16 t_step) 2574 { 2575 struct si_power_info *si_pi = si_get_pi(rdev); 2576 u32 leakage; 2577 unsigned int i, j; 2578 s32 t; 2579 u32 smc_leakage; 2580 u32 scaling_factor; 2581 u16 voltage; 2582 2583 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2584 2585 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2586 t = (1000 * (i * t_step + t0)); 2587 2588 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2589 voltage = vddc_max - (vddc_step * j); 2590 2591 si_calculate_leakage_for_v_and_t(rdev, 2592 &si_pi->powertune_data->leakage_coefficients, 2593 voltage, 2594 t, 2595 si_pi->dyn_powertune_data.cac_leakage, 2596 &leakage); 2597 2598 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2599 2600 if (smc_leakage > 0xFFFF) 2601 smc_leakage = 0xFFFF; 2602 2603 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2604 cpu_to_be16((u16)smc_leakage); 2605 } 2606 } 2607 return 0; 2608 } 2609 2610 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2611 PP_SIslands_CacConfig *cac_tables, 2612 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2613 { 2614 struct si_power_info *si_pi = si_get_pi(rdev); 2615 u32 leakage; 2616 unsigned int i, j; 2617 u32 smc_leakage; 2618 u32 scaling_factor; 2619 u16 voltage; 2620 2621 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2622 2623 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2624 voltage = vddc_max - (vddc_step * j); 2625 2626 si_calculate_leakage_for_v(rdev, 2627 &si_pi->powertune_data->leakage_coefficients, 2628 si_pi->powertune_data->fixed_kt, 2629 voltage, 2630 si_pi->dyn_powertune_data.cac_leakage, 2631 &leakage); 2632 2633 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2634 2635 if (smc_leakage > 0xFFFF) 2636 smc_leakage = 0xFFFF; 2637 2638 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2639 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2640 cpu_to_be16((u16)smc_leakage); 2641 } 2642 return 0; 2643 } 2644 2645 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2646 { 2647 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2648 struct si_power_info *si_pi = si_get_pi(rdev); 2649 PP_SIslands_CacConfig *cac_tables = NULL; 2650 u16 vddc_max, vddc_min, vddc_step; 2651 u16 t0, t_step; 2652 u32 load_line_slope, reg; 2653 int ret = 0; 2654 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2655 2656 if (ni_pi->enable_cac == false) 2657 return 0; 2658 2659 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2660 if (!cac_tables) 2661 return -ENOMEM; 2662 2663 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2664 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2665 WREG32(CG_CAC_CTRL, reg); 2666 2667 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2668 si_pi->dyn_powertune_data.dc_pwr_value = 2669 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2670 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2671 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2672 2673 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2674 2675 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2676 if (ret) 2677 goto done_free; 2678 2679 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2680 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2681 t_step = 4; 2682 t0 = 60; 2683 2684 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2685 ret = si_init_dte_leakage_table(rdev, cac_tables, 2686 vddc_max, vddc_min, vddc_step, 2687 t0, t_step); 2688 else 2689 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2690 vddc_max, vddc_min, vddc_step); 2691 if (ret) 2692 goto done_free; 2693 2694 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2695 2696 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2697 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2698 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2699 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2700 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2701 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2702 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2703 cac_tables->calculation_repeats = cpu_to_be32(2); 2704 cac_tables->dc_cac = cpu_to_be32(0); 2705 cac_tables->log2_PG_LKG_SCALE = 12; 2706 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2707 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2708 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2709 2710 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2711 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2712 2713 if (ret) 2714 goto done_free; 2715 2716 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2717 2718 done_free: 2719 if (ret) { 2720 ni_pi->enable_cac = false; 2721 ni_pi->enable_power_containment = false; 2722 } 2723 2724 kfree(cac_tables); 2725 2726 return 0; 2727 } 2728 2729 static int si_program_cac_config_registers(struct radeon_device *rdev, 2730 const struct si_cac_config_reg *cac_config_regs) 2731 { 2732 const struct si_cac_config_reg *config_regs = cac_config_regs; 2733 u32 data = 0, offset; 2734 2735 if (!config_regs) 2736 return -EINVAL; 2737 2738 while (config_regs->offset != 0xFFFFFFFF) { 2739 switch (config_regs->type) { 2740 case SISLANDS_CACCONFIG_CGIND: 2741 offset = SMC_CG_IND_START + config_regs->offset; 2742 if (offset < SMC_CG_IND_END) 2743 data = RREG32_SMC(offset); 2744 break; 2745 default: 2746 data = RREG32(config_regs->offset << 2); 2747 break; 2748 } 2749 2750 data &= ~config_regs->mask; 2751 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2752 2753 switch (config_regs->type) { 2754 case SISLANDS_CACCONFIG_CGIND: 2755 offset = SMC_CG_IND_START + config_regs->offset; 2756 if (offset < SMC_CG_IND_END) 2757 WREG32_SMC(offset, data); 2758 break; 2759 default: 2760 WREG32(config_regs->offset << 2, data); 2761 break; 2762 } 2763 config_regs++; 2764 } 2765 return 0; 2766 } 2767 2768 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2769 { 2770 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2771 struct si_power_info *si_pi = si_get_pi(rdev); 2772 int ret; 2773 2774 if ((ni_pi->enable_cac == false) || 2775 (ni_pi->cac_configuration_required == false)) 2776 return 0; 2777 2778 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2779 if (ret) 2780 return ret; 2781 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2782 if (ret) 2783 return ret; 2784 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2785 if (ret) 2786 return ret; 2787 2788 return 0; 2789 } 2790 2791 static int si_enable_smc_cac(struct radeon_device *rdev, 2792 struct radeon_ps *radeon_new_state, 2793 bool enable) 2794 { 2795 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2796 struct si_power_info *si_pi = si_get_pi(rdev); 2797 PPSMC_Result smc_result; 2798 int ret = 0; 2799 2800 if (ni_pi->enable_cac) { 2801 if (enable) { 2802 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2803 if (ni_pi->support_cac_long_term_average) { 2804 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2805 if (smc_result != PPSMC_Result_OK) 2806 ni_pi->support_cac_long_term_average = false; 2807 } 2808 2809 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2810 if (smc_result != PPSMC_Result_OK) { 2811 ret = -EINVAL; 2812 ni_pi->cac_enabled = false; 2813 } else { 2814 ni_pi->cac_enabled = true; 2815 } 2816 2817 if (si_pi->enable_dte) { 2818 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2819 if (smc_result != PPSMC_Result_OK) 2820 ret = -EINVAL; 2821 } 2822 } 2823 } else if (ni_pi->cac_enabled) { 2824 if (si_pi->enable_dte) 2825 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2826 2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2828 2829 ni_pi->cac_enabled = false; 2830 2831 if (ni_pi->support_cac_long_term_average) 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2833 } 2834 } 2835 return ret; 2836 } 2837 2838 static int si_init_smc_spll_table(struct radeon_device *rdev) 2839 { 2840 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2841 struct si_power_info *si_pi = si_get_pi(rdev); 2842 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2843 SISLANDS_SMC_SCLK_VALUE sclk_params; 2844 u32 fb_div, p_div; 2845 u32 clk_s, clk_v; 2846 u32 sclk = 0; 2847 int ret = 0; 2848 u32 tmp; 2849 int i; 2850 2851 if (si_pi->spll_table_start == 0) 2852 return -EINVAL; 2853 2854 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2855 if (spll_table == NULL) 2856 return -ENOMEM; 2857 2858 for (i = 0; i < 256; i++) { 2859 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2860 if (ret) 2861 break; 2862 2863 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2864 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2865 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2866 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2867 2868 fb_div &= ~0x00001FFF; 2869 fb_div >>= 1; 2870 clk_v >>= 6; 2871 2872 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2873 ret = -EINVAL; 2874 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2875 ret = -EINVAL; 2876 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2877 ret = -EINVAL; 2878 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2879 ret = -EINVAL; 2880 2881 if (ret) 2882 break; 2883 2884 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2885 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2886 spll_table->freq[i] = cpu_to_be32(tmp); 2887 2888 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2889 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2890 spll_table->ss[i] = cpu_to_be32(tmp); 2891 2892 sclk += 512; 2893 } 2894 2895 2896 if (!ret) 2897 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2898 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2899 si_pi->sram_end); 2900 2901 if (ret) 2902 ni_pi->enable_power_containment = false; 2903 2904 kfree(spll_table); 2905 2906 return ret; 2907 } 2908 2909 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2910 struct radeon_ps *rps) 2911 { 2912 struct ni_ps *ps = ni_get_ps(rps); 2913 struct radeon_clock_and_voltage_limits *max_limits; 2914 bool disable_mclk_switching = false; 2915 bool disable_sclk_switching = false; 2916 u32 mclk, sclk; 2917 u16 vddc, vddci; 2918 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2919 int i; 2920 2921 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2922 ni_dpm_vblank_too_short(rdev)) 2923 disable_mclk_switching = true; 2924 2925 if (rps->vclk || rps->dclk) { 2926 disable_mclk_switching = true; 2927 disable_sclk_switching = true; 2928 } 2929 2930 if (rdev->pm.dpm.ac_power) 2931 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2932 else 2933 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2934 2935 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2936 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2937 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2938 } 2939 if (rdev->pm.dpm.ac_power == false) { 2940 for (i = 0; i < ps->performance_level_count; i++) { 2941 if (ps->performance_levels[i].mclk > max_limits->mclk) 2942 ps->performance_levels[i].mclk = max_limits->mclk; 2943 if (ps->performance_levels[i].sclk > max_limits->sclk) 2944 ps->performance_levels[i].sclk = max_limits->sclk; 2945 if (ps->performance_levels[i].vddc > max_limits->vddc) 2946 ps->performance_levels[i].vddc = max_limits->vddc; 2947 if (ps->performance_levels[i].vddci > max_limits->vddci) 2948 ps->performance_levels[i].vddci = max_limits->vddci; 2949 } 2950 } 2951 2952 /* limit clocks to max supported clocks based on voltage dependency tables */ 2953 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2954 &max_sclk_vddc); 2955 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2956 &max_mclk_vddci); 2957 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2958 &max_mclk_vddc); 2959 2960 for (i = 0; i < ps->performance_level_count; i++) { 2961 if (max_sclk_vddc) { 2962 if (ps->performance_levels[i].sclk > max_sclk_vddc) 2963 ps->performance_levels[i].sclk = max_sclk_vddc; 2964 } 2965 if (max_mclk_vddci) { 2966 if (ps->performance_levels[i].mclk > max_mclk_vddci) 2967 ps->performance_levels[i].mclk = max_mclk_vddci; 2968 } 2969 if (max_mclk_vddc) { 2970 if (ps->performance_levels[i].mclk > max_mclk_vddc) 2971 ps->performance_levels[i].mclk = max_mclk_vddc; 2972 } 2973 } 2974 2975 /* XXX validate the min clocks required for display */ 2976 2977 if (disable_mclk_switching) { 2978 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2979 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2980 } else { 2981 mclk = ps->performance_levels[0].mclk; 2982 vddci = ps->performance_levels[0].vddci; 2983 } 2984 2985 if (disable_sclk_switching) { 2986 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2987 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2988 } else { 2989 sclk = ps->performance_levels[0].sclk; 2990 vddc = ps->performance_levels[0].vddc; 2991 } 2992 2993 /* adjusted low state */ 2994 ps->performance_levels[0].sclk = sclk; 2995 ps->performance_levels[0].mclk = mclk; 2996 ps->performance_levels[0].vddc = vddc; 2997 ps->performance_levels[0].vddci = vddci; 2998 2999 if (disable_sclk_switching) { 3000 sclk = ps->performance_levels[0].sclk; 3001 for (i = 1; i < ps->performance_level_count; i++) { 3002 if (sclk < ps->performance_levels[i].sclk) 3003 sclk = ps->performance_levels[i].sclk; 3004 } 3005 for (i = 0; i < ps->performance_level_count; i++) { 3006 ps->performance_levels[i].sclk = sclk; 3007 ps->performance_levels[i].vddc = vddc; 3008 } 3009 } else { 3010 for (i = 1; i < ps->performance_level_count; i++) { 3011 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3012 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3013 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3014 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3015 } 3016 } 3017 3018 if (disable_mclk_switching) { 3019 mclk = ps->performance_levels[0].mclk; 3020 for (i = 1; i < ps->performance_level_count; i++) { 3021 if (mclk < ps->performance_levels[i].mclk) 3022 mclk = ps->performance_levels[i].mclk; 3023 } 3024 for (i = 0; i < ps->performance_level_count; i++) { 3025 ps->performance_levels[i].mclk = mclk; 3026 ps->performance_levels[i].vddci = vddci; 3027 } 3028 } else { 3029 for (i = 1; i < ps->performance_level_count; i++) { 3030 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3031 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3032 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3033 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3034 } 3035 } 3036 3037 for (i = 0; i < ps->performance_level_count; i++) 3038 btc_adjust_clock_combinations(rdev, max_limits, 3039 &ps->performance_levels[i]); 3040 3041 for (i = 0; i < ps->performance_level_count; i++) { 3042 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3043 ps->performance_levels[i].sclk, 3044 max_limits->vddc, &ps->performance_levels[i].vddc); 3045 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3046 ps->performance_levels[i].mclk, 3047 max_limits->vddci, &ps->performance_levels[i].vddci); 3048 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3049 ps->performance_levels[i].mclk, 3050 max_limits->vddc, &ps->performance_levels[i].vddc); 3051 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3052 rdev->clock.current_dispclk, 3053 max_limits->vddc, &ps->performance_levels[i].vddc); 3054 } 3055 3056 for (i = 0; i < ps->performance_level_count; i++) { 3057 btc_apply_voltage_delta_rules(rdev, 3058 max_limits->vddc, max_limits->vddci, 3059 &ps->performance_levels[i].vddc, 3060 &ps->performance_levels[i].vddci); 3061 } 3062 3063 ps->dc_compatible = true; 3064 for (i = 0; i < ps->performance_level_count; i++) { 3065 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3066 ps->dc_compatible = false; 3067 } 3068 3069 } 3070 3071 #if 0 3072 static int si_read_smc_soft_register(struct radeon_device *rdev, 3073 u16 reg_offset, u32 *value) 3074 { 3075 struct si_power_info *si_pi = si_get_pi(rdev); 3076 3077 return si_read_smc_sram_dword(rdev, 3078 si_pi->soft_regs_start + reg_offset, value, 3079 si_pi->sram_end); 3080 } 3081 #endif 3082 3083 static int si_write_smc_soft_register(struct radeon_device *rdev, 3084 u16 reg_offset, u32 value) 3085 { 3086 struct si_power_info *si_pi = si_get_pi(rdev); 3087 3088 return si_write_smc_sram_dword(rdev, 3089 si_pi->soft_regs_start + reg_offset, 3090 value, si_pi->sram_end); 3091 } 3092 3093 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3094 { 3095 bool ret = false; 3096 u32 tmp, width, row, column, bank, density; 3097 bool is_memory_gddr5, is_special; 3098 3099 tmp = RREG32(MC_SEQ_MISC0); 3100 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3101 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3102 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3103 3104 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3105 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3106 3107 tmp = RREG32(MC_ARB_RAMCFG); 3108 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3109 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3110 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3111 3112 density = (1 << (row + column - 20 + bank)) * width; 3113 3114 if ((rdev->pdev->device == 0x6819) && 3115 is_memory_gddr5 && is_special && (density == 0x400)) 3116 ret = true; 3117 3118 return ret; 3119 } 3120 3121 static void si_get_leakage_vddc(struct radeon_device *rdev) 3122 { 3123 struct si_power_info *si_pi = si_get_pi(rdev); 3124 u16 vddc, count = 0; 3125 int i, ret; 3126 3127 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3128 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3129 3130 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3131 si_pi->leakage_voltage.entries[count].voltage = vddc; 3132 si_pi->leakage_voltage.entries[count].leakage_index = 3133 SISLANDS_LEAKAGE_INDEX0 + i; 3134 count++; 3135 } 3136 } 3137 si_pi->leakage_voltage.count = count; 3138 } 3139 3140 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3141 u32 index, u16 *leakage_voltage) 3142 { 3143 struct si_power_info *si_pi = si_get_pi(rdev); 3144 int i; 3145 3146 if (leakage_voltage == NULL) 3147 return -EINVAL; 3148 3149 if ((index & 0xff00) != 0xff00) 3150 return -EINVAL; 3151 3152 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3153 return -EINVAL; 3154 3155 if (index < SISLANDS_LEAKAGE_INDEX0) 3156 return -EINVAL; 3157 3158 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3159 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3160 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3161 return 0; 3162 } 3163 } 3164 return -EAGAIN; 3165 } 3166 3167 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3168 { 3169 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3170 bool want_thermal_protection; 3171 enum radeon_dpm_event_src dpm_event_src; 3172 3173 switch (sources) { 3174 case 0: 3175 default: 3176 want_thermal_protection = false; 3177 break; 3178 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3179 want_thermal_protection = true; 3180 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3181 break; 3182 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3183 want_thermal_protection = true; 3184 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3185 break; 3186 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3187 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3188 want_thermal_protection = true; 3189 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3190 break; 3191 } 3192 3193 if (want_thermal_protection) { 3194 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3195 if (pi->thermal_protection) 3196 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3197 } else { 3198 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3199 } 3200 } 3201 3202 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3203 enum radeon_dpm_auto_throttle_src source, 3204 bool enable) 3205 { 3206 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3207 3208 if (enable) { 3209 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3210 pi->active_auto_throttle_sources |= 1 << source; 3211 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3212 } 3213 } else { 3214 if (pi->active_auto_throttle_sources & (1 << source)) { 3215 pi->active_auto_throttle_sources &= ~(1 << source); 3216 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3217 } 3218 } 3219 } 3220 3221 static void si_start_dpm(struct radeon_device *rdev) 3222 { 3223 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3224 } 3225 3226 static void si_stop_dpm(struct radeon_device *rdev) 3227 { 3228 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3229 } 3230 3231 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3232 { 3233 if (enable) 3234 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3235 else 3236 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3237 3238 } 3239 3240 #if 0 3241 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3242 u32 thermal_level) 3243 { 3244 PPSMC_Result ret; 3245 3246 if (thermal_level == 0) { 3247 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3248 if (ret == PPSMC_Result_OK) 3249 return 0; 3250 else 3251 return -EINVAL; 3252 } 3253 return 0; 3254 } 3255 3256 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3257 { 3258 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3259 } 3260 #endif 3261 3262 #if 0 3263 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3264 { 3265 if (ac_power) 3266 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3267 0 : -EINVAL; 3268 3269 return 0; 3270 } 3271 #endif 3272 3273 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3274 PPSMC_Msg msg, u32 parameter) 3275 { 3276 WREG32(SMC_SCRATCH0, parameter); 3277 return si_send_msg_to_smc(rdev, msg); 3278 } 3279 3280 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3281 { 3282 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3283 return -EINVAL; 3284 3285 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3286 0 : -EINVAL; 3287 } 3288 3289 int si_dpm_force_performance_level(struct radeon_device *rdev, 3290 enum radeon_dpm_forced_level level) 3291 { 3292 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3293 struct ni_ps *ps = ni_get_ps(rps); 3294 u32 levels = ps->performance_level_count; 3295 3296 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3297 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3298 return -EINVAL; 3299 3300 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3301 return -EINVAL; 3302 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3303 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3304 return -EINVAL; 3305 3306 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3307 return -EINVAL; 3308 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3309 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3310 return -EINVAL; 3311 3312 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3313 return -EINVAL; 3314 } 3315 3316 rdev->pm.dpm.forced_level = level; 3317 3318 return 0; 3319 } 3320 3321 #if 0 3322 static int si_set_boot_state(struct radeon_device *rdev) 3323 { 3324 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3325 0 : -EINVAL; 3326 } 3327 #endif 3328 3329 static int si_set_sw_state(struct radeon_device *rdev) 3330 { 3331 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3332 0 : -EINVAL; 3333 } 3334 3335 static int si_halt_smc(struct radeon_device *rdev) 3336 { 3337 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3338 return -EINVAL; 3339 3340 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3341 0 : -EINVAL; 3342 } 3343 3344 static int si_resume_smc(struct radeon_device *rdev) 3345 { 3346 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3347 return -EINVAL; 3348 3349 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3350 0 : -EINVAL; 3351 } 3352 3353 static void si_dpm_start_smc(struct radeon_device *rdev) 3354 { 3355 si_program_jump_on_start(rdev); 3356 si_start_smc(rdev); 3357 si_start_smc_clock(rdev); 3358 } 3359 3360 static void si_dpm_stop_smc(struct radeon_device *rdev) 3361 { 3362 si_reset_smc(rdev); 3363 si_stop_smc_clock(rdev); 3364 } 3365 3366 static int si_process_firmware_header(struct radeon_device *rdev) 3367 { 3368 struct si_power_info *si_pi = si_get_pi(rdev); 3369 u32 tmp; 3370 int ret; 3371 3372 ret = si_read_smc_sram_dword(rdev, 3373 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3374 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3375 &tmp, si_pi->sram_end); 3376 if (ret) 3377 return ret; 3378 3379 si_pi->state_table_start = tmp; 3380 3381 ret = si_read_smc_sram_dword(rdev, 3382 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3383 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3384 &tmp, si_pi->sram_end); 3385 if (ret) 3386 return ret; 3387 3388 si_pi->soft_regs_start = tmp; 3389 3390 ret = si_read_smc_sram_dword(rdev, 3391 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3392 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3393 &tmp, si_pi->sram_end); 3394 if (ret) 3395 return ret; 3396 3397 si_pi->mc_reg_table_start = tmp; 3398 3399 ret = si_read_smc_sram_dword(rdev, 3400 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3401 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3402 &tmp, si_pi->sram_end); 3403 if (ret) 3404 return ret; 3405 3406 si_pi->arb_table_start = tmp; 3407 3408 ret = si_read_smc_sram_dword(rdev, 3409 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3410 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3411 &tmp, si_pi->sram_end); 3412 if (ret) 3413 return ret; 3414 3415 si_pi->cac_table_start = tmp; 3416 3417 ret = si_read_smc_sram_dword(rdev, 3418 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3419 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3420 &tmp, si_pi->sram_end); 3421 if (ret) 3422 return ret; 3423 3424 si_pi->dte_table_start = tmp; 3425 3426 ret = si_read_smc_sram_dword(rdev, 3427 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3428 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3429 &tmp, si_pi->sram_end); 3430 if (ret) 3431 return ret; 3432 3433 si_pi->spll_table_start = tmp; 3434 3435 ret = si_read_smc_sram_dword(rdev, 3436 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3437 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3438 &tmp, si_pi->sram_end); 3439 if (ret) 3440 return ret; 3441 3442 si_pi->papm_cfg_table_start = tmp; 3443 3444 return ret; 3445 } 3446 3447 static void si_read_clock_registers(struct radeon_device *rdev) 3448 { 3449 struct si_power_info *si_pi = si_get_pi(rdev); 3450 3451 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3452 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3453 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3454 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3455 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3456 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3457 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3458 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3459 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3460 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3461 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3462 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3463 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3464 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3465 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3466 } 3467 3468 static void si_enable_thermal_protection(struct radeon_device *rdev, 3469 bool enable) 3470 { 3471 if (enable) 3472 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3473 else 3474 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3475 } 3476 3477 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3478 { 3479 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3480 } 3481 3482 #if 0 3483 static int si_enter_ulp_state(struct radeon_device *rdev) 3484 { 3485 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3486 3487 udelay(25000); 3488 3489 return 0; 3490 } 3491 3492 static int si_exit_ulp_state(struct radeon_device *rdev) 3493 { 3494 int i; 3495 3496 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3497 3498 udelay(7000); 3499 3500 for (i = 0; i < rdev->usec_timeout; i++) { 3501 if (RREG32(SMC_RESP_0) == 1) 3502 break; 3503 udelay(1000); 3504 } 3505 3506 return 0; 3507 } 3508 #endif 3509 3510 static int si_notify_smc_display_change(struct radeon_device *rdev, 3511 bool has_display) 3512 { 3513 PPSMC_Msg msg = has_display ? 3514 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3515 3516 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3517 0 : -EINVAL; 3518 } 3519 3520 static void si_program_response_times(struct radeon_device *rdev) 3521 { 3522 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3523 u32 vddc_dly, acpi_dly, vbi_dly; 3524 u32 reference_clock; 3525 3526 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3527 3528 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3529 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3530 3531 if (voltage_response_time == 0) 3532 voltage_response_time = 1000; 3533 3534 acpi_delay_time = 15000; 3535 vbi_time_out = 100000; 3536 3537 reference_clock = radeon_get_xclk(rdev); 3538 3539 vddc_dly = (voltage_response_time * reference_clock) / 100; 3540 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3541 vbi_dly = (vbi_time_out * reference_clock) / 100; 3542 3543 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3544 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3545 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3546 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3547 } 3548 3549 static void si_program_ds_registers(struct radeon_device *rdev) 3550 { 3551 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3552 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3553 3554 if (eg_pi->sclk_deep_sleep) { 3555 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3556 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3557 ~AUTOSCALE_ON_SS_CLEAR); 3558 } 3559 } 3560 3561 static void si_program_display_gap(struct radeon_device *rdev) 3562 { 3563 u32 tmp, pipe; 3564 int i; 3565 3566 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3567 if (rdev->pm.dpm.new_active_crtc_count > 0) 3568 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3569 else 3570 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3571 3572 if (rdev->pm.dpm.new_active_crtc_count > 1) 3573 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3574 else 3575 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3576 3577 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3578 3579 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3580 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3581 3582 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3583 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3584 /* find the first active crtc */ 3585 for (i = 0; i < rdev->num_crtc; i++) { 3586 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3587 break; 3588 } 3589 if (i == rdev->num_crtc) 3590 pipe = 0; 3591 else 3592 pipe = i; 3593 3594 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3595 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3596 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3597 } 3598 3599 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3600 * This can be a problem on PowerXpress systems or if you want to use the card 3601 * for offscreen rendering or compute if there are no crtcs enabled. 3602 */ 3603 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3604 } 3605 3606 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3607 { 3608 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3609 3610 if (enable) { 3611 if (pi->sclk_ss) 3612 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3613 } else { 3614 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3615 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3616 } 3617 } 3618 3619 static void si_setup_bsp(struct radeon_device *rdev) 3620 { 3621 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3622 u32 xclk = radeon_get_xclk(rdev); 3623 3624 r600_calculate_u_and_p(pi->asi, 3625 xclk, 3626 16, 3627 &pi->bsp, 3628 &pi->bsu); 3629 3630 r600_calculate_u_and_p(pi->pasi, 3631 xclk, 3632 16, 3633 &pi->pbsp, 3634 &pi->pbsu); 3635 3636 3637 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3638 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3639 3640 WREG32(CG_BSP, pi->dsp); 3641 } 3642 3643 static void si_program_git(struct radeon_device *rdev) 3644 { 3645 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3646 } 3647 3648 static void si_program_tp(struct radeon_device *rdev) 3649 { 3650 int i; 3651 enum r600_td td = R600_TD_DFLT; 3652 3653 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3654 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3655 3656 if (td == R600_TD_AUTO) 3657 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3658 else 3659 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3660 3661 if (td == R600_TD_UP) 3662 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3663 3664 if (td == R600_TD_DOWN) 3665 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3666 } 3667 3668 static void si_program_tpp(struct radeon_device *rdev) 3669 { 3670 WREG32(CG_TPC, R600_TPC_DFLT); 3671 } 3672 3673 static void si_program_sstp(struct radeon_device *rdev) 3674 { 3675 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3676 } 3677 3678 static void si_enable_display_gap(struct radeon_device *rdev) 3679 { 3680 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3681 3682 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3683 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3684 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3685 3686 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3687 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3688 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3689 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3690 } 3691 3692 static void si_program_vc(struct radeon_device *rdev) 3693 { 3694 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3695 3696 WREG32(CG_FTV, pi->vrc); 3697 } 3698 3699 static void si_clear_vc(struct radeon_device *rdev) 3700 { 3701 WREG32(CG_FTV, 0); 3702 } 3703 3704 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3705 { 3706 u8 mc_para_index; 3707 3708 if (memory_clock < 10000) 3709 mc_para_index = 0; 3710 else if (memory_clock >= 80000) 3711 mc_para_index = 0x0f; 3712 else 3713 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3714 return mc_para_index; 3715 } 3716 3717 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3718 { 3719 u8 mc_para_index; 3720 3721 if (strobe_mode) { 3722 if (memory_clock < 12500) 3723 mc_para_index = 0x00; 3724 else if (memory_clock > 47500) 3725 mc_para_index = 0x0f; 3726 else 3727 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3728 } else { 3729 if (memory_clock < 65000) 3730 mc_para_index = 0x00; 3731 else if (memory_clock > 135000) 3732 mc_para_index = 0x0f; 3733 else 3734 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3735 } 3736 return mc_para_index; 3737 } 3738 3739 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3740 { 3741 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3742 bool strobe_mode = false; 3743 u8 result = 0; 3744 3745 if (mclk <= pi->mclk_strobe_mode_threshold) 3746 strobe_mode = true; 3747 3748 if (pi->mem_gddr5) 3749 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3750 else 3751 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3752 3753 if (strobe_mode) 3754 result |= SISLANDS_SMC_STROBE_ENABLE; 3755 3756 return result; 3757 } 3758 3759 static int si_upload_firmware(struct radeon_device *rdev) 3760 { 3761 struct si_power_info *si_pi = si_get_pi(rdev); 3762 int ret; 3763 3764 si_reset_smc(rdev); 3765 si_stop_smc_clock(rdev); 3766 3767 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3768 3769 return ret; 3770 } 3771 3772 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3773 const struct atom_voltage_table *table, 3774 const struct radeon_phase_shedding_limits_table *limits) 3775 { 3776 u32 data, num_bits, num_levels; 3777 3778 if ((table == NULL) || (limits == NULL)) 3779 return false; 3780 3781 data = table->mask_low; 3782 3783 num_bits = hweight32(data); 3784 3785 if (num_bits == 0) 3786 return false; 3787 3788 num_levels = (1 << num_bits); 3789 3790 if (table->count != num_levels) 3791 return false; 3792 3793 if (limits->count != (num_levels - 1)) 3794 return false; 3795 3796 return true; 3797 } 3798 3799 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3800 u32 max_voltage_steps, 3801 struct atom_voltage_table *voltage_table) 3802 { 3803 unsigned int i, diff; 3804 3805 if (voltage_table->count <= max_voltage_steps) 3806 return; 3807 3808 diff = voltage_table->count - max_voltage_steps; 3809 3810 for (i= 0; i < max_voltage_steps; i++) 3811 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3812 3813 voltage_table->count = max_voltage_steps; 3814 } 3815 3816 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3817 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3818 struct atom_voltage_table *voltage_table) 3819 { 3820 u32 i; 3821 3822 if (voltage_dependency_table == NULL) 3823 return -EINVAL; 3824 3825 voltage_table->mask_low = 0; 3826 voltage_table->phase_delay = 0; 3827 3828 voltage_table->count = voltage_dependency_table->count; 3829 for (i = 0; i < voltage_table->count; i++) { 3830 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3831 voltage_table->entries[i].smio_low = 0; 3832 } 3833 3834 return 0; 3835 } 3836 3837 static int si_construct_voltage_tables(struct radeon_device *rdev) 3838 { 3839 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3840 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3841 struct si_power_info *si_pi = si_get_pi(rdev); 3842 int ret; 3843 3844 if (pi->voltage_control) { 3845 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3846 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3847 if (ret) 3848 return ret; 3849 3850 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3851 si_trim_voltage_table_to_fit_state_table(rdev, 3852 SISLANDS_MAX_NO_VREG_STEPS, 3853 &eg_pi->vddc_voltage_table); 3854 } else if (si_pi->voltage_control_svi2) { 3855 ret = si_get_svi2_voltage_table(rdev, 3856 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3857 &eg_pi->vddc_voltage_table); 3858 if (ret) 3859 return ret; 3860 } else { 3861 return -EINVAL; 3862 } 3863 3864 if (eg_pi->vddci_control) { 3865 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3866 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3867 if (ret) 3868 return ret; 3869 3870 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3871 si_trim_voltage_table_to_fit_state_table(rdev, 3872 SISLANDS_MAX_NO_VREG_STEPS, 3873 &eg_pi->vddci_voltage_table); 3874 } 3875 if (si_pi->vddci_control_svi2) { 3876 ret = si_get_svi2_voltage_table(rdev, 3877 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3878 &eg_pi->vddci_voltage_table); 3879 if (ret) 3880 return ret; 3881 } 3882 3883 if (pi->mvdd_control) { 3884 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3885 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3886 3887 if (ret) { 3888 pi->mvdd_control = false; 3889 return ret; 3890 } 3891 3892 if (si_pi->mvdd_voltage_table.count == 0) { 3893 pi->mvdd_control = false; 3894 return -EINVAL; 3895 } 3896 3897 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3898 si_trim_voltage_table_to_fit_state_table(rdev, 3899 SISLANDS_MAX_NO_VREG_STEPS, 3900 &si_pi->mvdd_voltage_table); 3901 } 3902 3903 if (si_pi->vddc_phase_shed_control) { 3904 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3905 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3906 if (ret) 3907 si_pi->vddc_phase_shed_control = false; 3908 3909 if ((si_pi->vddc_phase_shed_table.count == 0) || 3910 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3911 si_pi->vddc_phase_shed_control = false; 3912 } 3913 3914 return 0; 3915 } 3916 3917 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3918 const struct atom_voltage_table *voltage_table, 3919 SISLANDS_SMC_STATETABLE *table) 3920 { 3921 unsigned int i; 3922 3923 for (i = 0; i < voltage_table->count; i++) 3924 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3925 } 3926 3927 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3928 SISLANDS_SMC_STATETABLE *table) 3929 { 3930 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3931 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3932 struct si_power_info *si_pi = si_get_pi(rdev); 3933 u8 i; 3934 3935 if (si_pi->voltage_control_svi2) { 3936 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 3937 si_pi->svc_gpio_id); 3938 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 3939 si_pi->svd_gpio_id); 3940 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 3941 2); 3942 } else { 3943 if (eg_pi->vddc_voltage_table.count) { 3944 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3945 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3946 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3947 3948 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3949 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3950 table->maxVDDCIndexInPPTable = i; 3951 break; 3952 } 3953 } 3954 } 3955 3956 if (eg_pi->vddci_voltage_table.count) { 3957 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3958 3959 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3960 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3961 } 3962 3963 3964 if (si_pi->mvdd_voltage_table.count) { 3965 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3966 3967 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3968 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3969 } 3970 3971 if (si_pi->vddc_phase_shed_control) { 3972 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3973 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3974 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3975 3976 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3977 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3978 3979 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3980 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3981 } else { 3982 si_pi->vddc_phase_shed_control = false; 3983 } 3984 } 3985 } 3986 3987 return 0; 3988 } 3989 3990 static int si_populate_voltage_value(struct radeon_device *rdev, 3991 const struct atom_voltage_table *table, 3992 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3993 { 3994 unsigned int i; 3995 3996 for (i = 0; i < table->count; i++) { 3997 if (value <= table->entries[i].value) { 3998 voltage->index = (u8)i; 3999 voltage->value = cpu_to_be16(table->entries[i].value); 4000 break; 4001 } 4002 } 4003 4004 if (i >= table->count) 4005 return -EINVAL; 4006 4007 return 0; 4008 } 4009 4010 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4011 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4012 { 4013 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4014 struct si_power_info *si_pi = si_get_pi(rdev); 4015 4016 if (pi->mvdd_control) { 4017 if (mclk <= pi->mvdd_split_frequency) 4018 voltage->index = 0; 4019 else 4020 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4021 4022 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4023 } 4024 return 0; 4025 } 4026 4027 static int si_get_std_voltage_value(struct radeon_device *rdev, 4028 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4029 u16 *std_voltage) 4030 { 4031 u16 v_index; 4032 bool voltage_found = false; 4033 *std_voltage = be16_to_cpu(voltage->value); 4034 4035 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4036 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4037 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4038 return -EINVAL; 4039 4040 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4041 if (be16_to_cpu(voltage->value) == 4042 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4043 voltage_found = true; 4044 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4045 *std_voltage = 4046 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4047 else 4048 *std_voltage = 4049 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4050 break; 4051 } 4052 } 4053 4054 if (!voltage_found) { 4055 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4056 if (be16_to_cpu(voltage->value) <= 4057 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4058 voltage_found = true; 4059 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4060 *std_voltage = 4061 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4062 else 4063 *std_voltage = 4064 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4065 break; 4066 } 4067 } 4068 } 4069 } else { 4070 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4071 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4072 } 4073 } 4074 4075 return 0; 4076 } 4077 4078 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4079 u16 value, u8 index, 4080 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4081 { 4082 voltage->index = index; 4083 voltage->value = cpu_to_be16(value); 4084 4085 return 0; 4086 } 4087 4088 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4089 const struct radeon_phase_shedding_limits_table *limits, 4090 u16 voltage, u32 sclk, u32 mclk, 4091 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4092 { 4093 unsigned int i; 4094 4095 for (i = 0; i < limits->count; i++) { 4096 if ((voltage <= limits->entries[i].voltage) && 4097 (sclk <= limits->entries[i].sclk) && 4098 (mclk <= limits->entries[i].mclk)) 4099 break; 4100 } 4101 4102 smc_voltage->phase_settings = (u8)i; 4103 4104 return 0; 4105 } 4106 4107 static int si_init_arb_table_index(struct radeon_device *rdev) 4108 { 4109 struct si_power_info *si_pi = si_get_pi(rdev); 4110 u32 tmp; 4111 int ret; 4112 4113 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4114 if (ret) 4115 return ret; 4116 4117 tmp &= 0x00FFFFFF; 4118 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4119 4120 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4121 } 4122 4123 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4124 { 4125 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4126 } 4127 4128 static int si_reset_to_default(struct radeon_device *rdev) 4129 { 4130 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4131 0 : -EINVAL; 4132 } 4133 4134 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4135 { 4136 struct si_power_info *si_pi = si_get_pi(rdev); 4137 u32 tmp; 4138 int ret; 4139 4140 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4141 &tmp, si_pi->sram_end); 4142 if (ret) 4143 return ret; 4144 4145 tmp = (tmp >> 24) & 0xff; 4146 4147 if (tmp == MC_CG_ARB_FREQ_F0) 4148 return 0; 4149 4150 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4151 } 4152 4153 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4154 u32 engine_clock) 4155 { 4156 u32 dram_rows; 4157 u32 dram_refresh_rate; 4158 u32 mc_arb_rfsh_rate; 4159 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4160 4161 if (tmp >= 4) 4162 dram_rows = 16384; 4163 else 4164 dram_rows = 1 << (tmp + 10); 4165 4166 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4167 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4168 4169 return mc_arb_rfsh_rate; 4170 } 4171 4172 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4173 struct rv7xx_pl *pl, 4174 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4175 { 4176 u32 dram_timing; 4177 u32 dram_timing2; 4178 u32 burst_time; 4179 4180 arb_regs->mc_arb_rfsh_rate = 4181 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4182 4183 radeon_atom_set_engine_dram_timings(rdev, 4184 pl->sclk, 4185 pl->mclk); 4186 4187 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4188 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4189 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4190 4191 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4192 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4193 arb_regs->mc_arb_burst_time = (u8)burst_time; 4194 4195 return 0; 4196 } 4197 4198 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4199 struct radeon_ps *radeon_state, 4200 unsigned int first_arb_set) 4201 { 4202 struct si_power_info *si_pi = si_get_pi(rdev); 4203 struct ni_ps *state = ni_get_ps(radeon_state); 4204 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4205 int i, ret = 0; 4206 4207 for (i = 0; i < state->performance_level_count; i++) { 4208 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4209 if (ret) 4210 break; 4211 ret = si_copy_bytes_to_smc(rdev, 4212 si_pi->arb_table_start + 4213 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4214 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4215 (u8 *)&arb_regs, 4216 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4217 si_pi->sram_end); 4218 if (ret) 4219 break; 4220 } 4221 4222 return ret; 4223 } 4224 4225 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4226 struct radeon_ps *radeon_new_state) 4227 { 4228 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4229 SISLANDS_DRIVER_STATE_ARB_INDEX); 4230 } 4231 4232 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4233 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4234 { 4235 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4236 struct si_power_info *si_pi = si_get_pi(rdev); 4237 4238 if (pi->mvdd_control) 4239 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4240 si_pi->mvdd_bootup_value, voltage); 4241 4242 return 0; 4243 } 4244 4245 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4246 struct radeon_ps *radeon_initial_state, 4247 SISLANDS_SMC_STATETABLE *table) 4248 { 4249 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4250 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4251 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4252 struct si_power_info *si_pi = si_get_pi(rdev); 4253 u32 reg; 4254 int ret; 4255 4256 table->initialState.levels[0].mclk.vDLL_CNTL = 4257 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4258 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4259 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4260 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4261 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4262 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4263 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4264 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4265 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4266 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4267 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4268 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4269 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4270 table->initialState.levels[0].mclk.vMPLL_SS = 4271 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4272 table->initialState.levels[0].mclk.vMPLL_SS2 = 4273 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4274 4275 table->initialState.levels[0].mclk.mclk_value = 4276 cpu_to_be32(initial_state->performance_levels[0].mclk); 4277 4278 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4279 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4280 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4281 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4282 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4283 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4284 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4285 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4286 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4287 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4288 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4289 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4290 4291 table->initialState.levels[0].sclk.sclk_value = 4292 cpu_to_be32(initial_state->performance_levels[0].sclk); 4293 4294 table->initialState.levels[0].arbRefreshState = 4295 SISLANDS_INITIAL_STATE_ARB_INDEX; 4296 4297 table->initialState.levels[0].ACIndex = 0; 4298 4299 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4300 initial_state->performance_levels[0].vddc, 4301 &table->initialState.levels[0].vddc); 4302 4303 if (!ret) { 4304 u16 std_vddc; 4305 4306 ret = si_get_std_voltage_value(rdev, 4307 &table->initialState.levels[0].vddc, 4308 &std_vddc); 4309 if (!ret) 4310 si_populate_std_voltage_value(rdev, std_vddc, 4311 table->initialState.levels[0].vddc.index, 4312 &table->initialState.levels[0].std_vddc); 4313 } 4314 4315 if (eg_pi->vddci_control) 4316 si_populate_voltage_value(rdev, 4317 &eg_pi->vddci_voltage_table, 4318 initial_state->performance_levels[0].vddci, 4319 &table->initialState.levels[0].vddci); 4320 4321 if (si_pi->vddc_phase_shed_control) 4322 si_populate_phase_shedding_value(rdev, 4323 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4324 initial_state->performance_levels[0].vddc, 4325 initial_state->performance_levels[0].sclk, 4326 initial_state->performance_levels[0].mclk, 4327 &table->initialState.levels[0].vddc); 4328 4329 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4330 4331 reg = CG_R(0xffff) | CG_L(0); 4332 table->initialState.levels[0].aT = cpu_to_be32(reg); 4333 4334 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4335 4336 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4337 4338 if (pi->mem_gddr5) { 4339 table->initialState.levels[0].strobeMode = 4340 si_get_strobe_mode_settings(rdev, 4341 initial_state->performance_levels[0].mclk); 4342 4343 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4344 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4345 else 4346 table->initialState.levels[0].mcFlags = 0; 4347 } 4348 4349 table->initialState.levelCount = 1; 4350 4351 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4352 4353 table->initialState.levels[0].dpm2.MaxPS = 0; 4354 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4355 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4356 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4357 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4358 4359 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4360 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4361 4362 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4363 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4364 4365 return 0; 4366 } 4367 4368 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4369 SISLANDS_SMC_STATETABLE *table) 4370 { 4371 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4372 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4373 struct si_power_info *si_pi = si_get_pi(rdev); 4374 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4375 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4376 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4377 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4378 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4379 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4380 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4381 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4382 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4383 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4384 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4385 u32 reg; 4386 int ret; 4387 4388 table->ACPIState = table->initialState; 4389 4390 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4391 4392 if (pi->acpi_vddc) { 4393 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4394 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4395 if (!ret) { 4396 u16 std_vddc; 4397 4398 ret = si_get_std_voltage_value(rdev, 4399 &table->ACPIState.levels[0].vddc, &std_vddc); 4400 if (!ret) 4401 si_populate_std_voltage_value(rdev, std_vddc, 4402 table->ACPIState.levels[0].vddc.index, 4403 &table->ACPIState.levels[0].std_vddc); 4404 } 4405 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4406 4407 if (si_pi->vddc_phase_shed_control) { 4408 si_populate_phase_shedding_value(rdev, 4409 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4410 pi->acpi_vddc, 4411 0, 4412 0, 4413 &table->ACPIState.levels[0].vddc); 4414 } 4415 } else { 4416 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4417 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4418 if (!ret) { 4419 u16 std_vddc; 4420 4421 ret = si_get_std_voltage_value(rdev, 4422 &table->ACPIState.levels[0].vddc, &std_vddc); 4423 4424 if (!ret) 4425 si_populate_std_voltage_value(rdev, std_vddc, 4426 table->ACPIState.levels[0].vddc.index, 4427 &table->ACPIState.levels[0].std_vddc); 4428 } 4429 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4430 si_pi->sys_pcie_mask, 4431 si_pi->boot_pcie_gen, 4432 RADEON_PCIE_GEN1); 4433 4434 if (si_pi->vddc_phase_shed_control) 4435 si_populate_phase_shedding_value(rdev, 4436 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4437 pi->min_vddc_in_table, 4438 0, 4439 0, 4440 &table->ACPIState.levels[0].vddc); 4441 } 4442 4443 if (pi->acpi_vddc) { 4444 if (eg_pi->acpi_vddci) 4445 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4446 eg_pi->acpi_vddci, 4447 &table->ACPIState.levels[0].vddci); 4448 } 4449 4450 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4451 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4452 4453 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4454 4455 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4456 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4457 4458 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4459 cpu_to_be32(dll_cntl); 4460 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4461 cpu_to_be32(mclk_pwrmgt_cntl); 4462 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4463 cpu_to_be32(mpll_ad_func_cntl); 4464 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4465 cpu_to_be32(mpll_dq_func_cntl); 4466 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4467 cpu_to_be32(mpll_func_cntl); 4468 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4469 cpu_to_be32(mpll_func_cntl_1); 4470 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4471 cpu_to_be32(mpll_func_cntl_2); 4472 table->ACPIState.levels[0].mclk.vMPLL_SS = 4473 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4474 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4475 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4476 4477 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4478 cpu_to_be32(spll_func_cntl); 4479 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4480 cpu_to_be32(spll_func_cntl_2); 4481 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4482 cpu_to_be32(spll_func_cntl_3); 4483 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4484 cpu_to_be32(spll_func_cntl_4); 4485 4486 table->ACPIState.levels[0].mclk.mclk_value = 0; 4487 table->ACPIState.levels[0].sclk.sclk_value = 0; 4488 4489 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4490 4491 if (eg_pi->dynamic_ac_timing) 4492 table->ACPIState.levels[0].ACIndex = 0; 4493 4494 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4495 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4496 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4497 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4498 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4499 4500 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4501 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4502 4503 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4504 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4505 4506 return 0; 4507 } 4508 4509 static int si_populate_ulv_state(struct radeon_device *rdev, 4510 SISLANDS_SMC_SWSTATE *state) 4511 { 4512 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4513 struct si_power_info *si_pi = si_get_pi(rdev); 4514 struct si_ulv_param *ulv = &si_pi->ulv; 4515 u32 sclk_in_sr = 1350; /* ??? */ 4516 int ret; 4517 4518 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4519 &state->levels[0]); 4520 if (!ret) { 4521 if (eg_pi->sclk_deep_sleep) { 4522 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4523 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4524 else 4525 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4526 } 4527 if (ulv->one_pcie_lane_in_ulv) 4528 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4529 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4530 state->levels[0].ACIndex = 1; 4531 state->levels[0].std_vddc = state->levels[0].vddc; 4532 state->levelCount = 1; 4533 4534 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4535 } 4536 4537 return ret; 4538 } 4539 4540 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4541 { 4542 struct si_power_info *si_pi = si_get_pi(rdev); 4543 struct si_ulv_param *ulv = &si_pi->ulv; 4544 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4545 int ret; 4546 4547 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4548 &arb_regs); 4549 if (ret) 4550 return ret; 4551 4552 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4553 ulv->volt_change_delay); 4554 4555 ret = si_copy_bytes_to_smc(rdev, 4556 si_pi->arb_table_start + 4557 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4558 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4559 (u8 *)&arb_regs, 4560 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4561 si_pi->sram_end); 4562 4563 return ret; 4564 } 4565 4566 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4567 { 4568 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4569 4570 pi->mvdd_split_frequency = 30000; 4571 } 4572 4573 static int si_init_smc_table(struct radeon_device *rdev) 4574 { 4575 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4576 struct si_power_info *si_pi = si_get_pi(rdev); 4577 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4578 const struct si_ulv_param *ulv = &si_pi->ulv; 4579 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4580 int ret; 4581 u32 lane_width; 4582 u32 vr_hot_gpio; 4583 4584 si_populate_smc_voltage_tables(rdev, table); 4585 4586 switch (rdev->pm.int_thermal_type) { 4587 case THERMAL_TYPE_SI: 4588 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4589 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4590 break; 4591 case THERMAL_TYPE_NONE: 4592 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4593 break; 4594 default: 4595 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4596 break; 4597 } 4598 4599 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4600 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4601 4602 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4603 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4604 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4605 } 4606 4607 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4608 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4609 4610 if (pi->mem_gddr5) 4611 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4612 4613 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4614 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4615 4616 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4617 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4618 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4619 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4620 vr_hot_gpio); 4621 } 4622 4623 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4624 if (ret) 4625 return ret; 4626 4627 ret = si_populate_smc_acpi_state(rdev, table); 4628 if (ret) 4629 return ret; 4630 4631 table->driverState = table->initialState; 4632 4633 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4634 SISLANDS_INITIAL_STATE_ARB_INDEX); 4635 if (ret) 4636 return ret; 4637 4638 if (ulv->supported && ulv->pl.vddc) { 4639 ret = si_populate_ulv_state(rdev, &table->ULVState); 4640 if (ret) 4641 return ret; 4642 4643 ret = si_program_ulv_memory_timing_parameters(rdev); 4644 if (ret) 4645 return ret; 4646 4647 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4648 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4649 4650 lane_width = radeon_get_pcie_lanes(rdev); 4651 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4652 } else { 4653 table->ULVState = table->initialState; 4654 } 4655 4656 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4657 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4658 si_pi->sram_end); 4659 } 4660 4661 static int si_calculate_sclk_params(struct radeon_device *rdev, 4662 u32 engine_clock, 4663 SISLANDS_SMC_SCLK_VALUE *sclk) 4664 { 4665 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4666 struct si_power_info *si_pi = si_get_pi(rdev); 4667 struct atom_clock_dividers dividers; 4668 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4669 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4670 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4671 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4672 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4673 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4674 u64 tmp; 4675 u32 reference_clock = rdev->clock.spll.reference_freq; 4676 u32 reference_divider; 4677 u32 fbdiv; 4678 int ret; 4679 4680 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4681 engine_clock, false, ÷rs); 4682 if (ret) 4683 return ret; 4684 4685 reference_divider = 1 + dividers.ref_div; 4686 4687 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4688 do_div(tmp, reference_clock); 4689 fbdiv = (u32) tmp; 4690 4691 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4692 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4693 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4694 4695 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4696 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4697 4698 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4699 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4700 spll_func_cntl_3 |= SPLL_DITHEN; 4701 4702 if (pi->sclk_ss) { 4703 struct radeon_atom_ss ss; 4704 u32 vco_freq = engine_clock * dividers.post_div; 4705 4706 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4707 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4708 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4709 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4710 4711 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4712 cg_spll_spread_spectrum |= CLK_S(clk_s); 4713 cg_spll_spread_spectrum |= SSEN; 4714 4715 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4716 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4717 } 4718 } 4719 4720 sclk->sclk_value = engine_clock; 4721 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4722 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4723 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4724 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4725 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4726 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4727 4728 return 0; 4729 } 4730 4731 static int si_populate_sclk_value(struct radeon_device *rdev, 4732 u32 engine_clock, 4733 SISLANDS_SMC_SCLK_VALUE *sclk) 4734 { 4735 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4736 int ret; 4737 4738 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4739 if (!ret) { 4740 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4741 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4742 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4743 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4744 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4745 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4746 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4747 } 4748 4749 return ret; 4750 } 4751 4752 static int si_populate_mclk_value(struct radeon_device *rdev, 4753 u32 engine_clock, 4754 u32 memory_clock, 4755 SISLANDS_SMC_MCLK_VALUE *mclk, 4756 bool strobe_mode, 4757 bool dll_state_on) 4758 { 4759 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4760 struct si_power_info *si_pi = si_get_pi(rdev); 4761 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4762 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4763 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4764 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4765 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4766 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4767 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4768 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4769 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4770 struct atom_mpll_param mpll_param; 4771 int ret; 4772 4773 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4774 if (ret) 4775 return ret; 4776 4777 mpll_func_cntl &= ~BWCTRL_MASK; 4778 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4779 4780 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4781 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4782 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4783 4784 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4785 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4786 4787 if (pi->mem_gddr5) { 4788 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4789 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4790 YCLK_POST_DIV(mpll_param.post_div); 4791 } 4792 4793 if (pi->mclk_ss) { 4794 struct radeon_atom_ss ss; 4795 u32 freq_nom; 4796 u32 tmp; 4797 u32 reference_clock = rdev->clock.mpll.reference_freq; 4798 4799 if (pi->mem_gddr5) 4800 freq_nom = memory_clock * 4; 4801 else 4802 freq_nom = memory_clock * 2; 4803 4804 tmp = freq_nom / reference_clock; 4805 tmp = tmp * tmp; 4806 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4807 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4808 u32 clks = reference_clock * 5 / ss.rate; 4809 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4810 4811 mpll_ss1 &= ~CLKV_MASK; 4812 mpll_ss1 |= CLKV(clkv); 4813 4814 mpll_ss2 &= ~CLKS_MASK; 4815 mpll_ss2 |= CLKS(clks); 4816 } 4817 } 4818 4819 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4820 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4821 4822 if (dll_state_on) 4823 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4824 else 4825 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4826 4827 mclk->mclk_value = cpu_to_be32(memory_clock); 4828 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4829 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4830 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4831 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4832 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4833 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4834 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4835 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4836 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4837 4838 return 0; 4839 } 4840 4841 static void si_populate_smc_sp(struct radeon_device *rdev, 4842 struct radeon_ps *radeon_state, 4843 SISLANDS_SMC_SWSTATE *smc_state) 4844 { 4845 struct ni_ps *ps = ni_get_ps(radeon_state); 4846 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4847 int i; 4848 4849 for (i = 0; i < ps->performance_level_count - 1; i++) 4850 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4851 4852 smc_state->levels[ps->performance_level_count - 1].bSP = 4853 cpu_to_be32(pi->psp); 4854 } 4855 4856 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4857 struct rv7xx_pl *pl, 4858 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4859 { 4860 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4861 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4862 struct si_power_info *si_pi = si_get_pi(rdev); 4863 int ret; 4864 bool dll_state_on; 4865 u16 std_vddc; 4866 bool gmc_pg = false; 4867 4868 if (eg_pi->pcie_performance_request && 4869 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4870 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4871 else 4872 level->gen2PCIE = (u8)pl->pcie_gen; 4873 4874 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4875 if (ret) 4876 return ret; 4877 4878 level->mcFlags = 0; 4879 4880 if (pi->mclk_stutter_mode_threshold && 4881 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4882 !eg_pi->uvd_enabled && 4883 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4884 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4885 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4886 4887 if (gmc_pg) 4888 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4889 } 4890 4891 if (pi->mem_gddr5) { 4892 if (pl->mclk > pi->mclk_edc_enable_threshold) 4893 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4894 4895 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4896 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4897 4898 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4899 4900 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4901 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4902 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4903 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4904 else 4905 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4906 } else { 4907 dll_state_on = false; 4908 } 4909 } else { 4910 level->strobeMode = si_get_strobe_mode_settings(rdev, 4911 pl->mclk); 4912 4913 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4914 } 4915 4916 ret = si_populate_mclk_value(rdev, 4917 pl->sclk, 4918 pl->mclk, 4919 &level->mclk, 4920 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4921 if (ret) 4922 return ret; 4923 4924 ret = si_populate_voltage_value(rdev, 4925 &eg_pi->vddc_voltage_table, 4926 pl->vddc, &level->vddc); 4927 if (ret) 4928 return ret; 4929 4930 4931 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4932 if (ret) 4933 return ret; 4934 4935 ret = si_populate_std_voltage_value(rdev, std_vddc, 4936 level->vddc.index, &level->std_vddc); 4937 if (ret) 4938 return ret; 4939 4940 if (eg_pi->vddci_control) { 4941 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4942 pl->vddci, &level->vddci); 4943 if (ret) 4944 return ret; 4945 } 4946 4947 if (si_pi->vddc_phase_shed_control) { 4948 ret = si_populate_phase_shedding_value(rdev, 4949 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4950 pl->vddc, 4951 pl->sclk, 4952 pl->mclk, 4953 &level->vddc); 4954 if (ret) 4955 return ret; 4956 } 4957 4958 level->MaxPoweredUpCU = si_pi->max_cu; 4959 4960 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4961 4962 return ret; 4963 } 4964 4965 static int si_populate_smc_t(struct radeon_device *rdev, 4966 struct radeon_ps *radeon_state, 4967 SISLANDS_SMC_SWSTATE *smc_state) 4968 { 4969 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4970 struct ni_ps *state = ni_get_ps(radeon_state); 4971 u32 a_t; 4972 u32 t_l, t_h; 4973 u32 high_bsp; 4974 int i, ret; 4975 4976 if (state->performance_level_count >= 9) 4977 return -EINVAL; 4978 4979 if (state->performance_level_count < 2) { 4980 a_t = CG_R(0xffff) | CG_L(0); 4981 smc_state->levels[0].aT = cpu_to_be32(a_t); 4982 return 0; 4983 } 4984 4985 smc_state->levels[0].aT = cpu_to_be32(0); 4986 4987 for (i = 0; i <= state->performance_level_count - 2; i++) { 4988 ret = r600_calculate_at( 4989 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4990 100 * R600_AH_DFLT, 4991 state->performance_levels[i + 1].sclk, 4992 state->performance_levels[i].sclk, 4993 &t_l, 4994 &t_h); 4995 4996 if (ret) { 4997 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4998 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4999 } 5000 5001 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5002 a_t |= CG_R(t_l * pi->bsp / 20000); 5003 smc_state->levels[i].aT = cpu_to_be32(a_t); 5004 5005 high_bsp = (i == state->performance_level_count - 2) ? 5006 pi->pbsp : pi->bsp; 5007 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5008 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5009 } 5010 5011 return 0; 5012 } 5013 5014 static int si_disable_ulv(struct radeon_device *rdev) 5015 { 5016 struct si_power_info *si_pi = si_get_pi(rdev); 5017 struct si_ulv_param *ulv = &si_pi->ulv; 5018 5019 if (ulv->supported) 5020 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5021 0 : -EINVAL; 5022 5023 return 0; 5024 } 5025 5026 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5027 struct radeon_ps *radeon_state) 5028 { 5029 const struct si_power_info *si_pi = si_get_pi(rdev); 5030 const struct si_ulv_param *ulv = &si_pi->ulv; 5031 const struct ni_ps *state = ni_get_ps(radeon_state); 5032 int i; 5033 5034 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5035 return false; 5036 5037 /* XXX validate against display requirements! */ 5038 5039 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5040 if (rdev->clock.current_dispclk <= 5041 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5042 if (ulv->pl.vddc < 5043 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5044 return false; 5045 } 5046 } 5047 5048 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5049 return false; 5050 5051 return true; 5052 } 5053 5054 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5055 struct radeon_ps *radeon_new_state) 5056 { 5057 const struct si_power_info *si_pi = si_get_pi(rdev); 5058 const struct si_ulv_param *ulv = &si_pi->ulv; 5059 5060 if (ulv->supported) { 5061 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5062 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5063 0 : -EINVAL; 5064 } 5065 return 0; 5066 } 5067 5068 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5069 struct radeon_ps *radeon_state, 5070 SISLANDS_SMC_SWSTATE *smc_state) 5071 { 5072 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5073 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5074 struct si_power_info *si_pi = si_get_pi(rdev); 5075 struct ni_ps *state = ni_get_ps(radeon_state); 5076 int i, ret; 5077 u32 threshold; 5078 u32 sclk_in_sr = 1350; /* ??? */ 5079 5080 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5081 return -EINVAL; 5082 5083 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5084 5085 if (radeon_state->vclk && radeon_state->dclk) { 5086 eg_pi->uvd_enabled = true; 5087 if (eg_pi->smu_uvd_hs) 5088 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5089 } else { 5090 eg_pi->uvd_enabled = false; 5091 } 5092 5093 if (state->dc_compatible) 5094 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5095 5096 smc_state->levelCount = 0; 5097 for (i = 0; i < state->performance_level_count; i++) { 5098 if (eg_pi->sclk_deep_sleep) { 5099 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5100 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5101 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5102 else 5103 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5104 } 5105 } 5106 5107 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5108 &smc_state->levels[i]); 5109 smc_state->levels[i].arbRefreshState = 5110 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5111 5112 if (ret) 5113 return ret; 5114 5115 if (ni_pi->enable_power_containment) 5116 smc_state->levels[i].displayWatermark = 5117 (state->performance_levels[i].sclk < threshold) ? 5118 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5119 else 5120 smc_state->levels[i].displayWatermark = (i < 2) ? 5121 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5122 5123 if (eg_pi->dynamic_ac_timing) 5124 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5125 else 5126 smc_state->levels[i].ACIndex = 0; 5127 5128 smc_state->levelCount++; 5129 } 5130 5131 si_write_smc_soft_register(rdev, 5132 SI_SMC_SOFT_REGISTER_watermark_threshold, 5133 threshold / 512); 5134 5135 si_populate_smc_sp(rdev, radeon_state, smc_state); 5136 5137 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5138 if (ret) 5139 ni_pi->enable_power_containment = false; 5140 5141 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5142 if (ret) 5143 ni_pi->enable_sq_ramping = false; 5144 5145 return si_populate_smc_t(rdev, radeon_state, smc_state); 5146 } 5147 5148 static int si_upload_sw_state(struct radeon_device *rdev, 5149 struct radeon_ps *radeon_new_state) 5150 { 5151 struct si_power_info *si_pi = si_get_pi(rdev); 5152 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5153 int ret; 5154 u32 address = si_pi->state_table_start + 5155 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5156 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5157 ((new_state->performance_level_count - 1) * 5158 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5159 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5160 5161 memset(smc_state, 0, state_size); 5162 5163 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5164 if (ret) 5165 return ret; 5166 5167 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5168 state_size, si_pi->sram_end); 5169 5170 return ret; 5171 } 5172 5173 static int si_upload_ulv_state(struct radeon_device *rdev) 5174 { 5175 struct si_power_info *si_pi = si_get_pi(rdev); 5176 struct si_ulv_param *ulv = &si_pi->ulv; 5177 int ret = 0; 5178 5179 if (ulv->supported && ulv->pl.vddc) { 5180 u32 address = si_pi->state_table_start + 5181 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5182 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5183 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5184 5185 memset(smc_state, 0, state_size); 5186 5187 ret = si_populate_ulv_state(rdev, smc_state); 5188 if (!ret) 5189 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5190 state_size, si_pi->sram_end); 5191 } 5192 5193 return ret; 5194 } 5195 5196 static int si_upload_smc_data(struct radeon_device *rdev) 5197 { 5198 struct radeon_crtc *radeon_crtc = NULL; 5199 int i; 5200 5201 if (rdev->pm.dpm.new_active_crtc_count == 0) 5202 return 0; 5203 5204 for (i = 0; i < rdev->num_crtc; i++) { 5205 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5206 radeon_crtc = rdev->mode_info.crtcs[i]; 5207 break; 5208 } 5209 } 5210 5211 if (radeon_crtc == NULL) 5212 return 0; 5213 5214 if (radeon_crtc->line_time <= 0) 5215 return 0; 5216 5217 if (si_write_smc_soft_register(rdev, 5218 SI_SMC_SOFT_REGISTER_crtc_index, 5219 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5220 return 0; 5221 5222 if (si_write_smc_soft_register(rdev, 5223 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5224 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5225 return 0; 5226 5227 if (si_write_smc_soft_register(rdev, 5228 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5229 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5230 return 0; 5231 5232 return 0; 5233 } 5234 5235 static int si_set_mc_special_registers(struct radeon_device *rdev, 5236 struct si_mc_reg_table *table) 5237 { 5238 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5239 u8 i, j, k; 5240 u32 temp_reg; 5241 5242 for (i = 0, j = table->last; i < table->last; i++) { 5243 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5244 return -EINVAL; 5245 switch (table->mc_reg_address[i].s1 << 2) { 5246 case MC_SEQ_MISC1: 5247 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5248 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5249 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5250 for (k = 0; k < table->num_entries; k++) 5251 table->mc_reg_table_entry[k].mc_data[j] = 5252 ((temp_reg & 0xffff0000)) | 5253 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5254 j++; 5255 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5256 return -EINVAL; 5257 5258 temp_reg = RREG32(MC_PMG_CMD_MRS); 5259 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5260 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5261 for (k = 0; k < table->num_entries; k++) { 5262 table->mc_reg_table_entry[k].mc_data[j] = 5263 (temp_reg & 0xffff0000) | 5264 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5265 if (!pi->mem_gddr5) 5266 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5267 } 5268 j++; 5269 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5270 return -EINVAL; 5271 5272 if (!pi->mem_gddr5) { 5273 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5274 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5275 for (k = 0; k < table->num_entries; k++) 5276 table->mc_reg_table_entry[k].mc_data[j] = 5277 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5278 j++; 5279 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5280 return -EINVAL; 5281 } 5282 break; 5283 case MC_SEQ_RESERVE_M: 5284 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5285 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5286 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5287 for(k = 0; k < table->num_entries; k++) 5288 table->mc_reg_table_entry[k].mc_data[j] = 5289 (temp_reg & 0xffff0000) | 5290 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5291 j++; 5292 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5293 return -EINVAL; 5294 break; 5295 default: 5296 break; 5297 } 5298 } 5299 5300 table->last = j; 5301 5302 return 0; 5303 } 5304 5305 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5306 { 5307 bool result = true; 5308 5309 switch (in_reg) { 5310 case MC_SEQ_RAS_TIMING >> 2: 5311 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5312 break; 5313 case MC_SEQ_CAS_TIMING >> 2: 5314 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5315 break; 5316 case MC_SEQ_MISC_TIMING >> 2: 5317 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5318 break; 5319 case MC_SEQ_MISC_TIMING2 >> 2: 5320 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5321 break; 5322 case MC_SEQ_RD_CTL_D0 >> 2: 5323 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5324 break; 5325 case MC_SEQ_RD_CTL_D1 >> 2: 5326 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5327 break; 5328 case MC_SEQ_WR_CTL_D0 >> 2: 5329 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5330 break; 5331 case MC_SEQ_WR_CTL_D1 >> 2: 5332 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5333 break; 5334 case MC_PMG_CMD_EMRS >> 2: 5335 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5336 break; 5337 case MC_PMG_CMD_MRS >> 2: 5338 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5339 break; 5340 case MC_PMG_CMD_MRS1 >> 2: 5341 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5342 break; 5343 case MC_SEQ_PMG_TIMING >> 2: 5344 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5345 break; 5346 case MC_PMG_CMD_MRS2 >> 2: 5347 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5348 break; 5349 case MC_SEQ_WR_CTL_2 >> 2: 5350 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5351 break; 5352 default: 5353 result = false; 5354 break; 5355 } 5356 5357 return result; 5358 } 5359 5360 static void si_set_valid_flag(struct si_mc_reg_table *table) 5361 { 5362 u8 i, j; 5363 5364 for (i = 0; i < table->last; i++) { 5365 for (j = 1; j < table->num_entries; j++) { 5366 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5367 table->valid_flag |= 1 << i; 5368 break; 5369 } 5370 } 5371 } 5372 } 5373 5374 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5375 { 5376 u32 i; 5377 u16 address; 5378 5379 for (i = 0; i < table->last; i++) 5380 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5381 address : table->mc_reg_address[i].s1; 5382 5383 } 5384 5385 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5386 struct si_mc_reg_table *si_table) 5387 { 5388 u8 i, j; 5389 5390 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5391 return -EINVAL; 5392 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5393 return -EINVAL; 5394 5395 for (i = 0; i < table->last; i++) 5396 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5397 si_table->last = table->last; 5398 5399 for (i = 0; i < table->num_entries; i++) { 5400 si_table->mc_reg_table_entry[i].mclk_max = 5401 table->mc_reg_table_entry[i].mclk_max; 5402 for (j = 0; j < table->last; j++) { 5403 si_table->mc_reg_table_entry[i].mc_data[j] = 5404 table->mc_reg_table_entry[i].mc_data[j]; 5405 } 5406 } 5407 si_table->num_entries = table->num_entries; 5408 5409 return 0; 5410 } 5411 5412 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5413 { 5414 struct si_power_info *si_pi = si_get_pi(rdev); 5415 struct atom_mc_reg_table *table; 5416 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5417 u8 module_index = rv770_get_memory_module_index(rdev); 5418 int ret; 5419 5420 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5421 if (!table) 5422 return -ENOMEM; 5423 5424 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5425 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5426 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5427 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5428 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5429 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5430 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5431 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5432 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5433 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5434 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5435 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5436 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5437 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5438 5439 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5440 if (ret) 5441 goto init_mc_done; 5442 5443 ret = si_copy_vbios_mc_reg_table(table, si_table); 5444 if (ret) 5445 goto init_mc_done; 5446 5447 si_set_s0_mc_reg_index(si_table); 5448 5449 ret = si_set_mc_special_registers(rdev, si_table); 5450 if (ret) 5451 goto init_mc_done; 5452 5453 si_set_valid_flag(si_table); 5454 5455 init_mc_done: 5456 kfree(table); 5457 5458 return ret; 5459 5460 } 5461 5462 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5463 SMC_SIslands_MCRegisters *mc_reg_table) 5464 { 5465 struct si_power_info *si_pi = si_get_pi(rdev); 5466 u32 i, j; 5467 5468 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5469 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5470 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5471 break; 5472 mc_reg_table->address[i].s0 = 5473 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5474 mc_reg_table->address[i].s1 = 5475 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5476 i++; 5477 } 5478 } 5479 mc_reg_table->last = (u8)i; 5480 } 5481 5482 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5483 SMC_SIslands_MCRegisterSet *data, 5484 u32 num_entries, u32 valid_flag) 5485 { 5486 u32 i, j; 5487 5488 for(i = 0, j = 0; j < num_entries; j++) { 5489 if (valid_flag & (1 << j)) { 5490 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5491 i++; 5492 } 5493 } 5494 } 5495 5496 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5497 struct rv7xx_pl *pl, 5498 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5499 { 5500 struct si_power_info *si_pi = si_get_pi(rdev); 5501 u32 i = 0; 5502 5503 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5504 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5505 break; 5506 } 5507 5508 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5509 --i; 5510 5511 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5512 mc_reg_table_data, si_pi->mc_reg_table.last, 5513 si_pi->mc_reg_table.valid_flag); 5514 } 5515 5516 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5517 struct radeon_ps *radeon_state, 5518 SMC_SIslands_MCRegisters *mc_reg_table) 5519 { 5520 struct ni_ps *state = ni_get_ps(radeon_state); 5521 int i; 5522 5523 for (i = 0; i < state->performance_level_count; i++) { 5524 si_convert_mc_reg_table_entry_to_smc(rdev, 5525 &state->performance_levels[i], 5526 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5527 } 5528 } 5529 5530 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5531 struct radeon_ps *radeon_boot_state) 5532 { 5533 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5534 struct si_power_info *si_pi = si_get_pi(rdev); 5535 struct si_ulv_param *ulv = &si_pi->ulv; 5536 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5537 5538 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5539 5540 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5541 5542 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5543 5544 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5545 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5546 5547 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5548 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5549 si_pi->mc_reg_table.last, 5550 si_pi->mc_reg_table.valid_flag); 5551 5552 if (ulv->supported && ulv->pl.vddc != 0) 5553 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5554 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5555 else 5556 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5557 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5558 si_pi->mc_reg_table.last, 5559 si_pi->mc_reg_table.valid_flag); 5560 5561 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5562 5563 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5564 (u8 *)smc_mc_reg_table, 5565 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5566 } 5567 5568 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5569 struct radeon_ps *radeon_new_state) 5570 { 5571 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5572 struct si_power_info *si_pi = si_get_pi(rdev); 5573 u32 address = si_pi->mc_reg_table_start + 5574 offsetof(SMC_SIslands_MCRegisters, 5575 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5576 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5577 5578 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5579 5580 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5581 5582 5583 return si_copy_bytes_to_smc(rdev, address, 5584 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5585 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5586 si_pi->sram_end); 5587 5588 } 5589 5590 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5591 { 5592 if (enable) 5593 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5594 else 5595 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5596 } 5597 5598 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5599 struct radeon_ps *radeon_state) 5600 { 5601 struct ni_ps *state = ni_get_ps(radeon_state); 5602 int i; 5603 u16 pcie_speed, max_speed = 0; 5604 5605 for (i = 0; i < state->performance_level_count; i++) { 5606 pcie_speed = state->performance_levels[i].pcie_gen; 5607 if (max_speed < pcie_speed) 5608 max_speed = pcie_speed; 5609 } 5610 return max_speed; 5611 } 5612 5613 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5614 { 5615 u32 speed_cntl; 5616 5617 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5618 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5619 5620 return (u16)speed_cntl; 5621 } 5622 5623 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5624 struct radeon_ps *radeon_new_state, 5625 struct radeon_ps *radeon_current_state) 5626 { 5627 struct si_power_info *si_pi = si_get_pi(rdev); 5628 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5629 enum radeon_pcie_gen current_link_speed; 5630 5631 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5632 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5633 else 5634 current_link_speed = si_pi->force_pcie_gen; 5635 5636 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5637 si_pi->pspp_notify_required = false; 5638 if (target_link_speed > current_link_speed) { 5639 switch (target_link_speed) { 5640 #if defined(CONFIG_ACPI) 5641 case RADEON_PCIE_GEN3: 5642 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5643 break; 5644 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5645 if (current_link_speed == RADEON_PCIE_GEN2) 5646 break; 5647 case RADEON_PCIE_GEN2: 5648 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5649 break; 5650 #endif 5651 default: 5652 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5653 break; 5654 } 5655 } else { 5656 if (target_link_speed < current_link_speed) 5657 si_pi->pspp_notify_required = true; 5658 } 5659 } 5660 5661 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5662 struct radeon_ps *radeon_new_state, 5663 struct radeon_ps *radeon_current_state) 5664 { 5665 struct si_power_info *si_pi = si_get_pi(rdev); 5666 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5667 u8 request; 5668 5669 if (si_pi->pspp_notify_required) { 5670 if (target_link_speed == RADEON_PCIE_GEN3) 5671 request = PCIE_PERF_REQ_PECI_GEN3; 5672 else if (target_link_speed == RADEON_PCIE_GEN2) 5673 request = PCIE_PERF_REQ_PECI_GEN2; 5674 else 5675 request = PCIE_PERF_REQ_PECI_GEN1; 5676 5677 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5678 (si_get_current_pcie_speed(rdev) > 0)) 5679 return; 5680 5681 #if defined(CONFIG_ACPI) 5682 radeon_acpi_pcie_performance_request(rdev, request, false); 5683 #endif 5684 } 5685 } 5686 5687 #if 0 5688 static int si_ds_request(struct radeon_device *rdev, 5689 bool ds_status_on, u32 count_write) 5690 { 5691 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5692 5693 if (eg_pi->sclk_deep_sleep) { 5694 if (ds_status_on) 5695 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5696 PPSMC_Result_OK) ? 5697 0 : -EINVAL; 5698 else 5699 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5700 PPSMC_Result_OK) ? 0 : -EINVAL; 5701 } 5702 return 0; 5703 } 5704 #endif 5705 5706 static void si_set_max_cu_value(struct radeon_device *rdev) 5707 { 5708 struct si_power_info *si_pi = si_get_pi(rdev); 5709 5710 if (rdev->family == CHIP_VERDE) { 5711 switch (rdev->pdev->device) { 5712 case 0x6820: 5713 case 0x6825: 5714 case 0x6821: 5715 case 0x6823: 5716 case 0x6827: 5717 si_pi->max_cu = 10; 5718 break; 5719 case 0x682D: 5720 case 0x6824: 5721 case 0x682F: 5722 case 0x6826: 5723 si_pi->max_cu = 8; 5724 break; 5725 case 0x6828: 5726 case 0x6830: 5727 case 0x6831: 5728 case 0x6838: 5729 case 0x6839: 5730 case 0x683D: 5731 si_pi->max_cu = 10; 5732 break; 5733 case 0x683B: 5734 case 0x683F: 5735 case 0x6829: 5736 si_pi->max_cu = 8; 5737 break; 5738 default: 5739 si_pi->max_cu = 0; 5740 break; 5741 } 5742 } else { 5743 si_pi->max_cu = 0; 5744 } 5745 } 5746 5747 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5748 struct radeon_clock_voltage_dependency_table *table) 5749 { 5750 u32 i; 5751 int j; 5752 u16 leakage_voltage; 5753 5754 if (table) { 5755 for (i = 0; i < table->count; i++) { 5756 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5757 table->entries[i].v, 5758 &leakage_voltage)) { 5759 case 0: 5760 table->entries[i].v = leakage_voltage; 5761 break; 5762 case -EAGAIN: 5763 return -EINVAL; 5764 case -EINVAL: 5765 default: 5766 break; 5767 } 5768 } 5769 5770 for (j = (table->count - 2); j >= 0; j--) { 5771 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5772 table->entries[j].v : table->entries[j + 1].v; 5773 } 5774 } 5775 return 0; 5776 } 5777 5778 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5779 { 5780 int ret = 0; 5781 5782 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5783 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5784 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5785 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5786 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5787 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5788 return ret; 5789 } 5790 5791 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5792 struct radeon_ps *radeon_new_state, 5793 struct radeon_ps *radeon_current_state) 5794 { 5795 u32 lane_width; 5796 u32 new_lane_width = 5797 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5798 u32 current_lane_width = 5799 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5800 5801 if (new_lane_width != current_lane_width) { 5802 radeon_set_pcie_lanes(rdev, new_lane_width); 5803 lane_width = radeon_get_pcie_lanes(rdev); 5804 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5805 } 5806 } 5807 5808 void si_dpm_setup_asic(struct radeon_device *rdev) 5809 { 5810 int r; 5811 5812 r = si_mc_load_microcode(rdev); 5813 if (r) 5814 DRM_ERROR("Failed to load MC firmware!\n"); 5815 rv770_get_memory_type(rdev); 5816 si_read_clock_registers(rdev); 5817 si_enable_acpi_power_management(rdev); 5818 } 5819 5820 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5821 int min_temp, int max_temp) 5822 { 5823 int low_temp = 0 * 1000; 5824 int high_temp = 255 * 1000; 5825 5826 if (low_temp < min_temp) 5827 low_temp = min_temp; 5828 if (high_temp > max_temp) 5829 high_temp = max_temp; 5830 if (high_temp < low_temp) { 5831 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5832 return -EINVAL; 5833 } 5834 5835 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5836 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5837 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5838 5839 rdev->pm.dpm.thermal.min_temp = low_temp; 5840 rdev->pm.dpm.thermal.max_temp = high_temp; 5841 5842 return 0; 5843 } 5844 5845 int si_dpm_enable(struct radeon_device *rdev) 5846 { 5847 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5848 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5849 struct si_power_info *si_pi = si_get_pi(rdev); 5850 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5851 int ret; 5852 5853 if (si_is_smc_running(rdev)) 5854 return -EINVAL; 5855 if (pi->voltage_control || si_pi->voltage_control_svi2) 5856 si_enable_voltage_control(rdev, true); 5857 if (pi->mvdd_control) 5858 si_get_mvdd_configuration(rdev); 5859 if (pi->voltage_control || si_pi->voltage_control_svi2) { 5860 ret = si_construct_voltage_tables(rdev); 5861 if (ret) { 5862 DRM_ERROR("si_construct_voltage_tables failed\n"); 5863 return ret; 5864 } 5865 } 5866 if (eg_pi->dynamic_ac_timing) { 5867 ret = si_initialize_mc_reg_table(rdev); 5868 if (ret) 5869 eg_pi->dynamic_ac_timing = false; 5870 } 5871 if (pi->dynamic_ss) 5872 si_enable_spread_spectrum(rdev, true); 5873 if (pi->thermal_protection) 5874 si_enable_thermal_protection(rdev, true); 5875 si_setup_bsp(rdev); 5876 si_program_git(rdev); 5877 si_program_tp(rdev); 5878 si_program_tpp(rdev); 5879 si_program_sstp(rdev); 5880 si_enable_display_gap(rdev); 5881 si_program_vc(rdev); 5882 ret = si_upload_firmware(rdev); 5883 if (ret) { 5884 DRM_ERROR("si_upload_firmware failed\n"); 5885 return ret; 5886 } 5887 ret = si_process_firmware_header(rdev); 5888 if (ret) { 5889 DRM_ERROR("si_process_firmware_header failed\n"); 5890 return ret; 5891 } 5892 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5893 if (ret) { 5894 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5895 return ret; 5896 } 5897 ret = si_init_smc_table(rdev); 5898 if (ret) { 5899 DRM_ERROR("si_init_smc_table failed\n"); 5900 return ret; 5901 } 5902 ret = si_init_smc_spll_table(rdev); 5903 if (ret) { 5904 DRM_ERROR("si_init_smc_spll_table failed\n"); 5905 return ret; 5906 } 5907 ret = si_init_arb_table_index(rdev); 5908 if (ret) { 5909 DRM_ERROR("si_init_arb_table_index failed\n"); 5910 return ret; 5911 } 5912 if (eg_pi->dynamic_ac_timing) { 5913 ret = si_populate_mc_reg_table(rdev, boot_ps); 5914 if (ret) { 5915 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5916 return ret; 5917 } 5918 } 5919 ret = si_initialize_smc_cac_tables(rdev); 5920 if (ret) { 5921 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5922 return ret; 5923 } 5924 ret = si_initialize_hardware_cac_manager(rdev); 5925 if (ret) { 5926 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5927 return ret; 5928 } 5929 ret = si_initialize_smc_dte_tables(rdev); 5930 if (ret) { 5931 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5932 return ret; 5933 } 5934 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5935 if (ret) { 5936 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5937 return ret; 5938 } 5939 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5940 if (ret) { 5941 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5942 return ret; 5943 } 5944 si_program_response_times(rdev); 5945 si_program_ds_registers(rdev); 5946 si_dpm_start_smc(rdev); 5947 ret = si_notify_smc_display_change(rdev, false); 5948 if (ret) { 5949 DRM_ERROR("si_notify_smc_display_change failed\n"); 5950 return ret; 5951 } 5952 si_enable_sclk_control(rdev, true); 5953 si_start_dpm(rdev); 5954 5955 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5956 5957 ni_update_current_ps(rdev, boot_ps); 5958 5959 return 0; 5960 } 5961 5962 int si_dpm_late_enable(struct radeon_device *rdev) 5963 { 5964 int ret; 5965 5966 if (rdev->irq.installed && 5967 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5968 PPSMC_Result result; 5969 5970 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5971 if (ret) 5972 return ret; 5973 rdev->irq.dpm_thermal = true; 5974 radeon_irq_set(rdev); 5975 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5976 5977 if (result != PPSMC_Result_OK) 5978 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5979 } 5980 5981 return 0; 5982 } 5983 5984 void si_dpm_disable(struct radeon_device *rdev) 5985 { 5986 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5987 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5988 5989 if (!si_is_smc_running(rdev)) 5990 return; 5991 si_disable_ulv(rdev); 5992 si_clear_vc(rdev); 5993 if (pi->thermal_protection) 5994 si_enable_thermal_protection(rdev, false); 5995 si_enable_power_containment(rdev, boot_ps, false); 5996 si_enable_smc_cac(rdev, boot_ps, false); 5997 si_enable_spread_spectrum(rdev, false); 5998 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5999 si_stop_dpm(rdev); 6000 si_reset_to_default(rdev); 6001 si_dpm_stop_smc(rdev); 6002 si_force_switch_to_arb_f0(rdev); 6003 6004 ni_update_current_ps(rdev, boot_ps); 6005 } 6006 6007 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6008 { 6009 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6010 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6011 struct radeon_ps *new_ps = &requested_ps; 6012 6013 ni_update_requested_ps(rdev, new_ps); 6014 6015 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6016 6017 return 0; 6018 } 6019 6020 static int si_power_control_set_level(struct radeon_device *rdev) 6021 { 6022 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6023 int ret; 6024 6025 ret = si_restrict_performance_levels_before_switch(rdev); 6026 if (ret) 6027 return ret; 6028 ret = si_halt_smc(rdev); 6029 if (ret) 6030 return ret; 6031 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6032 if (ret) 6033 return ret; 6034 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6035 if (ret) 6036 return ret; 6037 ret = si_resume_smc(rdev); 6038 if (ret) 6039 return ret; 6040 ret = si_set_sw_state(rdev); 6041 if (ret) 6042 return ret; 6043 return 0; 6044 } 6045 6046 int si_dpm_set_power_state(struct radeon_device *rdev) 6047 { 6048 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6049 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6050 struct radeon_ps *old_ps = &eg_pi->current_rps; 6051 int ret; 6052 6053 ret = si_disable_ulv(rdev); 6054 if (ret) { 6055 DRM_ERROR("si_disable_ulv failed\n"); 6056 return ret; 6057 } 6058 ret = si_restrict_performance_levels_before_switch(rdev); 6059 if (ret) { 6060 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6061 return ret; 6062 } 6063 if (eg_pi->pcie_performance_request) 6064 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6065 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6066 ret = si_enable_power_containment(rdev, new_ps, false); 6067 if (ret) { 6068 DRM_ERROR("si_enable_power_containment failed\n"); 6069 return ret; 6070 } 6071 ret = si_enable_smc_cac(rdev, new_ps, false); 6072 if (ret) { 6073 DRM_ERROR("si_enable_smc_cac failed\n"); 6074 return ret; 6075 } 6076 ret = si_halt_smc(rdev); 6077 if (ret) { 6078 DRM_ERROR("si_halt_smc failed\n"); 6079 return ret; 6080 } 6081 ret = si_upload_sw_state(rdev, new_ps); 6082 if (ret) { 6083 DRM_ERROR("si_upload_sw_state failed\n"); 6084 return ret; 6085 } 6086 ret = si_upload_smc_data(rdev); 6087 if (ret) { 6088 DRM_ERROR("si_upload_smc_data failed\n"); 6089 return ret; 6090 } 6091 ret = si_upload_ulv_state(rdev); 6092 if (ret) { 6093 DRM_ERROR("si_upload_ulv_state failed\n"); 6094 return ret; 6095 } 6096 if (eg_pi->dynamic_ac_timing) { 6097 ret = si_upload_mc_reg_table(rdev, new_ps); 6098 if (ret) { 6099 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6100 return ret; 6101 } 6102 } 6103 ret = si_program_memory_timing_parameters(rdev, new_ps); 6104 if (ret) { 6105 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6106 return ret; 6107 } 6108 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6109 6110 ret = si_resume_smc(rdev); 6111 if (ret) { 6112 DRM_ERROR("si_resume_smc failed\n"); 6113 return ret; 6114 } 6115 ret = si_set_sw_state(rdev); 6116 if (ret) { 6117 DRM_ERROR("si_set_sw_state failed\n"); 6118 return ret; 6119 } 6120 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6121 if (eg_pi->pcie_performance_request) 6122 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6123 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6124 if (ret) { 6125 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6126 return ret; 6127 } 6128 ret = si_enable_smc_cac(rdev, new_ps, true); 6129 if (ret) { 6130 DRM_ERROR("si_enable_smc_cac failed\n"); 6131 return ret; 6132 } 6133 ret = si_enable_power_containment(rdev, new_ps, true); 6134 if (ret) { 6135 DRM_ERROR("si_enable_power_containment failed\n"); 6136 return ret; 6137 } 6138 6139 ret = si_power_control_set_level(rdev); 6140 if (ret) { 6141 DRM_ERROR("si_power_control_set_level failed\n"); 6142 return ret; 6143 } 6144 6145 return 0; 6146 } 6147 6148 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6149 { 6150 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6151 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6152 6153 ni_update_current_ps(rdev, new_ps); 6154 } 6155 6156 #if 0 6157 void si_dpm_reset_asic(struct radeon_device *rdev) 6158 { 6159 si_restrict_performance_levels_before_switch(rdev); 6160 si_disable_ulv(rdev); 6161 si_set_boot_state(rdev); 6162 } 6163 #endif 6164 6165 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6166 { 6167 si_program_display_gap(rdev); 6168 } 6169 6170 union power_info { 6171 struct _ATOM_POWERPLAY_INFO info; 6172 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6173 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6174 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6175 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6176 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6177 }; 6178 6179 union pplib_clock_info { 6180 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6181 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6182 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6183 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6184 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6185 }; 6186 6187 union pplib_power_state { 6188 struct _ATOM_PPLIB_STATE v1; 6189 struct _ATOM_PPLIB_STATE_V2 v2; 6190 }; 6191 6192 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6193 struct radeon_ps *rps, 6194 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6195 u8 table_rev) 6196 { 6197 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6198 rps->class = le16_to_cpu(non_clock_info->usClassification); 6199 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6200 6201 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6202 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6203 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6204 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6205 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6206 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6207 } else { 6208 rps->vclk = 0; 6209 rps->dclk = 0; 6210 } 6211 6212 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6213 rdev->pm.dpm.boot_ps = rps; 6214 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6215 rdev->pm.dpm.uvd_ps = rps; 6216 } 6217 6218 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6219 struct radeon_ps *rps, int index, 6220 union pplib_clock_info *clock_info) 6221 { 6222 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6223 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6224 struct si_power_info *si_pi = si_get_pi(rdev); 6225 struct ni_ps *ps = ni_get_ps(rps); 6226 u16 leakage_voltage; 6227 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6228 int ret; 6229 6230 ps->performance_level_count = index + 1; 6231 6232 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6233 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6234 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6235 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6236 6237 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6238 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6239 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6240 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6241 si_pi->sys_pcie_mask, 6242 si_pi->boot_pcie_gen, 6243 clock_info->si.ucPCIEGen); 6244 6245 /* patch up vddc if necessary */ 6246 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6247 &leakage_voltage); 6248 if (ret == 0) 6249 pl->vddc = leakage_voltage; 6250 6251 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6252 pi->acpi_vddc = pl->vddc; 6253 eg_pi->acpi_vddci = pl->vddci; 6254 si_pi->acpi_pcie_gen = pl->pcie_gen; 6255 } 6256 6257 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6258 index == 0) { 6259 /* XXX disable for A0 tahiti */ 6260 si_pi->ulv.supported = false; 6261 si_pi->ulv.pl = *pl; 6262 si_pi->ulv.one_pcie_lane_in_ulv = false; 6263 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6264 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6265 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6266 } 6267 6268 if (pi->min_vddc_in_table > pl->vddc) 6269 pi->min_vddc_in_table = pl->vddc; 6270 6271 if (pi->max_vddc_in_table < pl->vddc) 6272 pi->max_vddc_in_table = pl->vddc; 6273 6274 /* patch up boot state */ 6275 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6276 u16 vddc, vddci, mvdd; 6277 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6278 pl->mclk = rdev->clock.default_mclk; 6279 pl->sclk = rdev->clock.default_sclk; 6280 pl->vddc = vddc; 6281 pl->vddci = vddci; 6282 si_pi->mvdd_bootup_value = mvdd; 6283 } 6284 6285 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6286 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6287 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6288 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6289 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6290 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6291 } 6292 } 6293 6294 static int si_parse_power_table(struct radeon_device *rdev) 6295 { 6296 struct radeon_mode_info *mode_info = &rdev->mode_info; 6297 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6298 union pplib_power_state *power_state; 6299 int i, j, k, non_clock_array_index, clock_array_index; 6300 union pplib_clock_info *clock_info; 6301 struct _StateArray *state_array; 6302 struct _ClockInfoArray *clock_info_array; 6303 struct _NonClockInfoArray *non_clock_info_array; 6304 union power_info *power_info; 6305 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6306 u16 data_offset; 6307 u8 frev, crev; 6308 u8 *power_state_offset; 6309 struct ni_ps *ps; 6310 6311 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6312 &frev, &crev, &data_offset)) 6313 return -EINVAL; 6314 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6315 6316 state_array = (struct _StateArray *) 6317 (mode_info->atom_context->bios + data_offset + 6318 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6319 clock_info_array = (struct _ClockInfoArray *) 6320 (mode_info->atom_context->bios + data_offset + 6321 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6322 non_clock_info_array = (struct _NonClockInfoArray *) 6323 (mode_info->atom_context->bios + data_offset + 6324 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6325 6326 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6327 state_array->ucNumEntries, GFP_KERNEL); 6328 if (!rdev->pm.dpm.ps) 6329 return -ENOMEM; 6330 power_state_offset = (u8 *)state_array->states; 6331 for (i = 0; i < state_array->ucNumEntries; i++) { 6332 u8 *idx; 6333 power_state = (union pplib_power_state *)power_state_offset; 6334 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6335 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6336 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6337 if (!rdev->pm.power_state[i].clock_info) 6338 return -EINVAL; 6339 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6340 if (ps == NULL) { 6341 kfree(rdev->pm.dpm.ps); 6342 return -ENOMEM; 6343 } 6344 rdev->pm.dpm.ps[i].ps_priv = ps; 6345 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6346 non_clock_info, 6347 non_clock_info_array->ucEntrySize); 6348 k = 0; 6349 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6350 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6351 clock_array_index = idx[j]; 6352 if (clock_array_index >= clock_info_array->ucNumEntries) 6353 continue; 6354 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6355 break; 6356 clock_info = (union pplib_clock_info *) 6357 ((u8 *)&clock_info_array->clockInfo[0] + 6358 (clock_array_index * clock_info_array->ucEntrySize)); 6359 si_parse_pplib_clock_info(rdev, 6360 &rdev->pm.dpm.ps[i], k, 6361 clock_info); 6362 k++; 6363 } 6364 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6365 } 6366 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6367 return 0; 6368 } 6369 6370 int si_dpm_init(struct radeon_device *rdev) 6371 { 6372 struct rv7xx_power_info *pi; 6373 struct evergreen_power_info *eg_pi; 6374 struct ni_power_info *ni_pi; 6375 struct si_power_info *si_pi; 6376 struct atom_clock_dividers dividers; 6377 int ret; 6378 u32 mask; 6379 6380 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6381 if (si_pi == NULL) 6382 return -ENOMEM; 6383 rdev->pm.dpm.priv = si_pi; 6384 ni_pi = &si_pi->ni; 6385 eg_pi = &ni_pi->eg; 6386 pi = &eg_pi->rv7xx; 6387 6388 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6389 if (ret) 6390 si_pi->sys_pcie_mask = 0; 6391 else 6392 si_pi->sys_pcie_mask = mask; 6393 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6394 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6395 6396 si_set_max_cu_value(rdev); 6397 6398 rv770_get_max_vddc(rdev); 6399 si_get_leakage_vddc(rdev); 6400 si_patch_dependency_tables_based_on_leakage(rdev); 6401 6402 pi->acpi_vddc = 0; 6403 eg_pi->acpi_vddci = 0; 6404 pi->min_vddc_in_table = 0; 6405 pi->max_vddc_in_table = 0; 6406 6407 ret = r600_get_platform_caps(rdev); 6408 if (ret) 6409 return ret; 6410 6411 ret = si_parse_power_table(rdev); 6412 if (ret) 6413 return ret; 6414 ret = r600_parse_extended_power_table(rdev); 6415 if (ret) 6416 return ret; 6417 6418 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6419 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6420 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6421 r600_free_extended_power_table(rdev); 6422 return -ENOMEM; 6423 } 6424 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6425 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6426 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6427 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6428 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6429 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6430 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6431 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6432 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6433 6434 if (rdev->pm.dpm.voltage_response_time == 0) 6435 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6436 if (rdev->pm.dpm.backbias_response_time == 0) 6437 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6438 6439 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6440 0, false, ÷rs); 6441 if (ret) 6442 pi->ref_div = dividers.ref_div + 1; 6443 else 6444 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6445 6446 eg_pi->smu_uvd_hs = false; 6447 6448 pi->mclk_strobe_mode_threshold = 40000; 6449 if (si_is_special_1gb_platform(rdev)) 6450 pi->mclk_stutter_mode_threshold = 0; 6451 else 6452 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6453 pi->mclk_edc_enable_threshold = 40000; 6454 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6455 6456 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6457 6458 pi->voltage_control = 6459 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6460 VOLTAGE_OBJ_GPIO_LUT); 6461 if (!pi->voltage_control) { 6462 si_pi->voltage_control_svi2 = 6463 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6464 VOLTAGE_OBJ_SVID2); 6465 if (si_pi->voltage_control_svi2) 6466 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6467 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6468 } 6469 6470 pi->mvdd_control = 6471 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6472 VOLTAGE_OBJ_GPIO_LUT); 6473 6474 eg_pi->vddci_control = 6475 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6476 VOLTAGE_OBJ_GPIO_LUT); 6477 if (!eg_pi->vddci_control) 6478 si_pi->vddci_control_svi2 = 6479 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6480 VOLTAGE_OBJ_SVID2); 6481 6482 si_pi->vddc_phase_shed_control = 6483 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6484 VOLTAGE_OBJ_PHASE_LUT); 6485 6486 rv770_get_engine_memory_ss(rdev); 6487 6488 pi->asi = RV770_ASI_DFLT; 6489 pi->pasi = CYPRESS_HASI_DFLT; 6490 pi->vrc = SISLANDS_VRC_DFLT; 6491 6492 pi->gfx_clock_gating = true; 6493 6494 eg_pi->sclk_deep_sleep = true; 6495 si_pi->sclk_deep_sleep_above_low = false; 6496 6497 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6498 pi->thermal_protection = true; 6499 else 6500 pi->thermal_protection = false; 6501 6502 eg_pi->dynamic_ac_timing = true; 6503 6504 eg_pi->light_sleep = true; 6505 #if defined(CONFIG_ACPI) 6506 eg_pi->pcie_performance_request = 6507 radeon_acpi_is_pcie_performance_request_supported(rdev); 6508 #else 6509 eg_pi->pcie_performance_request = false; 6510 #endif 6511 6512 si_pi->sram_end = SMC_RAM_END; 6513 6514 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6515 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6516 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6517 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6518 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6519 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6520 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6521 6522 si_initialize_powertune_defaults(rdev); 6523 6524 /* make sure dc limits are valid */ 6525 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6526 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6527 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6528 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6529 6530 return 0; 6531 } 6532 6533 void si_dpm_fini(struct radeon_device *rdev) 6534 { 6535 int i; 6536 6537 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6538 kfree(rdev->pm.dpm.ps[i].ps_priv); 6539 } 6540 kfree(rdev->pm.dpm.ps); 6541 kfree(rdev->pm.dpm.priv); 6542 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6543 r600_free_extended_power_table(rdev); 6544 } 6545 6546 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6547 struct seq_file *m) 6548 { 6549 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6550 struct radeon_ps *rps = &eg_pi->current_rps; 6551 struct ni_ps *ps = ni_get_ps(rps); 6552 struct rv7xx_pl *pl; 6553 u32 current_index = 6554 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6555 CURRENT_STATE_INDEX_SHIFT; 6556 6557 if (current_index >= ps->performance_level_count) { 6558 seq_printf(m, "invalid dpm profile %d\n", current_index); 6559 } else { 6560 pl = &ps->performance_levels[current_index]; 6561 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6562 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6563 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6564 } 6565 } 6566