1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 #if 0 /* unused */ 255 static const struct si_dte_data dte_data_tahiti_le = 256 { 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271 }; 272 #endif 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1745 1746 static int si_populate_voltage_value(struct radeon_device *rdev, 1747 const struct atom_voltage_table *table, 1748 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1749 static int si_get_std_voltage_value(struct radeon_device *rdev, 1750 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1751 u16 *std_voltage); 1752 static int si_write_smc_soft_register(struct radeon_device *rdev, 1753 u16 reg_offset, u32 value); 1754 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1755 struct rv7xx_pl *pl, 1756 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1757 static int si_calculate_sclk_params(struct radeon_device *rdev, 1758 u32 engine_clock, 1759 SISLANDS_SMC_SCLK_VALUE *sclk); 1760 1761 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1762 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1763 1764 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1765 { 1766 struct si_power_info *pi = rdev->pm.dpm.priv; 1767 1768 return pi; 1769 } 1770 1771 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1772 u16 v, s32 t, u32 ileakage, u32 *leakage) 1773 { 1774 s64 kt, kv, leakage_w, i_leakage, vddc; 1775 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1776 s64 tmp; 1777 1778 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1779 vddc = div64_s64(drm_int2fixp(v), 1000); 1780 temperature = div64_s64(drm_int2fixp(t), 1000); 1781 1782 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1783 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1784 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1785 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1786 t_ref = drm_int2fixp(coeff->t_ref); 1787 1788 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1789 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1790 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1791 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1792 1793 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1794 1795 *leakage = drm_fixp2int(leakage_w * 1000); 1796 } 1797 1798 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1799 const struct ni_leakage_coeffients *coeff, 1800 u16 v, 1801 s32 t, 1802 u32 i_leakage, 1803 u32 *leakage) 1804 { 1805 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1806 } 1807 1808 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1809 const u32 fixed_kt, u16 v, 1810 u32 ileakage, u32 *leakage) 1811 { 1812 s64 kt, kv, leakage_w, i_leakage, vddc; 1813 1814 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1815 vddc = div64_s64(drm_int2fixp(v), 1000); 1816 1817 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1818 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1819 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1820 1821 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1822 1823 *leakage = drm_fixp2int(leakage_w * 1000); 1824 } 1825 1826 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1827 const struct ni_leakage_coeffients *coeff, 1828 const u32 fixed_kt, 1829 u16 v, 1830 u32 i_leakage, 1831 u32 *leakage) 1832 { 1833 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1834 } 1835 1836 1837 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1838 struct si_dte_data *dte_data) 1839 { 1840 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1841 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1842 u32 k = dte_data->k; 1843 u32 t_max = dte_data->max_t; 1844 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1845 u32 t_0 = dte_data->t0; 1846 u32 i; 1847 1848 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1849 dte_data->tdep_count = 3; 1850 1851 for (i = 0; i < k; i++) { 1852 dte_data->r[i] = 1853 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1854 (p_limit2 * (u32)100); 1855 } 1856 1857 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1858 1859 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1860 dte_data->tdep_r[i] = dte_data->r[4]; 1861 } 1862 } else { 1863 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1864 } 1865 } 1866 1867 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1868 { 1869 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1870 struct si_power_info *si_pi = si_get_pi(rdev); 1871 bool update_dte_from_pl2 = false; 1872 1873 if (rdev->family == CHIP_TAHITI) { 1874 si_pi->cac_weights = cac_weights_tahiti; 1875 si_pi->lcac_config = lcac_tahiti; 1876 si_pi->cac_override = cac_override_tahiti; 1877 si_pi->powertune_data = &powertune_data_tahiti; 1878 si_pi->dte_data = dte_data_tahiti; 1879 1880 switch (rdev->pdev->device) { 1881 case 0x6798: 1882 si_pi->dte_data.enable_dte_by_default = true; 1883 break; 1884 case 0x6799: 1885 si_pi->dte_data = dte_data_new_zealand; 1886 break; 1887 case 0x6790: 1888 case 0x6791: 1889 case 0x6792: 1890 case 0x679E: 1891 si_pi->dte_data = dte_data_aruba_pro; 1892 update_dte_from_pl2 = true; 1893 break; 1894 case 0x679B: 1895 si_pi->dte_data = dte_data_malta; 1896 update_dte_from_pl2 = true; 1897 break; 1898 case 0x679A: 1899 si_pi->dte_data = dte_data_tahiti_pro; 1900 update_dte_from_pl2 = true; 1901 break; 1902 default: 1903 if (si_pi->dte_data.enable_dte_by_default == true) 1904 DRM_ERROR("DTE is not enabled!\n"); 1905 break; 1906 } 1907 } else if (rdev->family == CHIP_PITCAIRN) { 1908 switch (rdev->pdev->device) { 1909 case 0x6810: 1910 case 0x6818: 1911 si_pi->cac_weights = cac_weights_pitcairn; 1912 si_pi->lcac_config = lcac_pitcairn; 1913 si_pi->cac_override = cac_override_pitcairn; 1914 si_pi->powertune_data = &powertune_data_pitcairn; 1915 si_pi->dte_data = dte_data_curacao_xt; 1916 update_dte_from_pl2 = true; 1917 break; 1918 case 0x6819: 1919 case 0x6811: 1920 si_pi->cac_weights = cac_weights_pitcairn; 1921 si_pi->lcac_config = lcac_pitcairn; 1922 si_pi->cac_override = cac_override_pitcairn; 1923 si_pi->powertune_data = &powertune_data_pitcairn; 1924 si_pi->dte_data = dte_data_curacao_pro; 1925 update_dte_from_pl2 = true; 1926 break; 1927 case 0x6800: 1928 case 0x6806: 1929 si_pi->cac_weights = cac_weights_pitcairn; 1930 si_pi->lcac_config = lcac_pitcairn; 1931 si_pi->cac_override = cac_override_pitcairn; 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1933 si_pi->dte_data = dte_data_neptune_xt; 1934 update_dte_from_pl2 = true; 1935 break; 1936 default: 1937 si_pi->cac_weights = cac_weights_pitcairn; 1938 si_pi->lcac_config = lcac_pitcairn; 1939 si_pi->cac_override = cac_override_pitcairn; 1940 si_pi->powertune_data = &powertune_data_pitcairn; 1941 si_pi->dte_data = dte_data_pitcairn; 1942 break; 1943 } 1944 } else if (rdev->family == CHIP_VERDE) { 1945 si_pi->lcac_config = lcac_cape_verde; 1946 si_pi->cac_override = cac_override_cape_verde; 1947 si_pi->powertune_data = &powertune_data_cape_verde; 1948 1949 switch (rdev->pdev->device) { 1950 case 0x683B: 1951 case 0x683F: 1952 case 0x6829: 1953 case 0x6835: 1954 si_pi->cac_weights = cac_weights_cape_verde_pro; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x682C: 1958 si_pi->cac_weights = cac_weights_cape_verde_pro; 1959 si_pi->dte_data = dte_data_sun_xt; 1960 break; 1961 case 0x6825: 1962 case 0x6827: 1963 si_pi->cac_weights = cac_weights_heathrow; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x6824: 1967 case 0x682D: 1968 si_pi->cac_weights = cac_weights_chelsea_xt; 1969 si_pi->dte_data = dte_data_cape_verde; 1970 break; 1971 case 0x682F: 1972 si_pi->cac_weights = cac_weights_chelsea_pro; 1973 si_pi->dte_data = dte_data_cape_verde; 1974 break; 1975 case 0x6820: 1976 si_pi->cac_weights = cac_weights_heathrow; 1977 si_pi->dte_data = dte_data_venus_xtx; 1978 break; 1979 case 0x6821: 1980 si_pi->cac_weights = cac_weights_heathrow; 1981 si_pi->dte_data = dte_data_venus_xt; 1982 break; 1983 case 0x6823: 1984 case 0x682B: 1985 case 0x6822: 1986 case 0x682A: 1987 si_pi->cac_weights = cac_weights_chelsea_pro; 1988 si_pi->dte_data = dte_data_venus_pro; 1989 break; 1990 default: 1991 si_pi->cac_weights = cac_weights_cape_verde; 1992 si_pi->dte_data = dte_data_cape_verde; 1993 break; 1994 } 1995 } else if (rdev->family == CHIP_OLAND) { 1996 switch (rdev->pdev->device) { 1997 case 0x6601: 1998 case 0x6621: 1999 case 0x6603: 2000 case 0x6605: 2001 si_pi->cac_weights = cac_weights_mars_pro; 2002 si_pi->lcac_config = lcac_mars_pro; 2003 si_pi->cac_override = cac_override_oland; 2004 si_pi->powertune_data = &powertune_data_mars_pro; 2005 si_pi->dte_data = dte_data_mars_pro; 2006 update_dte_from_pl2 = true; 2007 break; 2008 case 0x6600: 2009 case 0x6606: 2010 case 0x6620: 2011 case 0x6604: 2012 si_pi->cac_weights = cac_weights_mars_xt; 2013 si_pi->lcac_config = lcac_mars_pro; 2014 si_pi->cac_override = cac_override_oland; 2015 si_pi->powertune_data = &powertune_data_mars_pro; 2016 si_pi->dte_data = dte_data_mars_pro; 2017 update_dte_from_pl2 = true; 2018 break; 2019 case 0x6611: 2020 case 0x6613: 2021 case 0x6608: 2022 si_pi->cac_weights = cac_weights_oland_pro; 2023 si_pi->lcac_config = lcac_mars_pro; 2024 si_pi->cac_override = cac_override_oland; 2025 si_pi->powertune_data = &powertune_data_mars_pro; 2026 si_pi->dte_data = dte_data_mars_pro; 2027 update_dte_from_pl2 = true; 2028 break; 2029 case 0x6610: 2030 si_pi->cac_weights = cac_weights_oland_xt; 2031 si_pi->lcac_config = lcac_mars_pro; 2032 si_pi->cac_override = cac_override_oland; 2033 si_pi->powertune_data = &powertune_data_mars_pro; 2034 si_pi->dte_data = dte_data_mars_pro; 2035 update_dte_from_pl2 = true; 2036 break; 2037 default: 2038 si_pi->cac_weights = cac_weights_oland; 2039 si_pi->lcac_config = lcac_oland; 2040 si_pi->cac_override = cac_override_oland; 2041 si_pi->powertune_data = &powertune_data_oland; 2042 si_pi->dte_data = dte_data_oland; 2043 break; 2044 } 2045 } else if (rdev->family == CHIP_HAINAN) { 2046 si_pi->cac_weights = cac_weights_hainan; 2047 si_pi->lcac_config = lcac_oland; 2048 si_pi->cac_override = cac_override_oland; 2049 si_pi->powertune_data = &powertune_data_hainan; 2050 si_pi->dte_data = dte_data_sun_xt; 2051 update_dte_from_pl2 = true; 2052 } else { 2053 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2054 return; 2055 } 2056 2057 ni_pi->enable_power_containment = false; 2058 ni_pi->enable_cac = false; 2059 ni_pi->enable_sq_ramping = false; 2060 si_pi->enable_dte = false; 2061 2062 if (si_pi->powertune_data->enable_powertune_by_default) { 2063 ni_pi->enable_power_containment= true; 2064 ni_pi->enable_cac = true; 2065 if (si_pi->dte_data.enable_dte_by_default) { 2066 si_pi->enable_dte = true; 2067 if (update_dte_from_pl2) 2068 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2069 2070 } 2071 ni_pi->enable_sq_ramping = true; 2072 } 2073 2074 ni_pi->driver_calculate_cac_leakage = true; 2075 ni_pi->cac_configuration_required = true; 2076 2077 if (ni_pi->cac_configuration_required) { 2078 ni_pi->support_cac_long_term_average = true; 2079 si_pi->dyn_powertune_data.l2_lta_window_size = 2080 si_pi->powertune_data->l2_lta_window_size_default; 2081 si_pi->dyn_powertune_data.lts_truncate = 2082 si_pi->powertune_data->lts_truncate_default; 2083 } else { 2084 ni_pi->support_cac_long_term_average = false; 2085 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2086 si_pi->dyn_powertune_data.lts_truncate = 0; 2087 } 2088 2089 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2090 } 2091 2092 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2093 { 2094 return 1; 2095 } 2096 2097 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2098 { 2099 u32 xclk; 2100 u32 wintime; 2101 u32 cac_window; 2102 u32 cac_window_size; 2103 2104 xclk = radeon_get_xclk(rdev); 2105 2106 if (xclk == 0) 2107 return 0; 2108 2109 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2110 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2111 2112 wintime = (cac_window_size * 100) / xclk; 2113 2114 return wintime; 2115 } 2116 2117 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2118 { 2119 return power_in_watts; 2120 } 2121 2122 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2123 bool adjust_polarity, 2124 u32 tdp_adjustment, 2125 u32 *tdp_limit, 2126 u32 *near_tdp_limit) 2127 { 2128 u32 adjustment_delta, max_tdp_limit; 2129 2130 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2131 return -EINVAL; 2132 2133 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2134 2135 if (adjust_polarity) { 2136 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2138 } else { 2139 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2140 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2141 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2142 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2143 else 2144 *near_tdp_limit = 0; 2145 } 2146 2147 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2148 return -EINVAL; 2149 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2150 return -EINVAL; 2151 2152 return 0; 2153 } 2154 2155 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2156 struct radeon_ps *radeon_state) 2157 { 2158 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2159 struct si_power_info *si_pi = si_get_pi(rdev); 2160 2161 if (ni_pi->enable_power_containment) { 2162 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2163 PP_SIslands_PAPMParameters *papm_parm; 2164 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2165 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2166 u32 tdp_limit; 2167 u32 near_tdp_limit; 2168 int ret; 2169 2170 if (scaling_factor == 0) 2171 return -EINVAL; 2172 2173 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2174 2175 ret = si_calculate_adjusted_tdp_limits(rdev, 2176 false, /* ??? */ 2177 rdev->pm.dpm.tdp_adjustment, 2178 &tdp_limit, 2179 &near_tdp_limit); 2180 if (ret) 2181 return ret; 2182 2183 smc_table->dpm2Params.TDPLimit = 2184 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2185 smc_table->dpm2Params.NearTDPLimit = 2186 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2187 smc_table->dpm2Params.SafePowerLimit = 2188 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2189 2190 ret = si_copy_bytes_to_smc(rdev, 2191 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2192 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2193 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2194 sizeof(u32) * 3, 2195 si_pi->sram_end); 2196 if (ret) 2197 return ret; 2198 2199 if (si_pi->enable_ppm) { 2200 papm_parm = &si_pi->papm_parm; 2201 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2202 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2203 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2204 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2205 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2206 papm_parm->PlatformPowerLimit = 0xffffffff; 2207 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2208 2209 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2210 (u8 *)papm_parm, 2211 sizeof(PP_SIslands_PAPMParameters), 2212 si_pi->sram_end); 2213 if (ret) 2214 return ret; 2215 } 2216 } 2217 return 0; 2218 } 2219 2220 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2221 struct radeon_ps *radeon_state) 2222 { 2223 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2224 struct si_power_info *si_pi = si_get_pi(rdev); 2225 2226 if (ni_pi->enable_power_containment) { 2227 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2228 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2229 int ret; 2230 2231 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2232 2233 smc_table->dpm2Params.NearTDPLimit = 2234 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2235 smc_table->dpm2Params.SafePowerLimit = 2236 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2237 2238 ret = si_copy_bytes_to_smc(rdev, 2239 (si_pi->state_table_start + 2240 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2241 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2242 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2243 sizeof(u32) * 2, 2244 si_pi->sram_end); 2245 if (ret) 2246 return ret; 2247 } 2248 2249 return 0; 2250 } 2251 2252 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2253 const u16 prev_std_vddc, 2254 const u16 curr_std_vddc) 2255 { 2256 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2257 u64 prev_vddc = (u64)prev_std_vddc; 2258 u64 curr_vddc = (u64)curr_std_vddc; 2259 u64 pwr_efficiency_ratio, n, d; 2260 2261 if ((prev_vddc == 0) || (curr_vddc == 0)) 2262 return 0; 2263 2264 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2265 d = prev_vddc * prev_vddc; 2266 pwr_efficiency_ratio = div64_u64(n, d); 2267 2268 if (pwr_efficiency_ratio > (u64)0xFFFF) 2269 return 0; 2270 2271 return (u16)pwr_efficiency_ratio; 2272 } 2273 2274 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2275 struct radeon_ps *radeon_state) 2276 { 2277 struct si_power_info *si_pi = si_get_pi(rdev); 2278 2279 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2280 radeon_state->vclk && radeon_state->dclk) 2281 return true; 2282 2283 return false; 2284 } 2285 2286 static int si_populate_power_containment_values(struct radeon_device *rdev, 2287 struct radeon_ps *radeon_state, 2288 SISLANDS_SMC_SWSTATE *smc_state) 2289 { 2290 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2291 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2292 struct ni_ps *state = ni_get_ps(radeon_state); 2293 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2294 u32 prev_sclk; 2295 u32 max_sclk; 2296 u32 min_sclk; 2297 u16 prev_std_vddc; 2298 u16 curr_std_vddc; 2299 int i; 2300 u16 pwr_efficiency_ratio; 2301 u8 max_ps_percent; 2302 bool disable_uvd_power_tune; 2303 int ret; 2304 2305 if (ni_pi->enable_power_containment == false) 2306 return 0; 2307 2308 if (state->performance_level_count == 0) 2309 return -EINVAL; 2310 2311 if (smc_state->levelCount != state->performance_level_count) 2312 return -EINVAL; 2313 2314 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2315 2316 smc_state->levels[0].dpm2.MaxPS = 0; 2317 smc_state->levels[0].dpm2.NearTDPDec = 0; 2318 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2319 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2320 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2321 2322 for (i = 1; i < state->performance_level_count; i++) { 2323 prev_sclk = state->performance_levels[i-1].sclk; 2324 max_sclk = state->performance_levels[i].sclk; 2325 if (i == 1) 2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2327 else 2328 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2329 2330 if (prev_sclk > max_sclk) 2331 return -EINVAL; 2332 2333 if ((max_ps_percent == 0) || 2334 (prev_sclk == max_sclk) || 2335 disable_uvd_power_tune) { 2336 min_sclk = max_sclk; 2337 } else if (i == 1) { 2338 min_sclk = prev_sclk; 2339 } else { 2340 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2341 } 2342 2343 if (min_sclk < state->performance_levels[0].sclk) 2344 min_sclk = state->performance_levels[0].sclk; 2345 2346 if (min_sclk == 0) 2347 return -EINVAL; 2348 2349 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2350 state->performance_levels[i-1].vddc, &vddc); 2351 if (ret) 2352 return ret; 2353 2354 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2359 state->performance_levels[i].vddc, &vddc); 2360 if (ret) 2361 return ret; 2362 2363 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2364 if (ret) 2365 return ret; 2366 2367 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2368 prev_std_vddc, curr_std_vddc); 2369 2370 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2371 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2372 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2373 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2374 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2375 } 2376 2377 return 0; 2378 } 2379 2380 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2381 struct radeon_ps *radeon_state, 2382 SISLANDS_SMC_SWSTATE *smc_state) 2383 { 2384 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2385 struct ni_ps *state = ni_get_ps(radeon_state); 2386 u32 sq_power_throttle, sq_power_throttle2; 2387 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2388 int i; 2389 2390 if (state->performance_level_count == 0) 2391 return -EINVAL; 2392 2393 if (smc_state->levelCount != state->performance_level_count) 2394 return -EINVAL; 2395 2396 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2397 return -EINVAL; 2398 2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2403 enable_sq_ramping = false; 2404 2405 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2406 enable_sq_ramping = false; 2407 2408 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2409 enable_sq_ramping = false; 2410 2411 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2412 enable_sq_ramping = false; 2413 2414 for (i = 0; i < state->performance_level_count; i++) { 2415 sq_power_throttle = 0; 2416 sq_power_throttle2 = 0; 2417 2418 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2419 enable_sq_ramping) { 2420 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2421 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2422 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2423 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2424 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2425 } else { 2426 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2427 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2428 } 2429 2430 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2431 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2432 } 2433 2434 return 0; 2435 } 2436 2437 static int si_enable_power_containment(struct radeon_device *rdev, 2438 struct radeon_ps *radeon_new_state, 2439 bool enable) 2440 { 2441 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2442 PPSMC_Result smc_result; 2443 int ret = 0; 2444 2445 if (ni_pi->enable_power_containment) { 2446 if (enable) { 2447 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2448 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2449 if (smc_result != PPSMC_Result_OK) { 2450 ret = -EINVAL; 2451 ni_pi->pc_enabled = false; 2452 } else { 2453 ni_pi->pc_enabled = true; 2454 } 2455 } 2456 } else { 2457 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2458 if (smc_result != PPSMC_Result_OK) 2459 ret = -EINVAL; 2460 ni_pi->pc_enabled = false; 2461 } 2462 } 2463 2464 return ret; 2465 } 2466 2467 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2468 { 2469 struct si_power_info *si_pi = si_get_pi(rdev); 2470 int ret = 0; 2471 struct si_dte_data *dte_data = &si_pi->dte_data; 2472 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2473 u32 table_size; 2474 u8 tdep_count; 2475 u32 i; 2476 2477 if (dte_data == NULL) 2478 si_pi->enable_dte = false; 2479 2480 if (si_pi->enable_dte == false) 2481 return 0; 2482 2483 if (dte_data->k <= 0) 2484 return -EINVAL; 2485 2486 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2487 if (dte_tables == NULL) { 2488 si_pi->enable_dte = false; 2489 return -ENOMEM; 2490 } 2491 2492 table_size = dte_data->k; 2493 2494 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2495 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2496 2497 tdep_count = dte_data->tdep_count; 2498 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2499 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2500 2501 dte_tables->K = cpu_to_be32(table_size); 2502 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2503 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2504 dte_tables->WindowSize = dte_data->window_size; 2505 dte_tables->temp_select = dte_data->temp_select; 2506 dte_tables->DTE_mode = dte_data->dte_mode; 2507 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2508 2509 if (tdep_count > 0) 2510 table_size--; 2511 2512 for (i = 0; i < table_size; i++) { 2513 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2514 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2515 } 2516 2517 dte_tables->Tdep_count = tdep_count; 2518 2519 for (i = 0; i < (u32)tdep_count; i++) { 2520 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2521 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2522 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2523 } 2524 2525 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2526 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2527 kfree(dte_tables); 2528 2529 return ret; 2530 } 2531 2532 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2533 u16 *max, u16 *min) 2534 { 2535 struct si_power_info *si_pi = si_get_pi(rdev); 2536 struct radeon_cac_leakage_table *table = 2537 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2538 u32 i; 2539 u32 v0_loadline; 2540 2541 2542 if (table == NULL) 2543 return -EINVAL; 2544 2545 *max = 0; 2546 *min = 0xFFFF; 2547 2548 for (i = 0; i < table->count; i++) { 2549 if (table->entries[i].vddc > *max) 2550 *max = table->entries[i].vddc; 2551 if (table->entries[i].vddc < *min) 2552 *min = table->entries[i].vddc; 2553 } 2554 2555 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2556 return -EINVAL; 2557 2558 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2559 2560 if (v0_loadline > 0xFFFFUL) 2561 return -EINVAL; 2562 2563 *min = (u16)v0_loadline; 2564 2565 if ((*min > *max) || (*max == 0) || (*min == 0)) 2566 return -EINVAL; 2567 2568 return 0; 2569 } 2570 2571 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2572 { 2573 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2574 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2575 } 2576 2577 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2578 PP_SIslands_CacConfig *cac_tables, 2579 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2580 u16 t0, u16 t_step) 2581 { 2582 struct si_power_info *si_pi = si_get_pi(rdev); 2583 u32 leakage; 2584 unsigned int i, j; 2585 s32 t; 2586 u32 smc_leakage; 2587 u32 scaling_factor; 2588 u16 voltage; 2589 2590 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2591 2592 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2593 t = (1000 * (i * t_step + t0)); 2594 2595 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2596 voltage = vddc_max - (vddc_step * j); 2597 2598 si_calculate_leakage_for_v_and_t(rdev, 2599 &si_pi->powertune_data->leakage_coefficients, 2600 voltage, 2601 t, 2602 si_pi->dyn_powertune_data.cac_leakage, 2603 &leakage); 2604 2605 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2606 2607 if (smc_leakage > 0xFFFF) 2608 smc_leakage = 0xFFFF; 2609 2610 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2611 cpu_to_be16((u16)smc_leakage); 2612 } 2613 } 2614 return 0; 2615 } 2616 2617 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2618 PP_SIslands_CacConfig *cac_tables, 2619 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2620 { 2621 struct si_power_info *si_pi = si_get_pi(rdev); 2622 u32 leakage; 2623 unsigned int i, j; 2624 u32 smc_leakage; 2625 u32 scaling_factor; 2626 u16 voltage; 2627 2628 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2629 2630 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2631 voltage = vddc_max - (vddc_step * j); 2632 2633 si_calculate_leakage_for_v(rdev, 2634 &si_pi->powertune_data->leakage_coefficients, 2635 si_pi->powertune_data->fixed_kt, 2636 voltage, 2637 si_pi->dyn_powertune_data.cac_leakage, 2638 &leakage); 2639 2640 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2641 2642 if (smc_leakage > 0xFFFF) 2643 smc_leakage = 0xFFFF; 2644 2645 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2646 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2647 cpu_to_be16((u16)smc_leakage); 2648 } 2649 return 0; 2650 } 2651 2652 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2653 { 2654 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2655 struct si_power_info *si_pi = si_get_pi(rdev); 2656 PP_SIslands_CacConfig *cac_tables = NULL; 2657 u16 vddc_max, vddc_min, vddc_step; 2658 u16 t0, t_step; 2659 u32 load_line_slope, reg; 2660 int ret = 0; 2661 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2662 2663 if (ni_pi->enable_cac == false) 2664 return 0; 2665 2666 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2667 if (!cac_tables) 2668 return -ENOMEM; 2669 2670 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2671 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2672 WREG32(CG_CAC_CTRL, reg); 2673 2674 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2675 si_pi->dyn_powertune_data.dc_pwr_value = 2676 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2677 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2678 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2679 2680 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2681 2682 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2683 if (ret) 2684 goto done_free; 2685 2686 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2687 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2688 t_step = 4; 2689 t0 = 60; 2690 2691 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2692 ret = si_init_dte_leakage_table(rdev, cac_tables, 2693 vddc_max, vddc_min, vddc_step, 2694 t0, t_step); 2695 else 2696 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2697 vddc_max, vddc_min, vddc_step); 2698 if (ret) 2699 goto done_free; 2700 2701 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2702 2703 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2704 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2705 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2706 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2707 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2708 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2709 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2710 cac_tables->calculation_repeats = cpu_to_be32(2); 2711 cac_tables->dc_cac = cpu_to_be32(0); 2712 cac_tables->log2_PG_LKG_SCALE = 12; 2713 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2714 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2715 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2716 2717 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2718 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2719 2720 if (ret) 2721 goto done_free; 2722 2723 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2724 2725 done_free: 2726 if (ret) { 2727 ni_pi->enable_cac = false; 2728 ni_pi->enable_power_containment = false; 2729 } 2730 2731 kfree(cac_tables); 2732 2733 return 0; 2734 } 2735 2736 static int si_program_cac_config_registers(struct radeon_device *rdev, 2737 const struct si_cac_config_reg *cac_config_regs) 2738 { 2739 const struct si_cac_config_reg *config_regs = cac_config_regs; 2740 u32 data = 0, offset; 2741 2742 if (!config_regs) 2743 return -EINVAL; 2744 2745 while (config_regs->offset != 0xFFFFFFFF) { 2746 switch (config_regs->type) { 2747 case SISLANDS_CACCONFIG_CGIND: 2748 offset = SMC_CG_IND_START + config_regs->offset; 2749 if (offset < SMC_CG_IND_END) 2750 data = RREG32_SMC(offset); 2751 break; 2752 default: 2753 data = RREG32(config_regs->offset << 2); 2754 break; 2755 } 2756 2757 data &= ~config_regs->mask; 2758 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2759 2760 switch (config_regs->type) { 2761 case SISLANDS_CACCONFIG_CGIND: 2762 offset = SMC_CG_IND_START + config_regs->offset; 2763 if (offset < SMC_CG_IND_END) 2764 WREG32_SMC(offset, data); 2765 break; 2766 default: 2767 WREG32(config_regs->offset << 2, data); 2768 break; 2769 } 2770 config_regs++; 2771 } 2772 return 0; 2773 } 2774 2775 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2776 { 2777 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2778 struct si_power_info *si_pi = si_get_pi(rdev); 2779 int ret; 2780 2781 if ((ni_pi->enable_cac == false) || 2782 (ni_pi->cac_configuration_required == false)) 2783 return 0; 2784 2785 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2786 if (ret) 2787 return ret; 2788 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2789 if (ret) 2790 return ret; 2791 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2792 if (ret) 2793 return ret; 2794 2795 return 0; 2796 } 2797 2798 static int si_enable_smc_cac(struct radeon_device *rdev, 2799 struct radeon_ps *radeon_new_state, 2800 bool enable) 2801 { 2802 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2803 struct si_power_info *si_pi = si_get_pi(rdev); 2804 PPSMC_Result smc_result; 2805 int ret = 0; 2806 2807 if (ni_pi->enable_cac) { 2808 if (enable) { 2809 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2810 if (ni_pi->support_cac_long_term_average) { 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2812 if (smc_result != PPSMC_Result_OK) 2813 ni_pi->support_cac_long_term_average = false; 2814 } 2815 2816 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2817 if (smc_result != PPSMC_Result_OK) { 2818 ret = -EINVAL; 2819 ni_pi->cac_enabled = false; 2820 } else { 2821 ni_pi->cac_enabled = true; 2822 } 2823 2824 if (si_pi->enable_dte) { 2825 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2826 if (smc_result != PPSMC_Result_OK) 2827 ret = -EINVAL; 2828 } 2829 } 2830 } else if (ni_pi->cac_enabled) { 2831 if (si_pi->enable_dte) 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2833 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2835 2836 ni_pi->cac_enabled = false; 2837 2838 if (ni_pi->support_cac_long_term_average) 2839 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2840 } 2841 } 2842 return ret; 2843 } 2844 2845 static int si_init_smc_spll_table(struct radeon_device *rdev) 2846 { 2847 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2848 struct si_power_info *si_pi = si_get_pi(rdev); 2849 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2850 SISLANDS_SMC_SCLK_VALUE sclk_params; 2851 u32 fb_div, p_div; 2852 u32 clk_s, clk_v; 2853 u32 sclk = 0; 2854 int ret = 0; 2855 u32 tmp; 2856 int i; 2857 2858 if (si_pi->spll_table_start == 0) 2859 return -EINVAL; 2860 2861 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2862 if (spll_table == NULL) 2863 return -ENOMEM; 2864 2865 for (i = 0; i < 256; i++) { 2866 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2867 if (ret) 2868 break; 2869 2870 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2871 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2872 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2873 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2874 2875 fb_div &= ~0x00001FFF; 2876 fb_div >>= 1; 2877 clk_v >>= 6; 2878 2879 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2880 ret = -EINVAL; 2881 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2882 ret = -EINVAL; 2883 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2884 ret = -EINVAL; 2885 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2886 ret = -EINVAL; 2887 2888 if (ret) 2889 break; 2890 2891 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2892 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2893 spll_table->freq[i] = cpu_to_be32(tmp); 2894 2895 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2896 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2897 spll_table->ss[i] = cpu_to_be32(tmp); 2898 2899 sclk += 512; 2900 } 2901 2902 2903 if (!ret) 2904 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2905 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2906 si_pi->sram_end); 2907 2908 if (ret) 2909 ni_pi->enable_power_containment = false; 2910 2911 kfree(spll_table); 2912 2913 return ret; 2914 } 2915 2916 struct si_dpm_quirk { 2917 u32 chip_vendor; 2918 u32 chip_device; 2919 u32 subsys_vendor; 2920 u32 subsys_device; 2921 u32 max_sclk; 2922 u32 max_mclk; 2923 }; 2924 2925 /* cards with dpm stability problems */ 2926 static struct si_dpm_quirk si_dpm_quirk_list[] = { 2927 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 2928 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2929 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 2930 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 }, 2931 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, 2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 2934 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, 2935 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, 2936 { 0, 0, 0, 0 }, 2937 }; 2938 2939 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2940 u16 vce_voltage) 2941 { 2942 u16 highest_leakage = 0; 2943 struct si_power_info *si_pi = si_get_pi(rdev); 2944 int i; 2945 2946 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2947 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2948 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2949 } 2950 2951 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2952 return highest_leakage; 2953 2954 return vce_voltage; 2955 } 2956 2957 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2958 u32 evclk, u32 ecclk, u16 *voltage) 2959 { 2960 u32 i; 2961 int ret = -EINVAL; 2962 struct radeon_vce_clock_voltage_dependency_table *table = 2963 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2964 2965 if (((evclk == 0) && (ecclk == 0)) || 2966 (table && (table->count == 0))) { 2967 *voltage = 0; 2968 return 0; 2969 } 2970 2971 for (i = 0; i < table->count; i++) { 2972 if ((evclk <= table->entries[i].evclk) && 2973 (ecclk <= table->entries[i].ecclk)) { 2974 *voltage = table->entries[i].v; 2975 ret = 0; 2976 break; 2977 } 2978 } 2979 2980 /* if no match return the highest voltage */ 2981 if (ret) 2982 *voltage = table->entries[table->count - 1].v; 2983 2984 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2985 2986 return ret; 2987 } 2988 2989 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2990 struct radeon_ps *rps) 2991 { 2992 struct ni_ps *ps = ni_get_ps(rps); 2993 struct radeon_clock_and_voltage_limits *max_limits; 2994 bool disable_mclk_switching = false; 2995 bool disable_sclk_switching = false; 2996 u32 mclk, sclk; 2997 u16 vddc, vddci, min_vce_voltage = 0; 2998 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2999 u32 max_sclk = 0, max_mclk = 0; 3000 int i; 3001 struct si_dpm_quirk *p = si_dpm_quirk_list; 3002 3003 /* limit all SI kickers */ 3004 if (rdev->family == CHIP_PITCAIRN) { 3005 if ((rdev->pdev->revision == 0x81) || 3006 (rdev->pdev->device == 0x6810) || 3007 (rdev->pdev->device == 0x6811) || 3008 (rdev->pdev->device == 0x6816) || 3009 (rdev->pdev->device == 0x6817) || 3010 (rdev->pdev->device == 0x6806)) 3011 max_mclk = 120000; 3012 } else if (rdev->family == CHIP_HAINAN) { 3013 if ((rdev->pdev->revision == 0x81) || 3014 (rdev->pdev->revision == 0x83) || 3015 (rdev->pdev->revision == 0xC3) || 3016 (rdev->pdev->device == 0x6664) || 3017 (rdev->pdev->device == 0x6665) || 3018 (rdev->pdev->device == 0x6667)) { 3019 max_sclk = 75000; 3020 } 3021 } 3022 /* Apply dpm quirks */ 3023 while (p && p->chip_device != 0) { 3024 if (rdev->pdev->vendor == p->chip_vendor && 3025 rdev->pdev->device == p->chip_device && 3026 rdev->pdev->subsystem_vendor == p->subsys_vendor && 3027 rdev->pdev->subsystem_device == p->subsys_device) { 3028 max_sclk = p->max_sclk; 3029 max_mclk = p->max_mclk; 3030 break; 3031 } 3032 ++p; 3033 } 3034 3035 if (rps->vce_active) { 3036 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3037 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3038 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3039 &min_vce_voltage); 3040 } else { 3041 rps->evclk = 0; 3042 rps->ecclk = 0; 3043 } 3044 3045 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3046 ni_dpm_vblank_too_short(rdev)) 3047 disable_mclk_switching = true; 3048 3049 if (rps->vclk || rps->dclk) { 3050 disable_mclk_switching = true; 3051 disable_sclk_switching = true; 3052 } 3053 3054 if (rdev->pm.dpm.ac_power) 3055 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3056 else 3057 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3058 3059 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3060 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3061 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3062 } 3063 if (rdev->pm.dpm.ac_power == false) { 3064 for (i = 0; i < ps->performance_level_count; i++) { 3065 if (ps->performance_levels[i].mclk > max_limits->mclk) 3066 ps->performance_levels[i].mclk = max_limits->mclk; 3067 if (ps->performance_levels[i].sclk > max_limits->sclk) 3068 ps->performance_levels[i].sclk = max_limits->sclk; 3069 if (ps->performance_levels[i].vddc > max_limits->vddc) 3070 ps->performance_levels[i].vddc = max_limits->vddc; 3071 if (ps->performance_levels[i].vddci > max_limits->vddci) 3072 ps->performance_levels[i].vddci = max_limits->vddci; 3073 } 3074 } 3075 3076 /* limit clocks to max supported clocks based on voltage dependency tables */ 3077 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3078 &max_sclk_vddc); 3079 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3080 &max_mclk_vddci); 3081 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3082 &max_mclk_vddc); 3083 3084 for (i = 0; i < ps->performance_level_count; i++) { 3085 if (max_sclk_vddc) { 3086 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3087 ps->performance_levels[i].sclk = max_sclk_vddc; 3088 } 3089 if (max_mclk_vddci) { 3090 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3091 ps->performance_levels[i].mclk = max_mclk_vddci; 3092 } 3093 if (max_mclk_vddc) { 3094 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3095 ps->performance_levels[i].mclk = max_mclk_vddc; 3096 } 3097 if (max_mclk) { 3098 if (ps->performance_levels[i].mclk > max_mclk) 3099 ps->performance_levels[i].mclk = max_mclk; 3100 } 3101 if (max_sclk) { 3102 if (ps->performance_levels[i].sclk > max_sclk) 3103 ps->performance_levels[i].sclk = max_sclk; 3104 } 3105 } 3106 3107 /* XXX validate the min clocks required for display */ 3108 3109 if (disable_mclk_switching) { 3110 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3111 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3112 } else { 3113 mclk = ps->performance_levels[0].mclk; 3114 vddci = ps->performance_levels[0].vddci; 3115 } 3116 3117 if (disable_sclk_switching) { 3118 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3119 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3120 } else { 3121 sclk = ps->performance_levels[0].sclk; 3122 vddc = ps->performance_levels[0].vddc; 3123 } 3124 3125 if (rps->vce_active) { 3126 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3127 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3128 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3129 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3130 } 3131 3132 /* adjusted low state */ 3133 ps->performance_levels[0].sclk = sclk; 3134 ps->performance_levels[0].mclk = mclk; 3135 ps->performance_levels[0].vddc = vddc; 3136 ps->performance_levels[0].vddci = vddci; 3137 3138 if (disable_sclk_switching) { 3139 sclk = ps->performance_levels[0].sclk; 3140 for (i = 1; i < ps->performance_level_count; i++) { 3141 if (sclk < ps->performance_levels[i].sclk) 3142 sclk = ps->performance_levels[i].sclk; 3143 } 3144 for (i = 0; i < ps->performance_level_count; i++) { 3145 ps->performance_levels[i].sclk = sclk; 3146 ps->performance_levels[i].vddc = vddc; 3147 } 3148 } else { 3149 for (i = 1; i < ps->performance_level_count; i++) { 3150 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3151 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3152 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3153 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3154 } 3155 } 3156 3157 if (disable_mclk_switching) { 3158 mclk = ps->performance_levels[0].mclk; 3159 for (i = 1; i < ps->performance_level_count; i++) { 3160 if (mclk < ps->performance_levels[i].mclk) 3161 mclk = ps->performance_levels[i].mclk; 3162 } 3163 for (i = 0; i < ps->performance_level_count; i++) { 3164 ps->performance_levels[i].mclk = mclk; 3165 ps->performance_levels[i].vddci = vddci; 3166 } 3167 } else { 3168 for (i = 1; i < ps->performance_level_count; i++) { 3169 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3170 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3171 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3172 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3173 } 3174 } 3175 3176 for (i = 0; i < ps->performance_level_count; i++) 3177 btc_adjust_clock_combinations(rdev, max_limits, 3178 &ps->performance_levels[i]); 3179 3180 for (i = 0; i < ps->performance_level_count; i++) { 3181 if (ps->performance_levels[i].vddc < min_vce_voltage) 3182 ps->performance_levels[i].vddc = min_vce_voltage; 3183 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3184 ps->performance_levels[i].sclk, 3185 max_limits->vddc, &ps->performance_levels[i].vddc); 3186 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3187 ps->performance_levels[i].mclk, 3188 max_limits->vddci, &ps->performance_levels[i].vddci); 3189 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3190 ps->performance_levels[i].mclk, 3191 max_limits->vddc, &ps->performance_levels[i].vddc); 3192 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3193 rdev->clock.current_dispclk, 3194 max_limits->vddc, &ps->performance_levels[i].vddc); 3195 } 3196 3197 for (i = 0; i < ps->performance_level_count; i++) { 3198 btc_apply_voltage_delta_rules(rdev, 3199 max_limits->vddc, max_limits->vddci, 3200 &ps->performance_levels[i].vddc, 3201 &ps->performance_levels[i].vddci); 3202 } 3203 3204 ps->dc_compatible = true; 3205 for (i = 0; i < ps->performance_level_count; i++) { 3206 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3207 ps->dc_compatible = false; 3208 } 3209 } 3210 3211 #if 0 3212 static int si_read_smc_soft_register(struct radeon_device *rdev, 3213 u16 reg_offset, u32 *value) 3214 { 3215 struct si_power_info *si_pi = si_get_pi(rdev); 3216 3217 return si_read_smc_sram_dword(rdev, 3218 si_pi->soft_regs_start + reg_offset, value, 3219 si_pi->sram_end); 3220 } 3221 #endif 3222 3223 static int si_write_smc_soft_register(struct radeon_device *rdev, 3224 u16 reg_offset, u32 value) 3225 { 3226 struct si_power_info *si_pi = si_get_pi(rdev); 3227 3228 return si_write_smc_sram_dword(rdev, 3229 si_pi->soft_regs_start + reg_offset, 3230 value, si_pi->sram_end); 3231 } 3232 3233 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3234 { 3235 bool ret = false; 3236 u32 tmp, width, row, column, bank, density; 3237 bool is_memory_gddr5, is_special; 3238 3239 tmp = RREG32(MC_SEQ_MISC0); 3240 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3241 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3242 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3243 3244 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3245 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3246 3247 tmp = RREG32(MC_ARB_RAMCFG); 3248 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3249 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3250 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3251 3252 density = (1 << (row + column - 20 + bank)) * width; 3253 3254 if ((rdev->pdev->device == 0x6819) && 3255 is_memory_gddr5 && is_special && (density == 0x400)) 3256 ret = true; 3257 3258 return ret; 3259 } 3260 3261 static void si_get_leakage_vddc(struct radeon_device *rdev) 3262 { 3263 struct si_power_info *si_pi = si_get_pi(rdev); 3264 u16 vddc, count = 0; 3265 int i, ret; 3266 3267 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3268 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3269 3270 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3271 si_pi->leakage_voltage.entries[count].voltage = vddc; 3272 si_pi->leakage_voltage.entries[count].leakage_index = 3273 SISLANDS_LEAKAGE_INDEX0 + i; 3274 count++; 3275 } 3276 } 3277 si_pi->leakage_voltage.count = count; 3278 } 3279 3280 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3281 u32 index, u16 *leakage_voltage) 3282 { 3283 struct si_power_info *si_pi = si_get_pi(rdev); 3284 int i; 3285 3286 if (leakage_voltage == NULL) 3287 return -EINVAL; 3288 3289 if ((index & 0xff00) != 0xff00) 3290 return -EINVAL; 3291 3292 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3293 return -EINVAL; 3294 3295 if (index < SISLANDS_LEAKAGE_INDEX0) 3296 return -EINVAL; 3297 3298 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3299 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3300 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3301 return 0; 3302 } 3303 } 3304 return -EAGAIN; 3305 } 3306 3307 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3308 { 3309 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3310 bool want_thermal_protection; 3311 enum radeon_dpm_event_src dpm_event_src; 3312 3313 switch (sources) { 3314 case 0: 3315 default: 3316 want_thermal_protection = false; 3317 break; 3318 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3319 want_thermal_protection = true; 3320 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3321 break; 3322 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3323 want_thermal_protection = true; 3324 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3325 break; 3326 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3327 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3328 want_thermal_protection = true; 3329 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3330 break; 3331 } 3332 3333 if (want_thermal_protection) { 3334 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3335 if (pi->thermal_protection) 3336 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3337 } else { 3338 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3339 } 3340 } 3341 3342 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3343 enum radeon_dpm_auto_throttle_src source, 3344 bool enable) 3345 { 3346 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3347 3348 if (enable) { 3349 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3350 pi->active_auto_throttle_sources |= 1 << source; 3351 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3352 } 3353 } else { 3354 if (pi->active_auto_throttle_sources & (1 << source)) { 3355 pi->active_auto_throttle_sources &= ~(1 << source); 3356 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3357 } 3358 } 3359 } 3360 3361 static void si_start_dpm(struct radeon_device *rdev) 3362 { 3363 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3364 } 3365 3366 static void si_stop_dpm(struct radeon_device *rdev) 3367 { 3368 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3369 } 3370 3371 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3372 { 3373 if (enable) 3374 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3375 else 3376 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3377 3378 } 3379 3380 #if 0 3381 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3382 u32 thermal_level) 3383 { 3384 PPSMC_Result ret; 3385 3386 if (thermal_level == 0) { 3387 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3388 if (ret == PPSMC_Result_OK) 3389 return 0; 3390 else 3391 return -EINVAL; 3392 } 3393 return 0; 3394 } 3395 3396 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3397 { 3398 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3399 } 3400 #endif 3401 3402 #if 0 3403 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3404 { 3405 if (ac_power) 3406 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3407 0 : -EINVAL; 3408 3409 return 0; 3410 } 3411 #endif 3412 3413 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3414 PPSMC_Msg msg, u32 parameter) 3415 { 3416 WREG32(SMC_SCRATCH0, parameter); 3417 return si_send_msg_to_smc(rdev, msg); 3418 } 3419 3420 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3421 { 3422 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3423 return -EINVAL; 3424 3425 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3426 0 : -EINVAL; 3427 } 3428 3429 int si_dpm_force_performance_level(struct radeon_device *rdev, 3430 enum radeon_dpm_forced_level level) 3431 { 3432 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3433 struct ni_ps *ps = ni_get_ps(rps); 3434 u32 levels = ps->performance_level_count; 3435 3436 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3437 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3438 return -EINVAL; 3439 3440 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3441 return -EINVAL; 3442 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3443 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3444 return -EINVAL; 3445 3446 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3447 return -EINVAL; 3448 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3449 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3450 return -EINVAL; 3451 3452 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3453 return -EINVAL; 3454 } 3455 3456 rdev->pm.dpm.forced_level = level; 3457 3458 return 0; 3459 } 3460 3461 #if 0 3462 static int si_set_boot_state(struct radeon_device *rdev) 3463 { 3464 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3465 0 : -EINVAL; 3466 } 3467 #endif 3468 3469 static int si_set_sw_state(struct radeon_device *rdev) 3470 { 3471 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3472 0 : -EINVAL; 3473 } 3474 3475 static int si_halt_smc(struct radeon_device *rdev) 3476 { 3477 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3478 return -EINVAL; 3479 3480 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3481 0 : -EINVAL; 3482 } 3483 3484 static int si_resume_smc(struct radeon_device *rdev) 3485 { 3486 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3487 return -EINVAL; 3488 3489 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3490 0 : -EINVAL; 3491 } 3492 3493 static void si_dpm_start_smc(struct radeon_device *rdev) 3494 { 3495 si_program_jump_on_start(rdev); 3496 si_start_smc(rdev); 3497 si_start_smc_clock(rdev); 3498 } 3499 3500 static void si_dpm_stop_smc(struct radeon_device *rdev) 3501 { 3502 si_reset_smc(rdev); 3503 si_stop_smc_clock(rdev); 3504 } 3505 3506 static int si_process_firmware_header(struct radeon_device *rdev) 3507 { 3508 struct si_power_info *si_pi = si_get_pi(rdev); 3509 u32 tmp; 3510 int ret; 3511 3512 ret = si_read_smc_sram_dword(rdev, 3513 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3514 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3515 &tmp, si_pi->sram_end); 3516 if (ret) 3517 return ret; 3518 3519 si_pi->state_table_start = tmp; 3520 3521 ret = si_read_smc_sram_dword(rdev, 3522 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3523 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3524 &tmp, si_pi->sram_end); 3525 if (ret) 3526 return ret; 3527 3528 si_pi->soft_regs_start = tmp; 3529 3530 ret = si_read_smc_sram_dword(rdev, 3531 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3532 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3533 &tmp, si_pi->sram_end); 3534 if (ret) 3535 return ret; 3536 3537 si_pi->mc_reg_table_start = tmp; 3538 3539 ret = si_read_smc_sram_dword(rdev, 3540 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3541 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3542 &tmp, si_pi->sram_end); 3543 if (ret) 3544 return ret; 3545 3546 si_pi->fan_table_start = tmp; 3547 3548 ret = si_read_smc_sram_dword(rdev, 3549 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3550 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3551 &tmp, si_pi->sram_end); 3552 if (ret) 3553 return ret; 3554 3555 si_pi->arb_table_start = tmp; 3556 3557 ret = si_read_smc_sram_dword(rdev, 3558 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3559 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3560 &tmp, si_pi->sram_end); 3561 if (ret) 3562 return ret; 3563 3564 si_pi->cac_table_start = tmp; 3565 3566 ret = si_read_smc_sram_dword(rdev, 3567 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3568 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3569 &tmp, si_pi->sram_end); 3570 if (ret) 3571 return ret; 3572 3573 si_pi->dte_table_start = tmp; 3574 3575 ret = si_read_smc_sram_dword(rdev, 3576 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3577 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3578 &tmp, si_pi->sram_end); 3579 if (ret) 3580 return ret; 3581 3582 si_pi->spll_table_start = tmp; 3583 3584 ret = si_read_smc_sram_dword(rdev, 3585 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3586 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3587 &tmp, si_pi->sram_end); 3588 if (ret) 3589 return ret; 3590 3591 si_pi->papm_cfg_table_start = tmp; 3592 3593 return ret; 3594 } 3595 3596 static void si_read_clock_registers(struct radeon_device *rdev) 3597 { 3598 struct si_power_info *si_pi = si_get_pi(rdev); 3599 3600 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3601 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3602 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3603 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3604 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3605 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3606 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3607 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3608 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3609 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3610 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3611 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3612 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3613 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3614 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3615 } 3616 3617 static void si_enable_thermal_protection(struct radeon_device *rdev, 3618 bool enable) 3619 { 3620 if (enable) 3621 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3622 else 3623 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3624 } 3625 3626 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3627 { 3628 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3629 } 3630 3631 #if 0 3632 static int si_enter_ulp_state(struct radeon_device *rdev) 3633 { 3634 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3635 3636 udelay(25000); 3637 3638 return 0; 3639 } 3640 3641 static int si_exit_ulp_state(struct radeon_device *rdev) 3642 { 3643 int i; 3644 3645 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3646 3647 udelay(7000); 3648 3649 for (i = 0; i < rdev->usec_timeout; i++) { 3650 if (RREG32(SMC_RESP_0) == 1) 3651 break; 3652 udelay(1000); 3653 } 3654 3655 return 0; 3656 } 3657 #endif 3658 3659 static int si_notify_smc_display_change(struct radeon_device *rdev, 3660 bool has_display) 3661 { 3662 PPSMC_Msg msg = has_display ? 3663 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3664 3665 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3666 0 : -EINVAL; 3667 } 3668 3669 static void si_program_response_times(struct radeon_device *rdev) 3670 { 3671 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3672 u32 vddc_dly, acpi_dly, vbi_dly; 3673 u32 reference_clock; 3674 3675 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3676 3677 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3678 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3679 3680 if (voltage_response_time == 0) 3681 voltage_response_time = 1000; 3682 3683 acpi_delay_time = 15000; 3684 vbi_time_out = 100000; 3685 3686 reference_clock = radeon_get_xclk(rdev); 3687 3688 vddc_dly = (voltage_response_time * reference_clock) / 100; 3689 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3690 vbi_dly = (vbi_time_out * reference_clock) / 100; 3691 3692 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3693 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3694 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3695 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3696 } 3697 3698 static void si_program_ds_registers(struct radeon_device *rdev) 3699 { 3700 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3701 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3702 3703 if (eg_pi->sclk_deep_sleep) { 3704 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3705 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3706 ~AUTOSCALE_ON_SS_CLEAR); 3707 } 3708 } 3709 3710 static void si_program_display_gap(struct radeon_device *rdev) 3711 { 3712 u32 tmp, pipe; 3713 int i; 3714 3715 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3716 if (rdev->pm.dpm.new_active_crtc_count > 0) 3717 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3718 else 3719 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3720 3721 if (rdev->pm.dpm.new_active_crtc_count > 1) 3722 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3723 else 3724 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3725 3726 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3727 3728 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3729 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3730 3731 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3732 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3733 /* find the first active crtc */ 3734 for (i = 0; i < rdev->num_crtc; i++) { 3735 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3736 break; 3737 } 3738 if (i == rdev->num_crtc) 3739 pipe = 0; 3740 else 3741 pipe = i; 3742 3743 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3744 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3745 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3746 } 3747 3748 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3749 * This can be a problem on PowerXpress systems or if you want to use the card 3750 * for offscreen rendering or compute if there are no crtcs enabled. 3751 */ 3752 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3753 } 3754 3755 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3756 { 3757 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3758 3759 if (enable) { 3760 if (pi->sclk_ss) 3761 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3762 } else { 3763 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3764 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3765 } 3766 } 3767 3768 static void si_setup_bsp(struct radeon_device *rdev) 3769 { 3770 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3771 u32 xclk = radeon_get_xclk(rdev); 3772 3773 r600_calculate_u_and_p(pi->asi, 3774 xclk, 3775 16, 3776 &pi->bsp, 3777 &pi->bsu); 3778 3779 r600_calculate_u_and_p(pi->pasi, 3780 xclk, 3781 16, 3782 &pi->pbsp, 3783 &pi->pbsu); 3784 3785 3786 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3787 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3788 3789 WREG32(CG_BSP, pi->dsp); 3790 } 3791 3792 static void si_program_git(struct radeon_device *rdev) 3793 { 3794 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3795 } 3796 3797 static void si_program_tp(struct radeon_device *rdev) 3798 { 3799 int i; 3800 enum r600_td td = R600_TD_DFLT; 3801 3802 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3803 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3804 3805 if (td == R600_TD_AUTO) 3806 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3807 else 3808 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3809 3810 if (td == R600_TD_UP) 3811 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3812 3813 if (td == R600_TD_DOWN) 3814 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3815 } 3816 3817 static void si_program_tpp(struct radeon_device *rdev) 3818 { 3819 WREG32(CG_TPC, R600_TPC_DFLT); 3820 } 3821 3822 static void si_program_sstp(struct radeon_device *rdev) 3823 { 3824 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3825 } 3826 3827 static void si_enable_display_gap(struct radeon_device *rdev) 3828 { 3829 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3830 3831 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3832 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3833 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3834 3835 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3836 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3837 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3838 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3839 } 3840 3841 static void si_program_vc(struct radeon_device *rdev) 3842 { 3843 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3844 3845 WREG32(CG_FTV, pi->vrc); 3846 } 3847 3848 static void si_clear_vc(struct radeon_device *rdev) 3849 { 3850 WREG32(CG_FTV, 0); 3851 } 3852 3853 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3854 { 3855 u8 mc_para_index; 3856 3857 if (memory_clock < 10000) 3858 mc_para_index = 0; 3859 else if (memory_clock >= 80000) 3860 mc_para_index = 0x0f; 3861 else 3862 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3863 return mc_para_index; 3864 } 3865 3866 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3867 { 3868 u8 mc_para_index; 3869 3870 if (strobe_mode) { 3871 if (memory_clock < 12500) 3872 mc_para_index = 0x00; 3873 else if (memory_clock > 47500) 3874 mc_para_index = 0x0f; 3875 else 3876 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3877 } else { 3878 if (memory_clock < 65000) 3879 mc_para_index = 0x00; 3880 else if (memory_clock > 135000) 3881 mc_para_index = 0x0f; 3882 else 3883 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3884 } 3885 return mc_para_index; 3886 } 3887 3888 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3889 { 3890 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3891 bool strobe_mode = false; 3892 u8 result = 0; 3893 3894 if (mclk <= pi->mclk_strobe_mode_threshold) 3895 strobe_mode = true; 3896 3897 if (pi->mem_gddr5) 3898 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3899 else 3900 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3901 3902 if (strobe_mode) 3903 result |= SISLANDS_SMC_STROBE_ENABLE; 3904 3905 return result; 3906 } 3907 3908 static int si_upload_firmware(struct radeon_device *rdev) 3909 { 3910 struct si_power_info *si_pi = si_get_pi(rdev); 3911 int ret; 3912 3913 si_reset_smc(rdev); 3914 si_stop_smc_clock(rdev); 3915 3916 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3917 3918 return ret; 3919 } 3920 3921 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3922 const struct atom_voltage_table *table, 3923 const struct radeon_phase_shedding_limits_table *limits) 3924 { 3925 u32 data, num_bits, num_levels; 3926 3927 if ((table == NULL) || (limits == NULL)) 3928 return false; 3929 3930 data = table->mask_low; 3931 3932 num_bits = hweight32(data); 3933 3934 if (num_bits == 0) 3935 return false; 3936 3937 num_levels = (1 << num_bits); 3938 3939 if (table->count != num_levels) 3940 return false; 3941 3942 if (limits->count != (num_levels - 1)) 3943 return false; 3944 3945 return true; 3946 } 3947 3948 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3949 u32 max_voltage_steps, 3950 struct atom_voltage_table *voltage_table) 3951 { 3952 unsigned int i, diff; 3953 3954 if (voltage_table->count <= max_voltage_steps) 3955 return; 3956 3957 diff = voltage_table->count - max_voltage_steps; 3958 3959 for (i= 0; i < max_voltage_steps; i++) 3960 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3961 3962 voltage_table->count = max_voltage_steps; 3963 } 3964 3965 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3966 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3967 struct atom_voltage_table *voltage_table) 3968 { 3969 u32 i; 3970 3971 if (voltage_dependency_table == NULL) 3972 return -EINVAL; 3973 3974 voltage_table->mask_low = 0; 3975 voltage_table->phase_delay = 0; 3976 3977 voltage_table->count = voltage_dependency_table->count; 3978 for (i = 0; i < voltage_table->count; i++) { 3979 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3980 voltage_table->entries[i].smio_low = 0; 3981 } 3982 3983 return 0; 3984 } 3985 3986 static int si_construct_voltage_tables(struct radeon_device *rdev) 3987 { 3988 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3989 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3990 struct si_power_info *si_pi = si_get_pi(rdev); 3991 int ret; 3992 3993 if (pi->voltage_control) { 3994 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3995 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3996 if (ret) 3997 return ret; 3998 3999 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4000 si_trim_voltage_table_to_fit_state_table(rdev, 4001 SISLANDS_MAX_NO_VREG_STEPS, 4002 &eg_pi->vddc_voltage_table); 4003 } else if (si_pi->voltage_control_svi2) { 4004 ret = si_get_svi2_voltage_table(rdev, 4005 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4006 &eg_pi->vddc_voltage_table); 4007 if (ret) 4008 return ret; 4009 } else { 4010 return -EINVAL; 4011 } 4012 4013 if (eg_pi->vddci_control) { 4014 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 4015 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4016 if (ret) 4017 return ret; 4018 4019 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4020 si_trim_voltage_table_to_fit_state_table(rdev, 4021 SISLANDS_MAX_NO_VREG_STEPS, 4022 &eg_pi->vddci_voltage_table); 4023 } 4024 if (si_pi->vddci_control_svi2) { 4025 ret = si_get_svi2_voltage_table(rdev, 4026 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4027 &eg_pi->vddci_voltage_table); 4028 if (ret) 4029 return ret; 4030 } 4031 4032 if (pi->mvdd_control) { 4033 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4034 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4035 4036 if (ret) { 4037 pi->mvdd_control = false; 4038 return ret; 4039 } 4040 4041 if (si_pi->mvdd_voltage_table.count == 0) { 4042 pi->mvdd_control = false; 4043 return -EINVAL; 4044 } 4045 4046 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4047 si_trim_voltage_table_to_fit_state_table(rdev, 4048 SISLANDS_MAX_NO_VREG_STEPS, 4049 &si_pi->mvdd_voltage_table); 4050 } 4051 4052 if (si_pi->vddc_phase_shed_control) { 4053 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4054 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4055 if (ret) 4056 si_pi->vddc_phase_shed_control = false; 4057 4058 if ((si_pi->vddc_phase_shed_table.count == 0) || 4059 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4060 si_pi->vddc_phase_shed_control = false; 4061 } 4062 4063 return 0; 4064 } 4065 4066 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4067 const struct atom_voltage_table *voltage_table, 4068 SISLANDS_SMC_STATETABLE *table) 4069 { 4070 unsigned int i; 4071 4072 for (i = 0; i < voltage_table->count; i++) 4073 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4074 } 4075 4076 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4077 SISLANDS_SMC_STATETABLE *table) 4078 { 4079 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4080 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4081 struct si_power_info *si_pi = si_get_pi(rdev); 4082 u8 i; 4083 4084 if (si_pi->voltage_control_svi2) { 4085 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4086 si_pi->svc_gpio_id); 4087 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4088 si_pi->svd_gpio_id); 4089 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4090 2); 4091 } else { 4092 if (eg_pi->vddc_voltage_table.count) { 4093 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4094 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4095 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4096 4097 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4098 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4099 table->maxVDDCIndexInPPTable = i; 4100 break; 4101 } 4102 } 4103 } 4104 4105 if (eg_pi->vddci_voltage_table.count) { 4106 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4107 4108 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4109 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4110 } 4111 4112 4113 if (si_pi->mvdd_voltage_table.count) { 4114 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4115 4116 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4117 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4118 } 4119 4120 if (si_pi->vddc_phase_shed_control) { 4121 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4122 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4123 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4124 4125 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4126 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4127 4128 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4129 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4130 } else { 4131 si_pi->vddc_phase_shed_control = false; 4132 } 4133 } 4134 } 4135 4136 return 0; 4137 } 4138 4139 static int si_populate_voltage_value(struct radeon_device *rdev, 4140 const struct atom_voltage_table *table, 4141 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4142 { 4143 unsigned int i; 4144 4145 for (i = 0; i < table->count; i++) { 4146 if (value <= table->entries[i].value) { 4147 voltage->index = (u8)i; 4148 voltage->value = cpu_to_be16(table->entries[i].value); 4149 break; 4150 } 4151 } 4152 4153 if (i >= table->count) 4154 return -EINVAL; 4155 4156 return 0; 4157 } 4158 4159 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4160 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4161 { 4162 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4163 struct si_power_info *si_pi = si_get_pi(rdev); 4164 4165 if (pi->mvdd_control) { 4166 if (mclk <= pi->mvdd_split_frequency) 4167 voltage->index = 0; 4168 else 4169 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4170 4171 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4172 } 4173 return 0; 4174 } 4175 4176 static int si_get_std_voltage_value(struct radeon_device *rdev, 4177 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4178 u16 *std_voltage) 4179 { 4180 u16 v_index; 4181 bool voltage_found = false; 4182 *std_voltage = be16_to_cpu(voltage->value); 4183 4184 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4185 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4186 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4187 return -EINVAL; 4188 4189 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4190 if (be16_to_cpu(voltage->value) == 4191 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4192 voltage_found = true; 4193 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4194 *std_voltage = 4195 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4196 else 4197 *std_voltage = 4198 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4199 break; 4200 } 4201 } 4202 4203 if (!voltage_found) { 4204 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4205 if (be16_to_cpu(voltage->value) <= 4206 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4207 voltage_found = true; 4208 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4209 *std_voltage = 4210 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4211 else 4212 *std_voltage = 4213 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4214 break; 4215 } 4216 } 4217 } 4218 } else { 4219 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4220 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4221 } 4222 } 4223 4224 return 0; 4225 } 4226 4227 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4228 u16 value, u8 index, 4229 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4230 { 4231 voltage->index = index; 4232 voltage->value = cpu_to_be16(value); 4233 4234 return 0; 4235 } 4236 4237 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4238 const struct radeon_phase_shedding_limits_table *limits, 4239 u16 voltage, u32 sclk, u32 mclk, 4240 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4241 { 4242 unsigned int i; 4243 4244 for (i = 0; i < limits->count; i++) { 4245 if ((voltage <= limits->entries[i].voltage) && 4246 (sclk <= limits->entries[i].sclk) && 4247 (mclk <= limits->entries[i].mclk)) 4248 break; 4249 } 4250 4251 smc_voltage->phase_settings = (u8)i; 4252 4253 return 0; 4254 } 4255 4256 static int si_init_arb_table_index(struct radeon_device *rdev) 4257 { 4258 struct si_power_info *si_pi = si_get_pi(rdev); 4259 u32 tmp; 4260 int ret; 4261 4262 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4263 if (ret) 4264 return ret; 4265 4266 tmp &= 0x00FFFFFF; 4267 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4268 4269 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4270 } 4271 4272 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4273 { 4274 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4275 } 4276 4277 static int si_reset_to_default(struct radeon_device *rdev) 4278 { 4279 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4280 0 : -EINVAL; 4281 } 4282 4283 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4284 { 4285 struct si_power_info *si_pi = si_get_pi(rdev); 4286 u32 tmp; 4287 int ret; 4288 4289 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4290 &tmp, si_pi->sram_end); 4291 if (ret) 4292 return ret; 4293 4294 tmp = (tmp >> 24) & 0xff; 4295 4296 if (tmp == MC_CG_ARB_FREQ_F0) 4297 return 0; 4298 4299 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4300 } 4301 4302 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4303 u32 engine_clock) 4304 { 4305 u32 dram_rows; 4306 u32 dram_refresh_rate; 4307 u32 mc_arb_rfsh_rate; 4308 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4309 4310 if (tmp >= 4) 4311 dram_rows = 16384; 4312 else 4313 dram_rows = 1 << (tmp + 10); 4314 4315 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4316 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4317 4318 return mc_arb_rfsh_rate; 4319 } 4320 4321 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4322 struct rv7xx_pl *pl, 4323 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4324 { 4325 u32 dram_timing; 4326 u32 dram_timing2; 4327 u32 burst_time; 4328 4329 arb_regs->mc_arb_rfsh_rate = 4330 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4331 4332 radeon_atom_set_engine_dram_timings(rdev, 4333 pl->sclk, 4334 pl->mclk); 4335 4336 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4337 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4338 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4339 4340 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4341 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4342 arb_regs->mc_arb_burst_time = (u8)burst_time; 4343 4344 return 0; 4345 } 4346 4347 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4348 struct radeon_ps *radeon_state, 4349 unsigned int first_arb_set) 4350 { 4351 struct si_power_info *si_pi = si_get_pi(rdev); 4352 struct ni_ps *state = ni_get_ps(radeon_state); 4353 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4354 int i, ret = 0; 4355 4356 for (i = 0; i < state->performance_level_count; i++) { 4357 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4358 if (ret) 4359 break; 4360 ret = si_copy_bytes_to_smc(rdev, 4361 si_pi->arb_table_start + 4362 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4363 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4364 (u8 *)&arb_regs, 4365 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4366 si_pi->sram_end); 4367 if (ret) 4368 break; 4369 } 4370 4371 return ret; 4372 } 4373 4374 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4375 struct radeon_ps *radeon_new_state) 4376 { 4377 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4378 SISLANDS_DRIVER_STATE_ARB_INDEX); 4379 } 4380 4381 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4382 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4383 { 4384 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4385 struct si_power_info *si_pi = si_get_pi(rdev); 4386 4387 if (pi->mvdd_control) 4388 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4389 si_pi->mvdd_bootup_value, voltage); 4390 4391 return 0; 4392 } 4393 4394 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4395 struct radeon_ps *radeon_initial_state, 4396 SISLANDS_SMC_STATETABLE *table) 4397 { 4398 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4399 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4400 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4401 struct si_power_info *si_pi = si_get_pi(rdev); 4402 u32 reg; 4403 int ret; 4404 4405 table->initialState.levels[0].mclk.vDLL_CNTL = 4406 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4407 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4408 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4409 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4410 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4411 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4412 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4413 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4414 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4415 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4416 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4417 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4418 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4419 table->initialState.levels[0].mclk.vMPLL_SS = 4420 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4421 table->initialState.levels[0].mclk.vMPLL_SS2 = 4422 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4423 4424 table->initialState.levels[0].mclk.mclk_value = 4425 cpu_to_be32(initial_state->performance_levels[0].mclk); 4426 4427 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4428 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4429 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4430 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4431 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4432 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4433 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4434 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4435 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4436 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4437 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4438 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4439 4440 table->initialState.levels[0].sclk.sclk_value = 4441 cpu_to_be32(initial_state->performance_levels[0].sclk); 4442 4443 table->initialState.levels[0].arbRefreshState = 4444 SISLANDS_INITIAL_STATE_ARB_INDEX; 4445 4446 table->initialState.levels[0].ACIndex = 0; 4447 4448 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4449 initial_state->performance_levels[0].vddc, 4450 &table->initialState.levels[0].vddc); 4451 4452 if (!ret) { 4453 u16 std_vddc; 4454 4455 ret = si_get_std_voltage_value(rdev, 4456 &table->initialState.levels[0].vddc, 4457 &std_vddc); 4458 if (!ret) 4459 si_populate_std_voltage_value(rdev, std_vddc, 4460 table->initialState.levels[0].vddc.index, 4461 &table->initialState.levels[0].std_vddc); 4462 } 4463 4464 if (eg_pi->vddci_control) 4465 si_populate_voltage_value(rdev, 4466 &eg_pi->vddci_voltage_table, 4467 initial_state->performance_levels[0].vddci, 4468 &table->initialState.levels[0].vddci); 4469 4470 if (si_pi->vddc_phase_shed_control) 4471 si_populate_phase_shedding_value(rdev, 4472 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4473 initial_state->performance_levels[0].vddc, 4474 initial_state->performance_levels[0].sclk, 4475 initial_state->performance_levels[0].mclk, 4476 &table->initialState.levels[0].vddc); 4477 4478 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4479 4480 reg = CG_R(0xffff) | CG_L(0); 4481 table->initialState.levels[0].aT = cpu_to_be32(reg); 4482 4483 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4484 4485 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4486 4487 if (pi->mem_gddr5) { 4488 table->initialState.levels[0].strobeMode = 4489 si_get_strobe_mode_settings(rdev, 4490 initial_state->performance_levels[0].mclk); 4491 4492 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4493 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4494 else 4495 table->initialState.levels[0].mcFlags = 0; 4496 } 4497 4498 table->initialState.levelCount = 1; 4499 4500 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4501 4502 table->initialState.levels[0].dpm2.MaxPS = 0; 4503 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4504 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4505 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4506 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4507 4508 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4509 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4510 4511 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4512 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4513 4514 return 0; 4515 } 4516 4517 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4518 SISLANDS_SMC_STATETABLE *table) 4519 { 4520 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4521 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4522 struct si_power_info *si_pi = si_get_pi(rdev); 4523 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4524 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4525 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4526 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4527 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4528 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4529 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4530 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4531 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4532 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4533 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4534 u32 reg; 4535 int ret; 4536 4537 table->ACPIState = table->initialState; 4538 4539 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4540 4541 if (pi->acpi_vddc) { 4542 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4543 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4544 if (!ret) { 4545 u16 std_vddc; 4546 4547 ret = si_get_std_voltage_value(rdev, 4548 &table->ACPIState.levels[0].vddc, &std_vddc); 4549 if (!ret) 4550 si_populate_std_voltage_value(rdev, std_vddc, 4551 table->ACPIState.levels[0].vddc.index, 4552 &table->ACPIState.levels[0].std_vddc); 4553 } 4554 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4555 4556 if (si_pi->vddc_phase_shed_control) { 4557 si_populate_phase_shedding_value(rdev, 4558 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4559 pi->acpi_vddc, 4560 0, 4561 0, 4562 &table->ACPIState.levels[0].vddc); 4563 } 4564 } else { 4565 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4566 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4567 if (!ret) { 4568 u16 std_vddc; 4569 4570 ret = si_get_std_voltage_value(rdev, 4571 &table->ACPIState.levels[0].vddc, &std_vddc); 4572 4573 if (!ret) 4574 si_populate_std_voltage_value(rdev, std_vddc, 4575 table->ACPIState.levels[0].vddc.index, 4576 &table->ACPIState.levels[0].std_vddc); 4577 } 4578 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4579 si_pi->sys_pcie_mask, 4580 si_pi->boot_pcie_gen, 4581 RADEON_PCIE_GEN1); 4582 4583 if (si_pi->vddc_phase_shed_control) 4584 si_populate_phase_shedding_value(rdev, 4585 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4586 pi->min_vddc_in_table, 4587 0, 4588 0, 4589 &table->ACPIState.levels[0].vddc); 4590 } 4591 4592 if (pi->acpi_vddc) { 4593 if (eg_pi->acpi_vddci) 4594 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4595 eg_pi->acpi_vddci, 4596 &table->ACPIState.levels[0].vddci); 4597 } 4598 4599 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4600 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4601 4602 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4603 4604 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4605 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4606 4607 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4608 cpu_to_be32(dll_cntl); 4609 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4610 cpu_to_be32(mclk_pwrmgt_cntl); 4611 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4612 cpu_to_be32(mpll_ad_func_cntl); 4613 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4614 cpu_to_be32(mpll_dq_func_cntl); 4615 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4616 cpu_to_be32(mpll_func_cntl); 4617 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4618 cpu_to_be32(mpll_func_cntl_1); 4619 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4620 cpu_to_be32(mpll_func_cntl_2); 4621 table->ACPIState.levels[0].mclk.vMPLL_SS = 4622 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4623 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4624 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4625 4626 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4627 cpu_to_be32(spll_func_cntl); 4628 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4629 cpu_to_be32(spll_func_cntl_2); 4630 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4631 cpu_to_be32(spll_func_cntl_3); 4632 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4633 cpu_to_be32(spll_func_cntl_4); 4634 4635 table->ACPIState.levels[0].mclk.mclk_value = 0; 4636 table->ACPIState.levels[0].sclk.sclk_value = 0; 4637 4638 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4639 4640 if (eg_pi->dynamic_ac_timing) 4641 table->ACPIState.levels[0].ACIndex = 0; 4642 4643 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4644 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4645 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4646 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4647 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4648 4649 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4650 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4651 4652 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4653 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4654 4655 return 0; 4656 } 4657 4658 static int si_populate_ulv_state(struct radeon_device *rdev, 4659 SISLANDS_SMC_SWSTATE *state) 4660 { 4661 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4662 struct si_power_info *si_pi = si_get_pi(rdev); 4663 struct si_ulv_param *ulv = &si_pi->ulv; 4664 u32 sclk_in_sr = 1350; /* ??? */ 4665 int ret; 4666 4667 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4668 &state->levels[0]); 4669 if (!ret) { 4670 if (eg_pi->sclk_deep_sleep) { 4671 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4672 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4673 else 4674 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4675 } 4676 if (ulv->one_pcie_lane_in_ulv) 4677 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4678 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4679 state->levels[0].ACIndex = 1; 4680 state->levels[0].std_vddc = state->levels[0].vddc; 4681 state->levelCount = 1; 4682 4683 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4684 } 4685 4686 return ret; 4687 } 4688 4689 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4690 { 4691 struct si_power_info *si_pi = si_get_pi(rdev); 4692 struct si_ulv_param *ulv = &si_pi->ulv; 4693 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4694 int ret; 4695 4696 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4697 &arb_regs); 4698 if (ret) 4699 return ret; 4700 4701 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4702 ulv->volt_change_delay); 4703 4704 ret = si_copy_bytes_to_smc(rdev, 4705 si_pi->arb_table_start + 4706 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4707 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4708 (u8 *)&arb_regs, 4709 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4710 si_pi->sram_end); 4711 4712 return ret; 4713 } 4714 4715 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4716 { 4717 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4718 4719 pi->mvdd_split_frequency = 30000; 4720 } 4721 4722 static int si_init_smc_table(struct radeon_device *rdev) 4723 { 4724 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4725 struct si_power_info *si_pi = si_get_pi(rdev); 4726 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4727 const struct si_ulv_param *ulv = &si_pi->ulv; 4728 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4729 int ret; 4730 u32 lane_width; 4731 u32 vr_hot_gpio; 4732 4733 si_populate_smc_voltage_tables(rdev, table); 4734 4735 switch (rdev->pm.int_thermal_type) { 4736 case THERMAL_TYPE_SI: 4737 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4738 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4739 break; 4740 case THERMAL_TYPE_NONE: 4741 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4742 break; 4743 default: 4744 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4745 break; 4746 } 4747 4748 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4749 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4750 4751 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4752 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4753 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4754 } 4755 4756 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4757 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4758 4759 if (pi->mem_gddr5) 4760 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4761 4762 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4763 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4764 4765 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4766 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4767 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4768 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4769 vr_hot_gpio); 4770 } 4771 4772 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4773 if (ret) 4774 return ret; 4775 4776 ret = si_populate_smc_acpi_state(rdev, table); 4777 if (ret) 4778 return ret; 4779 4780 table->driverState = table->initialState; 4781 4782 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4783 SISLANDS_INITIAL_STATE_ARB_INDEX); 4784 if (ret) 4785 return ret; 4786 4787 if (ulv->supported && ulv->pl.vddc) { 4788 ret = si_populate_ulv_state(rdev, &table->ULVState); 4789 if (ret) 4790 return ret; 4791 4792 ret = si_program_ulv_memory_timing_parameters(rdev); 4793 if (ret) 4794 return ret; 4795 4796 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4797 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4798 4799 lane_width = radeon_get_pcie_lanes(rdev); 4800 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4801 } else { 4802 table->ULVState = table->initialState; 4803 } 4804 4805 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4806 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4807 si_pi->sram_end); 4808 } 4809 4810 static int si_calculate_sclk_params(struct radeon_device *rdev, 4811 u32 engine_clock, 4812 SISLANDS_SMC_SCLK_VALUE *sclk) 4813 { 4814 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4815 struct si_power_info *si_pi = si_get_pi(rdev); 4816 struct atom_clock_dividers dividers; 4817 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4818 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4819 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4820 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4821 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4822 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4823 u64 tmp; 4824 u32 reference_clock = rdev->clock.spll.reference_freq; 4825 u32 reference_divider; 4826 u32 fbdiv; 4827 int ret; 4828 4829 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4830 engine_clock, false, ÷rs); 4831 if (ret) 4832 return ret; 4833 4834 reference_divider = 1 + dividers.ref_div; 4835 4836 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4837 do_div(tmp, reference_clock); 4838 fbdiv = (u32) tmp; 4839 4840 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4841 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4842 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4843 4844 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4845 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4846 4847 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4848 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4849 spll_func_cntl_3 |= SPLL_DITHEN; 4850 4851 if (pi->sclk_ss) { 4852 struct radeon_atom_ss ss; 4853 u32 vco_freq = engine_clock * dividers.post_div; 4854 4855 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4856 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4857 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4858 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4859 4860 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4861 cg_spll_spread_spectrum |= CLK_S(clk_s); 4862 cg_spll_spread_spectrum |= SSEN; 4863 4864 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4865 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4866 } 4867 } 4868 4869 sclk->sclk_value = engine_clock; 4870 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4871 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4872 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4873 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4874 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4875 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4876 4877 return 0; 4878 } 4879 4880 static int si_populate_sclk_value(struct radeon_device *rdev, 4881 u32 engine_clock, 4882 SISLANDS_SMC_SCLK_VALUE *sclk) 4883 { 4884 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4885 int ret; 4886 4887 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4888 if (!ret) { 4889 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4890 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4891 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4892 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4893 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4894 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4895 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4896 } 4897 4898 return ret; 4899 } 4900 4901 static int si_populate_mclk_value(struct radeon_device *rdev, 4902 u32 engine_clock, 4903 u32 memory_clock, 4904 SISLANDS_SMC_MCLK_VALUE *mclk, 4905 bool strobe_mode, 4906 bool dll_state_on) 4907 { 4908 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4909 struct si_power_info *si_pi = si_get_pi(rdev); 4910 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4911 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4912 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4913 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4914 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4915 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4916 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4917 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4918 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4919 struct atom_mpll_param mpll_param; 4920 int ret; 4921 4922 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4923 if (ret) 4924 return ret; 4925 4926 mpll_func_cntl &= ~BWCTRL_MASK; 4927 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4928 4929 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4930 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4931 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4932 4933 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4934 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4935 4936 if (pi->mem_gddr5) { 4937 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4938 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4939 YCLK_POST_DIV(mpll_param.post_div); 4940 } 4941 4942 if (pi->mclk_ss) { 4943 struct radeon_atom_ss ss; 4944 u32 freq_nom; 4945 u32 tmp; 4946 u32 reference_clock = rdev->clock.mpll.reference_freq; 4947 4948 if (pi->mem_gddr5) 4949 freq_nom = memory_clock * 4; 4950 else 4951 freq_nom = memory_clock * 2; 4952 4953 tmp = freq_nom / reference_clock; 4954 tmp = tmp * tmp; 4955 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4956 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4957 u32 clks = reference_clock * 5 / ss.rate; 4958 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4959 4960 mpll_ss1 &= ~CLKV_MASK; 4961 mpll_ss1 |= CLKV(clkv); 4962 4963 mpll_ss2 &= ~CLKS_MASK; 4964 mpll_ss2 |= CLKS(clks); 4965 } 4966 } 4967 4968 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4969 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4970 4971 if (dll_state_on) 4972 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4973 else 4974 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4975 4976 mclk->mclk_value = cpu_to_be32(memory_clock); 4977 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4978 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4979 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4980 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4981 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4982 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4983 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4984 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4985 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4986 4987 return 0; 4988 } 4989 4990 static void si_populate_smc_sp(struct radeon_device *rdev, 4991 struct radeon_ps *radeon_state, 4992 SISLANDS_SMC_SWSTATE *smc_state) 4993 { 4994 struct ni_ps *ps = ni_get_ps(radeon_state); 4995 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4996 int i; 4997 4998 for (i = 0; i < ps->performance_level_count - 1; i++) 4999 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5000 5001 smc_state->levels[ps->performance_level_count - 1].bSP = 5002 cpu_to_be32(pi->psp); 5003 } 5004 5005 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 5006 struct rv7xx_pl *pl, 5007 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5008 { 5009 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5010 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5011 struct si_power_info *si_pi = si_get_pi(rdev); 5012 int ret; 5013 bool dll_state_on; 5014 u16 std_vddc; 5015 bool gmc_pg = false; 5016 5017 if (eg_pi->pcie_performance_request && 5018 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 5019 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5020 else 5021 level->gen2PCIE = (u8)pl->pcie_gen; 5022 5023 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 5024 if (ret) 5025 return ret; 5026 5027 level->mcFlags = 0; 5028 5029 if (pi->mclk_stutter_mode_threshold && 5030 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5031 !eg_pi->uvd_enabled && 5032 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5033 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5034 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5035 5036 if (gmc_pg) 5037 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5038 } 5039 5040 if (pi->mem_gddr5) { 5041 if (pl->mclk > pi->mclk_edc_enable_threshold) 5042 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5043 5044 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5045 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5046 5047 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5048 5049 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5050 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5051 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5052 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5053 else 5054 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5055 } else { 5056 dll_state_on = false; 5057 } 5058 } else { 5059 level->strobeMode = si_get_strobe_mode_settings(rdev, 5060 pl->mclk); 5061 5062 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5063 } 5064 5065 ret = si_populate_mclk_value(rdev, 5066 pl->sclk, 5067 pl->mclk, 5068 &level->mclk, 5069 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5070 if (ret) 5071 return ret; 5072 5073 ret = si_populate_voltage_value(rdev, 5074 &eg_pi->vddc_voltage_table, 5075 pl->vddc, &level->vddc); 5076 if (ret) 5077 return ret; 5078 5079 5080 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5081 if (ret) 5082 return ret; 5083 5084 ret = si_populate_std_voltage_value(rdev, std_vddc, 5085 level->vddc.index, &level->std_vddc); 5086 if (ret) 5087 return ret; 5088 5089 if (eg_pi->vddci_control) { 5090 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5091 pl->vddci, &level->vddci); 5092 if (ret) 5093 return ret; 5094 } 5095 5096 if (si_pi->vddc_phase_shed_control) { 5097 ret = si_populate_phase_shedding_value(rdev, 5098 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5099 pl->vddc, 5100 pl->sclk, 5101 pl->mclk, 5102 &level->vddc); 5103 if (ret) 5104 return ret; 5105 } 5106 5107 level->MaxPoweredUpCU = si_pi->max_cu; 5108 5109 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5110 5111 return ret; 5112 } 5113 5114 static int si_populate_smc_t(struct radeon_device *rdev, 5115 struct radeon_ps *radeon_state, 5116 SISLANDS_SMC_SWSTATE *smc_state) 5117 { 5118 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5119 struct ni_ps *state = ni_get_ps(radeon_state); 5120 u32 a_t; 5121 u32 t_l, t_h; 5122 u32 high_bsp; 5123 int i, ret; 5124 5125 if (state->performance_level_count >= 9) 5126 return -EINVAL; 5127 5128 if (state->performance_level_count < 2) { 5129 a_t = CG_R(0xffff) | CG_L(0); 5130 smc_state->levels[0].aT = cpu_to_be32(a_t); 5131 return 0; 5132 } 5133 5134 smc_state->levels[0].aT = cpu_to_be32(0); 5135 5136 for (i = 0; i <= state->performance_level_count - 2; i++) { 5137 ret = r600_calculate_at( 5138 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5139 100 * R600_AH_DFLT, 5140 state->performance_levels[i + 1].sclk, 5141 state->performance_levels[i].sclk, 5142 &t_l, 5143 &t_h); 5144 5145 if (ret) { 5146 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5147 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5148 } 5149 5150 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5151 a_t |= CG_R(t_l * pi->bsp / 20000); 5152 smc_state->levels[i].aT = cpu_to_be32(a_t); 5153 5154 high_bsp = (i == state->performance_level_count - 2) ? 5155 pi->pbsp : pi->bsp; 5156 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5157 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5158 } 5159 5160 return 0; 5161 } 5162 5163 static int si_disable_ulv(struct radeon_device *rdev) 5164 { 5165 struct si_power_info *si_pi = si_get_pi(rdev); 5166 struct si_ulv_param *ulv = &si_pi->ulv; 5167 5168 if (ulv->supported) 5169 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5170 0 : -EINVAL; 5171 5172 return 0; 5173 } 5174 5175 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5176 struct radeon_ps *radeon_state) 5177 { 5178 const struct si_power_info *si_pi = si_get_pi(rdev); 5179 const struct si_ulv_param *ulv = &si_pi->ulv; 5180 const struct ni_ps *state = ni_get_ps(radeon_state); 5181 int i; 5182 5183 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5184 return false; 5185 5186 /* XXX validate against display requirements! */ 5187 5188 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5189 if (rdev->clock.current_dispclk <= 5190 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5191 if (ulv->pl.vddc < 5192 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5193 return false; 5194 } 5195 } 5196 5197 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5198 return false; 5199 5200 return true; 5201 } 5202 5203 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5204 struct radeon_ps *radeon_new_state) 5205 { 5206 const struct si_power_info *si_pi = si_get_pi(rdev); 5207 const struct si_ulv_param *ulv = &si_pi->ulv; 5208 5209 if (ulv->supported) { 5210 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5211 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5212 0 : -EINVAL; 5213 } 5214 return 0; 5215 } 5216 5217 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5218 struct radeon_ps *radeon_state, 5219 SISLANDS_SMC_SWSTATE *smc_state) 5220 { 5221 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5222 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5223 struct si_power_info *si_pi = si_get_pi(rdev); 5224 struct ni_ps *state = ni_get_ps(radeon_state); 5225 int i, ret; 5226 u32 threshold; 5227 u32 sclk_in_sr = 1350; /* ??? */ 5228 5229 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5230 return -EINVAL; 5231 5232 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5233 5234 if (radeon_state->vclk && radeon_state->dclk) { 5235 eg_pi->uvd_enabled = true; 5236 if (eg_pi->smu_uvd_hs) 5237 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5238 } else { 5239 eg_pi->uvd_enabled = false; 5240 } 5241 5242 if (state->dc_compatible) 5243 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5244 5245 smc_state->levelCount = 0; 5246 for (i = 0; i < state->performance_level_count; i++) { 5247 if (eg_pi->sclk_deep_sleep) { 5248 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5249 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5250 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5251 else 5252 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5253 } 5254 } 5255 5256 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5257 &smc_state->levels[i]); 5258 smc_state->levels[i].arbRefreshState = 5259 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5260 5261 if (ret) 5262 return ret; 5263 5264 if (ni_pi->enable_power_containment) 5265 smc_state->levels[i].displayWatermark = 5266 (state->performance_levels[i].sclk < threshold) ? 5267 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5268 else 5269 smc_state->levels[i].displayWatermark = (i < 2) ? 5270 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5271 5272 if (eg_pi->dynamic_ac_timing) 5273 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5274 else 5275 smc_state->levels[i].ACIndex = 0; 5276 5277 smc_state->levelCount++; 5278 } 5279 5280 si_write_smc_soft_register(rdev, 5281 SI_SMC_SOFT_REGISTER_watermark_threshold, 5282 threshold / 512); 5283 5284 si_populate_smc_sp(rdev, radeon_state, smc_state); 5285 5286 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5287 if (ret) 5288 ni_pi->enable_power_containment = false; 5289 5290 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5291 if (ret) 5292 ni_pi->enable_sq_ramping = false; 5293 5294 return si_populate_smc_t(rdev, radeon_state, smc_state); 5295 } 5296 5297 static int si_upload_sw_state(struct radeon_device *rdev, 5298 struct radeon_ps *radeon_new_state) 5299 { 5300 struct si_power_info *si_pi = si_get_pi(rdev); 5301 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5302 int ret; 5303 u32 address = si_pi->state_table_start + 5304 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5305 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5306 ((new_state->performance_level_count - 1) * 5307 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5308 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5309 5310 memset(smc_state, 0, state_size); 5311 5312 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5313 if (ret) 5314 return ret; 5315 5316 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5317 state_size, si_pi->sram_end); 5318 5319 return ret; 5320 } 5321 5322 static int si_upload_ulv_state(struct radeon_device *rdev) 5323 { 5324 struct si_power_info *si_pi = si_get_pi(rdev); 5325 struct si_ulv_param *ulv = &si_pi->ulv; 5326 int ret = 0; 5327 5328 if (ulv->supported && ulv->pl.vddc) { 5329 u32 address = si_pi->state_table_start + 5330 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5331 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5332 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5333 5334 memset(smc_state, 0, state_size); 5335 5336 ret = si_populate_ulv_state(rdev, smc_state); 5337 if (!ret) 5338 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5339 state_size, si_pi->sram_end); 5340 } 5341 5342 return ret; 5343 } 5344 5345 static int si_upload_smc_data(struct radeon_device *rdev) 5346 { 5347 struct radeon_crtc *radeon_crtc = NULL; 5348 int i; 5349 5350 if (rdev->pm.dpm.new_active_crtc_count == 0) 5351 return 0; 5352 5353 for (i = 0; i < rdev->num_crtc; i++) { 5354 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5355 radeon_crtc = rdev->mode_info.crtcs[i]; 5356 break; 5357 } 5358 } 5359 5360 if (radeon_crtc == NULL) 5361 return 0; 5362 5363 if (radeon_crtc->line_time <= 0) 5364 return 0; 5365 5366 if (si_write_smc_soft_register(rdev, 5367 SI_SMC_SOFT_REGISTER_crtc_index, 5368 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5369 return 0; 5370 5371 if (si_write_smc_soft_register(rdev, 5372 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5373 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5374 return 0; 5375 5376 if (si_write_smc_soft_register(rdev, 5377 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5378 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5379 return 0; 5380 5381 return 0; 5382 } 5383 5384 static int si_set_mc_special_registers(struct radeon_device *rdev, 5385 struct si_mc_reg_table *table) 5386 { 5387 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5388 u8 i, j, k; 5389 u32 temp_reg; 5390 5391 for (i = 0, j = table->last; i < table->last; i++) { 5392 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5393 return -EINVAL; 5394 switch (table->mc_reg_address[i].s1 << 2) { 5395 case MC_SEQ_MISC1: 5396 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5397 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5398 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5399 for (k = 0; k < table->num_entries; k++) 5400 table->mc_reg_table_entry[k].mc_data[j] = 5401 ((temp_reg & 0xffff0000)) | 5402 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5403 j++; 5404 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5405 return -EINVAL; 5406 5407 temp_reg = RREG32(MC_PMG_CMD_MRS); 5408 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5409 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5410 for (k = 0; k < table->num_entries; k++) { 5411 table->mc_reg_table_entry[k].mc_data[j] = 5412 (temp_reg & 0xffff0000) | 5413 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5414 if (!pi->mem_gddr5) 5415 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5416 } 5417 j++; 5418 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5419 return -EINVAL; 5420 5421 if (!pi->mem_gddr5) { 5422 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5423 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5424 for (k = 0; k < table->num_entries; k++) 5425 table->mc_reg_table_entry[k].mc_data[j] = 5426 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5427 j++; 5428 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5429 return -EINVAL; 5430 } 5431 break; 5432 case MC_SEQ_RESERVE_M: 5433 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5434 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5435 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5436 for(k = 0; k < table->num_entries; k++) 5437 table->mc_reg_table_entry[k].mc_data[j] = 5438 (temp_reg & 0xffff0000) | 5439 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5440 j++; 5441 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5442 return -EINVAL; 5443 break; 5444 default: 5445 break; 5446 } 5447 } 5448 5449 table->last = j; 5450 5451 return 0; 5452 } 5453 5454 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5455 { 5456 bool result = true; 5457 5458 switch (in_reg) { 5459 case MC_SEQ_RAS_TIMING >> 2: 5460 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5461 break; 5462 case MC_SEQ_CAS_TIMING >> 2: 5463 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5464 break; 5465 case MC_SEQ_MISC_TIMING >> 2: 5466 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5467 break; 5468 case MC_SEQ_MISC_TIMING2 >> 2: 5469 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5470 break; 5471 case MC_SEQ_RD_CTL_D0 >> 2: 5472 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5473 break; 5474 case MC_SEQ_RD_CTL_D1 >> 2: 5475 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5476 break; 5477 case MC_SEQ_WR_CTL_D0 >> 2: 5478 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5479 break; 5480 case MC_SEQ_WR_CTL_D1 >> 2: 5481 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5482 break; 5483 case MC_PMG_CMD_EMRS >> 2: 5484 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5485 break; 5486 case MC_PMG_CMD_MRS >> 2: 5487 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5488 break; 5489 case MC_PMG_CMD_MRS1 >> 2: 5490 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5491 break; 5492 case MC_SEQ_PMG_TIMING >> 2: 5493 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5494 break; 5495 case MC_PMG_CMD_MRS2 >> 2: 5496 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5497 break; 5498 case MC_SEQ_WR_CTL_2 >> 2: 5499 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5500 break; 5501 default: 5502 result = false; 5503 break; 5504 } 5505 5506 return result; 5507 } 5508 5509 static void si_set_valid_flag(struct si_mc_reg_table *table) 5510 { 5511 u8 i, j; 5512 5513 for (i = 0; i < table->last; i++) { 5514 for (j = 1; j < table->num_entries; j++) { 5515 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5516 table->valid_flag |= 1 << i; 5517 break; 5518 } 5519 } 5520 } 5521 } 5522 5523 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5524 { 5525 u32 i; 5526 u16 address; 5527 5528 for (i = 0; i < table->last; i++) 5529 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5530 address : table->mc_reg_address[i].s1; 5531 5532 } 5533 5534 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5535 struct si_mc_reg_table *si_table) 5536 { 5537 u8 i, j; 5538 5539 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5540 return -EINVAL; 5541 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5542 return -EINVAL; 5543 5544 for (i = 0; i < table->last; i++) 5545 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5546 si_table->last = table->last; 5547 5548 for (i = 0; i < table->num_entries; i++) { 5549 si_table->mc_reg_table_entry[i].mclk_max = 5550 table->mc_reg_table_entry[i].mclk_max; 5551 for (j = 0; j < table->last; j++) { 5552 si_table->mc_reg_table_entry[i].mc_data[j] = 5553 table->mc_reg_table_entry[i].mc_data[j]; 5554 } 5555 } 5556 si_table->num_entries = table->num_entries; 5557 5558 return 0; 5559 } 5560 5561 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5562 { 5563 struct si_power_info *si_pi = si_get_pi(rdev); 5564 struct atom_mc_reg_table *table; 5565 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5566 u8 module_index = rv770_get_memory_module_index(rdev); 5567 int ret; 5568 5569 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5570 if (!table) 5571 return -ENOMEM; 5572 5573 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5574 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5575 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5576 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5577 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5578 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5579 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5580 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5581 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5582 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5583 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5584 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5585 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5586 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5587 5588 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5589 if (ret) 5590 goto init_mc_done; 5591 5592 ret = si_copy_vbios_mc_reg_table(table, si_table); 5593 if (ret) 5594 goto init_mc_done; 5595 5596 si_set_s0_mc_reg_index(si_table); 5597 5598 ret = si_set_mc_special_registers(rdev, si_table); 5599 if (ret) 5600 goto init_mc_done; 5601 5602 si_set_valid_flag(si_table); 5603 5604 init_mc_done: 5605 kfree(table); 5606 5607 return ret; 5608 5609 } 5610 5611 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5612 SMC_SIslands_MCRegisters *mc_reg_table) 5613 { 5614 struct si_power_info *si_pi = si_get_pi(rdev); 5615 u32 i, j; 5616 5617 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5618 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5619 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5620 break; 5621 mc_reg_table->address[i].s0 = 5622 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5623 mc_reg_table->address[i].s1 = 5624 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5625 i++; 5626 } 5627 } 5628 mc_reg_table->last = (u8)i; 5629 } 5630 5631 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5632 SMC_SIslands_MCRegisterSet *data, 5633 u32 num_entries, u32 valid_flag) 5634 { 5635 u32 i, j; 5636 5637 for(i = 0, j = 0; j < num_entries; j++) { 5638 if (valid_flag & (1 << j)) { 5639 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5640 i++; 5641 } 5642 } 5643 } 5644 5645 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5646 struct rv7xx_pl *pl, 5647 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5648 { 5649 struct si_power_info *si_pi = si_get_pi(rdev); 5650 u32 i = 0; 5651 5652 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5653 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5654 break; 5655 } 5656 5657 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5658 --i; 5659 5660 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5661 mc_reg_table_data, si_pi->mc_reg_table.last, 5662 si_pi->mc_reg_table.valid_flag); 5663 } 5664 5665 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5666 struct radeon_ps *radeon_state, 5667 SMC_SIslands_MCRegisters *mc_reg_table) 5668 { 5669 struct ni_ps *state = ni_get_ps(radeon_state); 5670 int i; 5671 5672 for (i = 0; i < state->performance_level_count; i++) { 5673 si_convert_mc_reg_table_entry_to_smc(rdev, 5674 &state->performance_levels[i], 5675 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5676 } 5677 } 5678 5679 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5680 struct radeon_ps *radeon_boot_state) 5681 { 5682 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5683 struct si_power_info *si_pi = si_get_pi(rdev); 5684 struct si_ulv_param *ulv = &si_pi->ulv; 5685 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5686 5687 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5688 5689 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5690 5691 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5692 5693 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5694 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5695 5696 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5697 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5698 si_pi->mc_reg_table.last, 5699 si_pi->mc_reg_table.valid_flag); 5700 5701 if (ulv->supported && ulv->pl.vddc != 0) 5702 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5703 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5704 else 5705 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5706 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5707 si_pi->mc_reg_table.last, 5708 si_pi->mc_reg_table.valid_flag); 5709 5710 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5711 5712 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5713 (u8 *)smc_mc_reg_table, 5714 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5715 } 5716 5717 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5718 struct radeon_ps *radeon_new_state) 5719 { 5720 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5721 struct si_power_info *si_pi = si_get_pi(rdev); 5722 u32 address = si_pi->mc_reg_table_start + 5723 offsetof(SMC_SIslands_MCRegisters, 5724 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5725 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5726 5727 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5728 5729 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5730 5731 5732 return si_copy_bytes_to_smc(rdev, address, 5733 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5734 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5735 si_pi->sram_end); 5736 5737 } 5738 5739 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5740 { 5741 if (enable) 5742 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5743 else 5744 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5745 } 5746 5747 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5748 struct radeon_ps *radeon_state) 5749 { 5750 struct ni_ps *state = ni_get_ps(radeon_state); 5751 int i; 5752 u16 pcie_speed, max_speed = 0; 5753 5754 for (i = 0; i < state->performance_level_count; i++) { 5755 pcie_speed = state->performance_levels[i].pcie_gen; 5756 if (max_speed < pcie_speed) 5757 max_speed = pcie_speed; 5758 } 5759 return max_speed; 5760 } 5761 5762 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5763 { 5764 u32 speed_cntl; 5765 5766 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5767 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5768 5769 return (u16)speed_cntl; 5770 } 5771 5772 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5773 struct radeon_ps *radeon_new_state, 5774 struct radeon_ps *radeon_current_state) 5775 { 5776 struct si_power_info *si_pi = si_get_pi(rdev); 5777 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5778 enum radeon_pcie_gen current_link_speed; 5779 5780 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5781 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5782 else 5783 current_link_speed = si_pi->force_pcie_gen; 5784 5785 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5786 si_pi->pspp_notify_required = false; 5787 if (target_link_speed > current_link_speed) { 5788 switch (target_link_speed) { 5789 #if defined(CONFIG_ACPI) 5790 case RADEON_PCIE_GEN3: 5791 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5792 break; 5793 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5794 if (current_link_speed == RADEON_PCIE_GEN2) 5795 break; 5796 case RADEON_PCIE_GEN2: 5797 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5798 break; 5799 #endif 5800 default: 5801 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5802 break; 5803 } 5804 } else { 5805 if (target_link_speed < current_link_speed) 5806 si_pi->pspp_notify_required = true; 5807 } 5808 } 5809 5810 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5811 struct radeon_ps *radeon_new_state, 5812 struct radeon_ps *radeon_current_state) 5813 { 5814 struct si_power_info *si_pi = si_get_pi(rdev); 5815 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5816 u8 request; 5817 5818 if (si_pi->pspp_notify_required) { 5819 if (target_link_speed == RADEON_PCIE_GEN3) 5820 request = PCIE_PERF_REQ_PECI_GEN3; 5821 else if (target_link_speed == RADEON_PCIE_GEN2) 5822 request = PCIE_PERF_REQ_PECI_GEN2; 5823 else 5824 request = PCIE_PERF_REQ_PECI_GEN1; 5825 5826 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5827 (si_get_current_pcie_speed(rdev) > 0)) 5828 return; 5829 5830 #if defined(CONFIG_ACPI) 5831 radeon_acpi_pcie_performance_request(rdev, request, false); 5832 #endif 5833 } 5834 } 5835 5836 #if 0 5837 static int si_ds_request(struct radeon_device *rdev, 5838 bool ds_status_on, u32 count_write) 5839 { 5840 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5841 5842 if (eg_pi->sclk_deep_sleep) { 5843 if (ds_status_on) 5844 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5845 PPSMC_Result_OK) ? 5846 0 : -EINVAL; 5847 else 5848 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5849 PPSMC_Result_OK) ? 0 : -EINVAL; 5850 } 5851 return 0; 5852 } 5853 #endif 5854 5855 static void si_set_max_cu_value(struct radeon_device *rdev) 5856 { 5857 struct si_power_info *si_pi = si_get_pi(rdev); 5858 5859 if (rdev->family == CHIP_VERDE) { 5860 switch (rdev->pdev->device) { 5861 case 0x6820: 5862 case 0x6825: 5863 case 0x6821: 5864 case 0x6823: 5865 case 0x6827: 5866 si_pi->max_cu = 10; 5867 break; 5868 case 0x682D: 5869 case 0x6824: 5870 case 0x682F: 5871 case 0x6826: 5872 si_pi->max_cu = 8; 5873 break; 5874 case 0x6828: 5875 case 0x6830: 5876 case 0x6831: 5877 case 0x6838: 5878 case 0x6839: 5879 case 0x683D: 5880 si_pi->max_cu = 10; 5881 break; 5882 case 0x683B: 5883 case 0x683F: 5884 case 0x6829: 5885 si_pi->max_cu = 8; 5886 break; 5887 default: 5888 si_pi->max_cu = 0; 5889 break; 5890 } 5891 } else { 5892 si_pi->max_cu = 0; 5893 } 5894 } 5895 5896 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5897 struct radeon_clock_voltage_dependency_table *table) 5898 { 5899 u32 i; 5900 int j; 5901 u16 leakage_voltage; 5902 5903 if (table) { 5904 for (i = 0; i < table->count; i++) { 5905 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5906 table->entries[i].v, 5907 &leakage_voltage)) { 5908 case 0: 5909 table->entries[i].v = leakage_voltage; 5910 break; 5911 case -EAGAIN: 5912 return -EINVAL; 5913 case -EINVAL: 5914 default: 5915 break; 5916 } 5917 } 5918 5919 for (j = (table->count - 2); j >= 0; j--) { 5920 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5921 table->entries[j].v : table->entries[j + 1].v; 5922 } 5923 } 5924 return 0; 5925 } 5926 5927 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5928 { 5929 int ret = 0; 5930 5931 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5932 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5933 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5934 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5935 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5936 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5937 return ret; 5938 } 5939 5940 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5941 struct radeon_ps *radeon_new_state, 5942 struct radeon_ps *radeon_current_state) 5943 { 5944 u32 lane_width; 5945 u32 new_lane_width = 5946 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5947 u32 current_lane_width = 5948 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5949 5950 if (new_lane_width != current_lane_width) { 5951 radeon_set_pcie_lanes(rdev, new_lane_width); 5952 lane_width = radeon_get_pcie_lanes(rdev); 5953 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5954 } 5955 } 5956 5957 static void si_set_vce_clock(struct radeon_device *rdev, 5958 struct radeon_ps *new_rps, 5959 struct radeon_ps *old_rps) 5960 { 5961 if ((old_rps->evclk != new_rps->evclk) || 5962 (old_rps->ecclk != new_rps->ecclk)) { 5963 /* turn the clocks on when encoding, off otherwise */ 5964 if (new_rps->evclk || new_rps->ecclk) 5965 vce_v1_0_enable_mgcg(rdev, false); 5966 else 5967 vce_v1_0_enable_mgcg(rdev, true); 5968 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5969 } 5970 } 5971 5972 void si_dpm_setup_asic(struct radeon_device *rdev) 5973 { 5974 int r; 5975 5976 r = si_mc_load_microcode(rdev); 5977 if (r) 5978 DRM_ERROR("Failed to load MC firmware!\n"); 5979 rv770_get_memory_type(rdev); 5980 si_read_clock_registers(rdev); 5981 si_enable_acpi_power_management(rdev); 5982 } 5983 5984 static int si_thermal_enable_alert(struct radeon_device *rdev, 5985 bool enable) 5986 { 5987 u32 thermal_int = RREG32(CG_THERMAL_INT); 5988 5989 if (enable) { 5990 PPSMC_Result result; 5991 5992 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5993 WREG32(CG_THERMAL_INT, thermal_int); 5994 rdev->irq.dpm_thermal = false; 5995 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5996 if (result != PPSMC_Result_OK) { 5997 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5998 return -EINVAL; 5999 } 6000 } else { 6001 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 6002 WREG32(CG_THERMAL_INT, thermal_int); 6003 rdev->irq.dpm_thermal = true; 6004 } 6005 6006 return 0; 6007 } 6008 6009 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 6010 int min_temp, int max_temp) 6011 { 6012 int low_temp = 0 * 1000; 6013 int high_temp = 255 * 1000; 6014 6015 if (low_temp < min_temp) 6016 low_temp = min_temp; 6017 if (high_temp > max_temp) 6018 high_temp = max_temp; 6019 if (high_temp < low_temp) { 6020 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6021 return -EINVAL; 6022 } 6023 6024 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6025 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6026 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6027 6028 rdev->pm.dpm.thermal.min_temp = low_temp; 6029 rdev->pm.dpm.thermal.max_temp = high_temp; 6030 6031 return 0; 6032 } 6033 6034 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6035 { 6036 struct si_power_info *si_pi = si_get_pi(rdev); 6037 u32 tmp; 6038 6039 if (si_pi->fan_ctrl_is_in_default_mode) { 6040 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6041 si_pi->fan_ctrl_default_mode = tmp; 6042 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6043 si_pi->t_min = tmp; 6044 si_pi->fan_ctrl_is_in_default_mode = false; 6045 } 6046 6047 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6048 tmp |= TMIN(0); 6049 WREG32(CG_FDO_CTRL2, tmp); 6050 6051 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6052 tmp |= FDO_PWM_MODE(mode); 6053 WREG32(CG_FDO_CTRL2, tmp); 6054 } 6055 6056 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6057 { 6058 struct si_power_info *si_pi = si_get_pi(rdev); 6059 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6060 u32 duty100; 6061 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6062 u16 fdo_min, slope1, slope2; 6063 u32 reference_clock, tmp; 6064 int ret; 6065 u64 tmp64; 6066 6067 if (!si_pi->fan_table_start) { 6068 rdev->pm.dpm.fan.ucode_fan_control = false; 6069 return 0; 6070 } 6071 6072 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6073 6074 if (duty100 == 0) { 6075 rdev->pm.dpm.fan.ucode_fan_control = false; 6076 return 0; 6077 } 6078 6079 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6080 do_div(tmp64, 10000); 6081 fdo_min = (u16)tmp64; 6082 6083 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6084 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6085 6086 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6087 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6088 6089 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6090 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6091 6092 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6093 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6094 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6095 6096 fan_table.slope1 = cpu_to_be16(slope1); 6097 fan_table.slope2 = cpu_to_be16(slope2); 6098 6099 fan_table.fdo_min = cpu_to_be16(fdo_min); 6100 6101 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6102 6103 fan_table.hys_up = cpu_to_be16(1); 6104 6105 fan_table.hys_slope = cpu_to_be16(1); 6106 6107 fan_table.temp_resp_lim = cpu_to_be16(5); 6108 6109 reference_clock = radeon_get_xclk(rdev); 6110 6111 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6112 reference_clock) / 1600); 6113 6114 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6115 6116 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6117 fan_table.temp_src = (uint8_t)tmp; 6118 6119 ret = si_copy_bytes_to_smc(rdev, 6120 si_pi->fan_table_start, 6121 (u8 *)(&fan_table), 6122 sizeof(fan_table), 6123 si_pi->sram_end); 6124 6125 if (ret) { 6126 DRM_ERROR("Failed to load fan table to the SMC."); 6127 rdev->pm.dpm.fan.ucode_fan_control = false; 6128 } 6129 6130 return 0; 6131 } 6132 6133 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6134 { 6135 struct si_power_info *si_pi = si_get_pi(rdev); 6136 PPSMC_Result ret; 6137 6138 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6139 if (ret == PPSMC_Result_OK) { 6140 si_pi->fan_is_controlled_by_smc = true; 6141 return 0; 6142 } else { 6143 return -EINVAL; 6144 } 6145 } 6146 6147 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6148 { 6149 struct si_power_info *si_pi = si_get_pi(rdev); 6150 PPSMC_Result ret; 6151 6152 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6153 6154 if (ret == PPSMC_Result_OK) { 6155 si_pi->fan_is_controlled_by_smc = false; 6156 return 0; 6157 } else { 6158 return -EINVAL; 6159 } 6160 } 6161 6162 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6163 u32 *speed) 6164 { 6165 u32 duty, duty100; 6166 u64 tmp64; 6167 6168 if (rdev->pm.no_fan) 6169 return -ENOENT; 6170 6171 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6172 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6173 6174 if (duty100 == 0) 6175 return -EINVAL; 6176 6177 tmp64 = (u64)duty * 100; 6178 do_div(tmp64, duty100); 6179 *speed = (u32)tmp64; 6180 6181 if (*speed > 100) 6182 *speed = 100; 6183 6184 return 0; 6185 } 6186 6187 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6188 u32 speed) 6189 { 6190 struct si_power_info *si_pi = si_get_pi(rdev); 6191 u32 tmp; 6192 u32 duty, duty100; 6193 u64 tmp64; 6194 6195 if (rdev->pm.no_fan) 6196 return -ENOENT; 6197 6198 if (si_pi->fan_is_controlled_by_smc) 6199 return -EINVAL; 6200 6201 if (speed > 100) 6202 return -EINVAL; 6203 6204 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6205 6206 if (duty100 == 0) 6207 return -EINVAL; 6208 6209 tmp64 = (u64)speed * duty100; 6210 do_div(tmp64, 100); 6211 duty = (u32)tmp64; 6212 6213 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6214 tmp |= FDO_STATIC_DUTY(duty); 6215 WREG32(CG_FDO_CTRL0, tmp); 6216 6217 return 0; 6218 } 6219 6220 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6221 { 6222 if (mode) { 6223 /* stop auto-manage */ 6224 if (rdev->pm.dpm.fan.ucode_fan_control) 6225 si_fan_ctrl_stop_smc_fan_control(rdev); 6226 si_fan_ctrl_set_static_mode(rdev, mode); 6227 } else { 6228 /* restart auto-manage */ 6229 if (rdev->pm.dpm.fan.ucode_fan_control) 6230 si_thermal_start_smc_fan_control(rdev); 6231 else 6232 si_fan_ctrl_set_default_mode(rdev); 6233 } 6234 } 6235 6236 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6237 { 6238 struct si_power_info *si_pi = si_get_pi(rdev); 6239 u32 tmp; 6240 6241 if (si_pi->fan_is_controlled_by_smc) 6242 return 0; 6243 6244 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6245 return (tmp >> FDO_PWM_MODE_SHIFT); 6246 } 6247 6248 #if 0 6249 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6250 u32 *speed) 6251 { 6252 u32 tach_period; 6253 u32 xclk = radeon_get_xclk(rdev); 6254 6255 if (rdev->pm.no_fan) 6256 return -ENOENT; 6257 6258 if (rdev->pm.fan_pulses_per_revolution == 0) 6259 return -ENOENT; 6260 6261 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6262 if (tach_period == 0) 6263 return -ENOENT; 6264 6265 *speed = 60 * xclk * 10000 / tach_period; 6266 6267 return 0; 6268 } 6269 6270 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6271 u32 speed) 6272 { 6273 u32 tach_period, tmp; 6274 u32 xclk = radeon_get_xclk(rdev); 6275 6276 if (rdev->pm.no_fan) 6277 return -ENOENT; 6278 6279 if (rdev->pm.fan_pulses_per_revolution == 0) 6280 return -ENOENT; 6281 6282 if ((speed < rdev->pm.fan_min_rpm) || 6283 (speed > rdev->pm.fan_max_rpm)) 6284 return -EINVAL; 6285 6286 if (rdev->pm.dpm.fan.ucode_fan_control) 6287 si_fan_ctrl_stop_smc_fan_control(rdev); 6288 6289 tach_period = 60 * xclk * 10000 / (8 * speed); 6290 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6291 tmp |= TARGET_PERIOD(tach_period); 6292 WREG32(CG_TACH_CTRL, tmp); 6293 6294 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6295 6296 return 0; 6297 } 6298 #endif 6299 6300 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6301 { 6302 struct si_power_info *si_pi = si_get_pi(rdev); 6303 u32 tmp; 6304 6305 if (!si_pi->fan_ctrl_is_in_default_mode) { 6306 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6307 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6308 WREG32(CG_FDO_CTRL2, tmp); 6309 6310 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6311 tmp |= TMIN(si_pi->t_min); 6312 WREG32(CG_FDO_CTRL2, tmp); 6313 si_pi->fan_ctrl_is_in_default_mode = true; 6314 } 6315 } 6316 6317 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6318 { 6319 if (rdev->pm.dpm.fan.ucode_fan_control) { 6320 si_fan_ctrl_start_smc_fan_control(rdev); 6321 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6322 } 6323 } 6324 6325 static void si_thermal_initialize(struct radeon_device *rdev) 6326 { 6327 u32 tmp; 6328 6329 if (rdev->pm.fan_pulses_per_revolution) { 6330 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6331 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6332 WREG32(CG_TACH_CTRL, tmp); 6333 } 6334 6335 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6336 tmp |= TACH_PWM_RESP_RATE(0x28); 6337 WREG32(CG_FDO_CTRL2, tmp); 6338 } 6339 6340 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6341 { 6342 int ret; 6343 6344 si_thermal_initialize(rdev); 6345 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6346 if (ret) 6347 return ret; 6348 ret = si_thermal_enable_alert(rdev, true); 6349 if (ret) 6350 return ret; 6351 if (rdev->pm.dpm.fan.ucode_fan_control) { 6352 ret = si_halt_smc(rdev); 6353 if (ret) 6354 return ret; 6355 ret = si_thermal_setup_fan_table(rdev); 6356 if (ret) 6357 return ret; 6358 ret = si_resume_smc(rdev); 6359 if (ret) 6360 return ret; 6361 si_thermal_start_smc_fan_control(rdev); 6362 } 6363 6364 return 0; 6365 } 6366 6367 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6368 { 6369 if (!rdev->pm.no_fan) { 6370 si_fan_ctrl_set_default_mode(rdev); 6371 si_fan_ctrl_stop_smc_fan_control(rdev); 6372 } 6373 } 6374 6375 int si_dpm_enable(struct radeon_device *rdev) 6376 { 6377 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6378 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6379 struct si_power_info *si_pi = si_get_pi(rdev); 6380 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6381 int ret; 6382 6383 if (si_is_smc_running(rdev)) 6384 return -EINVAL; 6385 if (pi->voltage_control || si_pi->voltage_control_svi2) 6386 si_enable_voltage_control(rdev, true); 6387 if (pi->mvdd_control) 6388 si_get_mvdd_configuration(rdev); 6389 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6390 ret = si_construct_voltage_tables(rdev); 6391 if (ret) { 6392 DRM_ERROR("si_construct_voltage_tables failed\n"); 6393 return ret; 6394 } 6395 } 6396 if (eg_pi->dynamic_ac_timing) { 6397 ret = si_initialize_mc_reg_table(rdev); 6398 if (ret) 6399 eg_pi->dynamic_ac_timing = false; 6400 } 6401 if (pi->dynamic_ss) 6402 si_enable_spread_spectrum(rdev, true); 6403 if (pi->thermal_protection) 6404 si_enable_thermal_protection(rdev, true); 6405 si_setup_bsp(rdev); 6406 si_program_git(rdev); 6407 si_program_tp(rdev); 6408 si_program_tpp(rdev); 6409 si_program_sstp(rdev); 6410 si_enable_display_gap(rdev); 6411 si_program_vc(rdev); 6412 ret = si_upload_firmware(rdev); 6413 if (ret) { 6414 DRM_ERROR("si_upload_firmware failed\n"); 6415 return ret; 6416 } 6417 ret = si_process_firmware_header(rdev); 6418 if (ret) { 6419 DRM_ERROR("si_process_firmware_header failed\n"); 6420 return ret; 6421 } 6422 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6423 if (ret) { 6424 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6425 return ret; 6426 } 6427 ret = si_init_smc_table(rdev); 6428 if (ret) { 6429 DRM_ERROR("si_init_smc_table failed\n"); 6430 return ret; 6431 } 6432 ret = si_init_smc_spll_table(rdev); 6433 if (ret) { 6434 DRM_ERROR("si_init_smc_spll_table failed\n"); 6435 return ret; 6436 } 6437 ret = si_init_arb_table_index(rdev); 6438 if (ret) { 6439 DRM_ERROR("si_init_arb_table_index failed\n"); 6440 return ret; 6441 } 6442 if (eg_pi->dynamic_ac_timing) { 6443 ret = si_populate_mc_reg_table(rdev, boot_ps); 6444 if (ret) { 6445 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6446 return ret; 6447 } 6448 } 6449 ret = si_initialize_smc_cac_tables(rdev); 6450 if (ret) { 6451 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6452 return ret; 6453 } 6454 ret = si_initialize_hardware_cac_manager(rdev); 6455 if (ret) { 6456 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6457 return ret; 6458 } 6459 ret = si_initialize_smc_dte_tables(rdev); 6460 if (ret) { 6461 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6462 return ret; 6463 } 6464 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6465 if (ret) { 6466 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6467 return ret; 6468 } 6469 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6470 if (ret) { 6471 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6472 return ret; 6473 } 6474 si_program_response_times(rdev); 6475 si_program_ds_registers(rdev); 6476 si_dpm_start_smc(rdev); 6477 ret = si_notify_smc_display_change(rdev, false); 6478 if (ret) { 6479 DRM_ERROR("si_notify_smc_display_change failed\n"); 6480 return ret; 6481 } 6482 si_enable_sclk_control(rdev, true); 6483 si_start_dpm(rdev); 6484 6485 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6486 6487 si_thermal_start_thermal_controller(rdev); 6488 6489 ni_update_current_ps(rdev, boot_ps); 6490 6491 return 0; 6492 } 6493 6494 static int si_set_temperature_range(struct radeon_device *rdev) 6495 { 6496 int ret; 6497 6498 ret = si_thermal_enable_alert(rdev, false); 6499 if (ret) 6500 return ret; 6501 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6502 if (ret) 6503 return ret; 6504 ret = si_thermal_enable_alert(rdev, true); 6505 if (ret) 6506 return ret; 6507 6508 return ret; 6509 } 6510 6511 int si_dpm_late_enable(struct radeon_device *rdev) 6512 { 6513 int ret; 6514 6515 ret = si_set_temperature_range(rdev); 6516 if (ret) 6517 return ret; 6518 6519 return ret; 6520 } 6521 6522 void si_dpm_disable(struct radeon_device *rdev) 6523 { 6524 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6525 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6526 6527 if (!si_is_smc_running(rdev)) 6528 return; 6529 si_thermal_stop_thermal_controller(rdev); 6530 si_disable_ulv(rdev); 6531 si_clear_vc(rdev); 6532 if (pi->thermal_protection) 6533 si_enable_thermal_protection(rdev, false); 6534 si_enable_power_containment(rdev, boot_ps, false); 6535 si_enable_smc_cac(rdev, boot_ps, false); 6536 si_enable_spread_spectrum(rdev, false); 6537 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6538 si_stop_dpm(rdev); 6539 si_reset_to_default(rdev); 6540 si_dpm_stop_smc(rdev); 6541 si_force_switch_to_arb_f0(rdev); 6542 6543 ni_update_current_ps(rdev, boot_ps); 6544 } 6545 6546 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6547 { 6548 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6549 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6550 struct radeon_ps *new_ps = &requested_ps; 6551 6552 ni_update_requested_ps(rdev, new_ps); 6553 6554 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6555 6556 return 0; 6557 } 6558 6559 static int si_power_control_set_level(struct radeon_device *rdev) 6560 { 6561 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6562 int ret; 6563 6564 ret = si_restrict_performance_levels_before_switch(rdev); 6565 if (ret) 6566 return ret; 6567 ret = si_halt_smc(rdev); 6568 if (ret) 6569 return ret; 6570 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6571 if (ret) 6572 return ret; 6573 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6574 if (ret) 6575 return ret; 6576 ret = si_resume_smc(rdev); 6577 if (ret) 6578 return ret; 6579 ret = si_set_sw_state(rdev); 6580 if (ret) 6581 return ret; 6582 return 0; 6583 } 6584 6585 int si_dpm_set_power_state(struct radeon_device *rdev) 6586 { 6587 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6588 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6589 struct radeon_ps *old_ps = &eg_pi->current_rps; 6590 int ret; 6591 6592 ret = si_disable_ulv(rdev); 6593 if (ret) { 6594 DRM_ERROR("si_disable_ulv failed\n"); 6595 return ret; 6596 } 6597 ret = si_restrict_performance_levels_before_switch(rdev); 6598 if (ret) { 6599 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6600 return ret; 6601 } 6602 if (eg_pi->pcie_performance_request) 6603 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6604 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6605 ret = si_enable_power_containment(rdev, new_ps, false); 6606 if (ret) { 6607 DRM_ERROR("si_enable_power_containment failed\n"); 6608 return ret; 6609 } 6610 ret = si_enable_smc_cac(rdev, new_ps, false); 6611 if (ret) { 6612 DRM_ERROR("si_enable_smc_cac failed\n"); 6613 return ret; 6614 } 6615 ret = si_halt_smc(rdev); 6616 if (ret) { 6617 DRM_ERROR("si_halt_smc failed\n"); 6618 return ret; 6619 } 6620 ret = si_upload_sw_state(rdev, new_ps); 6621 if (ret) { 6622 DRM_ERROR("si_upload_sw_state failed\n"); 6623 return ret; 6624 } 6625 ret = si_upload_smc_data(rdev); 6626 if (ret) { 6627 DRM_ERROR("si_upload_smc_data failed\n"); 6628 return ret; 6629 } 6630 ret = si_upload_ulv_state(rdev); 6631 if (ret) { 6632 DRM_ERROR("si_upload_ulv_state failed\n"); 6633 return ret; 6634 } 6635 if (eg_pi->dynamic_ac_timing) { 6636 ret = si_upload_mc_reg_table(rdev, new_ps); 6637 if (ret) { 6638 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6639 return ret; 6640 } 6641 } 6642 ret = si_program_memory_timing_parameters(rdev, new_ps); 6643 if (ret) { 6644 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6645 return ret; 6646 } 6647 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6648 6649 ret = si_resume_smc(rdev); 6650 if (ret) { 6651 DRM_ERROR("si_resume_smc failed\n"); 6652 return ret; 6653 } 6654 ret = si_set_sw_state(rdev); 6655 if (ret) { 6656 DRM_ERROR("si_set_sw_state failed\n"); 6657 return ret; 6658 } 6659 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6660 si_set_vce_clock(rdev, new_ps, old_ps); 6661 if (eg_pi->pcie_performance_request) 6662 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6663 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6664 if (ret) { 6665 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6666 return ret; 6667 } 6668 ret = si_enable_smc_cac(rdev, new_ps, true); 6669 if (ret) { 6670 DRM_ERROR("si_enable_smc_cac failed\n"); 6671 return ret; 6672 } 6673 ret = si_enable_power_containment(rdev, new_ps, true); 6674 if (ret) { 6675 DRM_ERROR("si_enable_power_containment failed\n"); 6676 return ret; 6677 } 6678 6679 ret = si_power_control_set_level(rdev); 6680 if (ret) { 6681 DRM_ERROR("si_power_control_set_level failed\n"); 6682 return ret; 6683 } 6684 6685 return 0; 6686 } 6687 6688 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6689 { 6690 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6691 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6692 6693 ni_update_current_ps(rdev, new_ps); 6694 } 6695 6696 #if 0 6697 void si_dpm_reset_asic(struct radeon_device *rdev) 6698 { 6699 si_restrict_performance_levels_before_switch(rdev); 6700 si_disable_ulv(rdev); 6701 si_set_boot_state(rdev); 6702 } 6703 #endif 6704 6705 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6706 { 6707 si_program_display_gap(rdev); 6708 } 6709 6710 union power_info { 6711 struct _ATOM_POWERPLAY_INFO info; 6712 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6713 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6714 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6715 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6716 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6717 }; 6718 6719 union pplib_clock_info { 6720 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6721 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6722 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6723 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6724 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6725 }; 6726 6727 union pplib_power_state { 6728 struct _ATOM_PPLIB_STATE v1; 6729 struct _ATOM_PPLIB_STATE_V2 v2; 6730 }; 6731 6732 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6733 struct radeon_ps *rps, 6734 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6735 u8 table_rev) 6736 { 6737 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6738 rps->class = le16_to_cpu(non_clock_info->usClassification); 6739 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6740 6741 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6742 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6743 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6744 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6745 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6746 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6747 } else { 6748 rps->vclk = 0; 6749 rps->dclk = 0; 6750 } 6751 6752 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6753 rdev->pm.dpm.boot_ps = rps; 6754 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6755 rdev->pm.dpm.uvd_ps = rps; 6756 } 6757 6758 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6759 struct radeon_ps *rps, int index, 6760 union pplib_clock_info *clock_info) 6761 { 6762 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6763 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6764 struct si_power_info *si_pi = si_get_pi(rdev); 6765 struct ni_ps *ps = ni_get_ps(rps); 6766 u16 leakage_voltage; 6767 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6768 int ret; 6769 6770 ps->performance_level_count = index + 1; 6771 6772 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6773 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6774 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6775 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6776 6777 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6778 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6779 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6780 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6781 si_pi->sys_pcie_mask, 6782 si_pi->boot_pcie_gen, 6783 clock_info->si.ucPCIEGen); 6784 6785 /* patch up vddc if necessary */ 6786 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6787 &leakage_voltage); 6788 if (ret == 0) 6789 pl->vddc = leakage_voltage; 6790 6791 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6792 pi->acpi_vddc = pl->vddc; 6793 eg_pi->acpi_vddci = pl->vddci; 6794 si_pi->acpi_pcie_gen = pl->pcie_gen; 6795 } 6796 6797 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6798 index == 0) { 6799 /* XXX disable for A0 tahiti */ 6800 si_pi->ulv.supported = false; 6801 si_pi->ulv.pl = *pl; 6802 si_pi->ulv.one_pcie_lane_in_ulv = false; 6803 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6804 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6805 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6806 } 6807 6808 if (pi->min_vddc_in_table > pl->vddc) 6809 pi->min_vddc_in_table = pl->vddc; 6810 6811 if (pi->max_vddc_in_table < pl->vddc) 6812 pi->max_vddc_in_table = pl->vddc; 6813 6814 /* patch up boot state */ 6815 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6816 u16 vddc, vddci, mvdd; 6817 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6818 pl->mclk = rdev->clock.default_mclk; 6819 pl->sclk = rdev->clock.default_sclk; 6820 pl->vddc = vddc; 6821 pl->vddci = vddci; 6822 si_pi->mvdd_bootup_value = mvdd; 6823 } 6824 6825 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6826 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6827 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6828 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6829 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6830 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6831 } 6832 } 6833 6834 static int si_parse_power_table(struct radeon_device *rdev) 6835 { 6836 struct radeon_mode_info *mode_info = &rdev->mode_info; 6837 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6838 union pplib_power_state *power_state; 6839 int i, j, k, non_clock_array_index, clock_array_index; 6840 union pplib_clock_info *clock_info; 6841 struct _StateArray *state_array; 6842 struct _ClockInfoArray *clock_info_array; 6843 struct _NonClockInfoArray *non_clock_info_array; 6844 union power_info *power_info; 6845 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6846 u16 data_offset; 6847 u8 frev, crev; 6848 u8 *power_state_offset; 6849 struct ni_ps *ps; 6850 6851 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6852 &frev, &crev, &data_offset)) 6853 return -EINVAL; 6854 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6855 6856 state_array = (struct _StateArray *) 6857 (mode_info->atom_context->bios + data_offset + 6858 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6859 clock_info_array = (struct _ClockInfoArray *) 6860 (mode_info->atom_context->bios + data_offset + 6861 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6862 non_clock_info_array = (struct _NonClockInfoArray *) 6863 (mode_info->atom_context->bios + data_offset + 6864 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6865 6866 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6867 state_array->ucNumEntries, GFP_KERNEL); 6868 if (!rdev->pm.dpm.ps) 6869 return -ENOMEM; 6870 power_state_offset = (u8 *)state_array->states; 6871 for (i = 0; i < state_array->ucNumEntries; i++) { 6872 u8 *idx; 6873 power_state = (union pplib_power_state *)power_state_offset; 6874 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6875 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6876 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6877 if (!rdev->pm.power_state[i].clock_info) 6878 return -EINVAL; 6879 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6880 if (ps == NULL) { 6881 kfree(rdev->pm.dpm.ps); 6882 return -ENOMEM; 6883 } 6884 rdev->pm.dpm.ps[i].ps_priv = ps; 6885 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6886 non_clock_info, 6887 non_clock_info_array->ucEntrySize); 6888 k = 0; 6889 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6890 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6891 clock_array_index = idx[j]; 6892 if (clock_array_index >= clock_info_array->ucNumEntries) 6893 continue; 6894 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6895 break; 6896 clock_info = (union pplib_clock_info *) 6897 ((u8 *)&clock_info_array->clockInfo[0] + 6898 (clock_array_index * clock_info_array->ucEntrySize)); 6899 si_parse_pplib_clock_info(rdev, 6900 &rdev->pm.dpm.ps[i], k, 6901 clock_info); 6902 k++; 6903 } 6904 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6905 } 6906 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6907 6908 /* fill in the vce power states */ 6909 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6910 u32 sclk, mclk; 6911 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6912 clock_info = (union pplib_clock_info *) 6913 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6914 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6915 sclk |= clock_info->si.ucEngineClockHigh << 16; 6916 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6917 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6918 rdev->pm.dpm.vce_states[i].sclk = sclk; 6919 rdev->pm.dpm.vce_states[i].mclk = mclk; 6920 } 6921 6922 return 0; 6923 } 6924 6925 int si_dpm_init(struct radeon_device *rdev) 6926 { 6927 struct rv7xx_power_info *pi; 6928 struct evergreen_power_info *eg_pi; 6929 struct ni_power_info *ni_pi; 6930 struct si_power_info *si_pi; 6931 struct atom_clock_dividers dividers; 6932 int ret; 6933 u32 mask; 6934 6935 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6936 if (si_pi == NULL) 6937 return -ENOMEM; 6938 rdev->pm.dpm.priv = si_pi; 6939 ni_pi = &si_pi->ni; 6940 eg_pi = &ni_pi->eg; 6941 pi = &eg_pi->rv7xx; 6942 6943 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6944 if (ret) 6945 si_pi->sys_pcie_mask = 0; 6946 else 6947 si_pi->sys_pcie_mask = mask; 6948 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6949 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6950 6951 si_set_max_cu_value(rdev); 6952 6953 rv770_get_max_vddc(rdev); 6954 si_get_leakage_vddc(rdev); 6955 si_patch_dependency_tables_based_on_leakage(rdev); 6956 6957 pi->acpi_vddc = 0; 6958 eg_pi->acpi_vddci = 0; 6959 pi->min_vddc_in_table = 0; 6960 pi->max_vddc_in_table = 0; 6961 6962 ret = r600_get_platform_caps(rdev); 6963 if (ret) 6964 return ret; 6965 6966 ret = r600_parse_extended_power_table(rdev); 6967 if (ret) 6968 return ret; 6969 6970 ret = si_parse_power_table(rdev); 6971 if (ret) 6972 return ret; 6973 6974 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6975 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6976 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6977 r600_free_extended_power_table(rdev); 6978 return -ENOMEM; 6979 } 6980 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6981 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6982 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6983 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6984 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6985 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6986 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6987 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6988 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6989 6990 if (rdev->pm.dpm.voltage_response_time == 0) 6991 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6992 if (rdev->pm.dpm.backbias_response_time == 0) 6993 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6994 6995 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6996 0, false, ÷rs); 6997 if (ret) 6998 pi->ref_div = dividers.ref_div + 1; 6999 else 7000 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7001 7002 eg_pi->smu_uvd_hs = false; 7003 7004 pi->mclk_strobe_mode_threshold = 40000; 7005 if (si_is_special_1gb_platform(rdev)) 7006 pi->mclk_stutter_mode_threshold = 0; 7007 else 7008 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7009 pi->mclk_edc_enable_threshold = 40000; 7010 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7011 7012 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7013 7014 pi->voltage_control = 7015 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7016 VOLTAGE_OBJ_GPIO_LUT); 7017 if (!pi->voltage_control) { 7018 si_pi->voltage_control_svi2 = 7019 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7020 VOLTAGE_OBJ_SVID2); 7021 if (si_pi->voltage_control_svi2) 7022 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7023 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7024 } 7025 7026 pi->mvdd_control = 7027 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7028 VOLTAGE_OBJ_GPIO_LUT); 7029 7030 eg_pi->vddci_control = 7031 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7032 VOLTAGE_OBJ_GPIO_LUT); 7033 if (!eg_pi->vddci_control) 7034 si_pi->vddci_control_svi2 = 7035 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7036 VOLTAGE_OBJ_SVID2); 7037 7038 si_pi->vddc_phase_shed_control = 7039 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7040 VOLTAGE_OBJ_PHASE_LUT); 7041 7042 rv770_get_engine_memory_ss(rdev); 7043 7044 pi->asi = RV770_ASI_DFLT; 7045 pi->pasi = CYPRESS_HASI_DFLT; 7046 pi->vrc = SISLANDS_VRC_DFLT; 7047 7048 pi->gfx_clock_gating = true; 7049 7050 eg_pi->sclk_deep_sleep = true; 7051 si_pi->sclk_deep_sleep_above_low = false; 7052 7053 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7054 pi->thermal_protection = true; 7055 else 7056 pi->thermal_protection = false; 7057 7058 eg_pi->dynamic_ac_timing = true; 7059 7060 eg_pi->light_sleep = true; 7061 #if defined(CONFIG_ACPI) 7062 eg_pi->pcie_performance_request = 7063 radeon_acpi_is_pcie_performance_request_supported(rdev); 7064 #else 7065 eg_pi->pcie_performance_request = false; 7066 #endif 7067 7068 si_pi->sram_end = SMC_RAM_END; 7069 7070 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7071 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7072 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7073 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7074 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7075 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7076 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7077 7078 si_initialize_powertune_defaults(rdev); 7079 7080 /* make sure dc limits are valid */ 7081 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7082 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7083 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7084 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7085 7086 si_pi->fan_ctrl_is_in_default_mode = true; 7087 7088 return 0; 7089 } 7090 7091 void si_dpm_fini(struct radeon_device *rdev) 7092 { 7093 int i; 7094 7095 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7096 kfree(rdev->pm.dpm.ps[i].ps_priv); 7097 } 7098 kfree(rdev->pm.dpm.ps); 7099 kfree(rdev->pm.dpm.priv); 7100 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7101 r600_free_extended_power_table(rdev); 7102 } 7103 7104 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7105 struct seq_file *m) 7106 { 7107 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7108 struct radeon_ps *rps = &eg_pi->current_rps; 7109 struct ni_ps *ps = ni_get_ps(rps); 7110 struct rv7xx_pl *pl; 7111 u32 current_index = 7112 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7113 CURRENT_STATE_INDEX_SHIFT; 7114 7115 if (current_index >= ps->performance_level_count) { 7116 seq_printf(m, "invalid dpm profile %d\n", current_index); 7117 } else { 7118 pl = &ps->performance_levels[current_index]; 7119 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7120 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7121 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7122 } 7123 } 7124 7125 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7126 { 7127 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7128 struct radeon_ps *rps = &eg_pi->current_rps; 7129 struct ni_ps *ps = ni_get_ps(rps); 7130 struct rv7xx_pl *pl; 7131 u32 current_index = 7132 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7133 CURRENT_STATE_INDEX_SHIFT; 7134 7135 if (current_index >= ps->performance_level_count) { 7136 return 0; 7137 } else { 7138 pl = &ps->performance_levels[current_index]; 7139 return pl->sclk; 7140 } 7141 } 7142 7143 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7144 { 7145 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7146 struct radeon_ps *rps = &eg_pi->current_rps; 7147 struct ni_ps *ps = ni_get_ps(rps); 7148 struct rv7xx_pl *pl; 7149 u32 current_index = 7150 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7151 CURRENT_STATE_INDEX_SHIFT; 7152 7153 if (current_index >= ps->performance_level_count) { 7154 return 0; 7155 } else { 7156 pl = &ps->performance_levels[current_index]; 7157 return pl->mclk; 7158 } 7159 } 7160