1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 void si_dpm_reset_asic(struct radeon_device *rdev); 44 45 static const struct si_cac_config_reg cac_weights_tahiti[] = 46 { 47 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 50 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 51 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 57 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 58 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 59 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 60 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 61 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 62 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 65 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 66 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 67 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 68 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 69 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 78 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 82 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 85 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 87 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 106 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 107 { 0xFFFFFFFF } 108 }; 109 110 static const struct si_cac_config_reg lcac_tahiti[] = 111 { 112 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 119 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 135 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 159 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 171 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 185 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 197 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 198 { 0xFFFFFFFF } 199 200 }; 201 202 static const struct si_cac_config_reg cac_override_tahiti[] = 203 { 204 { 0xFFFFFFFF } 205 }; 206 207 static const struct si_powertune_data powertune_data_tahiti = 208 { 209 ((1 << 16) | 27027), 210 6, 211 0, 212 4, 213 95, 214 { 215 0UL, 216 0UL, 217 4521550UL, 218 309631529UL, 219 -1270850L, 220 4513710L, 221 40 222 }, 223 595000000UL, 224 12, 225 { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0 234 }, 235 true 236 }; 237 238 static const struct si_dte_data dte_data_tahiti = 239 { 240 { 1159409, 0, 0, 0, 0 }, 241 { 777, 0, 0, 0, 0 }, 242 2, 243 54000, 244 127000, 245 25, 246 2, 247 10, 248 13, 249 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 250 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 251 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 252 85, 253 false 254 }; 255 256 static const struct si_dte_data dte_data_tahiti_le = 257 { 258 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 259 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 260 0x5, 261 0xAFC8, 262 0x64, 263 0x32, 264 1, 265 0, 266 0x10, 267 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 268 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 269 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 270 85, 271 true 272 }; 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 static int si_populate_voltage_value(struct radeon_device *rdev, 1745 const struct atom_voltage_table *table, 1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1747 static int si_get_std_voltage_value(struct radeon_device *rdev, 1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1749 u16 *std_voltage); 1750 static int si_write_smc_soft_register(struct radeon_device *rdev, 1751 u16 reg_offset, u32 value); 1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1753 struct rv7xx_pl *pl, 1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1755 static int si_calculate_sclk_params(struct radeon_device *rdev, 1756 u32 engine_clock, 1757 SISLANDS_SMC_SCLK_VALUE *sclk); 1758 1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1760 { 1761 struct si_power_info *pi = rdev->pm.dpm.priv; 1762 1763 return pi; 1764 } 1765 1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1767 u16 v, s32 t, u32 ileakage, u32 *leakage) 1768 { 1769 s64 kt, kv, leakage_w, i_leakage, vddc; 1770 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1771 s64 tmp; 1772 1773 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1774 vddc = div64_s64(drm_int2fixp(v), 1000); 1775 temperature = div64_s64(drm_int2fixp(t), 1000); 1776 1777 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1778 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1779 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1780 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1781 t_ref = drm_int2fixp(coeff->t_ref); 1782 1783 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1784 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1785 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1786 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1787 1788 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1789 1790 *leakage = drm_fixp2int(leakage_w * 1000); 1791 } 1792 1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1794 const struct ni_leakage_coeffients *coeff, 1795 u16 v, 1796 s32 t, 1797 u32 i_leakage, 1798 u32 *leakage) 1799 { 1800 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1801 } 1802 1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1804 const u32 fixed_kt, u16 v, 1805 u32 ileakage, u32 *leakage) 1806 { 1807 s64 kt, kv, leakage_w, i_leakage, vddc; 1808 1809 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1810 vddc = div64_s64(drm_int2fixp(v), 1000); 1811 1812 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1813 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1814 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1815 1816 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1817 1818 *leakage = drm_fixp2int(leakage_w * 1000); 1819 } 1820 1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1822 const struct ni_leakage_coeffients *coeff, 1823 const u32 fixed_kt, 1824 u16 v, 1825 u32 i_leakage, 1826 u32 *leakage) 1827 { 1828 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1829 } 1830 1831 1832 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1833 struct si_dte_data *dte_data) 1834 { 1835 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1836 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1837 u32 k = dte_data->k; 1838 u32 t_max = dte_data->max_t; 1839 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1840 u32 t_0 = dte_data->t0; 1841 u32 i; 1842 1843 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1844 dte_data->tdep_count = 3; 1845 1846 for (i = 0; i < k; i++) { 1847 dte_data->r[i] = 1848 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1849 (p_limit2 * (u32)100); 1850 } 1851 1852 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1853 1854 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1855 dte_data->tdep_r[i] = dte_data->r[4]; 1856 } 1857 } else { 1858 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1859 } 1860 } 1861 1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1863 { 1864 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1865 struct si_power_info *si_pi = si_get_pi(rdev); 1866 bool update_dte_from_pl2 = false; 1867 1868 if (rdev->family == CHIP_TAHITI) { 1869 si_pi->cac_weights = cac_weights_tahiti; 1870 si_pi->lcac_config = lcac_tahiti; 1871 si_pi->cac_override = cac_override_tahiti; 1872 si_pi->powertune_data = &powertune_data_tahiti; 1873 si_pi->dte_data = dte_data_tahiti; 1874 1875 switch (rdev->ddev->pci_device) { 1876 case 0x6798: 1877 si_pi->dte_data.enable_dte_by_default = true; 1878 break; 1879 case 0x6799: 1880 si_pi->dte_data = dte_data_new_zealand; 1881 break; 1882 case 0x6790: 1883 case 0x6791: 1884 case 0x6792: 1885 case 0x679E: 1886 si_pi->dte_data = dte_data_aruba_pro; 1887 update_dte_from_pl2 = true; 1888 break; 1889 case 0x679B: 1890 si_pi->dte_data = dte_data_malta; 1891 update_dte_from_pl2 = true; 1892 break; 1893 case 0x679A: 1894 si_pi->dte_data = dte_data_tahiti_pro; 1895 update_dte_from_pl2 = true; 1896 break; 1897 default: 1898 if (si_pi->dte_data.enable_dte_by_default == true) 1899 DRM_ERROR("DTE is not enabled!\n"); 1900 break; 1901 } 1902 } else if (rdev->family == CHIP_PITCAIRN) { 1903 switch (rdev->ddev->pci_device) { 1904 case 0x6810: 1905 case 0x6818: 1906 si_pi->cac_weights = cac_weights_pitcairn; 1907 si_pi->lcac_config = lcac_pitcairn; 1908 si_pi->cac_override = cac_override_pitcairn; 1909 si_pi->powertune_data = &powertune_data_pitcairn; 1910 si_pi->dte_data = dte_data_curacao_xt; 1911 update_dte_from_pl2 = true; 1912 break; 1913 case 0x6819: 1914 case 0x6811: 1915 si_pi->cac_weights = cac_weights_pitcairn; 1916 si_pi->lcac_config = lcac_pitcairn; 1917 si_pi->cac_override = cac_override_pitcairn; 1918 si_pi->powertune_data = &powertune_data_pitcairn; 1919 si_pi->dte_data = dte_data_curacao_pro; 1920 update_dte_from_pl2 = true; 1921 break; 1922 case 0x6800: 1923 case 0x6806: 1924 si_pi->cac_weights = cac_weights_pitcairn; 1925 si_pi->lcac_config = lcac_pitcairn; 1926 si_pi->cac_override = cac_override_pitcairn; 1927 si_pi->powertune_data = &powertune_data_pitcairn; 1928 si_pi->dte_data = dte_data_neptune_xt; 1929 update_dte_from_pl2 = true; 1930 break; 1931 default: 1932 si_pi->cac_weights = cac_weights_pitcairn; 1933 si_pi->lcac_config = lcac_pitcairn; 1934 si_pi->cac_override = cac_override_pitcairn; 1935 si_pi->powertune_data = &powertune_data_pitcairn; 1936 si_pi->dte_data = dte_data_pitcairn; 1937 break; 1938 } 1939 } else if (rdev->family == CHIP_VERDE) { 1940 si_pi->lcac_config = lcac_cape_verde; 1941 si_pi->cac_override = cac_override_cape_verde; 1942 si_pi->powertune_data = &powertune_data_cape_verde; 1943 1944 switch (rdev->ddev->pci_device) { 1945 case 0x683B: 1946 case 0x683F: 1947 case 0x6829: 1948 case 0x6835: 1949 si_pi->cac_weights = cac_weights_cape_verde_pro; 1950 si_pi->dte_data = dte_data_cape_verde; 1951 break; 1952 case 0x6825: 1953 case 0x6827: 1954 si_pi->cac_weights = cac_weights_heathrow; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x6824: 1958 case 0x682D: 1959 si_pi->cac_weights = cac_weights_chelsea_xt; 1960 si_pi->dte_data = dte_data_cape_verde; 1961 break; 1962 case 0x682F: 1963 si_pi->cac_weights = cac_weights_chelsea_pro; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x6820: 1967 si_pi->cac_weights = cac_weights_heathrow; 1968 si_pi->dte_data = dte_data_venus_xtx; 1969 break; 1970 case 0x6821: 1971 si_pi->cac_weights = cac_weights_heathrow; 1972 si_pi->dte_data = dte_data_venus_xt; 1973 break; 1974 case 0x6823: 1975 si_pi->cac_weights = cac_weights_chelsea_pro; 1976 si_pi->dte_data = dte_data_venus_pro; 1977 break; 1978 case 0x682B: 1979 si_pi->cac_weights = cac_weights_chelsea_pro; 1980 si_pi->dte_data = dte_data_venus_pro; 1981 break; 1982 default: 1983 si_pi->cac_weights = cac_weights_cape_verde; 1984 si_pi->dte_data = dte_data_cape_verde; 1985 break; 1986 } 1987 } else if (rdev->family == CHIP_OLAND) { 1988 switch (rdev->ddev->pci_device) { 1989 case 0x6601: 1990 case 0x6621: 1991 case 0x6603: 1992 si_pi->cac_weights = cac_weights_mars_pro; 1993 si_pi->lcac_config = lcac_mars_pro; 1994 si_pi->cac_override = cac_override_oland; 1995 si_pi->powertune_data = &powertune_data_mars_pro; 1996 si_pi->dte_data = dte_data_mars_pro; 1997 update_dte_from_pl2 = true; 1998 break; 1999 case 0x6600: 2000 case 0x6606: 2001 case 0x6620: 2002 si_pi->cac_weights = cac_weights_mars_xt; 2003 si_pi->lcac_config = lcac_mars_pro; 2004 si_pi->cac_override = cac_override_oland; 2005 si_pi->powertune_data = &powertune_data_mars_pro; 2006 si_pi->dte_data = dte_data_mars_pro; 2007 update_dte_from_pl2 = true; 2008 break; 2009 case 0x6611: 2010 si_pi->cac_weights = cac_weights_oland_pro; 2011 si_pi->lcac_config = lcac_mars_pro; 2012 si_pi->cac_override = cac_override_oland; 2013 si_pi->powertune_data = &powertune_data_mars_pro; 2014 si_pi->dte_data = dte_data_mars_pro; 2015 update_dte_from_pl2 = true; 2016 break; 2017 case 0x6610: 2018 si_pi->cac_weights = cac_weights_oland_xt; 2019 si_pi->lcac_config = lcac_mars_pro; 2020 si_pi->cac_override = cac_override_oland; 2021 si_pi->powertune_data = &powertune_data_mars_pro; 2022 si_pi->dte_data = dte_data_mars_pro; 2023 update_dte_from_pl2 = true; 2024 break; 2025 default: 2026 si_pi->cac_weights = cac_weights_oland; 2027 si_pi->lcac_config = lcac_oland; 2028 si_pi->cac_override = cac_override_oland; 2029 si_pi->powertune_data = &powertune_data_oland; 2030 si_pi->dte_data = dte_data_oland; 2031 break; 2032 } 2033 } else if (rdev->family == CHIP_HAINAN) { 2034 si_pi->cac_weights = cac_weights_hainan; 2035 si_pi->lcac_config = lcac_oland; 2036 si_pi->cac_override = cac_override_oland; 2037 si_pi->powertune_data = &powertune_data_hainan; 2038 si_pi->dte_data = dte_data_sun_xt; 2039 update_dte_from_pl2 = true; 2040 } else { 2041 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2042 return; 2043 } 2044 2045 ni_pi->enable_power_containment = false; 2046 ni_pi->enable_cac = false; 2047 ni_pi->enable_sq_ramping = false; 2048 si_pi->enable_dte = false; 2049 2050 if (si_pi->powertune_data->enable_powertune_by_default) { 2051 ni_pi->enable_power_containment= true; 2052 ni_pi->enable_cac = true; 2053 if (si_pi->dte_data.enable_dte_by_default) { 2054 si_pi->enable_dte = true; 2055 if (update_dte_from_pl2) 2056 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2057 2058 } 2059 ni_pi->enable_sq_ramping = true; 2060 } 2061 2062 ni_pi->driver_calculate_cac_leakage = true; 2063 ni_pi->cac_configuration_required = true; 2064 2065 if (ni_pi->cac_configuration_required) { 2066 ni_pi->support_cac_long_term_average = true; 2067 si_pi->dyn_powertune_data.l2_lta_window_size = 2068 si_pi->powertune_data->l2_lta_window_size_default; 2069 si_pi->dyn_powertune_data.lts_truncate = 2070 si_pi->powertune_data->lts_truncate_default; 2071 } else { 2072 ni_pi->support_cac_long_term_average = false; 2073 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2074 si_pi->dyn_powertune_data.lts_truncate = 0; 2075 } 2076 2077 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2078 } 2079 2080 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2081 { 2082 return 1; 2083 } 2084 2085 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2086 { 2087 u32 xclk; 2088 u32 wintime; 2089 u32 cac_window; 2090 u32 cac_window_size; 2091 2092 xclk = radeon_get_xclk(rdev); 2093 2094 if (xclk == 0) 2095 return 0; 2096 2097 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2098 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2099 2100 wintime = (cac_window_size * 100) / xclk; 2101 2102 return wintime; 2103 } 2104 2105 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2106 { 2107 return power_in_watts; 2108 } 2109 2110 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2111 bool adjust_polarity, 2112 u32 tdp_adjustment, 2113 u32 *tdp_limit, 2114 u32 *near_tdp_limit) 2115 { 2116 u32 adjustment_delta, max_tdp_limit; 2117 2118 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2119 return -EINVAL; 2120 2121 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2122 2123 if (adjust_polarity) { 2124 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2126 } else { 2127 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2128 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2129 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2130 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2131 else 2132 *near_tdp_limit = 0; 2133 } 2134 2135 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2136 return -EINVAL; 2137 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2138 return -EINVAL; 2139 2140 return 0; 2141 } 2142 2143 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2144 struct radeon_ps *radeon_state) 2145 { 2146 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2147 struct si_power_info *si_pi = si_get_pi(rdev); 2148 2149 if (ni_pi->enable_power_containment) { 2150 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2151 PP_SIslands_PAPMParameters *papm_parm; 2152 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2153 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2154 u32 tdp_limit; 2155 u32 near_tdp_limit; 2156 int ret; 2157 2158 if (scaling_factor == 0) 2159 return -EINVAL; 2160 2161 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2162 2163 ret = si_calculate_adjusted_tdp_limits(rdev, 2164 false, /* ??? */ 2165 rdev->pm.dpm.tdp_adjustment, 2166 &tdp_limit, 2167 &near_tdp_limit); 2168 if (ret) 2169 return ret; 2170 2171 smc_table->dpm2Params.TDPLimit = 2172 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2173 smc_table->dpm2Params.NearTDPLimit = 2174 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2175 smc_table->dpm2Params.SafePowerLimit = 2176 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2177 2178 ret = si_copy_bytes_to_smc(rdev, 2179 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2180 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2181 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2182 sizeof(u32) * 3, 2183 si_pi->sram_end); 2184 if (ret) 2185 return ret; 2186 2187 if (si_pi->enable_ppm) { 2188 papm_parm = &si_pi->papm_parm; 2189 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2190 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2191 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2192 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2193 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2194 papm_parm->PlatformPowerLimit = 0xffffffff; 2195 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2196 2197 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2198 (u8 *)papm_parm, 2199 sizeof(PP_SIslands_PAPMParameters), 2200 si_pi->sram_end); 2201 if (ret) 2202 return ret; 2203 } 2204 } 2205 return 0; 2206 } 2207 2208 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2209 struct radeon_ps *radeon_state) 2210 { 2211 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2212 struct si_power_info *si_pi = si_get_pi(rdev); 2213 2214 if (ni_pi->enable_power_containment) { 2215 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2216 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2217 int ret; 2218 2219 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2220 2221 smc_table->dpm2Params.NearTDPLimit = 2222 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2223 smc_table->dpm2Params.SafePowerLimit = 2224 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2225 2226 ret = si_copy_bytes_to_smc(rdev, 2227 (si_pi->state_table_start + 2228 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2229 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2230 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2231 sizeof(u32) * 2, 2232 si_pi->sram_end); 2233 if (ret) 2234 return ret; 2235 } 2236 2237 return 0; 2238 } 2239 2240 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2241 const u16 prev_std_vddc, 2242 const u16 curr_std_vddc) 2243 { 2244 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2245 u64 prev_vddc = (u64)prev_std_vddc; 2246 u64 curr_vddc = (u64)curr_std_vddc; 2247 u64 pwr_efficiency_ratio, n, d; 2248 2249 if ((prev_vddc == 0) || (curr_vddc == 0)) 2250 return 0; 2251 2252 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2253 d = prev_vddc * prev_vddc; 2254 pwr_efficiency_ratio = div64_u64(n, d); 2255 2256 if (pwr_efficiency_ratio > (u64)0xFFFF) 2257 return 0; 2258 2259 return (u16)pwr_efficiency_ratio; 2260 } 2261 2262 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2263 struct radeon_ps *radeon_state) 2264 { 2265 struct si_power_info *si_pi = si_get_pi(rdev); 2266 2267 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2268 radeon_state->vclk && radeon_state->dclk) 2269 return true; 2270 2271 return false; 2272 } 2273 2274 static int si_populate_power_containment_values(struct radeon_device *rdev, 2275 struct radeon_ps *radeon_state, 2276 SISLANDS_SMC_SWSTATE *smc_state) 2277 { 2278 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2279 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2280 struct ni_ps *state = ni_get_ps(radeon_state); 2281 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2282 u32 prev_sclk; 2283 u32 max_sclk; 2284 u32 min_sclk; 2285 u16 prev_std_vddc; 2286 u16 curr_std_vddc; 2287 int i; 2288 u16 pwr_efficiency_ratio; 2289 u8 max_ps_percent; 2290 bool disable_uvd_power_tune; 2291 int ret; 2292 2293 if (ni_pi->enable_power_containment == false) 2294 return 0; 2295 2296 if (state->performance_level_count == 0) 2297 return -EINVAL; 2298 2299 if (smc_state->levelCount != state->performance_level_count) 2300 return -EINVAL; 2301 2302 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2303 2304 smc_state->levels[0].dpm2.MaxPS = 0; 2305 smc_state->levels[0].dpm2.NearTDPDec = 0; 2306 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2307 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2308 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2309 2310 for (i = 1; i < state->performance_level_count; i++) { 2311 prev_sclk = state->performance_levels[i-1].sclk; 2312 max_sclk = state->performance_levels[i].sclk; 2313 if (i == 1) 2314 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2315 else 2316 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2317 2318 if (prev_sclk > max_sclk) 2319 return -EINVAL; 2320 2321 if ((max_ps_percent == 0) || 2322 (prev_sclk == max_sclk) || 2323 disable_uvd_power_tune) { 2324 min_sclk = max_sclk; 2325 } else if (i == 1) { 2326 min_sclk = prev_sclk; 2327 } else { 2328 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2329 } 2330 2331 if (min_sclk < state->performance_levels[0].sclk) 2332 min_sclk = state->performance_levels[0].sclk; 2333 2334 if (min_sclk == 0) 2335 return -EINVAL; 2336 2337 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2338 state->performance_levels[i-1].vddc, &vddc); 2339 if (ret) 2340 return ret; 2341 2342 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2343 if (ret) 2344 return ret; 2345 2346 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2347 state->performance_levels[i].vddc, &vddc); 2348 if (ret) 2349 return ret; 2350 2351 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2352 if (ret) 2353 return ret; 2354 2355 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2356 prev_std_vddc, curr_std_vddc); 2357 2358 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2359 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2360 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2361 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2362 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2363 } 2364 2365 return 0; 2366 } 2367 2368 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2369 struct radeon_ps *radeon_state, 2370 SISLANDS_SMC_SWSTATE *smc_state) 2371 { 2372 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2373 struct ni_ps *state = ni_get_ps(radeon_state); 2374 u32 sq_power_throttle, sq_power_throttle2; 2375 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2376 int i; 2377 2378 if (state->performance_level_count == 0) 2379 return -EINVAL; 2380 2381 if (smc_state->levelCount != state->performance_level_count) 2382 return -EINVAL; 2383 2384 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2385 return -EINVAL; 2386 2387 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2388 enable_sq_ramping = false; 2389 2390 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2391 enable_sq_ramping = false; 2392 2393 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2394 enable_sq_ramping = false; 2395 2396 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2397 enable_sq_ramping = false; 2398 2399 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 for (i = 0; i < state->performance_level_count; i++) { 2403 sq_power_throttle = 0; 2404 sq_power_throttle2 = 0; 2405 2406 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2407 enable_sq_ramping) { 2408 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2409 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2410 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2411 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2412 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2413 } else { 2414 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2415 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2416 } 2417 2418 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2419 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2420 } 2421 2422 return 0; 2423 } 2424 2425 static int si_enable_power_containment(struct radeon_device *rdev, 2426 struct radeon_ps *radeon_new_state, 2427 bool enable) 2428 { 2429 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2430 PPSMC_Result smc_result; 2431 int ret = 0; 2432 2433 if (ni_pi->enable_power_containment) { 2434 if (enable) { 2435 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2436 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2437 if (smc_result != PPSMC_Result_OK) { 2438 ret = -EINVAL; 2439 ni_pi->pc_enabled = false; 2440 } else { 2441 ni_pi->pc_enabled = true; 2442 } 2443 } 2444 } else { 2445 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2446 if (smc_result != PPSMC_Result_OK) 2447 ret = -EINVAL; 2448 ni_pi->pc_enabled = false; 2449 } 2450 } 2451 2452 return ret; 2453 } 2454 2455 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2456 { 2457 struct si_power_info *si_pi = si_get_pi(rdev); 2458 int ret = 0; 2459 struct si_dte_data *dte_data = &si_pi->dte_data; 2460 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2461 u32 table_size; 2462 u8 tdep_count; 2463 u32 i; 2464 2465 if (dte_data == NULL) 2466 si_pi->enable_dte = false; 2467 2468 if (si_pi->enable_dte == false) 2469 return 0; 2470 2471 if (dte_data->k <= 0) 2472 return -EINVAL; 2473 2474 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2475 if (dte_tables == NULL) { 2476 si_pi->enable_dte = false; 2477 return -ENOMEM; 2478 } 2479 2480 table_size = dte_data->k; 2481 2482 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2483 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2484 2485 tdep_count = dte_data->tdep_count; 2486 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2487 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2488 2489 dte_tables->K = cpu_to_be32(table_size); 2490 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2491 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2492 dte_tables->WindowSize = dte_data->window_size; 2493 dte_tables->temp_select = dte_data->temp_select; 2494 dte_tables->DTE_mode = dte_data->dte_mode; 2495 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2496 2497 if (tdep_count > 0) 2498 table_size--; 2499 2500 for (i = 0; i < table_size; i++) { 2501 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2502 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2503 } 2504 2505 dte_tables->Tdep_count = tdep_count; 2506 2507 for (i = 0; i < (u32)tdep_count; i++) { 2508 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2509 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2510 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2511 } 2512 2513 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2514 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2515 kfree(dte_tables); 2516 2517 return ret; 2518 } 2519 2520 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2521 u16 *max, u16 *min) 2522 { 2523 struct si_power_info *si_pi = si_get_pi(rdev); 2524 struct radeon_cac_leakage_table *table = 2525 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2526 u32 i; 2527 u32 v0_loadline; 2528 2529 2530 if (table == NULL) 2531 return -EINVAL; 2532 2533 *max = 0; 2534 *min = 0xFFFF; 2535 2536 for (i = 0; i < table->count; i++) { 2537 if (table->entries[i].vddc > *max) 2538 *max = table->entries[i].vddc; 2539 if (table->entries[i].vddc < *min) 2540 *min = table->entries[i].vddc; 2541 } 2542 2543 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2544 return -EINVAL; 2545 2546 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2547 2548 if (v0_loadline > 0xFFFFUL) 2549 return -EINVAL; 2550 2551 *min = (u16)v0_loadline; 2552 2553 if ((*min > *max) || (*max == 0) || (*min == 0)) 2554 return -EINVAL; 2555 2556 return 0; 2557 } 2558 2559 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2560 { 2561 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2562 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2563 } 2564 2565 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2566 PP_SIslands_CacConfig *cac_tables, 2567 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2568 u16 t0, u16 t_step) 2569 { 2570 struct si_power_info *si_pi = si_get_pi(rdev); 2571 u32 leakage; 2572 unsigned int i, j; 2573 s32 t; 2574 u32 smc_leakage; 2575 u32 scaling_factor; 2576 u16 voltage; 2577 2578 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2579 2580 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2581 t = (1000 * (i * t_step + t0)); 2582 2583 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2584 voltage = vddc_max - (vddc_step * j); 2585 2586 si_calculate_leakage_for_v_and_t(rdev, 2587 &si_pi->powertune_data->leakage_coefficients, 2588 voltage, 2589 t, 2590 si_pi->dyn_powertune_data.cac_leakage, 2591 &leakage); 2592 2593 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2594 2595 if (smc_leakage > 0xFFFF) 2596 smc_leakage = 0xFFFF; 2597 2598 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2599 cpu_to_be16((u16)smc_leakage); 2600 } 2601 } 2602 return 0; 2603 } 2604 2605 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2606 PP_SIslands_CacConfig *cac_tables, 2607 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2608 { 2609 struct si_power_info *si_pi = si_get_pi(rdev); 2610 u32 leakage; 2611 unsigned int i, j; 2612 u32 smc_leakage; 2613 u32 scaling_factor; 2614 u16 voltage; 2615 2616 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2617 2618 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2619 voltage = vddc_max - (vddc_step * j); 2620 2621 si_calculate_leakage_for_v(rdev, 2622 &si_pi->powertune_data->leakage_coefficients, 2623 si_pi->powertune_data->fixed_kt, 2624 voltage, 2625 si_pi->dyn_powertune_data.cac_leakage, 2626 &leakage); 2627 2628 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2629 2630 if (smc_leakage > 0xFFFF) 2631 smc_leakage = 0xFFFF; 2632 2633 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2634 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2635 cpu_to_be16((u16)smc_leakage); 2636 } 2637 return 0; 2638 } 2639 2640 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2641 { 2642 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2643 struct si_power_info *si_pi = si_get_pi(rdev); 2644 PP_SIslands_CacConfig *cac_tables = NULL; 2645 u16 vddc_max, vddc_min, vddc_step; 2646 u16 t0, t_step; 2647 u32 load_line_slope, reg; 2648 int ret = 0; 2649 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2650 2651 if (ni_pi->enable_cac == false) 2652 return 0; 2653 2654 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2655 if (!cac_tables) 2656 return -ENOMEM; 2657 2658 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2659 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2660 WREG32(CG_CAC_CTRL, reg); 2661 2662 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2663 si_pi->dyn_powertune_data.dc_pwr_value = 2664 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2665 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2666 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2667 2668 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2669 2670 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2671 if (ret) 2672 goto done_free; 2673 2674 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2675 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2676 t_step = 4; 2677 t0 = 60; 2678 2679 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2680 ret = si_init_dte_leakage_table(rdev, cac_tables, 2681 vddc_max, vddc_min, vddc_step, 2682 t0, t_step); 2683 else 2684 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2685 vddc_max, vddc_min, vddc_step); 2686 if (ret) 2687 goto done_free; 2688 2689 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2690 2691 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2692 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2693 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2694 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2695 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2696 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2697 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2698 cac_tables->calculation_repeats = cpu_to_be32(2); 2699 cac_tables->dc_cac = cpu_to_be32(0); 2700 cac_tables->log2_PG_LKG_SCALE = 12; 2701 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2702 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2703 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2704 2705 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2706 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2707 2708 if (ret) 2709 goto done_free; 2710 2711 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2712 2713 done_free: 2714 if (ret) { 2715 ni_pi->enable_cac = false; 2716 ni_pi->enable_power_containment = false; 2717 } 2718 2719 kfree(cac_tables); 2720 2721 return 0; 2722 } 2723 2724 static int si_program_cac_config_registers(struct radeon_device *rdev, 2725 const struct si_cac_config_reg *cac_config_regs) 2726 { 2727 const struct si_cac_config_reg *config_regs = cac_config_regs; 2728 u32 data = 0, offset; 2729 2730 if (!config_regs) 2731 return -EINVAL; 2732 2733 while (config_regs->offset != 0xFFFFFFFF) { 2734 switch (config_regs->type) { 2735 case SISLANDS_CACCONFIG_CGIND: 2736 offset = SMC_CG_IND_START + config_regs->offset; 2737 if (offset < SMC_CG_IND_END) 2738 data = RREG32_SMC(offset); 2739 break; 2740 default: 2741 data = RREG32(config_regs->offset << 2); 2742 break; 2743 } 2744 2745 data &= ~config_regs->mask; 2746 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2747 2748 switch (config_regs->type) { 2749 case SISLANDS_CACCONFIG_CGIND: 2750 offset = SMC_CG_IND_START + config_regs->offset; 2751 if (offset < SMC_CG_IND_END) 2752 WREG32_SMC(offset, data); 2753 break; 2754 default: 2755 WREG32(config_regs->offset << 2, data); 2756 break; 2757 } 2758 config_regs++; 2759 } 2760 return 0; 2761 } 2762 2763 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2764 { 2765 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2766 struct si_power_info *si_pi = si_get_pi(rdev); 2767 int ret; 2768 2769 if ((ni_pi->enable_cac == false) || 2770 (ni_pi->cac_configuration_required == false)) 2771 return 0; 2772 2773 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2774 if (ret) 2775 return ret; 2776 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2777 if (ret) 2778 return ret; 2779 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2780 if (ret) 2781 return ret; 2782 2783 return 0; 2784 } 2785 2786 static int si_enable_smc_cac(struct radeon_device *rdev, 2787 struct radeon_ps *radeon_new_state, 2788 bool enable) 2789 { 2790 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2791 struct si_power_info *si_pi = si_get_pi(rdev); 2792 PPSMC_Result smc_result; 2793 int ret = 0; 2794 2795 if (ni_pi->enable_cac) { 2796 if (enable) { 2797 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2798 if (ni_pi->support_cac_long_term_average) { 2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2800 if (smc_result != PPSMC_Result_OK) 2801 ni_pi->support_cac_long_term_average = false; 2802 } 2803 2804 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2805 if (smc_result != PPSMC_Result_OK) { 2806 ret = -EINVAL; 2807 ni_pi->cac_enabled = false; 2808 } else { 2809 ni_pi->cac_enabled = true; 2810 } 2811 2812 if (si_pi->enable_dte) { 2813 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2814 if (smc_result != PPSMC_Result_OK) 2815 ret = -EINVAL; 2816 } 2817 } 2818 } else if (ni_pi->cac_enabled) { 2819 if (si_pi->enable_dte) 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2821 2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2823 2824 ni_pi->cac_enabled = false; 2825 2826 if (ni_pi->support_cac_long_term_average) 2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2828 } 2829 } 2830 return ret; 2831 } 2832 2833 static int si_init_smc_spll_table(struct radeon_device *rdev) 2834 { 2835 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2836 struct si_power_info *si_pi = si_get_pi(rdev); 2837 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2838 SISLANDS_SMC_SCLK_VALUE sclk_params; 2839 u32 fb_div, p_div; 2840 u32 clk_s, clk_v; 2841 u32 sclk = 0; 2842 int ret = 0; 2843 u32 tmp; 2844 int i; 2845 2846 if (si_pi->spll_table_start == 0) 2847 return -EINVAL; 2848 2849 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2850 if (spll_table == NULL) 2851 return -ENOMEM; 2852 2853 for (i = 0; i < 256; i++) { 2854 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2855 if (ret) 2856 break; 2857 2858 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2859 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2860 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2861 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2862 2863 fb_div &= ~0x00001FFF; 2864 fb_div >>= 1; 2865 clk_v >>= 6; 2866 2867 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2868 ret = -EINVAL; 2869 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2870 ret = -EINVAL; 2871 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2872 ret = -EINVAL; 2873 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2874 ret = -EINVAL; 2875 2876 if (ret) 2877 break; 2878 2879 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2880 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2881 spll_table->freq[i] = cpu_to_be32(tmp); 2882 2883 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2884 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2885 spll_table->ss[i] = cpu_to_be32(tmp); 2886 2887 sclk += 512; 2888 } 2889 2890 2891 if (!ret) 2892 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2893 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2894 si_pi->sram_end); 2895 2896 if (ret) 2897 ni_pi->enable_power_containment = false; 2898 2899 kfree(spll_table); 2900 2901 return ret; 2902 } 2903 2904 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2905 struct radeon_ps *rps) 2906 { 2907 struct ni_ps *ps = ni_get_ps(rps); 2908 struct radeon_clock_and_voltage_limits *max_limits; 2909 bool disable_mclk_switching = false; 2910 bool disable_sclk_switching = false; 2911 u32 mclk, sclk; 2912 u16 vddc, vddci; 2913 int i; 2914 2915 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2916 ni_dpm_vblank_too_short(rdev)) 2917 disable_mclk_switching = true; 2918 2919 if (rps->vclk || rps->dclk) { 2920 disable_mclk_switching = true; 2921 disable_sclk_switching = true; 2922 } 2923 2924 if (rdev->pm.dpm.ac_power) 2925 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2926 else 2927 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2928 2929 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2930 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2931 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2932 } 2933 if (rdev->pm.dpm.ac_power == false) { 2934 for (i = 0; i < ps->performance_level_count; i++) { 2935 if (ps->performance_levels[i].mclk > max_limits->mclk) 2936 ps->performance_levels[i].mclk = max_limits->mclk; 2937 if (ps->performance_levels[i].sclk > max_limits->sclk) 2938 ps->performance_levels[i].sclk = max_limits->sclk; 2939 if (ps->performance_levels[i].vddc > max_limits->vddc) 2940 ps->performance_levels[i].vddc = max_limits->vddc; 2941 if (ps->performance_levels[i].vddci > max_limits->vddci) 2942 ps->performance_levels[i].vddci = max_limits->vddci; 2943 } 2944 } 2945 2946 /* XXX validate the min clocks required for display */ 2947 2948 if (disable_mclk_switching) { 2949 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2950 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2951 } else { 2952 mclk = ps->performance_levels[0].mclk; 2953 vddci = ps->performance_levels[0].vddci; 2954 } 2955 2956 if (disable_sclk_switching) { 2957 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2958 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2959 } else { 2960 sclk = ps->performance_levels[0].sclk; 2961 vddc = ps->performance_levels[0].vddc; 2962 } 2963 2964 /* adjusted low state */ 2965 ps->performance_levels[0].sclk = sclk; 2966 ps->performance_levels[0].mclk = mclk; 2967 ps->performance_levels[0].vddc = vddc; 2968 ps->performance_levels[0].vddci = vddci; 2969 2970 if (disable_sclk_switching) { 2971 sclk = ps->performance_levels[0].sclk; 2972 for (i = 1; i < ps->performance_level_count; i++) { 2973 if (sclk < ps->performance_levels[i].sclk) 2974 sclk = ps->performance_levels[i].sclk; 2975 } 2976 for (i = 0; i < ps->performance_level_count; i++) { 2977 ps->performance_levels[i].sclk = sclk; 2978 ps->performance_levels[i].vddc = vddc; 2979 } 2980 } else { 2981 for (i = 1; i < ps->performance_level_count; i++) { 2982 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2983 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2984 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2985 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2986 } 2987 } 2988 2989 if (disable_mclk_switching) { 2990 mclk = ps->performance_levels[0].mclk; 2991 for (i = 1; i < ps->performance_level_count; i++) { 2992 if (mclk < ps->performance_levels[i].mclk) 2993 mclk = ps->performance_levels[i].mclk; 2994 } 2995 for (i = 0; i < ps->performance_level_count; i++) { 2996 ps->performance_levels[i].mclk = mclk; 2997 ps->performance_levels[i].vddci = vddci; 2998 } 2999 } else { 3000 for (i = 1; i < ps->performance_level_count; i++) { 3001 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3002 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3003 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3004 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3005 } 3006 } 3007 3008 for (i = 0; i < ps->performance_level_count; i++) 3009 btc_adjust_clock_combinations(rdev, max_limits, 3010 &ps->performance_levels[i]); 3011 3012 for (i = 0; i < ps->performance_level_count; i++) { 3013 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3014 ps->performance_levels[i].sclk, 3015 max_limits->vddc, &ps->performance_levels[i].vddc); 3016 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3017 ps->performance_levels[i].mclk, 3018 max_limits->vddci, &ps->performance_levels[i].vddci); 3019 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3020 ps->performance_levels[i].mclk, 3021 max_limits->vddc, &ps->performance_levels[i].vddc); 3022 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3023 rdev->clock.current_dispclk, 3024 max_limits->vddc, &ps->performance_levels[i].vddc); 3025 } 3026 3027 for (i = 0; i < ps->performance_level_count; i++) { 3028 btc_apply_voltage_delta_rules(rdev, 3029 max_limits->vddc, max_limits->vddci, 3030 &ps->performance_levels[i].vddc, 3031 &ps->performance_levels[i].vddci); 3032 } 3033 3034 ps->dc_compatible = true; 3035 for (i = 0; i < ps->performance_level_count; i++) { 3036 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3037 ps->dc_compatible = false; 3038 } 3039 3040 } 3041 3042 #if 0 3043 static int si_read_smc_soft_register(struct radeon_device *rdev, 3044 u16 reg_offset, u32 *value) 3045 { 3046 struct si_power_info *si_pi = si_get_pi(rdev); 3047 3048 return si_read_smc_sram_dword(rdev, 3049 si_pi->soft_regs_start + reg_offset, value, 3050 si_pi->sram_end); 3051 } 3052 #endif 3053 3054 static int si_write_smc_soft_register(struct radeon_device *rdev, 3055 u16 reg_offset, u32 value) 3056 { 3057 struct si_power_info *si_pi = si_get_pi(rdev); 3058 3059 return si_write_smc_sram_dword(rdev, 3060 si_pi->soft_regs_start + reg_offset, 3061 value, si_pi->sram_end); 3062 } 3063 3064 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3065 { 3066 bool ret = false; 3067 u32 tmp, width, row, column, bank, density; 3068 bool is_memory_gddr5, is_special; 3069 3070 tmp = RREG32(MC_SEQ_MISC0); 3071 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3072 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3073 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3074 3075 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3076 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3077 3078 tmp = RREG32(MC_ARB_RAMCFG); 3079 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3080 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3081 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3082 3083 density = (1 << (row + column - 20 + bank)) * width; 3084 3085 if ((rdev->ddev->pci_device == 0x6819) && 3086 is_memory_gddr5 && is_special && (density == 0x400)) 3087 ret = true; 3088 3089 return ret; 3090 } 3091 3092 static void si_get_leakage_vddc(struct radeon_device *rdev) 3093 { 3094 struct si_power_info *si_pi = si_get_pi(rdev); 3095 u16 vddc, count = 0; 3096 int i, ret; 3097 3098 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3099 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3100 3101 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3102 si_pi->leakage_voltage.entries[count].voltage = vddc; 3103 si_pi->leakage_voltage.entries[count].leakage_index = 3104 SISLANDS_LEAKAGE_INDEX0 + i; 3105 count++; 3106 } 3107 } 3108 si_pi->leakage_voltage.count = count; 3109 } 3110 3111 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3112 u32 index, u16 *leakage_voltage) 3113 { 3114 struct si_power_info *si_pi = si_get_pi(rdev); 3115 int i; 3116 3117 if (leakage_voltage == NULL) 3118 return -EINVAL; 3119 3120 if ((index & 0xff00) != 0xff00) 3121 return -EINVAL; 3122 3123 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3124 return -EINVAL; 3125 3126 if (index < SISLANDS_LEAKAGE_INDEX0) 3127 return -EINVAL; 3128 3129 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3130 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3131 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3132 return 0; 3133 } 3134 } 3135 return -EAGAIN; 3136 } 3137 3138 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3139 { 3140 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3141 bool want_thermal_protection; 3142 enum radeon_dpm_event_src dpm_event_src; 3143 3144 switch (sources) { 3145 case 0: 3146 default: 3147 want_thermal_protection = false; 3148 break; 3149 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3150 want_thermal_protection = true; 3151 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3152 break; 3153 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3154 want_thermal_protection = true; 3155 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3156 break; 3157 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3158 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3159 want_thermal_protection = true; 3160 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3161 break; 3162 } 3163 3164 if (want_thermal_protection) { 3165 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3166 if (pi->thermal_protection) 3167 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3168 } else { 3169 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3170 } 3171 } 3172 3173 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3174 enum radeon_dpm_auto_throttle_src source, 3175 bool enable) 3176 { 3177 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3178 3179 if (enable) { 3180 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3181 pi->active_auto_throttle_sources |= 1 << source; 3182 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3183 } 3184 } else { 3185 if (pi->active_auto_throttle_sources & (1 << source)) { 3186 pi->active_auto_throttle_sources &= ~(1 << source); 3187 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3188 } 3189 } 3190 } 3191 3192 static void si_start_dpm(struct radeon_device *rdev) 3193 { 3194 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3195 } 3196 3197 static void si_stop_dpm(struct radeon_device *rdev) 3198 { 3199 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3200 } 3201 3202 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3203 { 3204 if (enable) 3205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3206 else 3207 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3208 3209 } 3210 3211 #if 0 3212 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3213 u32 thermal_level) 3214 { 3215 PPSMC_Result ret; 3216 3217 if (thermal_level == 0) { 3218 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3219 if (ret == PPSMC_Result_OK) 3220 return 0; 3221 else 3222 return -EINVAL; 3223 } 3224 return 0; 3225 } 3226 3227 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3228 { 3229 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3230 } 3231 #endif 3232 3233 #if 0 3234 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3235 { 3236 if (ac_power) 3237 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3238 0 : -EINVAL; 3239 3240 return 0; 3241 } 3242 #endif 3243 3244 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3245 PPSMC_Msg msg, u32 parameter) 3246 { 3247 WREG32(SMC_SCRATCH0, parameter); 3248 return si_send_msg_to_smc(rdev, msg); 3249 } 3250 3251 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3252 { 3253 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3254 return -EINVAL; 3255 3256 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3257 0 : -EINVAL; 3258 } 3259 3260 int si_dpm_force_performance_level(struct radeon_device *rdev, 3261 enum radeon_dpm_forced_level level) 3262 { 3263 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3264 struct ni_ps *ps = ni_get_ps(rps); 3265 u32 levels = ps->performance_level_count; 3266 3267 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3268 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3269 return -EINVAL; 3270 3271 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3272 return -EINVAL; 3273 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3274 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3275 return -EINVAL; 3276 3277 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3278 return -EINVAL; 3279 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3280 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3281 return -EINVAL; 3282 3283 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3284 return -EINVAL; 3285 } 3286 3287 rdev->pm.dpm.forced_level = level; 3288 3289 return 0; 3290 } 3291 3292 static int si_set_boot_state(struct radeon_device *rdev) 3293 { 3294 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3295 0 : -EINVAL; 3296 } 3297 3298 static int si_set_sw_state(struct radeon_device *rdev) 3299 { 3300 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3301 0 : -EINVAL; 3302 } 3303 3304 static int si_halt_smc(struct radeon_device *rdev) 3305 { 3306 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3307 return -EINVAL; 3308 3309 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3310 0 : -EINVAL; 3311 } 3312 3313 static int si_resume_smc(struct radeon_device *rdev) 3314 { 3315 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3316 return -EINVAL; 3317 3318 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3319 0 : -EINVAL; 3320 } 3321 3322 static void si_dpm_start_smc(struct radeon_device *rdev) 3323 { 3324 si_program_jump_on_start(rdev); 3325 si_start_smc(rdev); 3326 si_start_smc_clock(rdev); 3327 } 3328 3329 static void si_dpm_stop_smc(struct radeon_device *rdev) 3330 { 3331 si_reset_smc(rdev); 3332 si_stop_smc_clock(rdev); 3333 } 3334 3335 static int si_process_firmware_header(struct radeon_device *rdev) 3336 { 3337 struct si_power_info *si_pi = si_get_pi(rdev); 3338 u32 tmp; 3339 int ret; 3340 3341 ret = si_read_smc_sram_dword(rdev, 3342 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3343 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3344 &tmp, si_pi->sram_end); 3345 if (ret) 3346 return ret; 3347 3348 si_pi->state_table_start = tmp; 3349 3350 ret = si_read_smc_sram_dword(rdev, 3351 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3352 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3353 &tmp, si_pi->sram_end); 3354 if (ret) 3355 return ret; 3356 3357 si_pi->soft_regs_start = tmp; 3358 3359 ret = si_read_smc_sram_dword(rdev, 3360 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3361 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3362 &tmp, si_pi->sram_end); 3363 if (ret) 3364 return ret; 3365 3366 si_pi->mc_reg_table_start = tmp; 3367 3368 ret = si_read_smc_sram_dword(rdev, 3369 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3370 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3371 &tmp, si_pi->sram_end); 3372 if (ret) 3373 return ret; 3374 3375 si_pi->arb_table_start = tmp; 3376 3377 ret = si_read_smc_sram_dword(rdev, 3378 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3379 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3380 &tmp, si_pi->sram_end); 3381 if (ret) 3382 return ret; 3383 3384 si_pi->cac_table_start = tmp; 3385 3386 ret = si_read_smc_sram_dword(rdev, 3387 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3388 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3389 &tmp, si_pi->sram_end); 3390 if (ret) 3391 return ret; 3392 3393 si_pi->dte_table_start = tmp; 3394 3395 ret = si_read_smc_sram_dword(rdev, 3396 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3397 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3398 &tmp, si_pi->sram_end); 3399 if (ret) 3400 return ret; 3401 3402 si_pi->spll_table_start = tmp; 3403 3404 ret = si_read_smc_sram_dword(rdev, 3405 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3406 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3407 &tmp, si_pi->sram_end); 3408 if (ret) 3409 return ret; 3410 3411 si_pi->papm_cfg_table_start = tmp; 3412 3413 return ret; 3414 } 3415 3416 static void si_read_clock_registers(struct radeon_device *rdev) 3417 { 3418 struct si_power_info *si_pi = si_get_pi(rdev); 3419 3420 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3421 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3422 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3423 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3424 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3425 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3426 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3427 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3428 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3429 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3430 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3431 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3432 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3433 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3434 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3435 } 3436 3437 static void si_enable_thermal_protection(struct radeon_device *rdev, 3438 bool enable) 3439 { 3440 if (enable) 3441 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3442 else 3443 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3444 } 3445 3446 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3447 { 3448 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3449 } 3450 3451 #if 0 3452 static int si_enter_ulp_state(struct radeon_device *rdev) 3453 { 3454 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3455 3456 udelay(25000); 3457 3458 return 0; 3459 } 3460 3461 static int si_exit_ulp_state(struct radeon_device *rdev) 3462 { 3463 int i; 3464 3465 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3466 3467 udelay(7000); 3468 3469 for (i = 0; i < rdev->usec_timeout; i++) { 3470 if (RREG32(SMC_RESP_0) == 1) 3471 break; 3472 udelay(1000); 3473 } 3474 3475 return 0; 3476 } 3477 #endif 3478 3479 static int si_notify_smc_display_change(struct radeon_device *rdev, 3480 bool has_display) 3481 { 3482 PPSMC_Msg msg = has_display ? 3483 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3484 3485 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3486 0 : -EINVAL; 3487 } 3488 3489 static void si_program_response_times(struct radeon_device *rdev) 3490 { 3491 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3492 u32 vddc_dly, acpi_dly, vbi_dly; 3493 u32 reference_clock; 3494 3495 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3496 3497 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3498 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3499 3500 if (voltage_response_time == 0) 3501 voltage_response_time = 1000; 3502 3503 acpi_delay_time = 15000; 3504 vbi_time_out = 100000; 3505 3506 reference_clock = radeon_get_xclk(rdev); 3507 3508 vddc_dly = (voltage_response_time * reference_clock) / 100; 3509 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3510 vbi_dly = (vbi_time_out * reference_clock) / 100; 3511 3512 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3513 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3514 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3515 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3516 } 3517 3518 static void si_program_ds_registers(struct radeon_device *rdev) 3519 { 3520 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3521 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3522 3523 if (eg_pi->sclk_deep_sleep) { 3524 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3525 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3526 ~AUTOSCALE_ON_SS_CLEAR); 3527 } 3528 } 3529 3530 static void si_program_display_gap(struct radeon_device *rdev) 3531 { 3532 u32 tmp, pipe; 3533 int i; 3534 3535 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3536 if (rdev->pm.dpm.new_active_crtc_count > 0) 3537 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3538 else 3539 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3540 3541 if (rdev->pm.dpm.new_active_crtc_count > 1) 3542 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3543 else 3544 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3545 3546 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3547 3548 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3549 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3550 3551 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3552 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3553 /* find the first active crtc */ 3554 for (i = 0; i < rdev->num_crtc; i++) { 3555 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3556 break; 3557 } 3558 if (i == rdev->num_crtc) 3559 pipe = 0; 3560 else 3561 pipe = i; 3562 3563 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3564 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3565 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3566 } 3567 3568 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3569 } 3570 3571 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3572 { 3573 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3574 3575 if (enable) { 3576 if (pi->sclk_ss) 3577 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3578 } else { 3579 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3580 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3581 } 3582 } 3583 3584 static void si_setup_bsp(struct radeon_device *rdev) 3585 { 3586 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3587 u32 xclk = radeon_get_xclk(rdev); 3588 3589 r600_calculate_u_and_p(pi->asi, 3590 xclk, 3591 16, 3592 &pi->bsp, 3593 &pi->bsu); 3594 3595 r600_calculate_u_and_p(pi->pasi, 3596 xclk, 3597 16, 3598 &pi->pbsp, 3599 &pi->pbsu); 3600 3601 3602 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3603 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3604 3605 WREG32(CG_BSP, pi->dsp); 3606 } 3607 3608 static void si_program_git(struct radeon_device *rdev) 3609 { 3610 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3611 } 3612 3613 static void si_program_tp(struct radeon_device *rdev) 3614 { 3615 int i; 3616 enum r600_td td = R600_TD_DFLT; 3617 3618 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3619 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3620 3621 if (td == R600_TD_AUTO) 3622 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3623 else 3624 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3625 3626 if (td == R600_TD_UP) 3627 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3628 3629 if (td == R600_TD_DOWN) 3630 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3631 } 3632 3633 static void si_program_tpp(struct radeon_device *rdev) 3634 { 3635 WREG32(CG_TPC, R600_TPC_DFLT); 3636 } 3637 3638 static void si_program_sstp(struct radeon_device *rdev) 3639 { 3640 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3641 } 3642 3643 static void si_enable_display_gap(struct radeon_device *rdev) 3644 { 3645 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3646 3647 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3648 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3649 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3650 3651 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3652 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3653 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3654 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3655 } 3656 3657 static void si_program_vc(struct radeon_device *rdev) 3658 { 3659 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3660 3661 WREG32(CG_FTV, pi->vrc); 3662 } 3663 3664 static void si_clear_vc(struct radeon_device *rdev) 3665 { 3666 WREG32(CG_FTV, 0); 3667 } 3668 3669 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3670 { 3671 u8 mc_para_index; 3672 3673 if (memory_clock < 10000) 3674 mc_para_index = 0; 3675 else if (memory_clock >= 80000) 3676 mc_para_index = 0x0f; 3677 else 3678 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3679 return mc_para_index; 3680 } 3681 3682 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3683 { 3684 u8 mc_para_index; 3685 3686 if (strobe_mode) { 3687 if (memory_clock < 12500) 3688 mc_para_index = 0x00; 3689 else if (memory_clock > 47500) 3690 mc_para_index = 0x0f; 3691 else 3692 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3693 } else { 3694 if (memory_clock < 65000) 3695 mc_para_index = 0x00; 3696 else if (memory_clock > 135000) 3697 mc_para_index = 0x0f; 3698 else 3699 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3700 } 3701 return mc_para_index; 3702 } 3703 3704 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3705 { 3706 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3707 bool strobe_mode = false; 3708 u8 result = 0; 3709 3710 if (mclk <= pi->mclk_strobe_mode_threshold) 3711 strobe_mode = true; 3712 3713 if (pi->mem_gddr5) 3714 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3715 else 3716 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3717 3718 if (strobe_mode) 3719 result |= SISLANDS_SMC_STROBE_ENABLE; 3720 3721 return result; 3722 } 3723 3724 static int si_upload_firmware(struct radeon_device *rdev) 3725 { 3726 struct si_power_info *si_pi = si_get_pi(rdev); 3727 int ret; 3728 3729 si_reset_smc(rdev); 3730 si_stop_smc_clock(rdev); 3731 3732 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3733 3734 return ret; 3735 } 3736 3737 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3738 const struct atom_voltage_table *table, 3739 const struct radeon_phase_shedding_limits_table *limits) 3740 { 3741 u32 data, num_bits, num_levels; 3742 3743 if ((table == NULL) || (limits == NULL)) 3744 return false; 3745 3746 data = table->mask_low; 3747 3748 num_bits = hweight32(data); 3749 3750 if (num_bits == 0) 3751 return false; 3752 3753 num_levels = (1 << num_bits); 3754 3755 if (table->count != num_levels) 3756 return false; 3757 3758 if (limits->count != (num_levels - 1)) 3759 return false; 3760 3761 return true; 3762 } 3763 3764 static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3765 struct atom_voltage_table *voltage_table) 3766 { 3767 unsigned int i, diff; 3768 3769 if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS) 3770 return; 3771 3772 diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS; 3773 3774 for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++) 3775 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3776 3777 voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS; 3778 } 3779 3780 static int si_construct_voltage_tables(struct radeon_device *rdev) 3781 { 3782 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3783 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3784 struct si_power_info *si_pi = si_get_pi(rdev); 3785 int ret; 3786 3787 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3788 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3789 if (ret) 3790 return ret; 3791 3792 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3793 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table); 3794 3795 if (eg_pi->vddci_control) { 3796 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3797 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3798 if (ret) 3799 return ret; 3800 3801 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3802 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table); 3803 } 3804 3805 if (pi->mvdd_control) { 3806 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3807 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3808 3809 if (ret) { 3810 pi->mvdd_control = false; 3811 return ret; 3812 } 3813 3814 if (si_pi->mvdd_voltage_table.count == 0) { 3815 pi->mvdd_control = false; 3816 return -EINVAL; 3817 } 3818 3819 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3820 si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table); 3821 } 3822 3823 if (si_pi->vddc_phase_shed_control) { 3824 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3825 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3826 if (ret) 3827 si_pi->vddc_phase_shed_control = false; 3828 3829 if ((si_pi->vddc_phase_shed_table.count == 0) || 3830 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3831 si_pi->vddc_phase_shed_control = false; 3832 } 3833 3834 return 0; 3835 } 3836 3837 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3838 const struct atom_voltage_table *voltage_table, 3839 SISLANDS_SMC_STATETABLE *table) 3840 { 3841 unsigned int i; 3842 3843 for (i = 0; i < voltage_table->count; i++) 3844 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3845 } 3846 3847 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3848 SISLANDS_SMC_STATETABLE *table) 3849 { 3850 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3851 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3852 struct si_power_info *si_pi = si_get_pi(rdev); 3853 u8 i; 3854 3855 if (eg_pi->vddc_voltage_table.count) { 3856 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3857 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3858 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3859 3860 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3861 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3862 table->maxVDDCIndexInPPTable = i; 3863 break; 3864 } 3865 } 3866 } 3867 3868 if (eg_pi->vddci_voltage_table.count) { 3869 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3870 3871 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3872 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3873 } 3874 3875 3876 if (si_pi->mvdd_voltage_table.count) { 3877 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3878 3879 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3880 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3881 } 3882 3883 if (si_pi->vddc_phase_shed_control) { 3884 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3885 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3886 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3887 3888 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3889 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3890 3891 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3892 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3893 } else { 3894 si_pi->vddc_phase_shed_control = false; 3895 } 3896 } 3897 3898 return 0; 3899 } 3900 3901 static int si_populate_voltage_value(struct radeon_device *rdev, 3902 const struct atom_voltage_table *table, 3903 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3904 { 3905 unsigned int i; 3906 3907 for (i = 0; i < table->count; i++) { 3908 if (value <= table->entries[i].value) { 3909 voltage->index = (u8)i; 3910 voltage->value = cpu_to_be16(table->entries[i].value); 3911 break; 3912 } 3913 } 3914 3915 if (i >= table->count) 3916 return -EINVAL; 3917 3918 return 0; 3919 } 3920 3921 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3922 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3923 { 3924 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3925 struct si_power_info *si_pi = si_get_pi(rdev); 3926 3927 if (pi->mvdd_control) { 3928 if (mclk <= pi->mvdd_split_frequency) 3929 voltage->index = 0; 3930 else 3931 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3932 3933 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3934 } 3935 return 0; 3936 } 3937 3938 static int si_get_std_voltage_value(struct radeon_device *rdev, 3939 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 3940 u16 *std_voltage) 3941 { 3942 u16 v_index; 3943 bool voltage_found = false; 3944 *std_voltage = be16_to_cpu(voltage->value); 3945 3946 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 3947 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 3948 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 3949 return -EINVAL; 3950 3951 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3952 if (be16_to_cpu(voltage->value) == 3953 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3954 voltage_found = true; 3955 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3956 *std_voltage = 3957 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3958 else 3959 *std_voltage = 3960 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3961 break; 3962 } 3963 } 3964 3965 if (!voltage_found) { 3966 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3967 if (be16_to_cpu(voltage->value) <= 3968 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3969 voltage_found = true; 3970 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3971 *std_voltage = 3972 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3973 else 3974 *std_voltage = 3975 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3976 break; 3977 } 3978 } 3979 } 3980 } else { 3981 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3982 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 3983 } 3984 } 3985 3986 return 0; 3987 } 3988 3989 static int si_populate_std_voltage_value(struct radeon_device *rdev, 3990 u16 value, u8 index, 3991 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3992 { 3993 voltage->index = index; 3994 voltage->value = cpu_to_be16(value); 3995 3996 return 0; 3997 } 3998 3999 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4000 const struct radeon_phase_shedding_limits_table *limits, 4001 u16 voltage, u32 sclk, u32 mclk, 4002 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4003 { 4004 unsigned int i; 4005 4006 for (i = 0; i < limits->count; i++) { 4007 if ((voltage <= limits->entries[i].voltage) && 4008 (sclk <= limits->entries[i].sclk) && 4009 (mclk <= limits->entries[i].mclk)) 4010 break; 4011 } 4012 4013 smc_voltage->phase_settings = (u8)i; 4014 4015 return 0; 4016 } 4017 4018 static int si_init_arb_table_index(struct radeon_device *rdev) 4019 { 4020 struct si_power_info *si_pi = si_get_pi(rdev); 4021 u32 tmp; 4022 int ret; 4023 4024 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4025 if (ret) 4026 return ret; 4027 4028 tmp &= 0x00FFFFFF; 4029 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4030 4031 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4032 } 4033 4034 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4035 { 4036 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4037 } 4038 4039 static int si_reset_to_default(struct radeon_device *rdev) 4040 { 4041 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4042 0 : -EINVAL; 4043 } 4044 4045 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4046 { 4047 struct si_power_info *si_pi = si_get_pi(rdev); 4048 u32 tmp; 4049 int ret; 4050 4051 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4052 &tmp, si_pi->sram_end); 4053 if (ret) 4054 return ret; 4055 4056 tmp = (tmp >> 24) & 0xff; 4057 4058 if (tmp == MC_CG_ARB_FREQ_F0) 4059 return 0; 4060 4061 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4062 } 4063 4064 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4065 u32 engine_clock) 4066 { 4067 u32 dram_rows; 4068 u32 dram_refresh_rate; 4069 u32 mc_arb_rfsh_rate; 4070 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4071 4072 if (tmp >= 4) 4073 dram_rows = 16384; 4074 else 4075 dram_rows = 1 << (tmp + 10); 4076 4077 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4078 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4079 4080 return mc_arb_rfsh_rate; 4081 } 4082 4083 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4084 struct rv7xx_pl *pl, 4085 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4086 { 4087 u32 dram_timing; 4088 u32 dram_timing2; 4089 u32 burst_time; 4090 4091 arb_regs->mc_arb_rfsh_rate = 4092 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4093 4094 radeon_atom_set_engine_dram_timings(rdev, 4095 pl->sclk, 4096 pl->mclk); 4097 4098 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4099 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4100 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4101 4102 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4103 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4104 arb_regs->mc_arb_burst_time = (u8)burst_time; 4105 4106 return 0; 4107 } 4108 4109 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4110 struct radeon_ps *radeon_state, 4111 unsigned int first_arb_set) 4112 { 4113 struct si_power_info *si_pi = si_get_pi(rdev); 4114 struct ni_ps *state = ni_get_ps(radeon_state); 4115 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4116 int i, ret = 0; 4117 4118 for (i = 0; i < state->performance_level_count; i++) { 4119 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4120 if (ret) 4121 break; 4122 ret = si_copy_bytes_to_smc(rdev, 4123 si_pi->arb_table_start + 4124 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4125 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4126 (u8 *)&arb_regs, 4127 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4128 si_pi->sram_end); 4129 if (ret) 4130 break; 4131 } 4132 4133 return ret; 4134 } 4135 4136 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4137 struct radeon_ps *radeon_new_state) 4138 { 4139 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4140 SISLANDS_DRIVER_STATE_ARB_INDEX); 4141 } 4142 4143 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4144 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4145 { 4146 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4147 struct si_power_info *si_pi = si_get_pi(rdev); 4148 4149 if (pi->mvdd_control) 4150 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4151 si_pi->mvdd_bootup_value, voltage); 4152 4153 return 0; 4154 } 4155 4156 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4157 struct radeon_ps *radeon_initial_state, 4158 SISLANDS_SMC_STATETABLE *table) 4159 { 4160 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4161 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4162 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4163 struct si_power_info *si_pi = si_get_pi(rdev); 4164 u32 reg; 4165 int ret; 4166 4167 table->initialState.levels[0].mclk.vDLL_CNTL = 4168 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4169 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4170 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4171 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4172 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4173 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4174 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4175 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4176 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4177 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4178 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4179 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4180 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4181 table->initialState.levels[0].mclk.vMPLL_SS = 4182 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4183 table->initialState.levels[0].mclk.vMPLL_SS2 = 4184 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4185 4186 table->initialState.levels[0].mclk.mclk_value = 4187 cpu_to_be32(initial_state->performance_levels[0].mclk); 4188 4189 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4190 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4191 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4192 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4193 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4194 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4195 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4196 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4197 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4198 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4199 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4200 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4201 4202 table->initialState.levels[0].sclk.sclk_value = 4203 cpu_to_be32(initial_state->performance_levels[0].sclk); 4204 4205 table->initialState.levels[0].arbRefreshState = 4206 SISLANDS_INITIAL_STATE_ARB_INDEX; 4207 4208 table->initialState.levels[0].ACIndex = 0; 4209 4210 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4211 initial_state->performance_levels[0].vddc, 4212 &table->initialState.levels[0].vddc); 4213 4214 if (!ret) { 4215 u16 std_vddc; 4216 4217 ret = si_get_std_voltage_value(rdev, 4218 &table->initialState.levels[0].vddc, 4219 &std_vddc); 4220 if (!ret) 4221 si_populate_std_voltage_value(rdev, std_vddc, 4222 table->initialState.levels[0].vddc.index, 4223 &table->initialState.levels[0].std_vddc); 4224 } 4225 4226 if (eg_pi->vddci_control) 4227 si_populate_voltage_value(rdev, 4228 &eg_pi->vddci_voltage_table, 4229 initial_state->performance_levels[0].vddci, 4230 &table->initialState.levels[0].vddci); 4231 4232 if (si_pi->vddc_phase_shed_control) 4233 si_populate_phase_shedding_value(rdev, 4234 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4235 initial_state->performance_levels[0].vddc, 4236 initial_state->performance_levels[0].sclk, 4237 initial_state->performance_levels[0].mclk, 4238 &table->initialState.levels[0].vddc); 4239 4240 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4241 4242 reg = CG_R(0xffff) | CG_L(0); 4243 table->initialState.levels[0].aT = cpu_to_be32(reg); 4244 4245 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4246 4247 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4248 4249 if (pi->mem_gddr5) { 4250 table->initialState.levels[0].strobeMode = 4251 si_get_strobe_mode_settings(rdev, 4252 initial_state->performance_levels[0].mclk); 4253 4254 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4255 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4256 else 4257 table->initialState.levels[0].mcFlags = 0; 4258 } 4259 4260 table->initialState.levelCount = 1; 4261 4262 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4263 4264 table->initialState.levels[0].dpm2.MaxPS = 0; 4265 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4266 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4267 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4268 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4269 4270 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4271 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4272 4273 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4274 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4275 4276 return 0; 4277 } 4278 4279 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4280 SISLANDS_SMC_STATETABLE *table) 4281 { 4282 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4283 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4284 struct si_power_info *si_pi = si_get_pi(rdev); 4285 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4286 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4287 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4288 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4289 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4290 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4291 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4292 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4293 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4294 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4295 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4296 u32 reg; 4297 int ret; 4298 4299 table->ACPIState = table->initialState; 4300 4301 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4302 4303 if (pi->acpi_vddc) { 4304 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4305 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4306 if (!ret) { 4307 u16 std_vddc; 4308 4309 ret = si_get_std_voltage_value(rdev, 4310 &table->ACPIState.levels[0].vddc, &std_vddc); 4311 if (!ret) 4312 si_populate_std_voltage_value(rdev, std_vddc, 4313 table->ACPIState.levels[0].vddc.index, 4314 &table->ACPIState.levels[0].std_vddc); 4315 } 4316 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4317 4318 if (si_pi->vddc_phase_shed_control) { 4319 si_populate_phase_shedding_value(rdev, 4320 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4321 pi->acpi_vddc, 4322 0, 4323 0, 4324 &table->ACPIState.levels[0].vddc); 4325 } 4326 } else { 4327 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4328 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4329 if (!ret) { 4330 u16 std_vddc; 4331 4332 ret = si_get_std_voltage_value(rdev, 4333 &table->ACPIState.levels[0].vddc, &std_vddc); 4334 4335 if (!ret) 4336 si_populate_std_voltage_value(rdev, std_vddc, 4337 table->ACPIState.levels[0].vddc.index, 4338 &table->ACPIState.levels[0].std_vddc); 4339 } 4340 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4341 si_pi->sys_pcie_mask, 4342 si_pi->boot_pcie_gen, 4343 RADEON_PCIE_GEN1); 4344 4345 if (si_pi->vddc_phase_shed_control) 4346 si_populate_phase_shedding_value(rdev, 4347 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4348 pi->min_vddc_in_table, 4349 0, 4350 0, 4351 &table->ACPIState.levels[0].vddc); 4352 } 4353 4354 if (pi->acpi_vddc) { 4355 if (eg_pi->acpi_vddci) 4356 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4357 eg_pi->acpi_vddci, 4358 &table->ACPIState.levels[0].vddci); 4359 } 4360 4361 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4362 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4363 4364 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4365 4366 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4367 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4368 4369 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4370 cpu_to_be32(dll_cntl); 4371 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4372 cpu_to_be32(mclk_pwrmgt_cntl); 4373 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4374 cpu_to_be32(mpll_ad_func_cntl); 4375 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4376 cpu_to_be32(mpll_dq_func_cntl); 4377 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4378 cpu_to_be32(mpll_func_cntl); 4379 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4380 cpu_to_be32(mpll_func_cntl_1); 4381 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4382 cpu_to_be32(mpll_func_cntl_2); 4383 table->ACPIState.levels[0].mclk.vMPLL_SS = 4384 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4385 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4386 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4387 4388 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4389 cpu_to_be32(spll_func_cntl); 4390 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4391 cpu_to_be32(spll_func_cntl_2); 4392 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4393 cpu_to_be32(spll_func_cntl_3); 4394 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4395 cpu_to_be32(spll_func_cntl_4); 4396 4397 table->ACPIState.levels[0].mclk.mclk_value = 0; 4398 table->ACPIState.levels[0].sclk.sclk_value = 0; 4399 4400 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4401 4402 if (eg_pi->dynamic_ac_timing) 4403 table->ACPIState.levels[0].ACIndex = 0; 4404 4405 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4406 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4407 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4408 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4409 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4410 4411 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4412 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4413 4414 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4415 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4416 4417 return 0; 4418 } 4419 4420 static int si_populate_ulv_state(struct radeon_device *rdev, 4421 SISLANDS_SMC_SWSTATE *state) 4422 { 4423 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4424 struct si_power_info *si_pi = si_get_pi(rdev); 4425 struct si_ulv_param *ulv = &si_pi->ulv; 4426 u32 sclk_in_sr = 1350; /* ??? */ 4427 int ret; 4428 4429 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4430 &state->levels[0]); 4431 if (!ret) { 4432 if (eg_pi->sclk_deep_sleep) { 4433 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4434 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4435 else 4436 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4437 } 4438 if (ulv->one_pcie_lane_in_ulv) 4439 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4440 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4441 state->levels[0].ACIndex = 1; 4442 state->levels[0].std_vddc = state->levels[0].vddc; 4443 state->levelCount = 1; 4444 4445 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4446 } 4447 4448 return ret; 4449 } 4450 4451 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4452 { 4453 struct si_power_info *si_pi = si_get_pi(rdev); 4454 struct si_ulv_param *ulv = &si_pi->ulv; 4455 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4456 int ret; 4457 4458 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4459 &arb_regs); 4460 if (ret) 4461 return ret; 4462 4463 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4464 ulv->volt_change_delay); 4465 4466 ret = si_copy_bytes_to_smc(rdev, 4467 si_pi->arb_table_start + 4468 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4469 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4470 (u8 *)&arb_regs, 4471 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4472 si_pi->sram_end); 4473 4474 return ret; 4475 } 4476 4477 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4478 { 4479 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4480 4481 pi->mvdd_split_frequency = 30000; 4482 } 4483 4484 static int si_init_smc_table(struct radeon_device *rdev) 4485 { 4486 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4487 struct si_power_info *si_pi = si_get_pi(rdev); 4488 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4489 const struct si_ulv_param *ulv = &si_pi->ulv; 4490 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4491 int ret; 4492 u32 lane_width; 4493 u32 vr_hot_gpio; 4494 4495 si_populate_smc_voltage_tables(rdev, table); 4496 4497 switch (rdev->pm.int_thermal_type) { 4498 case THERMAL_TYPE_SI: 4499 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4500 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4501 break; 4502 case THERMAL_TYPE_NONE: 4503 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4504 break; 4505 default: 4506 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4507 break; 4508 } 4509 4510 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4511 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4512 4513 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4514 if ((rdev->ddev->pci_device != 0x6818) && (rdev->ddev->pci_device != 0x6819)) 4515 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4516 } 4517 4518 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4519 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4520 4521 if (pi->mem_gddr5) 4522 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4523 4524 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4525 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4526 4527 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4528 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4529 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4530 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4531 vr_hot_gpio); 4532 } 4533 4534 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4535 if (ret) 4536 return ret; 4537 4538 ret = si_populate_smc_acpi_state(rdev, table); 4539 if (ret) 4540 return ret; 4541 4542 table->driverState = table->initialState; 4543 4544 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4545 SISLANDS_INITIAL_STATE_ARB_INDEX); 4546 if (ret) 4547 return ret; 4548 4549 if (ulv->supported && ulv->pl.vddc) { 4550 ret = si_populate_ulv_state(rdev, &table->ULVState); 4551 if (ret) 4552 return ret; 4553 4554 ret = si_program_ulv_memory_timing_parameters(rdev); 4555 if (ret) 4556 return ret; 4557 4558 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4559 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4560 4561 lane_width = radeon_get_pcie_lanes(rdev); 4562 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4563 } else { 4564 table->ULVState = table->initialState; 4565 } 4566 4567 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4568 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4569 si_pi->sram_end); 4570 } 4571 4572 static int si_calculate_sclk_params(struct radeon_device *rdev, 4573 u32 engine_clock, 4574 SISLANDS_SMC_SCLK_VALUE *sclk) 4575 { 4576 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4577 struct si_power_info *si_pi = si_get_pi(rdev); 4578 struct atom_clock_dividers dividers; 4579 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4580 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4581 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4582 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4583 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4584 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4585 u64 tmp; 4586 u32 reference_clock = rdev->clock.spll.reference_freq; 4587 u32 reference_divider; 4588 u32 fbdiv; 4589 int ret; 4590 4591 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4592 engine_clock, false, ÷rs); 4593 if (ret) 4594 return ret; 4595 4596 reference_divider = 1 + dividers.ref_div; 4597 4598 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4599 do_div(tmp, reference_clock); 4600 fbdiv = (u32) tmp; 4601 4602 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4603 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4604 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4605 4606 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4607 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4608 4609 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4610 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4611 spll_func_cntl_3 |= SPLL_DITHEN; 4612 4613 if (pi->sclk_ss) { 4614 struct radeon_atom_ss ss; 4615 u32 vco_freq = engine_clock * dividers.post_div; 4616 4617 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4618 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4619 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4620 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4621 4622 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4623 cg_spll_spread_spectrum |= CLK_S(clk_s); 4624 cg_spll_spread_spectrum |= SSEN; 4625 4626 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4627 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4628 } 4629 } 4630 4631 sclk->sclk_value = engine_clock; 4632 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4633 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4634 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4635 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4636 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4637 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4638 4639 return 0; 4640 } 4641 4642 static int si_populate_sclk_value(struct radeon_device *rdev, 4643 u32 engine_clock, 4644 SISLANDS_SMC_SCLK_VALUE *sclk) 4645 { 4646 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4647 int ret; 4648 4649 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4650 if (!ret) { 4651 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4652 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4653 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4654 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4655 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4656 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4657 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4658 } 4659 4660 return ret; 4661 } 4662 4663 static int si_populate_mclk_value(struct radeon_device *rdev, 4664 u32 engine_clock, 4665 u32 memory_clock, 4666 SISLANDS_SMC_MCLK_VALUE *mclk, 4667 bool strobe_mode, 4668 bool dll_state_on) 4669 { 4670 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4671 struct si_power_info *si_pi = si_get_pi(rdev); 4672 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4673 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4674 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4675 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4676 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4677 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4678 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4679 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4680 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4681 struct atom_mpll_param mpll_param; 4682 int ret; 4683 4684 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4685 if (ret) 4686 return ret; 4687 4688 mpll_func_cntl &= ~BWCTRL_MASK; 4689 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4690 4691 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4692 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4693 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4694 4695 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4696 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4697 4698 if (pi->mem_gddr5) { 4699 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4700 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4701 YCLK_POST_DIV(mpll_param.post_div); 4702 } 4703 4704 if (pi->mclk_ss) { 4705 struct radeon_atom_ss ss; 4706 u32 freq_nom; 4707 u32 tmp; 4708 u32 reference_clock = rdev->clock.mpll.reference_freq; 4709 4710 if (pi->mem_gddr5) 4711 freq_nom = memory_clock * 4; 4712 else 4713 freq_nom = memory_clock * 2; 4714 4715 tmp = freq_nom / reference_clock; 4716 tmp = tmp * tmp; 4717 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4718 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4719 u32 clks = reference_clock * 5 / ss.rate; 4720 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4721 4722 mpll_ss1 &= ~CLKV_MASK; 4723 mpll_ss1 |= CLKV(clkv); 4724 4725 mpll_ss2 &= ~CLKS_MASK; 4726 mpll_ss2 |= CLKS(clks); 4727 } 4728 } 4729 4730 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4731 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4732 4733 if (dll_state_on) 4734 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4735 else 4736 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4737 4738 mclk->mclk_value = cpu_to_be32(memory_clock); 4739 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4740 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4741 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4742 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4743 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4744 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4745 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4746 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4747 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4748 4749 return 0; 4750 } 4751 4752 static void si_populate_smc_sp(struct radeon_device *rdev, 4753 struct radeon_ps *radeon_state, 4754 SISLANDS_SMC_SWSTATE *smc_state) 4755 { 4756 struct ni_ps *ps = ni_get_ps(radeon_state); 4757 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4758 int i; 4759 4760 for (i = 0; i < ps->performance_level_count - 1; i++) 4761 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4762 4763 smc_state->levels[ps->performance_level_count - 1].bSP = 4764 cpu_to_be32(pi->psp); 4765 } 4766 4767 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4768 struct rv7xx_pl *pl, 4769 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4770 { 4771 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4772 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4773 struct si_power_info *si_pi = si_get_pi(rdev); 4774 int ret; 4775 bool dll_state_on; 4776 u16 std_vddc; 4777 bool gmc_pg = false; 4778 4779 if (eg_pi->pcie_performance_request && 4780 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4781 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4782 else 4783 level->gen2PCIE = (u8)pl->pcie_gen; 4784 4785 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4786 if (ret) 4787 return ret; 4788 4789 level->mcFlags = 0; 4790 4791 if (pi->mclk_stutter_mode_threshold && 4792 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4793 !eg_pi->uvd_enabled && 4794 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4795 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4796 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4797 4798 if (gmc_pg) 4799 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4800 } 4801 4802 if (pi->mem_gddr5) { 4803 if (pl->mclk > pi->mclk_edc_enable_threshold) 4804 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4805 4806 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4807 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4808 4809 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4810 4811 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4812 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4813 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4814 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4815 else 4816 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4817 } else { 4818 dll_state_on = false; 4819 } 4820 } else { 4821 level->strobeMode = si_get_strobe_mode_settings(rdev, 4822 pl->mclk); 4823 4824 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4825 } 4826 4827 ret = si_populate_mclk_value(rdev, 4828 pl->sclk, 4829 pl->mclk, 4830 &level->mclk, 4831 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4832 if (ret) 4833 return ret; 4834 4835 ret = si_populate_voltage_value(rdev, 4836 &eg_pi->vddc_voltage_table, 4837 pl->vddc, &level->vddc); 4838 if (ret) 4839 return ret; 4840 4841 4842 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4843 if (ret) 4844 return ret; 4845 4846 ret = si_populate_std_voltage_value(rdev, std_vddc, 4847 level->vddc.index, &level->std_vddc); 4848 if (ret) 4849 return ret; 4850 4851 if (eg_pi->vddci_control) { 4852 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4853 pl->vddci, &level->vddci); 4854 if (ret) 4855 return ret; 4856 } 4857 4858 if (si_pi->vddc_phase_shed_control) { 4859 ret = si_populate_phase_shedding_value(rdev, 4860 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4861 pl->vddc, 4862 pl->sclk, 4863 pl->mclk, 4864 &level->vddc); 4865 if (ret) 4866 return ret; 4867 } 4868 4869 level->MaxPoweredUpCU = si_pi->max_cu; 4870 4871 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4872 4873 return ret; 4874 } 4875 4876 static int si_populate_smc_t(struct radeon_device *rdev, 4877 struct radeon_ps *radeon_state, 4878 SISLANDS_SMC_SWSTATE *smc_state) 4879 { 4880 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4881 struct ni_ps *state = ni_get_ps(radeon_state); 4882 u32 a_t; 4883 u32 t_l, t_h; 4884 u32 high_bsp; 4885 int i, ret; 4886 4887 if (state->performance_level_count >= 9) 4888 return -EINVAL; 4889 4890 if (state->performance_level_count < 2) { 4891 a_t = CG_R(0xffff) | CG_L(0); 4892 smc_state->levels[0].aT = cpu_to_be32(a_t); 4893 return 0; 4894 } 4895 4896 smc_state->levels[0].aT = cpu_to_be32(0); 4897 4898 for (i = 0; i <= state->performance_level_count - 2; i++) { 4899 ret = r600_calculate_at( 4900 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4901 100 * R600_AH_DFLT, 4902 state->performance_levels[i + 1].sclk, 4903 state->performance_levels[i].sclk, 4904 &t_l, 4905 &t_h); 4906 4907 if (ret) { 4908 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4909 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4910 } 4911 4912 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4913 a_t |= CG_R(t_l * pi->bsp / 20000); 4914 smc_state->levels[i].aT = cpu_to_be32(a_t); 4915 4916 high_bsp = (i == state->performance_level_count - 2) ? 4917 pi->pbsp : pi->bsp; 4918 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4919 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4920 } 4921 4922 return 0; 4923 } 4924 4925 static int si_disable_ulv(struct radeon_device *rdev) 4926 { 4927 struct si_power_info *si_pi = si_get_pi(rdev); 4928 struct si_ulv_param *ulv = &si_pi->ulv; 4929 4930 if (ulv->supported) 4931 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4932 0 : -EINVAL; 4933 4934 return 0; 4935 } 4936 4937 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 4938 struct radeon_ps *radeon_state) 4939 { 4940 const struct si_power_info *si_pi = si_get_pi(rdev); 4941 const struct si_ulv_param *ulv = &si_pi->ulv; 4942 const struct ni_ps *state = ni_get_ps(radeon_state); 4943 int i; 4944 4945 if (state->performance_levels[0].mclk != ulv->pl.mclk) 4946 return false; 4947 4948 /* XXX validate against display requirements! */ 4949 4950 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 4951 if (rdev->clock.current_dispclk <= 4952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 4953 if (ulv->pl.vddc < 4954 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 4955 return false; 4956 } 4957 } 4958 4959 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 4960 return false; 4961 4962 return true; 4963 } 4964 4965 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 4966 struct radeon_ps *radeon_new_state) 4967 { 4968 const struct si_power_info *si_pi = si_get_pi(rdev); 4969 const struct si_ulv_param *ulv = &si_pi->ulv; 4970 4971 if (ulv->supported) { 4972 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 4973 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 4974 0 : -EINVAL; 4975 } 4976 return 0; 4977 } 4978 4979 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 4980 struct radeon_ps *radeon_state, 4981 SISLANDS_SMC_SWSTATE *smc_state) 4982 { 4983 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4984 struct ni_power_info *ni_pi = ni_get_pi(rdev); 4985 struct si_power_info *si_pi = si_get_pi(rdev); 4986 struct ni_ps *state = ni_get_ps(radeon_state); 4987 int i, ret; 4988 u32 threshold; 4989 u32 sclk_in_sr = 1350; /* ??? */ 4990 4991 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 4992 return -EINVAL; 4993 4994 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 4995 4996 if (radeon_state->vclk && radeon_state->dclk) { 4997 eg_pi->uvd_enabled = true; 4998 if (eg_pi->smu_uvd_hs) 4999 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5000 } else { 5001 eg_pi->uvd_enabled = false; 5002 } 5003 5004 if (state->dc_compatible) 5005 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5006 5007 smc_state->levelCount = 0; 5008 for (i = 0; i < state->performance_level_count; i++) { 5009 if (eg_pi->sclk_deep_sleep) { 5010 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5011 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5012 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5013 else 5014 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5015 } 5016 } 5017 5018 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5019 &smc_state->levels[i]); 5020 smc_state->levels[i].arbRefreshState = 5021 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5022 5023 if (ret) 5024 return ret; 5025 5026 if (ni_pi->enable_power_containment) 5027 smc_state->levels[i].displayWatermark = 5028 (state->performance_levels[i].sclk < threshold) ? 5029 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5030 else 5031 smc_state->levels[i].displayWatermark = (i < 2) ? 5032 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5033 5034 if (eg_pi->dynamic_ac_timing) 5035 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5036 else 5037 smc_state->levels[i].ACIndex = 0; 5038 5039 smc_state->levelCount++; 5040 } 5041 5042 si_write_smc_soft_register(rdev, 5043 SI_SMC_SOFT_REGISTER_watermark_threshold, 5044 threshold / 512); 5045 5046 si_populate_smc_sp(rdev, radeon_state, smc_state); 5047 5048 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5049 if (ret) 5050 ni_pi->enable_power_containment = false; 5051 5052 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5053 if (ret) 5054 ni_pi->enable_sq_ramping = false; 5055 5056 return si_populate_smc_t(rdev, radeon_state, smc_state); 5057 } 5058 5059 static int si_upload_sw_state(struct radeon_device *rdev, 5060 struct radeon_ps *radeon_new_state) 5061 { 5062 struct si_power_info *si_pi = si_get_pi(rdev); 5063 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5064 int ret; 5065 u32 address = si_pi->state_table_start + 5066 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5067 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5068 ((new_state->performance_level_count - 1) * 5069 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5070 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5071 5072 memset(smc_state, 0, state_size); 5073 5074 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5075 if (ret) 5076 return ret; 5077 5078 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5079 state_size, si_pi->sram_end); 5080 5081 return ret; 5082 } 5083 5084 static int si_upload_ulv_state(struct radeon_device *rdev) 5085 { 5086 struct si_power_info *si_pi = si_get_pi(rdev); 5087 struct si_ulv_param *ulv = &si_pi->ulv; 5088 int ret = 0; 5089 5090 if (ulv->supported && ulv->pl.vddc) { 5091 u32 address = si_pi->state_table_start + 5092 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5093 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5094 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5095 5096 memset(smc_state, 0, state_size); 5097 5098 ret = si_populate_ulv_state(rdev, smc_state); 5099 if (!ret) 5100 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5101 state_size, si_pi->sram_end); 5102 } 5103 5104 return ret; 5105 } 5106 5107 static int si_upload_smc_data(struct radeon_device *rdev) 5108 { 5109 struct radeon_crtc *radeon_crtc = NULL; 5110 int i; 5111 5112 if (rdev->pm.dpm.new_active_crtc_count == 0) 5113 return 0; 5114 5115 for (i = 0; i < rdev->num_crtc; i++) { 5116 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5117 radeon_crtc = rdev->mode_info.crtcs[i]; 5118 break; 5119 } 5120 } 5121 5122 if (radeon_crtc == NULL) 5123 return 0; 5124 5125 if (radeon_crtc->line_time <= 0) 5126 return 0; 5127 5128 if (si_write_smc_soft_register(rdev, 5129 SI_SMC_SOFT_REGISTER_crtc_index, 5130 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5131 return 0; 5132 5133 if (si_write_smc_soft_register(rdev, 5134 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5135 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5136 return 0; 5137 5138 if (si_write_smc_soft_register(rdev, 5139 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5140 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5141 return 0; 5142 5143 return 0; 5144 } 5145 5146 static int si_set_mc_special_registers(struct radeon_device *rdev, 5147 struct si_mc_reg_table *table) 5148 { 5149 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5150 u8 i, j, k; 5151 u32 temp_reg; 5152 5153 for (i = 0, j = table->last; i < table->last; i++) { 5154 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5155 return -EINVAL; 5156 switch (table->mc_reg_address[i].s1 << 2) { 5157 case MC_SEQ_MISC1: 5158 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5159 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5160 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5161 for (k = 0; k < table->num_entries; k++) 5162 table->mc_reg_table_entry[k].mc_data[j] = 5163 ((temp_reg & 0xffff0000)) | 5164 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5165 j++; 5166 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5167 return -EINVAL; 5168 5169 temp_reg = RREG32(MC_PMG_CMD_MRS); 5170 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5171 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5172 for (k = 0; k < table->num_entries; k++) { 5173 table->mc_reg_table_entry[k].mc_data[j] = 5174 (temp_reg & 0xffff0000) | 5175 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5176 if (!pi->mem_gddr5) 5177 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5178 } 5179 j++; 5180 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5181 return -EINVAL; 5182 5183 if (!pi->mem_gddr5) { 5184 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5185 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5186 for (k = 0; k < table->num_entries; k++) 5187 table->mc_reg_table_entry[k].mc_data[j] = 5188 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5189 j++; 5190 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5191 return -EINVAL; 5192 } 5193 break; 5194 case MC_SEQ_RESERVE_M: 5195 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5196 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5197 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5198 for(k = 0; k < table->num_entries; k++) 5199 table->mc_reg_table_entry[k].mc_data[j] = 5200 (temp_reg & 0xffff0000) | 5201 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5202 j++; 5203 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5204 return -EINVAL; 5205 break; 5206 default: 5207 break; 5208 } 5209 } 5210 5211 table->last = j; 5212 5213 return 0; 5214 } 5215 5216 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5217 { 5218 bool result = true; 5219 5220 switch (in_reg) { 5221 case MC_SEQ_RAS_TIMING >> 2: 5222 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5223 break; 5224 case MC_SEQ_CAS_TIMING >> 2: 5225 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5226 break; 5227 case MC_SEQ_MISC_TIMING >> 2: 5228 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5229 break; 5230 case MC_SEQ_MISC_TIMING2 >> 2: 5231 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5232 break; 5233 case MC_SEQ_RD_CTL_D0 >> 2: 5234 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5235 break; 5236 case MC_SEQ_RD_CTL_D1 >> 2: 5237 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5238 break; 5239 case MC_SEQ_WR_CTL_D0 >> 2: 5240 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5241 break; 5242 case MC_SEQ_WR_CTL_D1 >> 2: 5243 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5244 break; 5245 case MC_PMG_CMD_EMRS >> 2: 5246 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5247 break; 5248 case MC_PMG_CMD_MRS >> 2: 5249 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5250 break; 5251 case MC_PMG_CMD_MRS1 >> 2: 5252 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5253 break; 5254 case MC_SEQ_PMG_TIMING >> 2: 5255 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5256 break; 5257 case MC_PMG_CMD_MRS2 >> 2: 5258 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5259 break; 5260 case MC_SEQ_WR_CTL_2 >> 2: 5261 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5262 break; 5263 default: 5264 result = false; 5265 break; 5266 } 5267 5268 return result; 5269 } 5270 5271 static void si_set_valid_flag(struct si_mc_reg_table *table) 5272 { 5273 u8 i, j; 5274 5275 for (i = 0; i < table->last; i++) { 5276 for (j = 1; j < table->num_entries; j++) { 5277 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5278 table->valid_flag |= 1 << i; 5279 break; 5280 } 5281 } 5282 } 5283 } 5284 5285 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5286 { 5287 u32 i; 5288 u16 address; 5289 5290 for (i = 0; i < table->last; i++) 5291 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5292 address : table->mc_reg_address[i].s1; 5293 5294 } 5295 5296 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5297 struct si_mc_reg_table *si_table) 5298 { 5299 u8 i, j; 5300 5301 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5302 return -EINVAL; 5303 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5304 return -EINVAL; 5305 5306 for (i = 0; i < table->last; i++) 5307 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5308 si_table->last = table->last; 5309 5310 for (i = 0; i < table->num_entries; i++) { 5311 si_table->mc_reg_table_entry[i].mclk_max = 5312 table->mc_reg_table_entry[i].mclk_max; 5313 for (j = 0; j < table->last; j++) { 5314 si_table->mc_reg_table_entry[i].mc_data[j] = 5315 table->mc_reg_table_entry[i].mc_data[j]; 5316 } 5317 } 5318 si_table->num_entries = table->num_entries; 5319 5320 return 0; 5321 } 5322 5323 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5324 { 5325 struct si_power_info *si_pi = si_get_pi(rdev); 5326 struct atom_mc_reg_table *table; 5327 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5328 u8 module_index = rv770_get_memory_module_index(rdev); 5329 int ret; 5330 5331 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5332 if (!table) 5333 return -ENOMEM; 5334 5335 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5336 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5337 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5338 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5339 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5340 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5341 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5342 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5343 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5344 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5345 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5346 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5347 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5348 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5349 5350 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5351 if (ret) 5352 goto init_mc_done; 5353 5354 ret = si_copy_vbios_mc_reg_table(table, si_table); 5355 if (ret) 5356 goto init_mc_done; 5357 5358 si_set_s0_mc_reg_index(si_table); 5359 5360 ret = si_set_mc_special_registers(rdev, si_table); 5361 if (ret) 5362 goto init_mc_done; 5363 5364 si_set_valid_flag(si_table); 5365 5366 init_mc_done: 5367 kfree(table); 5368 5369 return ret; 5370 5371 } 5372 5373 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5374 SMC_SIslands_MCRegisters *mc_reg_table) 5375 { 5376 struct si_power_info *si_pi = si_get_pi(rdev); 5377 u32 i, j; 5378 5379 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5380 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5381 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 5382 break; 5383 mc_reg_table->address[i].s0 = 5384 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5385 mc_reg_table->address[i].s1 = 5386 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5387 i++; 5388 } 5389 } 5390 mc_reg_table->last = (u8)i; 5391 } 5392 5393 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5394 SMC_SIslands_MCRegisterSet *data, 5395 u32 num_entries, u32 valid_flag) 5396 { 5397 u32 i, j; 5398 5399 for(i = 0, j = 0; j < num_entries; j++) { 5400 if (valid_flag & (1 << j)) { 5401 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5402 i++; 5403 } 5404 } 5405 } 5406 5407 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5408 struct rv7xx_pl *pl, 5409 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5410 { 5411 struct si_power_info *si_pi = si_get_pi(rdev); 5412 u32 i = 0; 5413 5414 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5415 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5416 break; 5417 } 5418 5419 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5420 --i; 5421 5422 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5423 mc_reg_table_data, si_pi->mc_reg_table.last, 5424 si_pi->mc_reg_table.valid_flag); 5425 } 5426 5427 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5428 struct radeon_ps *radeon_state, 5429 SMC_SIslands_MCRegisters *mc_reg_table) 5430 { 5431 struct ni_ps *state = ni_get_ps(radeon_state); 5432 int i; 5433 5434 for (i = 0; i < state->performance_level_count; i++) { 5435 si_convert_mc_reg_table_entry_to_smc(rdev, 5436 &state->performance_levels[i], 5437 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5438 } 5439 } 5440 5441 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5442 struct radeon_ps *radeon_boot_state) 5443 { 5444 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5445 struct si_power_info *si_pi = si_get_pi(rdev); 5446 struct si_ulv_param *ulv = &si_pi->ulv; 5447 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5448 5449 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5450 5451 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5452 5453 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5454 5455 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5456 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5457 5458 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5459 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5460 si_pi->mc_reg_table.last, 5461 si_pi->mc_reg_table.valid_flag); 5462 5463 if (ulv->supported && ulv->pl.vddc != 0) 5464 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5465 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5466 else 5467 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5468 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5469 si_pi->mc_reg_table.last, 5470 si_pi->mc_reg_table.valid_flag); 5471 5472 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5473 5474 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5475 (u8 *)smc_mc_reg_table, 5476 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5477 } 5478 5479 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5480 struct radeon_ps *radeon_new_state) 5481 { 5482 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5483 struct si_power_info *si_pi = si_get_pi(rdev); 5484 u32 address = si_pi->mc_reg_table_start + 5485 offsetof(SMC_SIslands_MCRegisters, 5486 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5487 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5488 5489 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5490 5491 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5492 5493 5494 return si_copy_bytes_to_smc(rdev, address, 5495 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5496 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5497 si_pi->sram_end); 5498 5499 } 5500 5501 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5502 { 5503 if (enable) 5504 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5505 else 5506 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5507 } 5508 5509 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5510 struct radeon_ps *radeon_state) 5511 { 5512 struct ni_ps *state = ni_get_ps(radeon_state); 5513 int i; 5514 u16 pcie_speed, max_speed = 0; 5515 5516 for (i = 0; i < state->performance_level_count; i++) { 5517 pcie_speed = state->performance_levels[i].pcie_gen; 5518 if (max_speed < pcie_speed) 5519 max_speed = pcie_speed; 5520 } 5521 return max_speed; 5522 } 5523 5524 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5525 { 5526 u32 speed_cntl; 5527 5528 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5529 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5530 5531 return (u16)speed_cntl; 5532 } 5533 5534 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5535 struct radeon_ps *radeon_new_state, 5536 struct radeon_ps *radeon_current_state) 5537 { 5538 struct si_power_info *si_pi = si_get_pi(rdev); 5539 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5540 enum radeon_pcie_gen current_link_speed; 5541 5542 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5543 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5544 else 5545 current_link_speed = si_pi->force_pcie_gen; 5546 5547 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5548 si_pi->pspp_notify_required = false; 5549 if (target_link_speed > current_link_speed) { 5550 switch (target_link_speed) { 5551 #if defined(CONFIG_ACPI) 5552 case RADEON_PCIE_GEN3: 5553 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5554 break; 5555 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5556 if (current_link_speed == RADEON_PCIE_GEN2) 5557 break; 5558 case RADEON_PCIE_GEN2: 5559 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5560 break; 5561 #endif 5562 default: 5563 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5564 break; 5565 } 5566 } else { 5567 if (target_link_speed < current_link_speed) 5568 si_pi->pspp_notify_required = true; 5569 } 5570 } 5571 5572 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5573 struct radeon_ps *radeon_new_state, 5574 struct radeon_ps *radeon_current_state) 5575 { 5576 struct si_power_info *si_pi = si_get_pi(rdev); 5577 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5578 u8 request; 5579 5580 if (si_pi->pspp_notify_required) { 5581 if (target_link_speed == RADEON_PCIE_GEN3) 5582 request = PCIE_PERF_REQ_PECI_GEN3; 5583 else if (target_link_speed == RADEON_PCIE_GEN2) 5584 request = PCIE_PERF_REQ_PECI_GEN2; 5585 else 5586 request = PCIE_PERF_REQ_PECI_GEN1; 5587 5588 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5589 (si_get_current_pcie_speed(rdev) > 0)) 5590 return; 5591 5592 #if defined(CONFIG_ACPI) 5593 radeon_acpi_pcie_performance_request(rdev, request, false); 5594 #endif 5595 } 5596 } 5597 5598 #if 0 5599 static int si_ds_request(struct radeon_device *rdev, 5600 bool ds_status_on, u32 count_write) 5601 { 5602 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5603 5604 if (eg_pi->sclk_deep_sleep) { 5605 if (ds_status_on) 5606 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5607 PPSMC_Result_OK) ? 5608 0 : -EINVAL; 5609 else 5610 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5611 PPSMC_Result_OK) ? 0 : -EINVAL; 5612 } 5613 return 0; 5614 } 5615 #endif 5616 5617 static void si_set_max_cu_value(struct radeon_device *rdev) 5618 { 5619 struct si_power_info *si_pi = si_get_pi(rdev); 5620 5621 if (rdev->family == CHIP_VERDE) { 5622 switch (rdev->ddev->pci_device) { 5623 case 0x6820: 5624 case 0x6825: 5625 case 0x6821: 5626 case 0x6823: 5627 case 0x6827: 5628 si_pi->max_cu = 10; 5629 break; 5630 case 0x682D: 5631 case 0x6824: 5632 case 0x682F: 5633 case 0x6826: 5634 si_pi->max_cu = 8; 5635 break; 5636 case 0x6828: 5637 case 0x6830: 5638 case 0x6831: 5639 case 0x6838: 5640 case 0x6839: 5641 case 0x683D: 5642 si_pi->max_cu = 10; 5643 break; 5644 case 0x683B: 5645 case 0x683F: 5646 case 0x6829: 5647 si_pi->max_cu = 8; 5648 break; 5649 default: 5650 si_pi->max_cu = 0; 5651 break; 5652 } 5653 } else { 5654 si_pi->max_cu = 0; 5655 } 5656 } 5657 5658 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5659 struct radeon_clock_voltage_dependency_table *table) 5660 { 5661 u32 i; 5662 int j; 5663 u16 leakage_voltage; 5664 5665 if (table) { 5666 for (i = 0; i < table->count; i++) { 5667 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5668 table->entries[i].v, 5669 &leakage_voltage)) { 5670 case 0: 5671 table->entries[i].v = leakage_voltage; 5672 break; 5673 case -EAGAIN: 5674 return -EINVAL; 5675 case -EINVAL: 5676 default: 5677 break; 5678 } 5679 } 5680 5681 for (j = (table->count - 2); j >= 0; j--) { 5682 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5683 table->entries[j].v : table->entries[j + 1].v; 5684 } 5685 } 5686 return 0; 5687 } 5688 5689 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5690 { 5691 int ret = 0; 5692 5693 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5694 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5695 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5696 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5697 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5698 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5699 return ret; 5700 } 5701 5702 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5703 struct radeon_ps *radeon_new_state, 5704 struct radeon_ps *radeon_current_state) 5705 { 5706 u32 lane_width; 5707 u32 new_lane_width = 5708 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5709 u32 current_lane_width = 5710 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5711 5712 if (new_lane_width != current_lane_width) { 5713 radeon_set_pcie_lanes(rdev, new_lane_width); 5714 lane_width = radeon_get_pcie_lanes(rdev); 5715 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5716 } 5717 } 5718 5719 void si_dpm_setup_asic(struct radeon_device *rdev) 5720 { 5721 rv770_get_memory_type(rdev); 5722 si_read_clock_registers(rdev); 5723 si_enable_acpi_power_management(rdev); 5724 } 5725 5726 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5727 int min_temp, int max_temp) 5728 { 5729 int low_temp = 0 * 1000; 5730 int high_temp = 255 * 1000; 5731 5732 if (low_temp < min_temp) 5733 low_temp = min_temp; 5734 if (high_temp > max_temp) 5735 high_temp = max_temp; 5736 if (high_temp < low_temp) { 5737 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5738 return -EINVAL; 5739 } 5740 5741 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5742 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5743 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5744 5745 rdev->pm.dpm.thermal.min_temp = low_temp; 5746 rdev->pm.dpm.thermal.max_temp = high_temp; 5747 5748 return 0; 5749 } 5750 5751 int si_dpm_enable(struct radeon_device *rdev) 5752 { 5753 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5754 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5755 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5756 int ret; 5757 5758 if (si_is_smc_running(rdev)) 5759 return -EINVAL; 5760 if (pi->voltage_control) 5761 si_enable_voltage_control(rdev, true); 5762 if (pi->mvdd_control) 5763 si_get_mvdd_configuration(rdev); 5764 if (pi->voltage_control) { 5765 ret = si_construct_voltage_tables(rdev); 5766 if (ret) { 5767 DRM_ERROR("si_construct_voltage_tables failed\n"); 5768 return ret; 5769 } 5770 } 5771 if (eg_pi->dynamic_ac_timing) { 5772 ret = si_initialize_mc_reg_table(rdev); 5773 if (ret) 5774 eg_pi->dynamic_ac_timing = false; 5775 } 5776 if (pi->dynamic_ss) 5777 si_enable_spread_spectrum(rdev, true); 5778 if (pi->thermal_protection) 5779 si_enable_thermal_protection(rdev, true); 5780 si_setup_bsp(rdev); 5781 si_program_git(rdev); 5782 si_program_tp(rdev); 5783 si_program_tpp(rdev); 5784 si_program_sstp(rdev); 5785 si_enable_display_gap(rdev); 5786 si_program_vc(rdev); 5787 ret = si_upload_firmware(rdev); 5788 if (ret) { 5789 DRM_ERROR("si_upload_firmware failed\n"); 5790 return ret; 5791 } 5792 ret = si_process_firmware_header(rdev); 5793 if (ret) { 5794 DRM_ERROR("si_process_firmware_header failed\n"); 5795 return ret; 5796 } 5797 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5798 if (ret) { 5799 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5800 return ret; 5801 } 5802 ret = si_init_smc_table(rdev); 5803 if (ret) { 5804 DRM_ERROR("si_init_smc_table failed\n"); 5805 return ret; 5806 } 5807 ret = si_init_smc_spll_table(rdev); 5808 if (ret) { 5809 DRM_ERROR("si_init_smc_spll_table failed\n"); 5810 return ret; 5811 } 5812 ret = si_init_arb_table_index(rdev); 5813 if (ret) { 5814 DRM_ERROR("si_init_arb_table_index failed\n"); 5815 return ret; 5816 } 5817 if (eg_pi->dynamic_ac_timing) { 5818 ret = si_populate_mc_reg_table(rdev, boot_ps); 5819 if (ret) { 5820 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5821 return ret; 5822 } 5823 } 5824 ret = si_initialize_smc_cac_tables(rdev); 5825 if (ret) { 5826 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5827 return ret; 5828 } 5829 ret = si_initialize_hardware_cac_manager(rdev); 5830 if (ret) { 5831 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5832 return ret; 5833 } 5834 ret = si_initialize_smc_dte_tables(rdev); 5835 if (ret) { 5836 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5837 return ret; 5838 } 5839 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5840 if (ret) { 5841 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5842 return ret; 5843 } 5844 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5845 if (ret) { 5846 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5847 return ret; 5848 } 5849 si_program_response_times(rdev); 5850 si_program_ds_registers(rdev); 5851 si_dpm_start_smc(rdev); 5852 ret = si_notify_smc_display_change(rdev, false); 5853 if (ret) { 5854 DRM_ERROR("si_notify_smc_display_change failed\n"); 5855 return ret; 5856 } 5857 si_enable_sclk_control(rdev, true); 5858 si_start_dpm(rdev); 5859 5860 if (rdev->irq.installed && 5861 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5862 PPSMC_Result result; 5863 5864 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5865 if (ret) 5866 return ret; 5867 rdev->irq.dpm_thermal = true; 5868 radeon_irq_set(rdev); 5869 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5870 5871 if (result != PPSMC_Result_OK) 5872 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5873 } 5874 5875 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5876 5877 ni_update_current_ps(rdev, boot_ps); 5878 5879 return 0; 5880 } 5881 5882 void si_dpm_disable(struct radeon_device *rdev) 5883 { 5884 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5885 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5886 5887 if (!si_is_smc_running(rdev)) 5888 return; 5889 si_disable_ulv(rdev); 5890 si_clear_vc(rdev); 5891 if (pi->thermal_protection) 5892 si_enable_thermal_protection(rdev, false); 5893 si_enable_power_containment(rdev, boot_ps, false); 5894 si_enable_smc_cac(rdev, boot_ps, false); 5895 si_enable_spread_spectrum(rdev, false); 5896 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5897 si_stop_dpm(rdev); 5898 si_reset_to_default(rdev); 5899 si_dpm_stop_smc(rdev); 5900 si_force_switch_to_arb_f0(rdev); 5901 5902 ni_update_current_ps(rdev, boot_ps); 5903 } 5904 5905 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5906 { 5907 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5908 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5909 struct radeon_ps *new_ps = &requested_ps; 5910 5911 ni_update_requested_ps(rdev, new_ps); 5912 5913 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5914 5915 return 0; 5916 } 5917 5918 static int si_power_control_set_level(struct radeon_device *rdev) 5919 { 5920 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5921 int ret; 5922 5923 ret = si_restrict_performance_levels_before_switch(rdev); 5924 if (ret) 5925 return ret; 5926 ret = si_halt_smc(rdev); 5927 if (ret) 5928 return ret; 5929 ret = si_populate_smc_tdp_limits(rdev, new_ps); 5930 if (ret) 5931 return ret; 5932 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 5933 if (ret) 5934 return ret; 5935 ret = si_resume_smc(rdev); 5936 if (ret) 5937 return ret; 5938 ret = si_set_sw_state(rdev); 5939 if (ret) 5940 return ret; 5941 return 0; 5942 } 5943 5944 int si_dpm_set_power_state(struct radeon_device *rdev) 5945 { 5946 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5947 struct radeon_ps *new_ps = &eg_pi->requested_rps; 5948 struct radeon_ps *old_ps = &eg_pi->current_rps; 5949 int ret; 5950 5951 ret = si_disable_ulv(rdev); 5952 if (ret) { 5953 DRM_ERROR("si_disable_ulv failed\n"); 5954 return ret; 5955 } 5956 ret = si_restrict_performance_levels_before_switch(rdev); 5957 if (ret) { 5958 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 5959 return ret; 5960 } 5961 if (eg_pi->pcie_performance_request) 5962 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5963 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 5964 ret = si_enable_power_containment(rdev, new_ps, false); 5965 if (ret) { 5966 DRM_ERROR("si_enable_power_containment failed\n"); 5967 return ret; 5968 } 5969 ret = si_enable_smc_cac(rdev, new_ps, false); 5970 if (ret) { 5971 DRM_ERROR("si_enable_smc_cac failed\n"); 5972 return ret; 5973 } 5974 ret = si_halt_smc(rdev); 5975 if (ret) { 5976 DRM_ERROR("si_halt_smc failed\n"); 5977 return ret; 5978 } 5979 ret = si_upload_sw_state(rdev, new_ps); 5980 if (ret) { 5981 DRM_ERROR("si_upload_sw_state failed\n"); 5982 return ret; 5983 } 5984 ret = si_upload_smc_data(rdev); 5985 if (ret) { 5986 DRM_ERROR("si_upload_smc_data failed\n"); 5987 return ret; 5988 } 5989 ret = si_upload_ulv_state(rdev); 5990 if (ret) { 5991 DRM_ERROR("si_upload_ulv_state failed\n"); 5992 return ret; 5993 } 5994 if (eg_pi->dynamic_ac_timing) { 5995 ret = si_upload_mc_reg_table(rdev, new_ps); 5996 if (ret) { 5997 DRM_ERROR("si_upload_mc_reg_table failed\n"); 5998 return ret; 5999 } 6000 } 6001 ret = si_program_memory_timing_parameters(rdev, new_ps); 6002 if (ret) { 6003 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6004 return ret; 6005 } 6006 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6007 6008 ret = si_resume_smc(rdev); 6009 if (ret) { 6010 DRM_ERROR("si_resume_smc failed\n"); 6011 return ret; 6012 } 6013 ret = si_set_sw_state(rdev); 6014 if (ret) { 6015 DRM_ERROR("si_set_sw_state failed\n"); 6016 return ret; 6017 } 6018 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6019 if (eg_pi->pcie_performance_request) 6020 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6021 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6022 if (ret) { 6023 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6024 return ret; 6025 } 6026 ret = si_enable_smc_cac(rdev, new_ps, true); 6027 if (ret) { 6028 DRM_ERROR("si_enable_smc_cac failed\n"); 6029 return ret; 6030 } 6031 ret = si_enable_power_containment(rdev, new_ps, true); 6032 if (ret) { 6033 DRM_ERROR("si_enable_power_containment failed\n"); 6034 return ret; 6035 } 6036 6037 ret = si_power_control_set_level(rdev); 6038 if (ret) { 6039 DRM_ERROR("si_power_control_set_level failed\n"); 6040 return ret; 6041 } 6042 6043 ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO); 6044 if (ret) { 6045 DRM_ERROR("si_dpm_force_performance_level failed\n"); 6046 return ret; 6047 } 6048 6049 return 0; 6050 } 6051 6052 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6053 { 6054 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6055 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6056 6057 ni_update_current_ps(rdev, new_ps); 6058 } 6059 6060 6061 void si_dpm_reset_asic(struct radeon_device *rdev) 6062 { 6063 si_restrict_performance_levels_before_switch(rdev); 6064 si_disable_ulv(rdev); 6065 si_set_boot_state(rdev); 6066 } 6067 6068 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6069 { 6070 si_program_display_gap(rdev); 6071 } 6072 6073 union power_info { 6074 struct _ATOM_POWERPLAY_INFO info; 6075 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6076 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6077 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6078 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6079 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6080 }; 6081 6082 union pplib_clock_info { 6083 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6084 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6085 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6086 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6087 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6088 }; 6089 6090 union pplib_power_state { 6091 struct _ATOM_PPLIB_STATE v1; 6092 struct _ATOM_PPLIB_STATE_V2 v2; 6093 }; 6094 6095 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6096 struct radeon_ps *rps, 6097 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6098 u8 table_rev) 6099 { 6100 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6101 rps->class = le16_to_cpu(non_clock_info->usClassification); 6102 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6103 6104 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6105 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6106 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6107 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6108 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6109 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6110 } else { 6111 rps->vclk = 0; 6112 rps->dclk = 0; 6113 } 6114 6115 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6116 rdev->pm.dpm.boot_ps = rps; 6117 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6118 rdev->pm.dpm.uvd_ps = rps; 6119 } 6120 6121 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6122 struct radeon_ps *rps, int index, 6123 union pplib_clock_info *clock_info) 6124 { 6125 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6126 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6127 struct si_power_info *si_pi = si_get_pi(rdev); 6128 struct ni_ps *ps = ni_get_ps(rps); 6129 u16 leakage_voltage; 6130 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6131 int ret; 6132 6133 ps->performance_level_count = index + 1; 6134 6135 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6136 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6137 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6138 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6139 6140 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6141 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6142 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6143 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6144 si_pi->sys_pcie_mask, 6145 si_pi->boot_pcie_gen, 6146 clock_info->si.ucPCIEGen); 6147 6148 /* patch up vddc if necessary */ 6149 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6150 &leakage_voltage); 6151 if (ret == 0) 6152 pl->vddc = leakage_voltage; 6153 6154 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6155 pi->acpi_vddc = pl->vddc; 6156 eg_pi->acpi_vddci = pl->vddci; 6157 si_pi->acpi_pcie_gen = pl->pcie_gen; 6158 } 6159 6160 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6161 index == 0) { 6162 /* XXX disable for A0 tahiti */ 6163 si_pi->ulv.supported = true; 6164 si_pi->ulv.pl = *pl; 6165 si_pi->ulv.one_pcie_lane_in_ulv = false; 6166 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6167 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6168 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6169 } 6170 6171 if (pi->min_vddc_in_table > pl->vddc) 6172 pi->min_vddc_in_table = pl->vddc; 6173 6174 if (pi->max_vddc_in_table < pl->vddc) 6175 pi->max_vddc_in_table = pl->vddc; 6176 6177 /* patch up boot state */ 6178 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6179 u16 vddc, vddci, mvdd; 6180 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6181 pl->mclk = rdev->clock.default_mclk; 6182 pl->sclk = rdev->clock.default_sclk; 6183 pl->vddc = vddc; 6184 pl->vddci = vddci; 6185 si_pi->mvdd_bootup_value = mvdd; 6186 } 6187 6188 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6189 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6190 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6191 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6192 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6193 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6194 } 6195 } 6196 6197 static int si_parse_power_table(struct radeon_device *rdev) 6198 { 6199 struct radeon_mode_info *mode_info = &rdev->mode_info; 6200 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6201 union pplib_power_state *power_state; 6202 int i, j, k, non_clock_array_index, clock_array_index; 6203 union pplib_clock_info *clock_info; 6204 struct _StateArray *state_array; 6205 struct _ClockInfoArray *clock_info_array; 6206 struct _NonClockInfoArray *non_clock_info_array; 6207 union power_info *power_info; 6208 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6209 u16 data_offset; 6210 u8 frev, crev; 6211 u8 *power_state_offset; 6212 struct ni_ps *ps; 6213 6214 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6215 &frev, &crev, &data_offset)) 6216 return -EINVAL; 6217 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6218 6219 state_array = (struct _StateArray *) 6220 (mode_info->atom_context->bios + data_offset + 6221 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6222 clock_info_array = (struct _ClockInfoArray *) 6223 (mode_info->atom_context->bios + data_offset + 6224 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6225 non_clock_info_array = (struct _NonClockInfoArray *) 6226 (mode_info->atom_context->bios + data_offset + 6227 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6228 6229 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6230 state_array->ucNumEntries, GFP_KERNEL); 6231 if (!rdev->pm.dpm.ps) 6232 return -ENOMEM; 6233 power_state_offset = (u8 *)state_array->states; 6234 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 6235 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 6236 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 6237 for (i = 0; i < state_array->ucNumEntries; i++) { 6238 power_state = (union pplib_power_state *)power_state_offset; 6239 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6240 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6241 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6242 if (!rdev->pm.power_state[i].clock_info) 6243 return -EINVAL; 6244 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6245 if (ps == NULL) { 6246 kfree(rdev->pm.dpm.ps); 6247 return -ENOMEM; 6248 } 6249 rdev->pm.dpm.ps[i].ps_priv = ps; 6250 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6251 non_clock_info, 6252 non_clock_info_array->ucEntrySize); 6253 k = 0; 6254 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6255 clock_array_index = power_state->v2.clockInfoIndex[j]; 6256 if (clock_array_index >= clock_info_array->ucNumEntries) 6257 continue; 6258 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6259 break; 6260 clock_info = (union pplib_clock_info *) 6261 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6262 si_parse_pplib_clock_info(rdev, 6263 &rdev->pm.dpm.ps[i], k, 6264 clock_info); 6265 k++; 6266 } 6267 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6268 } 6269 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6270 return 0; 6271 } 6272 6273 int si_dpm_init(struct radeon_device *rdev) 6274 { 6275 struct rv7xx_power_info *pi; 6276 struct evergreen_power_info *eg_pi; 6277 struct ni_power_info *ni_pi; 6278 struct si_power_info *si_pi; 6279 struct atom_clock_dividers dividers; 6280 int ret; 6281 u32 mask; 6282 6283 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6284 if (si_pi == NULL) 6285 return -ENOMEM; 6286 rdev->pm.dpm.priv = si_pi; 6287 ni_pi = &si_pi->ni; 6288 eg_pi = &ni_pi->eg; 6289 pi = &eg_pi->rv7xx; 6290 6291 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6292 if (ret) 6293 si_pi->sys_pcie_mask = 0; 6294 else 6295 si_pi->sys_pcie_mask = mask; 6296 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6297 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6298 6299 si_set_max_cu_value(rdev); 6300 6301 rv770_get_max_vddc(rdev); 6302 si_get_leakage_vddc(rdev); 6303 si_patch_dependency_tables_based_on_leakage(rdev); 6304 6305 pi->acpi_vddc = 0; 6306 eg_pi->acpi_vddci = 0; 6307 pi->min_vddc_in_table = 0; 6308 pi->max_vddc_in_table = 0; 6309 6310 ret = si_parse_power_table(rdev); 6311 if (ret) 6312 return ret; 6313 ret = r600_parse_extended_power_table(rdev); 6314 if (ret) 6315 return ret; 6316 6317 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6318 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6319 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6320 r600_free_extended_power_table(rdev); 6321 return -ENOMEM; 6322 } 6323 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6324 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6325 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6326 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6327 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6328 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6329 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6330 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6331 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6332 6333 if (rdev->pm.dpm.voltage_response_time == 0) 6334 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6335 if (rdev->pm.dpm.backbias_response_time == 0) 6336 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6337 6338 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6339 0, false, ÷rs); 6340 if (ret) 6341 pi->ref_div = dividers.ref_div + 1; 6342 else 6343 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6344 6345 eg_pi->smu_uvd_hs = false; 6346 6347 pi->mclk_strobe_mode_threshold = 40000; 6348 if (si_is_special_1gb_platform(rdev)) 6349 pi->mclk_stutter_mode_threshold = 0; 6350 else 6351 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6352 pi->mclk_edc_enable_threshold = 40000; 6353 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6354 6355 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6356 6357 pi->voltage_control = 6358 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT); 6359 6360 pi->mvdd_control = 6361 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT); 6362 6363 eg_pi->vddci_control = 6364 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT); 6365 6366 si_pi->vddc_phase_shed_control = 6367 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6368 6369 rv770_get_engine_memory_ss(rdev); 6370 6371 pi->asi = RV770_ASI_DFLT; 6372 pi->pasi = CYPRESS_HASI_DFLT; 6373 pi->vrc = SISLANDS_VRC_DFLT; 6374 6375 pi->gfx_clock_gating = true; 6376 6377 eg_pi->sclk_deep_sleep = true; 6378 si_pi->sclk_deep_sleep_above_low = false; 6379 6380 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6381 pi->thermal_protection = true; 6382 else 6383 pi->thermal_protection = false; 6384 6385 eg_pi->dynamic_ac_timing = true; 6386 6387 eg_pi->light_sleep = true; 6388 #if defined(CONFIG_ACPI) 6389 eg_pi->pcie_performance_request = 6390 radeon_acpi_is_pcie_performance_request_supported(rdev); 6391 #else 6392 eg_pi->pcie_performance_request = false; 6393 #endif 6394 6395 si_pi->sram_end = SMC_RAM_END; 6396 6397 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6398 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6399 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6400 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6401 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6402 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6403 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6404 6405 si_initialize_powertune_defaults(rdev); 6406 6407 return 0; 6408 } 6409 6410 void si_dpm_fini(struct radeon_device *rdev) 6411 { 6412 int i; 6413 6414 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6415 kfree(rdev->pm.dpm.ps[i].ps_priv); 6416 } 6417 kfree(rdev->pm.dpm.ps); 6418 kfree(rdev->pm.dpm.priv); 6419 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6420 r600_free_extended_power_table(rdev); 6421 } 6422 6423 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6424 struct seq_file *m) 6425 { 6426 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 6427 struct ni_ps *ps = ni_get_ps(rps); 6428 struct rv7xx_pl *pl; 6429 u32 current_index = 6430 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6431 CURRENT_STATE_INDEX_SHIFT; 6432 6433 if (current_index >= ps->performance_level_count) { 6434 seq_printf(m, "invalid dpm profile %d\n", current_index); 6435 } else { 6436 pl = &ps->performance_levels[current_index]; 6437 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6438 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6439 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6440 } 6441 } 6442