1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 #if 0 /* unused */ 255 static const struct si_dte_data dte_data_tahiti_le = 256 { 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271 }; 272 #endif 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1745 1746 static int si_populate_voltage_value(struct radeon_device *rdev, 1747 const struct atom_voltage_table *table, 1748 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1749 static int si_get_std_voltage_value(struct radeon_device *rdev, 1750 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1751 u16 *std_voltage); 1752 static int si_write_smc_soft_register(struct radeon_device *rdev, 1753 u16 reg_offset, u32 value); 1754 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1755 struct rv7xx_pl *pl, 1756 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1757 static int si_calculate_sclk_params(struct radeon_device *rdev, 1758 u32 engine_clock, 1759 SISLANDS_SMC_SCLK_VALUE *sclk); 1760 1761 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1762 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1763 1764 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1765 { 1766 struct si_power_info *pi = rdev->pm.dpm.priv; 1767 1768 return pi; 1769 } 1770 1771 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1772 u16 v, s32 t, u32 ileakage, u32 *leakage) 1773 { 1774 s64 kt, kv, leakage_w, i_leakage, vddc; 1775 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1776 s64 tmp; 1777 1778 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1779 vddc = div64_s64(drm_int2fixp(v), 1000); 1780 temperature = div64_s64(drm_int2fixp(t), 1000); 1781 1782 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1783 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1784 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1785 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1786 t_ref = drm_int2fixp(coeff->t_ref); 1787 1788 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1789 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1790 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1791 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1792 1793 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1794 1795 *leakage = drm_fixp2int(leakage_w * 1000); 1796 } 1797 1798 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1799 const struct ni_leakage_coeffients *coeff, 1800 u16 v, 1801 s32 t, 1802 u32 i_leakage, 1803 u32 *leakage) 1804 { 1805 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1806 } 1807 1808 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1809 const u32 fixed_kt, u16 v, 1810 u32 ileakage, u32 *leakage) 1811 { 1812 s64 kt, kv, leakage_w, i_leakage, vddc; 1813 1814 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1815 vddc = div64_s64(drm_int2fixp(v), 1000); 1816 1817 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1818 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1819 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1820 1821 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1822 1823 *leakage = drm_fixp2int(leakage_w * 1000); 1824 } 1825 1826 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1827 const struct ni_leakage_coeffients *coeff, 1828 const u32 fixed_kt, 1829 u16 v, 1830 u32 i_leakage, 1831 u32 *leakage) 1832 { 1833 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1834 } 1835 1836 1837 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1838 struct si_dte_data *dte_data) 1839 { 1840 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1841 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1842 u32 k = dte_data->k; 1843 u32 t_max = dte_data->max_t; 1844 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1845 u32 t_0 = dte_data->t0; 1846 u32 i; 1847 1848 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1849 dte_data->tdep_count = 3; 1850 1851 for (i = 0; i < k; i++) { 1852 dte_data->r[i] = 1853 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1854 (p_limit2 * (u32)100); 1855 } 1856 1857 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1858 1859 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1860 dte_data->tdep_r[i] = dte_data->r[4]; 1861 } 1862 } else { 1863 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1864 } 1865 } 1866 1867 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1868 { 1869 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1870 struct si_power_info *si_pi = si_get_pi(rdev); 1871 bool update_dte_from_pl2 = false; 1872 1873 if (rdev->family == CHIP_TAHITI) { 1874 si_pi->cac_weights = cac_weights_tahiti; 1875 si_pi->lcac_config = lcac_tahiti; 1876 si_pi->cac_override = cac_override_tahiti; 1877 si_pi->powertune_data = &powertune_data_tahiti; 1878 si_pi->dte_data = dte_data_tahiti; 1879 1880 switch (rdev->pdev->device) { 1881 case 0x6798: 1882 si_pi->dte_data.enable_dte_by_default = true; 1883 break; 1884 case 0x6799: 1885 si_pi->dte_data = dte_data_new_zealand; 1886 break; 1887 case 0x6790: 1888 case 0x6791: 1889 case 0x6792: 1890 case 0x679E: 1891 si_pi->dte_data = dte_data_aruba_pro; 1892 update_dte_from_pl2 = true; 1893 break; 1894 case 0x679B: 1895 si_pi->dte_data = dte_data_malta; 1896 update_dte_from_pl2 = true; 1897 break; 1898 case 0x679A: 1899 si_pi->dte_data = dte_data_tahiti_pro; 1900 update_dte_from_pl2 = true; 1901 break; 1902 default: 1903 if (si_pi->dte_data.enable_dte_by_default == true) 1904 DRM_ERROR("DTE is not enabled!\n"); 1905 break; 1906 } 1907 } else if (rdev->family == CHIP_PITCAIRN) { 1908 switch (rdev->pdev->device) { 1909 case 0x6810: 1910 case 0x6818: 1911 si_pi->cac_weights = cac_weights_pitcairn; 1912 si_pi->lcac_config = lcac_pitcairn; 1913 si_pi->cac_override = cac_override_pitcairn; 1914 si_pi->powertune_data = &powertune_data_pitcairn; 1915 si_pi->dte_data = dte_data_curacao_xt; 1916 update_dte_from_pl2 = true; 1917 break; 1918 case 0x6819: 1919 case 0x6811: 1920 si_pi->cac_weights = cac_weights_pitcairn; 1921 si_pi->lcac_config = lcac_pitcairn; 1922 si_pi->cac_override = cac_override_pitcairn; 1923 si_pi->powertune_data = &powertune_data_pitcairn; 1924 si_pi->dte_data = dte_data_curacao_pro; 1925 update_dte_from_pl2 = true; 1926 break; 1927 case 0x6800: 1928 case 0x6806: 1929 si_pi->cac_weights = cac_weights_pitcairn; 1930 si_pi->lcac_config = lcac_pitcairn; 1931 si_pi->cac_override = cac_override_pitcairn; 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1933 si_pi->dte_data = dte_data_neptune_xt; 1934 update_dte_from_pl2 = true; 1935 break; 1936 default: 1937 si_pi->cac_weights = cac_weights_pitcairn; 1938 si_pi->lcac_config = lcac_pitcairn; 1939 si_pi->cac_override = cac_override_pitcairn; 1940 si_pi->powertune_data = &powertune_data_pitcairn; 1941 si_pi->dte_data = dte_data_pitcairn; 1942 break; 1943 } 1944 } else if (rdev->family == CHIP_VERDE) { 1945 si_pi->lcac_config = lcac_cape_verde; 1946 si_pi->cac_override = cac_override_cape_verde; 1947 si_pi->powertune_data = &powertune_data_cape_verde; 1948 1949 switch (rdev->pdev->device) { 1950 case 0x683B: 1951 case 0x683F: 1952 case 0x6829: 1953 case 0x6835: 1954 si_pi->cac_weights = cac_weights_cape_verde_pro; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x682C: 1958 si_pi->cac_weights = cac_weights_cape_verde_pro; 1959 si_pi->dte_data = dte_data_sun_xt; 1960 break; 1961 case 0x6825: 1962 case 0x6827: 1963 si_pi->cac_weights = cac_weights_heathrow; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x6824: 1967 case 0x682D: 1968 si_pi->cac_weights = cac_weights_chelsea_xt; 1969 si_pi->dte_data = dte_data_cape_verde; 1970 break; 1971 case 0x682F: 1972 si_pi->cac_weights = cac_weights_chelsea_pro; 1973 si_pi->dte_data = dte_data_cape_verde; 1974 break; 1975 case 0x6820: 1976 si_pi->cac_weights = cac_weights_heathrow; 1977 si_pi->dte_data = dte_data_venus_xtx; 1978 break; 1979 case 0x6821: 1980 si_pi->cac_weights = cac_weights_heathrow; 1981 si_pi->dte_data = dte_data_venus_xt; 1982 break; 1983 case 0x6823: 1984 case 0x682B: 1985 case 0x6822: 1986 case 0x682A: 1987 si_pi->cac_weights = cac_weights_chelsea_pro; 1988 si_pi->dte_data = dte_data_venus_pro; 1989 break; 1990 default: 1991 si_pi->cac_weights = cac_weights_cape_verde; 1992 si_pi->dte_data = dte_data_cape_verde; 1993 break; 1994 } 1995 } else if (rdev->family == CHIP_OLAND) { 1996 switch (rdev->pdev->device) { 1997 case 0x6601: 1998 case 0x6621: 1999 case 0x6603: 2000 case 0x6605: 2001 si_pi->cac_weights = cac_weights_mars_pro; 2002 si_pi->lcac_config = lcac_mars_pro; 2003 si_pi->cac_override = cac_override_oland; 2004 si_pi->powertune_data = &powertune_data_mars_pro; 2005 si_pi->dte_data = dte_data_mars_pro; 2006 update_dte_from_pl2 = true; 2007 break; 2008 case 0x6600: 2009 case 0x6606: 2010 case 0x6620: 2011 case 0x6604: 2012 si_pi->cac_weights = cac_weights_mars_xt; 2013 si_pi->lcac_config = lcac_mars_pro; 2014 si_pi->cac_override = cac_override_oland; 2015 si_pi->powertune_data = &powertune_data_mars_pro; 2016 si_pi->dte_data = dte_data_mars_pro; 2017 update_dte_from_pl2 = true; 2018 break; 2019 case 0x6611: 2020 case 0x6613: 2021 case 0x6608: 2022 si_pi->cac_weights = cac_weights_oland_pro; 2023 si_pi->lcac_config = lcac_mars_pro; 2024 si_pi->cac_override = cac_override_oland; 2025 si_pi->powertune_data = &powertune_data_mars_pro; 2026 si_pi->dte_data = dte_data_mars_pro; 2027 update_dte_from_pl2 = true; 2028 break; 2029 case 0x6610: 2030 si_pi->cac_weights = cac_weights_oland_xt; 2031 si_pi->lcac_config = lcac_mars_pro; 2032 si_pi->cac_override = cac_override_oland; 2033 si_pi->powertune_data = &powertune_data_mars_pro; 2034 si_pi->dte_data = dte_data_mars_pro; 2035 update_dte_from_pl2 = true; 2036 break; 2037 default: 2038 si_pi->cac_weights = cac_weights_oland; 2039 si_pi->lcac_config = lcac_oland; 2040 si_pi->cac_override = cac_override_oland; 2041 si_pi->powertune_data = &powertune_data_oland; 2042 si_pi->dte_data = dte_data_oland; 2043 break; 2044 } 2045 } else if (rdev->family == CHIP_HAINAN) { 2046 si_pi->cac_weights = cac_weights_hainan; 2047 si_pi->lcac_config = lcac_oland; 2048 si_pi->cac_override = cac_override_oland; 2049 si_pi->powertune_data = &powertune_data_hainan; 2050 si_pi->dte_data = dte_data_sun_xt; 2051 update_dte_from_pl2 = true; 2052 } else { 2053 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2054 return; 2055 } 2056 2057 ni_pi->enable_power_containment = false; 2058 ni_pi->enable_cac = false; 2059 ni_pi->enable_sq_ramping = false; 2060 si_pi->enable_dte = false; 2061 2062 if (si_pi->powertune_data->enable_powertune_by_default) { 2063 ni_pi->enable_power_containment= true; 2064 ni_pi->enable_cac = true; 2065 if (si_pi->dte_data.enable_dte_by_default) { 2066 si_pi->enable_dte = true; 2067 if (update_dte_from_pl2) 2068 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2069 2070 } 2071 ni_pi->enable_sq_ramping = true; 2072 } 2073 2074 ni_pi->driver_calculate_cac_leakage = true; 2075 ni_pi->cac_configuration_required = true; 2076 2077 if (ni_pi->cac_configuration_required) { 2078 ni_pi->support_cac_long_term_average = true; 2079 si_pi->dyn_powertune_data.l2_lta_window_size = 2080 si_pi->powertune_data->l2_lta_window_size_default; 2081 si_pi->dyn_powertune_data.lts_truncate = 2082 si_pi->powertune_data->lts_truncate_default; 2083 } else { 2084 ni_pi->support_cac_long_term_average = false; 2085 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2086 si_pi->dyn_powertune_data.lts_truncate = 0; 2087 } 2088 2089 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2090 } 2091 2092 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2093 { 2094 return 1; 2095 } 2096 2097 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2098 { 2099 u32 xclk; 2100 u32 wintime; 2101 u32 cac_window; 2102 u32 cac_window_size; 2103 2104 xclk = radeon_get_xclk(rdev); 2105 2106 if (xclk == 0) 2107 return 0; 2108 2109 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2110 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2111 2112 wintime = (cac_window_size * 100) / xclk; 2113 2114 return wintime; 2115 } 2116 2117 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2118 { 2119 return power_in_watts; 2120 } 2121 2122 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2123 bool adjust_polarity, 2124 u32 tdp_adjustment, 2125 u32 *tdp_limit, 2126 u32 *near_tdp_limit) 2127 { 2128 u32 adjustment_delta, max_tdp_limit; 2129 2130 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2131 return -EINVAL; 2132 2133 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2134 2135 if (adjust_polarity) { 2136 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2138 } else { 2139 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2140 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2141 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2142 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2143 else 2144 *near_tdp_limit = 0; 2145 } 2146 2147 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2148 return -EINVAL; 2149 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2150 return -EINVAL; 2151 2152 return 0; 2153 } 2154 2155 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2156 struct radeon_ps *radeon_state) 2157 { 2158 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2159 struct si_power_info *si_pi = si_get_pi(rdev); 2160 2161 if (ni_pi->enable_power_containment) { 2162 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2163 PP_SIslands_PAPMParameters *papm_parm; 2164 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2165 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2166 u32 tdp_limit; 2167 u32 near_tdp_limit; 2168 int ret; 2169 2170 if (scaling_factor == 0) 2171 return -EINVAL; 2172 2173 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2174 2175 ret = si_calculate_adjusted_tdp_limits(rdev, 2176 false, /* ??? */ 2177 rdev->pm.dpm.tdp_adjustment, 2178 &tdp_limit, 2179 &near_tdp_limit); 2180 if (ret) 2181 return ret; 2182 2183 smc_table->dpm2Params.TDPLimit = 2184 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2185 smc_table->dpm2Params.NearTDPLimit = 2186 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2187 smc_table->dpm2Params.SafePowerLimit = 2188 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2189 2190 ret = si_copy_bytes_to_smc(rdev, 2191 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2192 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2193 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2194 sizeof(u32) * 3, 2195 si_pi->sram_end); 2196 if (ret) 2197 return ret; 2198 2199 if (si_pi->enable_ppm) { 2200 papm_parm = &si_pi->papm_parm; 2201 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2202 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2203 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2204 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2205 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2206 papm_parm->PlatformPowerLimit = 0xffffffff; 2207 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2208 2209 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2210 (u8 *)papm_parm, 2211 sizeof(PP_SIslands_PAPMParameters), 2212 si_pi->sram_end); 2213 if (ret) 2214 return ret; 2215 } 2216 } 2217 return 0; 2218 } 2219 2220 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2221 struct radeon_ps *radeon_state) 2222 { 2223 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2224 struct si_power_info *si_pi = si_get_pi(rdev); 2225 2226 if (ni_pi->enable_power_containment) { 2227 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2228 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2229 int ret; 2230 2231 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2232 2233 smc_table->dpm2Params.NearTDPLimit = 2234 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2235 smc_table->dpm2Params.SafePowerLimit = 2236 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2237 2238 ret = si_copy_bytes_to_smc(rdev, 2239 (si_pi->state_table_start + 2240 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2241 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2242 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2243 sizeof(u32) * 2, 2244 si_pi->sram_end); 2245 if (ret) 2246 return ret; 2247 } 2248 2249 return 0; 2250 } 2251 2252 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2253 const u16 prev_std_vddc, 2254 const u16 curr_std_vddc) 2255 { 2256 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2257 u64 prev_vddc = (u64)prev_std_vddc; 2258 u64 curr_vddc = (u64)curr_std_vddc; 2259 u64 pwr_efficiency_ratio, n, d; 2260 2261 if ((prev_vddc == 0) || (curr_vddc == 0)) 2262 return 0; 2263 2264 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2265 d = prev_vddc * prev_vddc; 2266 pwr_efficiency_ratio = div64_u64(n, d); 2267 2268 if (pwr_efficiency_ratio > (u64)0xFFFF) 2269 return 0; 2270 2271 return (u16)pwr_efficiency_ratio; 2272 } 2273 2274 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2275 struct radeon_ps *radeon_state) 2276 { 2277 struct si_power_info *si_pi = si_get_pi(rdev); 2278 2279 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2280 radeon_state->vclk && radeon_state->dclk) 2281 return true; 2282 2283 return false; 2284 } 2285 2286 static int si_populate_power_containment_values(struct radeon_device *rdev, 2287 struct radeon_ps *radeon_state, 2288 SISLANDS_SMC_SWSTATE *smc_state) 2289 { 2290 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2291 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2292 struct ni_ps *state = ni_get_ps(radeon_state); 2293 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2294 u32 prev_sclk; 2295 u32 max_sclk; 2296 u32 min_sclk; 2297 u16 prev_std_vddc; 2298 u16 curr_std_vddc; 2299 int i; 2300 u16 pwr_efficiency_ratio; 2301 u8 max_ps_percent; 2302 bool disable_uvd_power_tune; 2303 int ret; 2304 2305 if (ni_pi->enable_power_containment == false) 2306 return 0; 2307 2308 if (state->performance_level_count == 0) 2309 return -EINVAL; 2310 2311 if (smc_state->levelCount != state->performance_level_count) 2312 return -EINVAL; 2313 2314 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2315 2316 smc_state->levels[0].dpm2.MaxPS = 0; 2317 smc_state->levels[0].dpm2.NearTDPDec = 0; 2318 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2319 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2320 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2321 2322 for (i = 1; i < state->performance_level_count; i++) { 2323 prev_sclk = state->performance_levels[i-1].sclk; 2324 max_sclk = state->performance_levels[i].sclk; 2325 if (i == 1) 2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2327 else 2328 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2329 2330 if (prev_sclk > max_sclk) 2331 return -EINVAL; 2332 2333 if ((max_ps_percent == 0) || 2334 (prev_sclk == max_sclk) || 2335 disable_uvd_power_tune) { 2336 min_sclk = max_sclk; 2337 } else if (i == 1) { 2338 min_sclk = prev_sclk; 2339 } else { 2340 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2341 } 2342 2343 if (min_sclk < state->performance_levels[0].sclk) 2344 min_sclk = state->performance_levels[0].sclk; 2345 2346 if (min_sclk == 0) 2347 return -EINVAL; 2348 2349 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2350 state->performance_levels[i-1].vddc, &vddc); 2351 if (ret) 2352 return ret; 2353 2354 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2359 state->performance_levels[i].vddc, &vddc); 2360 if (ret) 2361 return ret; 2362 2363 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2364 if (ret) 2365 return ret; 2366 2367 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2368 prev_std_vddc, curr_std_vddc); 2369 2370 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2371 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2372 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2373 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2374 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2375 } 2376 2377 return 0; 2378 } 2379 2380 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2381 struct radeon_ps *radeon_state, 2382 SISLANDS_SMC_SWSTATE *smc_state) 2383 { 2384 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2385 struct ni_ps *state = ni_get_ps(radeon_state); 2386 u32 sq_power_throttle, sq_power_throttle2; 2387 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2388 int i; 2389 2390 if (state->performance_level_count == 0) 2391 return -EINVAL; 2392 2393 if (smc_state->levelCount != state->performance_level_count) 2394 return -EINVAL; 2395 2396 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2397 return -EINVAL; 2398 2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2403 enable_sq_ramping = false; 2404 2405 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2406 enable_sq_ramping = false; 2407 2408 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2409 enable_sq_ramping = false; 2410 2411 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2412 enable_sq_ramping = false; 2413 2414 for (i = 0; i < state->performance_level_count; i++) { 2415 sq_power_throttle = 0; 2416 sq_power_throttle2 = 0; 2417 2418 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2419 enable_sq_ramping) { 2420 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2421 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2422 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2423 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2424 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2425 } else { 2426 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2427 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2428 } 2429 2430 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2431 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2432 } 2433 2434 return 0; 2435 } 2436 2437 static int si_enable_power_containment(struct radeon_device *rdev, 2438 struct radeon_ps *radeon_new_state, 2439 bool enable) 2440 { 2441 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2442 PPSMC_Result smc_result; 2443 int ret = 0; 2444 2445 if (ni_pi->enable_power_containment) { 2446 if (enable) { 2447 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2448 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2449 if (smc_result != PPSMC_Result_OK) { 2450 ret = -EINVAL; 2451 ni_pi->pc_enabled = false; 2452 } else { 2453 ni_pi->pc_enabled = true; 2454 } 2455 } 2456 } else { 2457 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2458 if (smc_result != PPSMC_Result_OK) 2459 ret = -EINVAL; 2460 ni_pi->pc_enabled = false; 2461 } 2462 } 2463 2464 return ret; 2465 } 2466 2467 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2468 { 2469 struct si_power_info *si_pi = si_get_pi(rdev); 2470 int ret = 0; 2471 struct si_dte_data *dte_data = &si_pi->dte_data; 2472 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2473 u32 table_size; 2474 u8 tdep_count; 2475 u32 i; 2476 2477 if (dte_data == NULL) 2478 si_pi->enable_dte = false; 2479 2480 if (si_pi->enable_dte == false) 2481 return 0; 2482 2483 if (dte_data->k <= 0) 2484 return -EINVAL; 2485 2486 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2487 if (dte_tables == NULL) { 2488 si_pi->enable_dte = false; 2489 return -ENOMEM; 2490 } 2491 2492 table_size = dte_data->k; 2493 2494 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2495 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2496 2497 tdep_count = dte_data->tdep_count; 2498 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2499 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2500 2501 dte_tables->K = cpu_to_be32(table_size); 2502 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2503 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2504 dte_tables->WindowSize = dte_data->window_size; 2505 dte_tables->temp_select = dte_data->temp_select; 2506 dte_tables->DTE_mode = dte_data->dte_mode; 2507 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2508 2509 if (tdep_count > 0) 2510 table_size--; 2511 2512 for (i = 0; i < table_size; i++) { 2513 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2514 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2515 } 2516 2517 dte_tables->Tdep_count = tdep_count; 2518 2519 for (i = 0; i < (u32)tdep_count; i++) { 2520 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2521 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2522 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2523 } 2524 2525 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2526 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2527 kfree(dte_tables); 2528 2529 return ret; 2530 } 2531 2532 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2533 u16 *max, u16 *min) 2534 { 2535 struct si_power_info *si_pi = si_get_pi(rdev); 2536 struct radeon_cac_leakage_table *table = 2537 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2538 u32 i; 2539 u32 v0_loadline; 2540 2541 2542 if (table == NULL) 2543 return -EINVAL; 2544 2545 *max = 0; 2546 *min = 0xFFFF; 2547 2548 for (i = 0; i < table->count; i++) { 2549 if (table->entries[i].vddc > *max) 2550 *max = table->entries[i].vddc; 2551 if (table->entries[i].vddc < *min) 2552 *min = table->entries[i].vddc; 2553 } 2554 2555 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2556 return -EINVAL; 2557 2558 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2559 2560 if (v0_loadline > 0xFFFFUL) 2561 return -EINVAL; 2562 2563 *min = (u16)v0_loadline; 2564 2565 if ((*min > *max) || (*max == 0) || (*min == 0)) 2566 return -EINVAL; 2567 2568 return 0; 2569 } 2570 2571 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2572 { 2573 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2574 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2575 } 2576 2577 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2578 PP_SIslands_CacConfig *cac_tables, 2579 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2580 u16 t0, u16 t_step) 2581 { 2582 struct si_power_info *si_pi = si_get_pi(rdev); 2583 u32 leakage; 2584 unsigned int i, j; 2585 s32 t; 2586 u32 smc_leakage; 2587 u32 scaling_factor; 2588 u16 voltage; 2589 2590 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2591 2592 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2593 t = (1000 * (i * t_step + t0)); 2594 2595 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2596 voltage = vddc_max - (vddc_step * j); 2597 2598 si_calculate_leakage_for_v_and_t(rdev, 2599 &si_pi->powertune_data->leakage_coefficients, 2600 voltage, 2601 t, 2602 si_pi->dyn_powertune_data.cac_leakage, 2603 &leakage); 2604 2605 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2606 2607 if (smc_leakage > 0xFFFF) 2608 smc_leakage = 0xFFFF; 2609 2610 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2611 cpu_to_be16((u16)smc_leakage); 2612 } 2613 } 2614 return 0; 2615 } 2616 2617 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2618 PP_SIslands_CacConfig *cac_tables, 2619 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2620 { 2621 struct si_power_info *si_pi = si_get_pi(rdev); 2622 u32 leakage; 2623 unsigned int i, j; 2624 u32 smc_leakage; 2625 u32 scaling_factor; 2626 u16 voltage; 2627 2628 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2629 2630 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2631 voltage = vddc_max - (vddc_step * j); 2632 2633 si_calculate_leakage_for_v(rdev, 2634 &si_pi->powertune_data->leakage_coefficients, 2635 si_pi->powertune_data->fixed_kt, 2636 voltage, 2637 si_pi->dyn_powertune_data.cac_leakage, 2638 &leakage); 2639 2640 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2641 2642 if (smc_leakage > 0xFFFF) 2643 smc_leakage = 0xFFFF; 2644 2645 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2646 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2647 cpu_to_be16((u16)smc_leakage); 2648 } 2649 return 0; 2650 } 2651 2652 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2653 { 2654 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2655 struct si_power_info *si_pi = si_get_pi(rdev); 2656 PP_SIslands_CacConfig *cac_tables = NULL; 2657 u16 vddc_max, vddc_min, vddc_step; 2658 u16 t0, t_step; 2659 u32 load_line_slope, reg; 2660 int ret = 0; 2661 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2662 2663 if (ni_pi->enable_cac == false) 2664 return 0; 2665 2666 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2667 if (!cac_tables) 2668 return -ENOMEM; 2669 2670 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2671 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2672 WREG32(CG_CAC_CTRL, reg); 2673 2674 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2675 si_pi->dyn_powertune_data.dc_pwr_value = 2676 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2677 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2678 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2679 2680 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2681 2682 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2683 if (ret) 2684 goto done_free; 2685 2686 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2687 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2688 t_step = 4; 2689 t0 = 60; 2690 2691 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2692 ret = si_init_dte_leakage_table(rdev, cac_tables, 2693 vddc_max, vddc_min, vddc_step, 2694 t0, t_step); 2695 else 2696 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2697 vddc_max, vddc_min, vddc_step); 2698 if (ret) 2699 goto done_free; 2700 2701 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2702 2703 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2704 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2705 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2706 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2707 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2708 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2709 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2710 cac_tables->calculation_repeats = cpu_to_be32(2); 2711 cac_tables->dc_cac = cpu_to_be32(0); 2712 cac_tables->log2_PG_LKG_SCALE = 12; 2713 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2714 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2715 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2716 2717 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2718 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2719 2720 if (ret) 2721 goto done_free; 2722 2723 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2724 2725 done_free: 2726 if (ret) { 2727 ni_pi->enable_cac = false; 2728 ni_pi->enable_power_containment = false; 2729 } 2730 2731 kfree(cac_tables); 2732 2733 return 0; 2734 } 2735 2736 static int si_program_cac_config_registers(struct radeon_device *rdev, 2737 const struct si_cac_config_reg *cac_config_regs) 2738 { 2739 const struct si_cac_config_reg *config_regs = cac_config_regs; 2740 u32 data = 0, offset; 2741 2742 if (!config_regs) 2743 return -EINVAL; 2744 2745 while (config_regs->offset != 0xFFFFFFFF) { 2746 switch (config_regs->type) { 2747 case SISLANDS_CACCONFIG_CGIND: 2748 offset = SMC_CG_IND_START + config_regs->offset; 2749 if (offset < SMC_CG_IND_END) 2750 data = RREG32_SMC(offset); 2751 break; 2752 default: 2753 data = RREG32(config_regs->offset << 2); 2754 break; 2755 } 2756 2757 data &= ~config_regs->mask; 2758 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2759 2760 switch (config_regs->type) { 2761 case SISLANDS_CACCONFIG_CGIND: 2762 offset = SMC_CG_IND_START + config_regs->offset; 2763 if (offset < SMC_CG_IND_END) 2764 WREG32_SMC(offset, data); 2765 break; 2766 default: 2767 WREG32(config_regs->offset << 2, data); 2768 break; 2769 } 2770 config_regs++; 2771 } 2772 return 0; 2773 } 2774 2775 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2776 { 2777 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2778 struct si_power_info *si_pi = si_get_pi(rdev); 2779 int ret; 2780 2781 if ((ni_pi->enable_cac == false) || 2782 (ni_pi->cac_configuration_required == false)) 2783 return 0; 2784 2785 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2786 if (ret) 2787 return ret; 2788 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2789 if (ret) 2790 return ret; 2791 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2792 if (ret) 2793 return ret; 2794 2795 return 0; 2796 } 2797 2798 static int si_enable_smc_cac(struct radeon_device *rdev, 2799 struct radeon_ps *radeon_new_state, 2800 bool enable) 2801 { 2802 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2803 struct si_power_info *si_pi = si_get_pi(rdev); 2804 PPSMC_Result smc_result; 2805 int ret = 0; 2806 2807 if (ni_pi->enable_cac) { 2808 if (enable) { 2809 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2810 if (ni_pi->support_cac_long_term_average) { 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2812 if (smc_result != PPSMC_Result_OK) 2813 ni_pi->support_cac_long_term_average = false; 2814 } 2815 2816 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2817 if (smc_result != PPSMC_Result_OK) { 2818 ret = -EINVAL; 2819 ni_pi->cac_enabled = false; 2820 } else { 2821 ni_pi->cac_enabled = true; 2822 } 2823 2824 if (si_pi->enable_dte) { 2825 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2826 if (smc_result != PPSMC_Result_OK) 2827 ret = -EINVAL; 2828 } 2829 } 2830 } else if (ni_pi->cac_enabled) { 2831 if (si_pi->enable_dte) 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2833 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2835 2836 ni_pi->cac_enabled = false; 2837 2838 if (ni_pi->support_cac_long_term_average) 2839 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2840 } 2841 } 2842 return ret; 2843 } 2844 2845 static int si_init_smc_spll_table(struct radeon_device *rdev) 2846 { 2847 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2848 struct si_power_info *si_pi = si_get_pi(rdev); 2849 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2850 SISLANDS_SMC_SCLK_VALUE sclk_params; 2851 u32 fb_div, p_div; 2852 u32 clk_s, clk_v; 2853 u32 sclk = 0; 2854 int ret = 0; 2855 u32 tmp; 2856 int i; 2857 2858 if (si_pi->spll_table_start == 0) 2859 return -EINVAL; 2860 2861 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2862 if (spll_table == NULL) 2863 return -ENOMEM; 2864 2865 for (i = 0; i < 256; i++) { 2866 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2867 if (ret) 2868 break; 2869 2870 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2871 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2872 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2873 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2874 2875 fb_div &= ~0x00001FFF; 2876 fb_div >>= 1; 2877 clk_v >>= 6; 2878 2879 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2880 ret = -EINVAL; 2881 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2882 ret = -EINVAL; 2883 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2884 ret = -EINVAL; 2885 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2886 ret = -EINVAL; 2887 2888 if (ret) 2889 break; 2890 2891 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2892 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2893 spll_table->freq[i] = cpu_to_be32(tmp); 2894 2895 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2896 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2897 spll_table->ss[i] = cpu_to_be32(tmp); 2898 2899 sclk += 512; 2900 } 2901 2902 2903 if (!ret) 2904 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2905 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2906 si_pi->sram_end); 2907 2908 if (ret) 2909 ni_pi->enable_power_containment = false; 2910 2911 kfree(spll_table); 2912 2913 return ret; 2914 } 2915 2916 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2917 u16 vce_voltage) 2918 { 2919 u16 highest_leakage = 0; 2920 struct si_power_info *si_pi = si_get_pi(rdev); 2921 int i; 2922 2923 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2924 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2925 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2926 } 2927 2928 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2929 return highest_leakage; 2930 2931 return vce_voltage; 2932 } 2933 2934 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2935 u32 evclk, u32 ecclk, u16 *voltage) 2936 { 2937 u32 i; 2938 int ret = -EINVAL; 2939 struct radeon_vce_clock_voltage_dependency_table *table = 2940 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2941 2942 if (((evclk == 0) && (ecclk == 0)) || 2943 (table && (table->count == 0))) { 2944 *voltage = 0; 2945 return 0; 2946 } 2947 2948 for (i = 0; i < table->count; i++) { 2949 if ((evclk <= table->entries[i].evclk) && 2950 (ecclk <= table->entries[i].ecclk)) { 2951 *voltage = table->entries[i].v; 2952 ret = 0; 2953 break; 2954 } 2955 } 2956 2957 /* if no match return the highest voltage */ 2958 if (ret) 2959 *voltage = table->entries[table->count - 1].v; 2960 2961 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2962 2963 return ret; 2964 } 2965 2966 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2967 struct radeon_ps *rps) 2968 { 2969 struct ni_ps *ps = ni_get_ps(rps); 2970 struct radeon_clock_and_voltage_limits *max_limits; 2971 bool disable_mclk_switching = false; 2972 bool disable_sclk_switching = false; 2973 u32 mclk, sclk; 2974 u16 vddc, vddci, min_vce_voltage = 0; 2975 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2976 u32 max_sclk = 0, max_mclk = 0; 2977 int i; 2978 2979 if (rdev->family == CHIP_HAINAN) { 2980 if ((rdev->pdev->revision == 0x81) || 2981 (rdev->pdev->revision == 0x83) || 2982 (rdev->pdev->revision == 0xC3) || 2983 (rdev->pdev->device == 0x6664) || 2984 (rdev->pdev->device == 0x6665) || 2985 (rdev->pdev->device == 0x6667)) { 2986 max_sclk = 75000; 2987 } 2988 if ((rdev->pdev->revision == 0xC3) || 2989 (rdev->pdev->device == 0x6665)) { 2990 max_sclk = 60000; 2991 max_mclk = 80000; 2992 } 2993 } else if (rdev->family == CHIP_OLAND) { 2994 if ((rdev->pdev->revision == 0xC7) || 2995 (rdev->pdev->revision == 0x80) || 2996 (rdev->pdev->revision == 0x81) || 2997 (rdev->pdev->revision == 0x83) || 2998 (rdev->pdev->revision == 0x87) || 2999 (rdev->pdev->device == 0x6604) || 3000 (rdev->pdev->device == 0x6605)) { 3001 max_sclk = 75000; 3002 } 3003 } 3004 3005 if (rps->vce_active) { 3006 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3007 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3008 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3009 &min_vce_voltage); 3010 } else { 3011 rps->evclk = 0; 3012 rps->ecclk = 0; 3013 } 3014 3015 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3016 ni_dpm_vblank_too_short(rdev)) 3017 disable_mclk_switching = true; 3018 3019 if (rps->vclk || rps->dclk) { 3020 disable_mclk_switching = true; 3021 disable_sclk_switching = true; 3022 } 3023 3024 if (rdev->pm.dpm.ac_power) 3025 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3026 else 3027 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3028 3029 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3030 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3031 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3032 } 3033 if (rdev->pm.dpm.ac_power == false) { 3034 for (i = 0; i < ps->performance_level_count; i++) { 3035 if (ps->performance_levels[i].mclk > max_limits->mclk) 3036 ps->performance_levels[i].mclk = max_limits->mclk; 3037 if (ps->performance_levels[i].sclk > max_limits->sclk) 3038 ps->performance_levels[i].sclk = max_limits->sclk; 3039 if (ps->performance_levels[i].vddc > max_limits->vddc) 3040 ps->performance_levels[i].vddc = max_limits->vddc; 3041 if (ps->performance_levels[i].vddci > max_limits->vddci) 3042 ps->performance_levels[i].vddci = max_limits->vddci; 3043 } 3044 } 3045 3046 /* limit clocks to max supported clocks based on voltage dependency tables */ 3047 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3048 &max_sclk_vddc); 3049 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3050 &max_mclk_vddci); 3051 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3052 &max_mclk_vddc); 3053 3054 for (i = 0; i < ps->performance_level_count; i++) { 3055 if (max_sclk_vddc) { 3056 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3057 ps->performance_levels[i].sclk = max_sclk_vddc; 3058 } 3059 if (max_mclk_vddci) { 3060 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3061 ps->performance_levels[i].mclk = max_mclk_vddci; 3062 } 3063 if (max_mclk_vddc) { 3064 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3065 ps->performance_levels[i].mclk = max_mclk_vddc; 3066 } 3067 if (max_mclk) { 3068 if (ps->performance_levels[i].mclk > max_mclk) 3069 ps->performance_levels[i].mclk = max_mclk; 3070 } 3071 if (max_sclk) { 3072 if (ps->performance_levels[i].sclk > max_sclk) 3073 ps->performance_levels[i].sclk = max_sclk; 3074 } 3075 } 3076 3077 /* XXX validate the min clocks required for display */ 3078 3079 if (disable_mclk_switching) { 3080 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3081 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3082 } else { 3083 mclk = ps->performance_levels[0].mclk; 3084 vddci = ps->performance_levels[0].vddci; 3085 } 3086 3087 if (disable_sclk_switching) { 3088 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3089 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3090 } else { 3091 sclk = ps->performance_levels[0].sclk; 3092 vddc = ps->performance_levels[0].vddc; 3093 } 3094 3095 if (rps->vce_active) { 3096 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3097 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3098 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3099 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3100 } 3101 3102 /* adjusted low state */ 3103 ps->performance_levels[0].sclk = sclk; 3104 ps->performance_levels[0].mclk = mclk; 3105 ps->performance_levels[0].vddc = vddc; 3106 ps->performance_levels[0].vddci = vddci; 3107 3108 if (disable_sclk_switching) { 3109 sclk = ps->performance_levels[0].sclk; 3110 for (i = 1; i < ps->performance_level_count; i++) { 3111 if (sclk < ps->performance_levels[i].sclk) 3112 sclk = ps->performance_levels[i].sclk; 3113 } 3114 for (i = 0; i < ps->performance_level_count; i++) { 3115 ps->performance_levels[i].sclk = sclk; 3116 ps->performance_levels[i].vddc = vddc; 3117 } 3118 } else { 3119 for (i = 1; i < ps->performance_level_count; i++) { 3120 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3121 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3122 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3123 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3124 } 3125 } 3126 3127 if (disable_mclk_switching) { 3128 mclk = ps->performance_levels[0].mclk; 3129 for (i = 1; i < ps->performance_level_count; i++) { 3130 if (mclk < ps->performance_levels[i].mclk) 3131 mclk = ps->performance_levels[i].mclk; 3132 } 3133 for (i = 0; i < ps->performance_level_count; i++) { 3134 ps->performance_levels[i].mclk = mclk; 3135 ps->performance_levels[i].vddci = vddci; 3136 } 3137 } else { 3138 for (i = 1; i < ps->performance_level_count; i++) { 3139 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3140 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3141 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3142 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3143 } 3144 } 3145 3146 for (i = 0; i < ps->performance_level_count; i++) 3147 btc_adjust_clock_combinations(rdev, max_limits, 3148 &ps->performance_levels[i]); 3149 3150 for (i = 0; i < ps->performance_level_count; i++) { 3151 if (ps->performance_levels[i].vddc < min_vce_voltage) 3152 ps->performance_levels[i].vddc = min_vce_voltage; 3153 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3154 ps->performance_levels[i].sclk, 3155 max_limits->vddc, &ps->performance_levels[i].vddc); 3156 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3157 ps->performance_levels[i].mclk, 3158 max_limits->vddci, &ps->performance_levels[i].vddci); 3159 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3160 ps->performance_levels[i].mclk, 3161 max_limits->vddc, &ps->performance_levels[i].vddc); 3162 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3163 rdev->clock.current_dispclk, 3164 max_limits->vddc, &ps->performance_levels[i].vddc); 3165 } 3166 3167 for (i = 0; i < ps->performance_level_count; i++) { 3168 btc_apply_voltage_delta_rules(rdev, 3169 max_limits->vddc, max_limits->vddci, 3170 &ps->performance_levels[i].vddc, 3171 &ps->performance_levels[i].vddci); 3172 } 3173 3174 ps->dc_compatible = true; 3175 for (i = 0; i < ps->performance_level_count; i++) { 3176 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3177 ps->dc_compatible = false; 3178 } 3179 } 3180 3181 #if 0 3182 static int si_read_smc_soft_register(struct radeon_device *rdev, 3183 u16 reg_offset, u32 *value) 3184 { 3185 struct si_power_info *si_pi = si_get_pi(rdev); 3186 3187 return si_read_smc_sram_dword(rdev, 3188 si_pi->soft_regs_start + reg_offset, value, 3189 si_pi->sram_end); 3190 } 3191 #endif 3192 3193 static int si_write_smc_soft_register(struct radeon_device *rdev, 3194 u16 reg_offset, u32 value) 3195 { 3196 struct si_power_info *si_pi = si_get_pi(rdev); 3197 3198 return si_write_smc_sram_dword(rdev, 3199 si_pi->soft_regs_start + reg_offset, 3200 value, si_pi->sram_end); 3201 } 3202 3203 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3204 { 3205 bool ret = false; 3206 u32 tmp, width, row, column, bank, density; 3207 bool is_memory_gddr5, is_special; 3208 3209 tmp = RREG32(MC_SEQ_MISC0); 3210 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3211 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3212 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3213 3214 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3215 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3216 3217 tmp = RREG32(MC_ARB_RAMCFG); 3218 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3219 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3220 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3221 3222 density = (1 << (row + column - 20 + bank)) * width; 3223 3224 if ((rdev->pdev->device == 0x6819) && 3225 is_memory_gddr5 && is_special && (density == 0x400)) 3226 ret = true; 3227 3228 return ret; 3229 } 3230 3231 static void si_get_leakage_vddc(struct radeon_device *rdev) 3232 { 3233 struct si_power_info *si_pi = si_get_pi(rdev); 3234 u16 vddc, count = 0; 3235 int i, ret; 3236 3237 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3238 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3239 3240 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3241 si_pi->leakage_voltage.entries[count].voltage = vddc; 3242 si_pi->leakage_voltage.entries[count].leakage_index = 3243 SISLANDS_LEAKAGE_INDEX0 + i; 3244 count++; 3245 } 3246 } 3247 si_pi->leakage_voltage.count = count; 3248 } 3249 3250 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3251 u32 index, u16 *leakage_voltage) 3252 { 3253 struct si_power_info *si_pi = si_get_pi(rdev); 3254 int i; 3255 3256 if (leakage_voltage == NULL) 3257 return -EINVAL; 3258 3259 if ((index & 0xff00) != 0xff00) 3260 return -EINVAL; 3261 3262 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3263 return -EINVAL; 3264 3265 if (index < SISLANDS_LEAKAGE_INDEX0) 3266 return -EINVAL; 3267 3268 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3269 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3270 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3271 return 0; 3272 } 3273 } 3274 return -EAGAIN; 3275 } 3276 3277 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3278 { 3279 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3280 bool want_thermal_protection; 3281 enum radeon_dpm_event_src dpm_event_src; 3282 3283 switch (sources) { 3284 case 0: 3285 default: 3286 want_thermal_protection = false; 3287 break; 3288 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3289 want_thermal_protection = true; 3290 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3291 break; 3292 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3293 want_thermal_protection = true; 3294 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3295 break; 3296 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3297 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3298 want_thermal_protection = true; 3299 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3300 break; 3301 } 3302 3303 if (want_thermal_protection) { 3304 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3305 if (pi->thermal_protection) 3306 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3307 } else { 3308 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3309 } 3310 } 3311 3312 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3313 enum radeon_dpm_auto_throttle_src source, 3314 bool enable) 3315 { 3316 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3317 3318 if (enable) { 3319 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3320 pi->active_auto_throttle_sources |= 1 << source; 3321 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3322 } 3323 } else { 3324 if (pi->active_auto_throttle_sources & (1 << source)) { 3325 pi->active_auto_throttle_sources &= ~(1 << source); 3326 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3327 } 3328 } 3329 } 3330 3331 static void si_start_dpm(struct radeon_device *rdev) 3332 { 3333 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3334 } 3335 3336 static void si_stop_dpm(struct radeon_device *rdev) 3337 { 3338 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3339 } 3340 3341 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3342 { 3343 if (enable) 3344 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3345 else 3346 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3347 3348 } 3349 3350 #if 0 3351 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3352 u32 thermal_level) 3353 { 3354 PPSMC_Result ret; 3355 3356 if (thermal_level == 0) { 3357 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3358 if (ret == PPSMC_Result_OK) 3359 return 0; 3360 else 3361 return -EINVAL; 3362 } 3363 return 0; 3364 } 3365 3366 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3367 { 3368 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3369 } 3370 #endif 3371 3372 #if 0 3373 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3374 { 3375 if (ac_power) 3376 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3377 0 : -EINVAL; 3378 3379 return 0; 3380 } 3381 #endif 3382 3383 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3384 PPSMC_Msg msg, u32 parameter) 3385 { 3386 WREG32(SMC_SCRATCH0, parameter); 3387 return si_send_msg_to_smc(rdev, msg); 3388 } 3389 3390 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3391 { 3392 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3393 return -EINVAL; 3394 3395 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3396 0 : -EINVAL; 3397 } 3398 3399 int si_dpm_force_performance_level(struct radeon_device *rdev, 3400 enum radeon_dpm_forced_level level) 3401 { 3402 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3403 struct ni_ps *ps = ni_get_ps(rps); 3404 u32 levels = ps->performance_level_count; 3405 3406 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3407 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3408 return -EINVAL; 3409 3410 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3411 return -EINVAL; 3412 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3413 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3414 return -EINVAL; 3415 3416 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3417 return -EINVAL; 3418 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3419 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3420 return -EINVAL; 3421 3422 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3423 return -EINVAL; 3424 } 3425 3426 rdev->pm.dpm.forced_level = level; 3427 3428 return 0; 3429 } 3430 3431 #if 0 3432 static int si_set_boot_state(struct radeon_device *rdev) 3433 { 3434 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3435 0 : -EINVAL; 3436 } 3437 #endif 3438 3439 static int si_set_sw_state(struct radeon_device *rdev) 3440 { 3441 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3442 0 : -EINVAL; 3443 } 3444 3445 static int si_halt_smc(struct radeon_device *rdev) 3446 { 3447 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3448 return -EINVAL; 3449 3450 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3451 0 : -EINVAL; 3452 } 3453 3454 static int si_resume_smc(struct radeon_device *rdev) 3455 { 3456 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3457 return -EINVAL; 3458 3459 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3460 0 : -EINVAL; 3461 } 3462 3463 static void si_dpm_start_smc(struct radeon_device *rdev) 3464 { 3465 si_program_jump_on_start(rdev); 3466 si_start_smc(rdev); 3467 si_start_smc_clock(rdev); 3468 } 3469 3470 static void si_dpm_stop_smc(struct radeon_device *rdev) 3471 { 3472 si_reset_smc(rdev); 3473 si_stop_smc_clock(rdev); 3474 } 3475 3476 static int si_process_firmware_header(struct radeon_device *rdev) 3477 { 3478 struct si_power_info *si_pi = si_get_pi(rdev); 3479 u32 tmp; 3480 int ret; 3481 3482 ret = si_read_smc_sram_dword(rdev, 3483 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3484 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3485 &tmp, si_pi->sram_end); 3486 if (ret) 3487 return ret; 3488 3489 si_pi->state_table_start = tmp; 3490 3491 ret = si_read_smc_sram_dword(rdev, 3492 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3493 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3494 &tmp, si_pi->sram_end); 3495 if (ret) 3496 return ret; 3497 3498 si_pi->soft_regs_start = tmp; 3499 3500 ret = si_read_smc_sram_dword(rdev, 3501 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3502 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3503 &tmp, si_pi->sram_end); 3504 if (ret) 3505 return ret; 3506 3507 si_pi->mc_reg_table_start = tmp; 3508 3509 ret = si_read_smc_sram_dword(rdev, 3510 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3511 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3512 &tmp, si_pi->sram_end); 3513 if (ret) 3514 return ret; 3515 3516 si_pi->fan_table_start = tmp; 3517 3518 ret = si_read_smc_sram_dword(rdev, 3519 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3520 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3521 &tmp, si_pi->sram_end); 3522 if (ret) 3523 return ret; 3524 3525 si_pi->arb_table_start = tmp; 3526 3527 ret = si_read_smc_sram_dword(rdev, 3528 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3529 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3530 &tmp, si_pi->sram_end); 3531 if (ret) 3532 return ret; 3533 3534 si_pi->cac_table_start = tmp; 3535 3536 ret = si_read_smc_sram_dword(rdev, 3537 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3538 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3539 &tmp, si_pi->sram_end); 3540 if (ret) 3541 return ret; 3542 3543 si_pi->dte_table_start = tmp; 3544 3545 ret = si_read_smc_sram_dword(rdev, 3546 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3547 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3548 &tmp, si_pi->sram_end); 3549 if (ret) 3550 return ret; 3551 3552 si_pi->spll_table_start = tmp; 3553 3554 ret = si_read_smc_sram_dword(rdev, 3555 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3556 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3557 &tmp, si_pi->sram_end); 3558 if (ret) 3559 return ret; 3560 3561 si_pi->papm_cfg_table_start = tmp; 3562 3563 return ret; 3564 } 3565 3566 static void si_read_clock_registers(struct radeon_device *rdev) 3567 { 3568 struct si_power_info *si_pi = si_get_pi(rdev); 3569 3570 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3571 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3572 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3573 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3574 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3575 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3576 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3577 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3578 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3579 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3580 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3581 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3582 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3583 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3584 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3585 } 3586 3587 static void si_enable_thermal_protection(struct radeon_device *rdev, 3588 bool enable) 3589 { 3590 if (enable) 3591 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3592 else 3593 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3594 } 3595 3596 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3597 { 3598 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3599 } 3600 3601 #if 0 3602 static int si_enter_ulp_state(struct radeon_device *rdev) 3603 { 3604 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3605 3606 udelay(25000); 3607 3608 return 0; 3609 } 3610 3611 static int si_exit_ulp_state(struct radeon_device *rdev) 3612 { 3613 int i; 3614 3615 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3616 3617 udelay(7000); 3618 3619 for (i = 0; i < rdev->usec_timeout; i++) { 3620 if (RREG32(SMC_RESP_0) == 1) 3621 break; 3622 udelay(1000); 3623 } 3624 3625 return 0; 3626 } 3627 #endif 3628 3629 static int si_notify_smc_display_change(struct radeon_device *rdev, 3630 bool has_display) 3631 { 3632 PPSMC_Msg msg = has_display ? 3633 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3634 3635 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3636 0 : -EINVAL; 3637 } 3638 3639 static void si_program_response_times(struct radeon_device *rdev) 3640 { 3641 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3642 u32 vddc_dly, acpi_dly, vbi_dly; 3643 u32 reference_clock; 3644 3645 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3646 3647 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3648 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3649 3650 if (voltage_response_time == 0) 3651 voltage_response_time = 1000; 3652 3653 acpi_delay_time = 15000; 3654 vbi_time_out = 100000; 3655 3656 reference_clock = radeon_get_xclk(rdev); 3657 3658 vddc_dly = (voltage_response_time * reference_clock) / 100; 3659 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3660 vbi_dly = (vbi_time_out * reference_clock) / 100; 3661 3662 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3663 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3664 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3665 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3666 } 3667 3668 static void si_program_ds_registers(struct radeon_device *rdev) 3669 { 3670 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3671 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3672 3673 if (eg_pi->sclk_deep_sleep) { 3674 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3675 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3676 ~AUTOSCALE_ON_SS_CLEAR); 3677 } 3678 } 3679 3680 static void si_program_display_gap(struct radeon_device *rdev) 3681 { 3682 u32 tmp, pipe; 3683 int i; 3684 3685 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3686 if (rdev->pm.dpm.new_active_crtc_count > 0) 3687 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3688 else 3689 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3690 3691 if (rdev->pm.dpm.new_active_crtc_count > 1) 3692 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3693 else 3694 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3695 3696 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3697 3698 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3699 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3700 3701 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3702 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3703 /* find the first active crtc */ 3704 for (i = 0; i < rdev->num_crtc; i++) { 3705 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3706 break; 3707 } 3708 if (i == rdev->num_crtc) 3709 pipe = 0; 3710 else 3711 pipe = i; 3712 3713 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3714 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3715 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3716 } 3717 3718 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3719 * This can be a problem on PowerXpress systems or if you want to use the card 3720 * for offscreen rendering or compute if there are no crtcs enabled. 3721 */ 3722 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3723 } 3724 3725 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3726 { 3727 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3728 3729 if (enable) { 3730 if (pi->sclk_ss) 3731 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3732 } else { 3733 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3734 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3735 } 3736 } 3737 3738 static void si_setup_bsp(struct radeon_device *rdev) 3739 { 3740 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3741 u32 xclk = radeon_get_xclk(rdev); 3742 3743 r600_calculate_u_and_p(pi->asi, 3744 xclk, 3745 16, 3746 &pi->bsp, 3747 &pi->bsu); 3748 3749 r600_calculate_u_and_p(pi->pasi, 3750 xclk, 3751 16, 3752 &pi->pbsp, 3753 &pi->pbsu); 3754 3755 3756 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3757 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3758 3759 WREG32(CG_BSP, pi->dsp); 3760 } 3761 3762 static void si_program_git(struct radeon_device *rdev) 3763 { 3764 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3765 } 3766 3767 static void si_program_tp(struct radeon_device *rdev) 3768 { 3769 int i; 3770 enum r600_td td = R600_TD_DFLT; 3771 3772 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3773 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3774 3775 if (td == R600_TD_AUTO) 3776 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3777 else 3778 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3779 3780 if (td == R600_TD_UP) 3781 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3782 3783 if (td == R600_TD_DOWN) 3784 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3785 } 3786 3787 static void si_program_tpp(struct radeon_device *rdev) 3788 { 3789 WREG32(CG_TPC, R600_TPC_DFLT); 3790 } 3791 3792 static void si_program_sstp(struct radeon_device *rdev) 3793 { 3794 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3795 } 3796 3797 static void si_enable_display_gap(struct radeon_device *rdev) 3798 { 3799 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3800 3801 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3802 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3803 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3804 3805 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3806 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3807 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3808 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3809 } 3810 3811 static void si_program_vc(struct radeon_device *rdev) 3812 { 3813 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3814 3815 WREG32(CG_FTV, pi->vrc); 3816 } 3817 3818 static void si_clear_vc(struct radeon_device *rdev) 3819 { 3820 WREG32(CG_FTV, 0); 3821 } 3822 3823 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3824 { 3825 u8 mc_para_index; 3826 3827 if (memory_clock < 10000) 3828 mc_para_index = 0; 3829 else if (memory_clock >= 80000) 3830 mc_para_index = 0x0f; 3831 else 3832 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3833 return mc_para_index; 3834 } 3835 3836 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3837 { 3838 u8 mc_para_index; 3839 3840 if (strobe_mode) { 3841 if (memory_clock < 12500) 3842 mc_para_index = 0x00; 3843 else if (memory_clock > 47500) 3844 mc_para_index = 0x0f; 3845 else 3846 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3847 } else { 3848 if (memory_clock < 65000) 3849 mc_para_index = 0x00; 3850 else if (memory_clock > 135000) 3851 mc_para_index = 0x0f; 3852 else 3853 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3854 } 3855 return mc_para_index; 3856 } 3857 3858 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3859 { 3860 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3861 bool strobe_mode = false; 3862 u8 result = 0; 3863 3864 if (mclk <= pi->mclk_strobe_mode_threshold) 3865 strobe_mode = true; 3866 3867 if (pi->mem_gddr5) 3868 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3869 else 3870 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3871 3872 if (strobe_mode) 3873 result |= SISLANDS_SMC_STROBE_ENABLE; 3874 3875 return result; 3876 } 3877 3878 static int si_upload_firmware(struct radeon_device *rdev) 3879 { 3880 struct si_power_info *si_pi = si_get_pi(rdev); 3881 int ret; 3882 3883 si_reset_smc(rdev); 3884 si_stop_smc_clock(rdev); 3885 3886 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3887 3888 return ret; 3889 } 3890 3891 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3892 const struct atom_voltage_table *table, 3893 const struct radeon_phase_shedding_limits_table *limits) 3894 { 3895 u32 data, num_bits, num_levels; 3896 3897 if ((table == NULL) || (limits == NULL)) 3898 return false; 3899 3900 data = table->mask_low; 3901 3902 num_bits = hweight32(data); 3903 3904 if (num_bits == 0) 3905 return false; 3906 3907 num_levels = (1 << num_bits); 3908 3909 if (table->count != num_levels) 3910 return false; 3911 3912 if (limits->count != (num_levels - 1)) 3913 return false; 3914 3915 return true; 3916 } 3917 3918 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3919 u32 max_voltage_steps, 3920 struct atom_voltage_table *voltage_table) 3921 { 3922 unsigned int i, diff; 3923 3924 if (voltage_table->count <= max_voltage_steps) 3925 return; 3926 3927 diff = voltage_table->count - max_voltage_steps; 3928 3929 for (i= 0; i < max_voltage_steps; i++) 3930 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3931 3932 voltage_table->count = max_voltage_steps; 3933 } 3934 3935 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3936 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3937 struct atom_voltage_table *voltage_table) 3938 { 3939 u32 i; 3940 3941 if (voltage_dependency_table == NULL) 3942 return -EINVAL; 3943 3944 voltage_table->mask_low = 0; 3945 voltage_table->phase_delay = 0; 3946 3947 voltage_table->count = voltage_dependency_table->count; 3948 for (i = 0; i < voltage_table->count; i++) { 3949 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3950 voltage_table->entries[i].smio_low = 0; 3951 } 3952 3953 return 0; 3954 } 3955 3956 static int si_construct_voltage_tables(struct radeon_device *rdev) 3957 { 3958 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3959 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3960 struct si_power_info *si_pi = si_get_pi(rdev); 3961 int ret; 3962 3963 if (pi->voltage_control) { 3964 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3965 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3966 if (ret) 3967 return ret; 3968 3969 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3970 si_trim_voltage_table_to_fit_state_table(rdev, 3971 SISLANDS_MAX_NO_VREG_STEPS, 3972 &eg_pi->vddc_voltage_table); 3973 } else if (si_pi->voltage_control_svi2) { 3974 ret = si_get_svi2_voltage_table(rdev, 3975 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3976 &eg_pi->vddc_voltage_table); 3977 if (ret) 3978 return ret; 3979 } else { 3980 return -EINVAL; 3981 } 3982 3983 if (eg_pi->vddci_control) { 3984 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3985 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3986 if (ret) 3987 return ret; 3988 3989 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3990 si_trim_voltage_table_to_fit_state_table(rdev, 3991 SISLANDS_MAX_NO_VREG_STEPS, 3992 &eg_pi->vddci_voltage_table); 3993 } 3994 if (si_pi->vddci_control_svi2) { 3995 ret = si_get_svi2_voltage_table(rdev, 3996 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3997 &eg_pi->vddci_voltage_table); 3998 if (ret) 3999 return ret; 4000 } 4001 4002 if (pi->mvdd_control) { 4003 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4004 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4005 4006 if (ret) { 4007 pi->mvdd_control = false; 4008 return ret; 4009 } 4010 4011 if (si_pi->mvdd_voltage_table.count == 0) { 4012 pi->mvdd_control = false; 4013 return -EINVAL; 4014 } 4015 4016 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4017 si_trim_voltage_table_to_fit_state_table(rdev, 4018 SISLANDS_MAX_NO_VREG_STEPS, 4019 &si_pi->mvdd_voltage_table); 4020 } 4021 4022 if (si_pi->vddc_phase_shed_control) { 4023 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4024 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4025 if (ret) 4026 si_pi->vddc_phase_shed_control = false; 4027 4028 if ((si_pi->vddc_phase_shed_table.count == 0) || 4029 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4030 si_pi->vddc_phase_shed_control = false; 4031 } 4032 4033 return 0; 4034 } 4035 4036 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4037 const struct atom_voltage_table *voltage_table, 4038 SISLANDS_SMC_STATETABLE *table) 4039 { 4040 unsigned int i; 4041 4042 for (i = 0; i < voltage_table->count; i++) 4043 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4044 } 4045 4046 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4047 SISLANDS_SMC_STATETABLE *table) 4048 { 4049 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4050 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4051 struct si_power_info *si_pi = si_get_pi(rdev); 4052 u8 i; 4053 4054 if (si_pi->voltage_control_svi2) { 4055 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4056 si_pi->svc_gpio_id); 4057 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4058 si_pi->svd_gpio_id); 4059 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4060 2); 4061 } else { 4062 if (eg_pi->vddc_voltage_table.count) { 4063 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4064 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4065 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4066 4067 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4068 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4069 table->maxVDDCIndexInPPTable = i; 4070 break; 4071 } 4072 } 4073 } 4074 4075 if (eg_pi->vddci_voltage_table.count) { 4076 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4077 4078 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4079 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4080 } 4081 4082 4083 if (si_pi->mvdd_voltage_table.count) { 4084 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4085 4086 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4087 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4088 } 4089 4090 if (si_pi->vddc_phase_shed_control) { 4091 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4092 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4093 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4094 4095 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4096 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4097 4098 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4099 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4100 } else { 4101 si_pi->vddc_phase_shed_control = false; 4102 } 4103 } 4104 } 4105 4106 return 0; 4107 } 4108 4109 static int si_populate_voltage_value(struct radeon_device *rdev, 4110 const struct atom_voltage_table *table, 4111 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4112 { 4113 unsigned int i; 4114 4115 for (i = 0; i < table->count; i++) { 4116 if (value <= table->entries[i].value) { 4117 voltage->index = (u8)i; 4118 voltage->value = cpu_to_be16(table->entries[i].value); 4119 break; 4120 } 4121 } 4122 4123 if (i >= table->count) 4124 return -EINVAL; 4125 4126 return 0; 4127 } 4128 4129 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4130 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4131 { 4132 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4133 struct si_power_info *si_pi = si_get_pi(rdev); 4134 4135 if (pi->mvdd_control) { 4136 if (mclk <= pi->mvdd_split_frequency) 4137 voltage->index = 0; 4138 else 4139 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4140 4141 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4142 } 4143 return 0; 4144 } 4145 4146 static int si_get_std_voltage_value(struct radeon_device *rdev, 4147 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4148 u16 *std_voltage) 4149 { 4150 u16 v_index; 4151 bool voltage_found = false; 4152 *std_voltage = be16_to_cpu(voltage->value); 4153 4154 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4155 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4156 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4157 return -EINVAL; 4158 4159 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4160 if (be16_to_cpu(voltage->value) == 4161 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4162 voltage_found = true; 4163 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4164 *std_voltage = 4165 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4166 else 4167 *std_voltage = 4168 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4169 break; 4170 } 4171 } 4172 4173 if (!voltage_found) { 4174 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4175 if (be16_to_cpu(voltage->value) <= 4176 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4177 voltage_found = true; 4178 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4179 *std_voltage = 4180 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4181 else 4182 *std_voltage = 4183 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4184 break; 4185 } 4186 } 4187 } 4188 } else { 4189 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4190 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4191 } 4192 } 4193 4194 return 0; 4195 } 4196 4197 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4198 u16 value, u8 index, 4199 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4200 { 4201 voltage->index = index; 4202 voltage->value = cpu_to_be16(value); 4203 4204 return 0; 4205 } 4206 4207 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4208 const struct radeon_phase_shedding_limits_table *limits, 4209 u16 voltage, u32 sclk, u32 mclk, 4210 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4211 { 4212 unsigned int i; 4213 4214 for (i = 0; i < limits->count; i++) { 4215 if ((voltage <= limits->entries[i].voltage) && 4216 (sclk <= limits->entries[i].sclk) && 4217 (mclk <= limits->entries[i].mclk)) 4218 break; 4219 } 4220 4221 smc_voltage->phase_settings = (u8)i; 4222 4223 return 0; 4224 } 4225 4226 static int si_init_arb_table_index(struct radeon_device *rdev) 4227 { 4228 struct si_power_info *si_pi = si_get_pi(rdev); 4229 u32 tmp; 4230 int ret; 4231 4232 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4233 if (ret) 4234 return ret; 4235 4236 tmp &= 0x00FFFFFF; 4237 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4238 4239 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4240 } 4241 4242 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4243 { 4244 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4245 } 4246 4247 static int si_reset_to_default(struct radeon_device *rdev) 4248 { 4249 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4250 0 : -EINVAL; 4251 } 4252 4253 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4254 { 4255 struct si_power_info *si_pi = si_get_pi(rdev); 4256 u32 tmp; 4257 int ret; 4258 4259 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4260 &tmp, si_pi->sram_end); 4261 if (ret) 4262 return ret; 4263 4264 tmp = (tmp >> 24) & 0xff; 4265 4266 if (tmp == MC_CG_ARB_FREQ_F0) 4267 return 0; 4268 4269 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4270 } 4271 4272 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4273 u32 engine_clock) 4274 { 4275 u32 dram_rows; 4276 u32 dram_refresh_rate; 4277 u32 mc_arb_rfsh_rate; 4278 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4279 4280 if (tmp >= 4) 4281 dram_rows = 16384; 4282 else 4283 dram_rows = 1 << (tmp + 10); 4284 4285 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4286 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4287 4288 return mc_arb_rfsh_rate; 4289 } 4290 4291 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4292 struct rv7xx_pl *pl, 4293 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4294 { 4295 u32 dram_timing; 4296 u32 dram_timing2; 4297 u32 burst_time; 4298 4299 arb_regs->mc_arb_rfsh_rate = 4300 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4301 4302 radeon_atom_set_engine_dram_timings(rdev, 4303 pl->sclk, 4304 pl->mclk); 4305 4306 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4307 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4308 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4309 4310 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4311 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4312 arb_regs->mc_arb_burst_time = (u8)burst_time; 4313 4314 return 0; 4315 } 4316 4317 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4318 struct radeon_ps *radeon_state, 4319 unsigned int first_arb_set) 4320 { 4321 struct si_power_info *si_pi = si_get_pi(rdev); 4322 struct ni_ps *state = ni_get_ps(radeon_state); 4323 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4324 int i, ret = 0; 4325 4326 for (i = 0; i < state->performance_level_count; i++) { 4327 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4328 if (ret) 4329 break; 4330 ret = si_copy_bytes_to_smc(rdev, 4331 si_pi->arb_table_start + 4332 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4333 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4334 (u8 *)&arb_regs, 4335 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4336 si_pi->sram_end); 4337 if (ret) 4338 break; 4339 } 4340 4341 return ret; 4342 } 4343 4344 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4345 struct radeon_ps *radeon_new_state) 4346 { 4347 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4348 SISLANDS_DRIVER_STATE_ARB_INDEX); 4349 } 4350 4351 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4352 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4353 { 4354 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4355 struct si_power_info *si_pi = si_get_pi(rdev); 4356 4357 if (pi->mvdd_control) 4358 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4359 si_pi->mvdd_bootup_value, voltage); 4360 4361 return 0; 4362 } 4363 4364 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4365 struct radeon_ps *radeon_initial_state, 4366 SISLANDS_SMC_STATETABLE *table) 4367 { 4368 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4369 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4370 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4371 struct si_power_info *si_pi = si_get_pi(rdev); 4372 u32 reg; 4373 int ret; 4374 4375 table->initialState.levels[0].mclk.vDLL_CNTL = 4376 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4377 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4378 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4379 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4380 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4381 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4382 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4383 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4384 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4385 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4386 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4387 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4388 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4389 table->initialState.levels[0].mclk.vMPLL_SS = 4390 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4391 table->initialState.levels[0].mclk.vMPLL_SS2 = 4392 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4393 4394 table->initialState.levels[0].mclk.mclk_value = 4395 cpu_to_be32(initial_state->performance_levels[0].mclk); 4396 4397 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4398 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4399 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4400 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4401 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4402 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4403 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4404 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4405 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4406 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4407 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4408 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4409 4410 table->initialState.levels[0].sclk.sclk_value = 4411 cpu_to_be32(initial_state->performance_levels[0].sclk); 4412 4413 table->initialState.levels[0].arbRefreshState = 4414 SISLANDS_INITIAL_STATE_ARB_INDEX; 4415 4416 table->initialState.levels[0].ACIndex = 0; 4417 4418 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4419 initial_state->performance_levels[0].vddc, 4420 &table->initialState.levels[0].vddc); 4421 4422 if (!ret) { 4423 u16 std_vddc; 4424 4425 ret = si_get_std_voltage_value(rdev, 4426 &table->initialState.levels[0].vddc, 4427 &std_vddc); 4428 if (!ret) 4429 si_populate_std_voltage_value(rdev, std_vddc, 4430 table->initialState.levels[0].vddc.index, 4431 &table->initialState.levels[0].std_vddc); 4432 } 4433 4434 if (eg_pi->vddci_control) 4435 si_populate_voltage_value(rdev, 4436 &eg_pi->vddci_voltage_table, 4437 initial_state->performance_levels[0].vddci, 4438 &table->initialState.levels[0].vddci); 4439 4440 if (si_pi->vddc_phase_shed_control) 4441 si_populate_phase_shedding_value(rdev, 4442 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4443 initial_state->performance_levels[0].vddc, 4444 initial_state->performance_levels[0].sclk, 4445 initial_state->performance_levels[0].mclk, 4446 &table->initialState.levels[0].vddc); 4447 4448 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4449 4450 reg = CG_R(0xffff) | CG_L(0); 4451 table->initialState.levels[0].aT = cpu_to_be32(reg); 4452 4453 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4454 4455 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4456 4457 if (pi->mem_gddr5) { 4458 table->initialState.levels[0].strobeMode = 4459 si_get_strobe_mode_settings(rdev, 4460 initial_state->performance_levels[0].mclk); 4461 4462 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4463 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4464 else 4465 table->initialState.levels[0].mcFlags = 0; 4466 } 4467 4468 table->initialState.levelCount = 1; 4469 4470 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4471 4472 table->initialState.levels[0].dpm2.MaxPS = 0; 4473 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4474 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4475 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4476 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4477 4478 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4479 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4480 4481 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4482 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4483 4484 return 0; 4485 } 4486 4487 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4488 SISLANDS_SMC_STATETABLE *table) 4489 { 4490 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4491 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4492 struct si_power_info *si_pi = si_get_pi(rdev); 4493 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4494 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4495 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4496 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4497 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4498 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4499 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4500 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4501 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4502 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4503 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4504 u32 reg; 4505 int ret; 4506 4507 table->ACPIState = table->initialState; 4508 4509 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4510 4511 if (pi->acpi_vddc) { 4512 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4513 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4514 if (!ret) { 4515 u16 std_vddc; 4516 4517 ret = si_get_std_voltage_value(rdev, 4518 &table->ACPIState.levels[0].vddc, &std_vddc); 4519 if (!ret) 4520 si_populate_std_voltage_value(rdev, std_vddc, 4521 table->ACPIState.levels[0].vddc.index, 4522 &table->ACPIState.levels[0].std_vddc); 4523 } 4524 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4525 4526 if (si_pi->vddc_phase_shed_control) { 4527 si_populate_phase_shedding_value(rdev, 4528 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4529 pi->acpi_vddc, 4530 0, 4531 0, 4532 &table->ACPIState.levels[0].vddc); 4533 } 4534 } else { 4535 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4536 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4537 if (!ret) { 4538 u16 std_vddc; 4539 4540 ret = si_get_std_voltage_value(rdev, 4541 &table->ACPIState.levels[0].vddc, &std_vddc); 4542 4543 if (!ret) 4544 si_populate_std_voltage_value(rdev, std_vddc, 4545 table->ACPIState.levels[0].vddc.index, 4546 &table->ACPIState.levels[0].std_vddc); 4547 } 4548 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4549 si_pi->sys_pcie_mask, 4550 si_pi->boot_pcie_gen, 4551 RADEON_PCIE_GEN1); 4552 4553 if (si_pi->vddc_phase_shed_control) 4554 si_populate_phase_shedding_value(rdev, 4555 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4556 pi->min_vddc_in_table, 4557 0, 4558 0, 4559 &table->ACPIState.levels[0].vddc); 4560 } 4561 4562 if (pi->acpi_vddc) { 4563 if (eg_pi->acpi_vddci) 4564 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4565 eg_pi->acpi_vddci, 4566 &table->ACPIState.levels[0].vddci); 4567 } 4568 4569 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4570 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4571 4572 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4573 4574 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4575 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4576 4577 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4578 cpu_to_be32(dll_cntl); 4579 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4580 cpu_to_be32(mclk_pwrmgt_cntl); 4581 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4582 cpu_to_be32(mpll_ad_func_cntl); 4583 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4584 cpu_to_be32(mpll_dq_func_cntl); 4585 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4586 cpu_to_be32(mpll_func_cntl); 4587 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4588 cpu_to_be32(mpll_func_cntl_1); 4589 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4590 cpu_to_be32(mpll_func_cntl_2); 4591 table->ACPIState.levels[0].mclk.vMPLL_SS = 4592 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4593 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4594 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4595 4596 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4597 cpu_to_be32(spll_func_cntl); 4598 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4599 cpu_to_be32(spll_func_cntl_2); 4600 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4601 cpu_to_be32(spll_func_cntl_3); 4602 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4603 cpu_to_be32(spll_func_cntl_4); 4604 4605 table->ACPIState.levels[0].mclk.mclk_value = 0; 4606 table->ACPIState.levels[0].sclk.sclk_value = 0; 4607 4608 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4609 4610 if (eg_pi->dynamic_ac_timing) 4611 table->ACPIState.levels[0].ACIndex = 0; 4612 4613 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4614 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4615 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4616 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4617 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4618 4619 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4620 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4621 4622 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4623 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4624 4625 return 0; 4626 } 4627 4628 static int si_populate_ulv_state(struct radeon_device *rdev, 4629 SISLANDS_SMC_SWSTATE *state) 4630 { 4631 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4632 struct si_power_info *si_pi = si_get_pi(rdev); 4633 struct si_ulv_param *ulv = &si_pi->ulv; 4634 u32 sclk_in_sr = 1350; /* ??? */ 4635 int ret; 4636 4637 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4638 &state->levels[0]); 4639 if (!ret) { 4640 if (eg_pi->sclk_deep_sleep) { 4641 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4642 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4643 else 4644 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4645 } 4646 if (ulv->one_pcie_lane_in_ulv) 4647 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4648 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4649 state->levels[0].ACIndex = 1; 4650 state->levels[0].std_vddc = state->levels[0].vddc; 4651 state->levelCount = 1; 4652 4653 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4654 } 4655 4656 return ret; 4657 } 4658 4659 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4660 { 4661 struct si_power_info *si_pi = si_get_pi(rdev); 4662 struct si_ulv_param *ulv = &si_pi->ulv; 4663 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4664 int ret; 4665 4666 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4667 &arb_regs); 4668 if (ret) 4669 return ret; 4670 4671 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4672 ulv->volt_change_delay); 4673 4674 ret = si_copy_bytes_to_smc(rdev, 4675 si_pi->arb_table_start + 4676 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4677 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4678 (u8 *)&arb_regs, 4679 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4680 si_pi->sram_end); 4681 4682 return ret; 4683 } 4684 4685 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4686 { 4687 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4688 4689 pi->mvdd_split_frequency = 30000; 4690 } 4691 4692 static int si_init_smc_table(struct radeon_device *rdev) 4693 { 4694 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4695 struct si_power_info *si_pi = si_get_pi(rdev); 4696 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4697 const struct si_ulv_param *ulv = &si_pi->ulv; 4698 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4699 int ret; 4700 u32 lane_width; 4701 u32 vr_hot_gpio; 4702 4703 si_populate_smc_voltage_tables(rdev, table); 4704 4705 switch (rdev->pm.int_thermal_type) { 4706 case THERMAL_TYPE_SI: 4707 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4708 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4709 break; 4710 case THERMAL_TYPE_NONE: 4711 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4712 break; 4713 default: 4714 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4715 break; 4716 } 4717 4718 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4719 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4720 4721 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4722 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4723 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4724 } 4725 4726 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4727 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4728 4729 if (pi->mem_gddr5) 4730 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4731 4732 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4733 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4734 4735 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4736 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4737 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4738 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4739 vr_hot_gpio); 4740 } 4741 4742 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4743 if (ret) 4744 return ret; 4745 4746 ret = si_populate_smc_acpi_state(rdev, table); 4747 if (ret) 4748 return ret; 4749 4750 table->driverState = table->initialState; 4751 4752 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4753 SISLANDS_INITIAL_STATE_ARB_INDEX); 4754 if (ret) 4755 return ret; 4756 4757 if (ulv->supported && ulv->pl.vddc) { 4758 ret = si_populate_ulv_state(rdev, &table->ULVState); 4759 if (ret) 4760 return ret; 4761 4762 ret = si_program_ulv_memory_timing_parameters(rdev); 4763 if (ret) 4764 return ret; 4765 4766 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4767 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4768 4769 lane_width = radeon_get_pcie_lanes(rdev); 4770 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4771 } else { 4772 table->ULVState = table->initialState; 4773 } 4774 4775 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4776 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4777 si_pi->sram_end); 4778 } 4779 4780 static int si_calculate_sclk_params(struct radeon_device *rdev, 4781 u32 engine_clock, 4782 SISLANDS_SMC_SCLK_VALUE *sclk) 4783 { 4784 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4785 struct si_power_info *si_pi = si_get_pi(rdev); 4786 struct atom_clock_dividers dividers; 4787 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4788 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4789 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4790 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4791 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4792 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4793 u64 tmp; 4794 u32 reference_clock = rdev->clock.spll.reference_freq; 4795 u32 reference_divider; 4796 u32 fbdiv; 4797 int ret; 4798 4799 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4800 engine_clock, false, ÷rs); 4801 if (ret) 4802 return ret; 4803 4804 reference_divider = 1 + dividers.ref_div; 4805 4806 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4807 do_div(tmp, reference_clock); 4808 fbdiv = (u32) tmp; 4809 4810 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4811 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4812 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4813 4814 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4815 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4816 4817 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4818 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4819 spll_func_cntl_3 |= SPLL_DITHEN; 4820 4821 if (pi->sclk_ss) { 4822 struct radeon_atom_ss ss; 4823 u32 vco_freq = engine_clock * dividers.post_div; 4824 4825 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4826 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4827 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4828 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4829 4830 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4831 cg_spll_spread_spectrum |= CLK_S(clk_s); 4832 cg_spll_spread_spectrum |= SSEN; 4833 4834 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4835 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4836 } 4837 } 4838 4839 sclk->sclk_value = engine_clock; 4840 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4841 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4842 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4843 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4844 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4845 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4846 4847 return 0; 4848 } 4849 4850 static int si_populate_sclk_value(struct radeon_device *rdev, 4851 u32 engine_clock, 4852 SISLANDS_SMC_SCLK_VALUE *sclk) 4853 { 4854 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4855 int ret; 4856 4857 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4858 if (!ret) { 4859 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4860 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4861 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4862 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4863 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4864 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4865 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4866 } 4867 4868 return ret; 4869 } 4870 4871 static int si_populate_mclk_value(struct radeon_device *rdev, 4872 u32 engine_clock, 4873 u32 memory_clock, 4874 SISLANDS_SMC_MCLK_VALUE *mclk, 4875 bool strobe_mode, 4876 bool dll_state_on) 4877 { 4878 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4879 struct si_power_info *si_pi = si_get_pi(rdev); 4880 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4881 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4882 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4883 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4884 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4885 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4886 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4887 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4888 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4889 struct atom_mpll_param mpll_param; 4890 int ret; 4891 4892 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4893 if (ret) 4894 return ret; 4895 4896 mpll_func_cntl &= ~BWCTRL_MASK; 4897 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4898 4899 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4900 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4901 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4902 4903 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4904 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4905 4906 if (pi->mem_gddr5) { 4907 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4908 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4909 YCLK_POST_DIV(mpll_param.post_div); 4910 } 4911 4912 if (pi->mclk_ss) { 4913 struct radeon_atom_ss ss; 4914 u32 freq_nom; 4915 u32 tmp; 4916 u32 reference_clock = rdev->clock.mpll.reference_freq; 4917 4918 if (pi->mem_gddr5) 4919 freq_nom = memory_clock * 4; 4920 else 4921 freq_nom = memory_clock * 2; 4922 4923 tmp = freq_nom / reference_clock; 4924 tmp = tmp * tmp; 4925 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4926 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4927 u32 clks = reference_clock * 5 / ss.rate; 4928 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4929 4930 mpll_ss1 &= ~CLKV_MASK; 4931 mpll_ss1 |= CLKV(clkv); 4932 4933 mpll_ss2 &= ~CLKS_MASK; 4934 mpll_ss2 |= CLKS(clks); 4935 } 4936 } 4937 4938 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4939 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4940 4941 if (dll_state_on) 4942 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4943 else 4944 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4945 4946 mclk->mclk_value = cpu_to_be32(memory_clock); 4947 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4948 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4949 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4950 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4951 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4952 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4953 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4954 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4955 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4956 4957 return 0; 4958 } 4959 4960 static void si_populate_smc_sp(struct radeon_device *rdev, 4961 struct radeon_ps *radeon_state, 4962 SISLANDS_SMC_SWSTATE *smc_state) 4963 { 4964 struct ni_ps *ps = ni_get_ps(radeon_state); 4965 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4966 int i; 4967 4968 for (i = 0; i < ps->performance_level_count - 1; i++) 4969 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4970 4971 smc_state->levels[ps->performance_level_count - 1].bSP = 4972 cpu_to_be32(pi->psp); 4973 } 4974 4975 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4976 struct rv7xx_pl *pl, 4977 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4978 { 4979 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4980 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4981 struct si_power_info *si_pi = si_get_pi(rdev); 4982 int ret; 4983 bool dll_state_on; 4984 u16 std_vddc; 4985 bool gmc_pg = false; 4986 4987 if (eg_pi->pcie_performance_request && 4988 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4989 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4990 else 4991 level->gen2PCIE = (u8)pl->pcie_gen; 4992 4993 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4994 if (ret) 4995 return ret; 4996 4997 level->mcFlags = 0; 4998 4999 if (pi->mclk_stutter_mode_threshold && 5000 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5001 !eg_pi->uvd_enabled && 5002 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5003 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5004 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5005 5006 if (gmc_pg) 5007 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5008 } 5009 5010 if (pi->mem_gddr5) { 5011 if (pl->mclk > pi->mclk_edc_enable_threshold) 5012 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5013 5014 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5015 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5016 5017 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5018 5019 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5020 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5021 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5022 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5023 else 5024 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5025 } else { 5026 dll_state_on = false; 5027 } 5028 } else { 5029 level->strobeMode = si_get_strobe_mode_settings(rdev, 5030 pl->mclk); 5031 5032 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5033 } 5034 5035 ret = si_populate_mclk_value(rdev, 5036 pl->sclk, 5037 pl->mclk, 5038 &level->mclk, 5039 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5040 if (ret) 5041 return ret; 5042 5043 ret = si_populate_voltage_value(rdev, 5044 &eg_pi->vddc_voltage_table, 5045 pl->vddc, &level->vddc); 5046 if (ret) 5047 return ret; 5048 5049 5050 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5051 if (ret) 5052 return ret; 5053 5054 ret = si_populate_std_voltage_value(rdev, std_vddc, 5055 level->vddc.index, &level->std_vddc); 5056 if (ret) 5057 return ret; 5058 5059 if (eg_pi->vddci_control) { 5060 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5061 pl->vddci, &level->vddci); 5062 if (ret) 5063 return ret; 5064 } 5065 5066 if (si_pi->vddc_phase_shed_control) { 5067 ret = si_populate_phase_shedding_value(rdev, 5068 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5069 pl->vddc, 5070 pl->sclk, 5071 pl->mclk, 5072 &level->vddc); 5073 if (ret) 5074 return ret; 5075 } 5076 5077 level->MaxPoweredUpCU = si_pi->max_cu; 5078 5079 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5080 5081 return ret; 5082 } 5083 5084 static int si_populate_smc_t(struct radeon_device *rdev, 5085 struct radeon_ps *radeon_state, 5086 SISLANDS_SMC_SWSTATE *smc_state) 5087 { 5088 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5089 struct ni_ps *state = ni_get_ps(radeon_state); 5090 u32 a_t; 5091 u32 t_l, t_h; 5092 u32 high_bsp; 5093 int i, ret; 5094 5095 if (state->performance_level_count >= 9) 5096 return -EINVAL; 5097 5098 if (state->performance_level_count < 2) { 5099 a_t = CG_R(0xffff) | CG_L(0); 5100 smc_state->levels[0].aT = cpu_to_be32(a_t); 5101 return 0; 5102 } 5103 5104 smc_state->levels[0].aT = cpu_to_be32(0); 5105 5106 for (i = 0; i <= state->performance_level_count - 2; i++) { 5107 ret = r600_calculate_at( 5108 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5109 100 * R600_AH_DFLT, 5110 state->performance_levels[i + 1].sclk, 5111 state->performance_levels[i].sclk, 5112 &t_l, 5113 &t_h); 5114 5115 if (ret) { 5116 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5117 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5118 } 5119 5120 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5121 a_t |= CG_R(t_l * pi->bsp / 20000); 5122 smc_state->levels[i].aT = cpu_to_be32(a_t); 5123 5124 high_bsp = (i == state->performance_level_count - 2) ? 5125 pi->pbsp : pi->bsp; 5126 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5127 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5128 } 5129 5130 return 0; 5131 } 5132 5133 static int si_disable_ulv(struct radeon_device *rdev) 5134 { 5135 struct si_power_info *si_pi = si_get_pi(rdev); 5136 struct si_ulv_param *ulv = &si_pi->ulv; 5137 5138 if (ulv->supported) 5139 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5140 0 : -EINVAL; 5141 5142 return 0; 5143 } 5144 5145 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5146 struct radeon_ps *radeon_state) 5147 { 5148 const struct si_power_info *si_pi = si_get_pi(rdev); 5149 const struct si_ulv_param *ulv = &si_pi->ulv; 5150 const struct ni_ps *state = ni_get_ps(radeon_state); 5151 int i; 5152 5153 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5154 return false; 5155 5156 /* XXX validate against display requirements! */ 5157 5158 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5159 if (rdev->clock.current_dispclk <= 5160 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5161 if (ulv->pl.vddc < 5162 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5163 return false; 5164 } 5165 } 5166 5167 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5168 return false; 5169 5170 return true; 5171 } 5172 5173 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5174 struct radeon_ps *radeon_new_state) 5175 { 5176 const struct si_power_info *si_pi = si_get_pi(rdev); 5177 const struct si_ulv_param *ulv = &si_pi->ulv; 5178 5179 if (ulv->supported) { 5180 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5181 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5182 0 : -EINVAL; 5183 } 5184 return 0; 5185 } 5186 5187 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5188 struct radeon_ps *radeon_state, 5189 SISLANDS_SMC_SWSTATE *smc_state) 5190 { 5191 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5192 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5193 struct si_power_info *si_pi = si_get_pi(rdev); 5194 struct ni_ps *state = ni_get_ps(radeon_state); 5195 int i, ret; 5196 u32 threshold; 5197 u32 sclk_in_sr = 1350; /* ??? */ 5198 5199 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5200 return -EINVAL; 5201 5202 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5203 5204 if (radeon_state->vclk && radeon_state->dclk) { 5205 eg_pi->uvd_enabled = true; 5206 if (eg_pi->smu_uvd_hs) 5207 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5208 } else { 5209 eg_pi->uvd_enabled = false; 5210 } 5211 5212 if (state->dc_compatible) 5213 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5214 5215 smc_state->levelCount = 0; 5216 for (i = 0; i < state->performance_level_count; i++) { 5217 if (eg_pi->sclk_deep_sleep) { 5218 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5219 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5220 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5221 else 5222 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5223 } 5224 } 5225 5226 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5227 &smc_state->levels[i]); 5228 smc_state->levels[i].arbRefreshState = 5229 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5230 5231 if (ret) 5232 return ret; 5233 5234 if (ni_pi->enable_power_containment) 5235 smc_state->levels[i].displayWatermark = 5236 (state->performance_levels[i].sclk < threshold) ? 5237 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5238 else 5239 smc_state->levels[i].displayWatermark = (i < 2) ? 5240 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5241 5242 if (eg_pi->dynamic_ac_timing) 5243 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5244 else 5245 smc_state->levels[i].ACIndex = 0; 5246 5247 smc_state->levelCount++; 5248 } 5249 5250 si_write_smc_soft_register(rdev, 5251 SI_SMC_SOFT_REGISTER_watermark_threshold, 5252 threshold / 512); 5253 5254 si_populate_smc_sp(rdev, radeon_state, smc_state); 5255 5256 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5257 if (ret) 5258 ni_pi->enable_power_containment = false; 5259 5260 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5261 if (ret) 5262 ni_pi->enable_sq_ramping = false; 5263 5264 return si_populate_smc_t(rdev, radeon_state, smc_state); 5265 } 5266 5267 static int si_upload_sw_state(struct radeon_device *rdev, 5268 struct radeon_ps *radeon_new_state) 5269 { 5270 struct si_power_info *si_pi = si_get_pi(rdev); 5271 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5272 int ret; 5273 u32 address = si_pi->state_table_start + 5274 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5275 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5276 ((new_state->performance_level_count - 1) * 5277 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5278 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5279 5280 memset(smc_state, 0, state_size); 5281 5282 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5283 if (ret) 5284 return ret; 5285 5286 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5287 state_size, si_pi->sram_end); 5288 5289 return ret; 5290 } 5291 5292 static int si_upload_ulv_state(struct radeon_device *rdev) 5293 { 5294 struct si_power_info *si_pi = si_get_pi(rdev); 5295 struct si_ulv_param *ulv = &si_pi->ulv; 5296 int ret = 0; 5297 5298 if (ulv->supported && ulv->pl.vddc) { 5299 u32 address = si_pi->state_table_start + 5300 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5301 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5302 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5303 5304 memset(smc_state, 0, state_size); 5305 5306 ret = si_populate_ulv_state(rdev, smc_state); 5307 if (!ret) 5308 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5309 state_size, si_pi->sram_end); 5310 } 5311 5312 return ret; 5313 } 5314 5315 static int si_upload_smc_data(struct radeon_device *rdev) 5316 { 5317 struct radeon_crtc *radeon_crtc = NULL; 5318 int i; 5319 5320 if (rdev->pm.dpm.new_active_crtc_count == 0) 5321 return 0; 5322 5323 for (i = 0; i < rdev->num_crtc; i++) { 5324 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5325 radeon_crtc = rdev->mode_info.crtcs[i]; 5326 break; 5327 } 5328 } 5329 5330 if (radeon_crtc == NULL) 5331 return 0; 5332 5333 if (radeon_crtc->line_time <= 0) 5334 return 0; 5335 5336 if (si_write_smc_soft_register(rdev, 5337 SI_SMC_SOFT_REGISTER_crtc_index, 5338 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5339 return 0; 5340 5341 if (si_write_smc_soft_register(rdev, 5342 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5343 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5344 return 0; 5345 5346 if (si_write_smc_soft_register(rdev, 5347 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5348 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5349 return 0; 5350 5351 return 0; 5352 } 5353 5354 static int si_set_mc_special_registers(struct radeon_device *rdev, 5355 struct si_mc_reg_table *table) 5356 { 5357 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5358 u8 i, j, k; 5359 u32 temp_reg; 5360 5361 for (i = 0, j = table->last; i < table->last; i++) { 5362 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5363 return -EINVAL; 5364 switch (table->mc_reg_address[i].s1 << 2) { 5365 case MC_SEQ_MISC1: 5366 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5367 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5368 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5369 for (k = 0; k < table->num_entries; k++) 5370 table->mc_reg_table_entry[k].mc_data[j] = 5371 ((temp_reg & 0xffff0000)) | 5372 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5373 j++; 5374 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5375 return -EINVAL; 5376 5377 temp_reg = RREG32(MC_PMG_CMD_MRS); 5378 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5379 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5380 for (k = 0; k < table->num_entries; k++) { 5381 table->mc_reg_table_entry[k].mc_data[j] = 5382 (temp_reg & 0xffff0000) | 5383 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5384 if (!pi->mem_gddr5) 5385 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5386 } 5387 j++; 5388 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5389 return -EINVAL; 5390 5391 if (!pi->mem_gddr5) { 5392 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5393 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5394 for (k = 0; k < table->num_entries; k++) 5395 table->mc_reg_table_entry[k].mc_data[j] = 5396 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5397 j++; 5398 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5399 return -EINVAL; 5400 } 5401 break; 5402 case MC_SEQ_RESERVE_M: 5403 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5404 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5405 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5406 for(k = 0; k < table->num_entries; k++) 5407 table->mc_reg_table_entry[k].mc_data[j] = 5408 (temp_reg & 0xffff0000) | 5409 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5410 j++; 5411 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5412 return -EINVAL; 5413 break; 5414 default: 5415 break; 5416 } 5417 } 5418 5419 table->last = j; 5420 5421 return 0; 5422 } 5423 5424 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5425 { 5426 bool result = true; 5427 5428 switch (in_reg) { 5429 case MC_SEQ_RAS_TIMING >> 2: 5430 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5431 break; 5432 case MC_SEQ_CAS_TIMING >> 2: 5433 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5434 break; 5435 case MC_SEQ_MISC_TIMING >> 2: 5436 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5437 break; 5438 case MC_SEQ_MISC_TIMING2 >> 2: 5439 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5440 break; 5441 case MC_SEQ_RD_CTL_D0 >> 2: 5442 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5443 break; 5444 case MC_SEQ_RD_CTL_D1 >> 2: 5445 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5446 break; 5447 case MC_SEQ_WR_CTL_D0 >> 2: 5448 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5449 break; 5450 case MC_SEQ_WR_CTL_D1 >> 2: 5451 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5452 break; 5453 case MC_PMG_CMD_EMRS >> 2: 5454 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5455 break; 5456 case MC_PMG_CMD_MRS >> 2: 5457 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5458 break; 5459 case MC_PMG_CMD_MRS1 >> 2: 5460 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5461 break; 5462 case MC_SEQ_PMG_TIMING >> 2: 5463 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5464 break; 5465 case MC_PMG_CMD_MRS2 >> 2: 5466 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5467 break; 5468 case MC_SEQ_WR_CTL_2 >> 2: 5469 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5470 break; 5471 default: 5472 result = false; 5473 break; 5474 } 5475 5476 return result; 5477 } 5478 5479 static void si_set_valid_flag(struct si_mc_reg_table *table) 5480 { 5481 u8 i, j; 5482 5483 for (i = 0; i < table->last; i++) { 5484 for (j = 1; j < table->num_entries; j++) { 5485 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5486 table->valid_flag |= 1 << i; 5487 break; 5488 } 5489 } 5490 } 5491 } 5492 5493 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5494 { 5495 u32 i; 5496 u16 address; 5497 5498 for (i = 0; i < table->last; i++) 5499 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5500 address : table->mc_reg_address[i].s1; 5501 5502 } 5503 5504 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5505 struct si_mc_reg_table *si_table) 5506 { 5507 u8 i, j; 5508 5509 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5510 return -EINVAL; 5511 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5512 return -EINVAL; 5513 5514 for (i = 0; i < table->last; i++) 5515 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5516 si_table->last = table->last; 5517 5518 for (i = 0; i < table->num_entries; i++) { 5519 si_table->mc_reg_table_entry[i].mclk_max = 5520 table->mc_reg_table_entry[i].mclk_max; 5521 for (j = 0; j < table->last; j++) { 5522 si_table->mc_reg_table_entry[i].mc_data[j] = 5523 table->mc_reg_table_entry[i].mc_data[j]; 5524 } 5525 } 5526 si_table->num_entries = table->num_entries; 5527 5528 return 0; 5529 } 5530 5531 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5532 { 5533 struct si_power_info *si_pi = si_get_pi(rdev); 5534 struct atom_mc_reg_table *table; 5535 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5536 u8 module_index = rv770_get_memory_module_index(rdev); 5537 int ret; 5538 5539 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5540 if (!table) 5541 return -ENOMEM; 5542 5543 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5544 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5545 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5546 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5547 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5548 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5549 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5550 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5551 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5552 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5553 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5554 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5555 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5556 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5557 5558 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5559 if (ret) 5560 goto init_mc_done; 5561 5562 ret = si_copy_vbios_mc_reg_table(table, si_table); 5563 if (ret) 5564 goto init_mc_done; 5565 5566 si_set_s0_mc_reg_index(si_table); 5567 5568 ret = si_set_mc_special_registers(rdev, si_table); 5569 if (ret) 5570 goto init_mc_done; 5571 5572 si_set_valid_flag(si_table); 5573 5574 init_mc_done: 5575 kfree(table); 5576 5577 return ret; 5578 5579 } 5580 5581 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5582 SMC_SIslands_MCRegisters *mc_reg_table) 5583 { 5584 struct si_power_info *si_pi = si_get_pi(rdev); 5585 u32 i, j; 5586 5587 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5588 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5589 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5590 break; 5591 mc_reg_table->address[i].s0 = 5592 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5593 mc_reg_table->address[i].s1 = 5594 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5595 i++; 5596 } 5597 } 5598 mc_reg_table->last = (u8)i; 5599 } 5600 5601 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5602 SMC_SIslands_MCRegisterSet *data, 5603 u32 num_entries, u32 valid_flag) 5604 { 5605 u32 i, j; 5606 5607 for(i = 0, j = 0; j < num_entries; j++) { 5608 if (valid_flag & (1 << j)) { 5609 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5610 i++; 5611 } 5612 } 5613 } 5614 5615 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5616 struct rv7xx_pl *pl, 5617 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5618 { 5619 struct si_power_info *si_pi = si_get_pi(rdev); 5620 u32 i = 0; 5621 5622 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5623 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5624 break; 5625 } 5626 5627 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5628 --i; 5629 5630 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5631 mc_reg_table_data, si_pi->mc_reg_table.last, 5632 si_pi->mc_reg_table.valid_flag); 5633 } 5634 5635 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5636 struct radeon_ps *radeon_state, 5637 SMC_SIslands_MCRegisters *mc_reg_table) 5638 { 5639 struct ni_ps *state = ni_get_ps(radeon_state); 5640 int i; 5641 5642 for (i = 0; i < state->performance_level_count; i++) { 5643 si_convert_mc_reg_table_entry_to_smc(rdev, 5644 &state->performance_levels[i], 5645 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5646 } 5647 } 5648 5649 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5650 struct radeon_ps *radeon_boot_state) 5651 { 5652 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5653 struct si_power_info *si_pi = si_get_pi(rdev); 5654 struct si_ulv_param *ulv = &si_pi->ulv; 5655 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5656 5657 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5658 5659 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5660 5661 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5662 5663 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5664 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5665 5666 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5667 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5668 si_pi->mc_reg_table.last, 5669 si_pi->mc_reg_table.valid_flag); 5670 5671 if (ulv->supported && ulv->pl.vddc != 0) 5672 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5673 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5674 else 5675 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5676 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5677 si_pi->mc_reg_table.last, 5678 si_pi->mc_reg_table.valid_flag); 5679 5680 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5681 5682 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5683 (u8 *)smc_mc_reg_table, 5684 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5685 } 5686 5687 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5688 struct radeon_ps *radeon_new_state) 5689 { 5690 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5691 struct si_power_info *si_pi = si_get_pi(rdev); 5692 u32 address = si_pi->mc_reg_table_start + 5693 offsetof(SMC_SIslands_MCRegisters, 5694 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5695 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5696 5697 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5698 5699 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5700 5701 5702 return si_copy_bytes_to_smc(rdev, address, 5703 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5704 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5705 si_pi->sram_end); 5706 5707 } 5708 5709 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5710 { 5711 if (enable) 5712 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5713 else 5714 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5715 } 5716 5717 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5718 struct radeon_ps *radeon_state) 5719 { 5720 struct ni_ps *state = ni_get_ps(radeon_state); 5721 int i; 5722 u16 pcie_speed, max_speed = 0; 5723 5724 for (i = 0; i < state->performance_level_count; i++) { 5725 pcie_speed = state->performance_levels[i].pcie_gen; 5726 if (max_speed < pcie_speed) 5727 max_speed = pcie_speed; 5728 } 5729 return max_speed; 5730 } 5731 5732 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5733 { 5734 u32 speed_cntl; 5735 5736 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5737 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5738 5739 return (u16)speed_cntl; 5740 } 5741 5742 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5743 struct radeon_ps *radeon_new_state, 5744 struct radeon_ps *radeon_current_state) 5745 { 5746 struct si_power_info *si_pi = si_get_pi(rdev); 5747 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5748 enum radeon_pcie_gen current_link_speed; 5749 5750 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5751 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5752 else 5753 current_link_speed = si_pi->force_pcie_gen; 5754 5755 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5756 si_pi->pspp_notify_required = false; 5757 if (target_link_speed > current_link_speed) { 5758 switch (target_link_speed) { 5759 #if defined(CONFIG_ACPI) 5760 case RADEON_PCIE_GEN3: 5761 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5762 break; 5763 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5764 if (current_link_speed == RADEON_PCIE_GEN2) 5765 break; 5766 case RADEON_PCIE_GEN2: 5767 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5768 break; 5769 #endif 5770 default: 5771 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5772 break; 5773 } 5774 } else { 5775 if (target_link_speed < current_link_speed) 5776 si_pi->pspp_notify_required = true; 5777 } 5778 } 5779 5780 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5781 struct radeon_ps *radeon_new_state, 5782 struct radeon_ps *radeon_current_state) 5783 { 5784 struct si_power_info *si_pi = si_get_pi(rdev); 5785 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5786 u8 request; 5787 5788 if (si_pi->pspp_notify_required) { 5789 if (target_link_speed == RADEON_PCIE_GEN3) 5790 request = PCIE_PERF_REQ_PECI_GEN3; 5791 else if (target_link_speed == RADEON_PCIE_GEN2) 5792 request = PCIE_PERF_REQ_PECI_GEN2; 5793 else 5794 request = PCIE_PERF_REQ_PECI_GEN1; 5795 5796 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5797 (si_get_current_pcie_speed(rdev) > 0)) 5798 return; 5799 5800 #if defined(CONFIG_ACPI) 5801 radeon_acpi_pcie_performance_request(rdev, request, false); 5802 #endif 5803 } 5804 } 5805 5806 #if 0 5807 static int si_ds_request(struct radeon_device *rdev, 5808 bool ds_status_on, u32 count_write) 5809 { 5810 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5811 5812 if (eg_pi->sclk_deep_sleep) { 5813 if (ds_status_on) 5814 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5815 PPSMC_Result_OK) ? 5816 0 : -EINVAL; 5817 else 5818 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5819 PPSMC_Result_OK) ? 0 : -EINVAL; 5820 } 5821 return 0; 5822 } 5823 #endif 5824 5825 static void si_set_max_cu_value(struct radeon_device *rdev) 5826 { 5827 struct si_power_info *si_pi = si_get_pi(rdev); 5828 5829 if (rdev->family == CHIP_VERDE) { 5830 switch (rdev->pdev->device) { 5831 case 0x6820: 5832 case 0x6825: 5833 case 0x6821: 5834 case 0x6823: 5835 case 0x6827: 5836 si_pi->max_cu = 10; 5837 break; 5838 case 0x682D: 5839 case 0x6824: 5840 case 0x682F: 5841 case 0x6826: 5842 si_pi->max_cu = 8; 5843 break; 5844 case 0x6828: 5845 case 0x6830: 5846 case 0x6831: 5847 case 0x6838: 5848 case 0x6839: 5849 case 0x683D: 5850 si_pi->max_cu = 10; 5851 break; 5852 case 0x683B: 5853 case 0x683F: 5854 case 0x6829: 5855 si_pi->max_cu = 8; 5856 break; 5857 default: 5858 si_pi->max_cu = 0; 5859 break; 5860 } 5861 } else { 5862 si_pi->max_cu = 0; 5863 } 5864 } 5865 5866 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5867 struct radeon_clock_voltage_dependency_table *table) 5868 { 5869 u32 i; 5870 int j; 5871 u16 leakage_voltage; 5872 5873 if (table) { 5874 for (i = 0; i < table->count; i++) { 5875 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5876 table->entries[i].v, 5877 &leakage_voltage)) { 5878 case 0: 5879 table->entries[i].v = leakage_voltage; 5880 break; 5881 case -EAGAIN: 5882 return -EINVAL; 5883 case -EINVAL: 5884 default: 5885 break; 5886 } 5887 } 5888 5889 for (j = (table->count - 2); j >= 0; j--) { 5890 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5891 table->entries[j].v : table->entries[j + 1].v; 5892 } 5893 } 5894 return 0; 5895 } 5896 5897 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5898 { 5899 int ret = 0; 5900 5901 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5902 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5903 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5904 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5905 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5906 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5907 return ret; 5908 } 5909 5910 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5911 struct radeon_ps *radeon_new_state, 5912 struct radeon_ps *radeon_current_state) 5913 { 5914 u32 lane_width; 5915 u32 new_lane_width = 5916 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5917 u32 current_lane_width = 5918 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5919 5920 if (new_lane_width != current_lane_width) { 5921 radeon_set_pcie_lanes(rdev, new_lane_width); 5922 lane_width = radeon_get_pcie_lanes(rdev); 5923 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5924 } 5925 } 5926 5927 static void si_set_vce_clock(struct radeon_device *rdev, 5928 struct radeon_ps *new_rps, 5929 struct radeon_ps *old_rps) 5930 { 5931 if ((old_rps->evclk != new_rps->evclk) || 5932 (old_rps->ecclk != new_rps->ecclk)) { 5933 /* turn the clocks on when encoding, off otherwise */ 5934 if (new_rps->evclk || new_rps->ecclk) 5935 vce_v1_0_enable_mgcg(rdev, false); 5936 else 5937 vce_v1_0_enable_mgcg(rdev, true); 5938 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5939 } 5940 } 5941 5942 void si_dpm_setup_asic(struct radeon_device *rdev) 5943 { 5944 int r; 5945 5946 r = si_mc_load_microcode(rdev); 5947 if (r) 5948 DRM_ERROR("Failed to load MC firmware!\n"); 5949 rv770_get_memory_type(rdev); 5950 si_read_clock_registers(rdev); 5951 si_enable_acpi_power_management(rdev); 5952 } 5953 5954 static int si_thermal_enable_alert(struct radeon_device *rdev, 5955 bool enable) 5956 { 5957 u32 thermal_int = RREG32(CG_THERMAL_INT); 5958 5959 if (enable) { 5960 PPSMC_Result result; 5961 5962 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5963 WREG32(CG_THERMAL_INT, thermal_int); 5964 rdev->irq.dpm_thermal = false; 5965 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5966 if (result != PPSMC_Result_OK) { 5967 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5968 return -EINVAL; 5969 } 5970 } else { 5971 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5972 WREG32(CG_THERMAL_INT, thermal_int); 5973 rdev->irq.dpm_thermal = true; 5974 } 5975 5976 return 0; 5977 } 5978 5979 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5980 int min_temp, int max_temp) 5981 { 5982 int low_temp = 0 * 1000; 5983 int high_temp = 255 * 1000; 5984 5985 if (low_temp < min_temp) 5986 low_temp = min_temp; 5987 if (high_temp > max_temp) 5988 high_temp = max_temp; 5989 if (high_temp < low_temp) { 5990 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5991 return -EINVAL; 5992 } 5993 5994 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5995 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5996 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5997 5998 rdev->pm.dpm.thermal.min_temp = low_temp; 5999 rdev->pm.dpm.thermal.max_temp = high_temp; 6000 6001 return 0; 6002 } 6003 6004 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6005 { 6006 struct si_power_info *si_pi = si_get_pi(rdev); 6007 u32 tmp; 6008 6009 if (si_pi->fan_ctrl_is_in_default_mode) { 6010 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6011 si_pi->fan_ctrl_default_mode = tmp; 6012 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6013 si_pi->t_min = tmp; 6014 si_pi->fan_ctrl_is_in_default_mode = false; 6015 } 6016 6017 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6018 tmp |= TMIN(0); 6019 WREG32(CG_FDO_CTRL2, tmp); 6020 6021 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6022 tmp |= FDO_PWM_MODE(mode); 6023 WREG32(CG_FDO_CTRL2, tmp); 6024 } 6025 6026 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6027 { 6028 struct si_power_info *si_pi = si_get_pi(rdev); 6029 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6030 u32 duty100; 6031 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6032 u16 fdo_min, slope1, slope2; 6033 u32 reference_clock, tmp; 6034 int ret; 6035 u64 tmp64; 6036 6037 if (!si_pi->fan_table_start) { 6038 rdev->pm.dpm.fan.ucode_fan_control = false; 6039 return 0; 6040 } 6041 6042 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6043 6044 if (duty100 == 0) { 6045 rdev->pm.dpm.fan.ucode_fan_control = false; 6046 return 0; 6047 } 6048 6049 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6050 do_div(tmp64, 10000); 6051 fdo_min = (u16)tmp64; 6052 6053 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6054 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6055 6056 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6057 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6058 6059 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6060 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6061 6062 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6063 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6064 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6065 6066 fan_table.slope1 = cpu_to_be16(slope1); 6067 fan_table.slope2 = cpu_to_be16(slope2); 6068 6069 fan_table.fdo_min = cpu_to_be16(fdo_min); 6070 6071 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6072 6073 fan_table.hys_up = cpu_to_be16(1); 6074 6075 fan_table.hys_slope = cpu_to_be16(1); 6076 6077 fan_table.temp_resp_lim = cpu_to_be16(5); 6078 6079 reference_clock = radeon_get_xclk(rdev); 6080 6081 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6082 reference_clock) / 1600); 6083 6084 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6085 6086 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6087 fan_table.temp_src = (uint8_t)tmp; 6088 6089 ret = si_copy_bytes_to_smc(rdev, 6090 si_pi->fan_table_start, 6091 (u8 *)(&fan_table), 6092 sizeof(fan_table), 6093 si_pi->sram_end); 6094 6095 if (ret) { 6096 DRM_ERROR("Failed to load fan table to the SMC."); 6097 rdev->pm.dpm.fan.ucode_fan_control = false; 6098 } 6099 6100 return 0; 6101 } 6102 6103 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6104 { 6105 struct si_power_info *si_pi = si_get_pi(rdev); 6106 PPSMC_Result ret; 6107 6108 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6109 if (ret == PPSMC_Result_OK) { 6110 si_pi->fan_is_controlled_by_smc = true; 6111 return 0; 6112 } else { 6113 return -EINVAL; 6114 } 6115 } 6116 6117 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6118 { 6119 struct si_power_info *si_pi = si_get_pi(rdev); 6120 PPSMC_Result ret; 6121 6122 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6123 6124 if (ret == PPSMC_Result_OK) { 6125 si_pi->fan_is_controlled_by_smc = false; 6126 return 0; 6127 } else { 6128 return -EINVAL; 6129 } 6130 } 6131 6132 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6133 u32 *speed) 6134 { 6135 u32 duty, duty100; 6136 u64 tmp64; 6137 6138 if (rdev->pm.no_fan) 6139 return -ENOENT; 6140 6141 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6142 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6143 6144 if (duty100 == 0) 6145 return -EINVAL; 6146 6147 tmp64 = (u64)duty * 100; 6148 do_div(tmp64, duty100); 6149 *speed = (u32)tmp64; 6150 6151 if (*speed > 100) 6152 *speed = 100; 6153 6154 return 0; 6155 } 6156 6157 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6158 u32 speed) 6159 { 6160 struct si_power_info *si_pi = si_get_pi(rdev); 6161 u32 tmp; 6162 u32 duty, duty100; 6163 u64 tmp64; 6164 6165 if (rdev->pm.no_fan) 6166 return -ENOENT; 6167 6168 if (si_pi->fan_is_controlled_by_smc) 6169 return -EINVAL; 6170 6171 if (speed > 100) 6172 return -EINVAL; 6173 6174 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6175 6176 if (duty100 == 0) 6177 return -EINVAL; 6178 6179 tmp64 = (u64)speed * duty100; 6180 do_div(tmp64, 100); 6181 duty = (u32)tmp64; 6182 6183 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6184 tmp |= FDO_STATIC_DUTY(duty); 6185 WREG32(CG_FDO_CTRL0, tmp); 6186 6187 return 0; 6188 } 6189 6190 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6191 { 6192 if (mode) { 6193 /* stop auto-manage */ 6194 if (rdev->pm.dpm.fan.ucode_fan_control) 6195 si_fan_ctrl_stop_smc_fan_control(rdev); 6196 si_fan_ctrl_set_static_mode(rdev, mode); 6197 } else { 6198 /* restart auto-manage */ 6199 if (rdev->pm.dpm.fan.ucode_fan_control) 6200 si_thermal_start_smc_fan_control(rdev); 6201 else 6202 si_fan_ctrl_set_default_mode(rdev); 6203 } 6204 } 6205 6206 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6207 { 6208 struct si_power_info *si_pi = si_get_pi(rdev); 6209 u32 tmp; 6210 6211 if (si_pi->fan_is_controlled_by_smc) 6212 return 0; 6213 6214 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6215 return (tmp >> FDO_PWM_MODE_SHIFT); 6216 } 6217 6218 #if 0 6219 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6220 u32 *speed) 6221 { 6222 u32 tach_period; 6223 u32 xclk = radeon_get_xclk(rdev); 6224 6225 if (rdev->pm.no_fan) 6226 return -ENOENT; 6227 6228 if (rdev->pm.fan_pulses_per_revolution == 0) 6229 return -ENOENT; 6230 6231 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6232 if (tach_period == 0) 6233 return -ENOENT; 6234 6235 *speed = 60 * xclk * 10000 / tach_period; 6236 6237 return 0; 6238 } 6239 6240 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6241 u32 speed) 6242 { 6243 u32 tach_period, tmp; 6244 u32 xclk = radeon_get_xclk(rdev); 6245 6246 if (rdev->pm.no_fan) 6247 return -ENOENT; 6248 6249 if (rdev->pm.fan_pulses_per_revolution == 0) 6250 return -ENOENT; 6251 6252 if ((speed < rdev->pm.fan_min_rpm) || 6253 (speed > rdev->pm.fan_max_rpm)) 6254 return -EINVAL; 6255 6256 if (rdev->pm.dpm.fan.ucode_fan_control) 6257 si_fan_ctrl_stop_smc_fan_control(rdev); 6258 6259 tach_period = 60 * xclk * 10000 / (8 * speed); 6260 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6261 tmp |= TARGET_PERIOD(tach_period); 6262 WREG32(CG_TACH_CTRL, tmp); 6263 6264 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6265 6266 return 0; 6267 } 6268 #endif 6269 6270 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6271 { 6272 struct si_power_info *si_pi = si_get_pi(rdev); 6273 u32 tmp; 6274 6275 if (!si_pi->fan_ctrl_is_in_default_mode) { 6276 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6277 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6278 WREG32(CG_FDO_CTRL2, tmp); 6279 6280 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6281 tmp |= TMIN(si_pi->t_min); 6282 WREG32(CG_FDO_CTRL2, tmp); 6283 si_pi->fan_ctrl_is_in_default_mode = true; 6284 } 6285 } 6286 6287 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6288 { 6289 if (rdev->pm.dpm.fan.ucode_fan_control) { 6290 si_fan_ctrl_start_smc_fan_control(rdev); 6291 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6292 } 6293 } 6294 6295 static void si_thermal_initialize(struct radeon_device *rdev) 6296 { 6297 u32 tmp; 6298 6299 if (rdev->pm.fan_pulses_per_revolution) { 6300 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6301 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6302 WREG32(CG_TACH_CTRL, tmp); 6303 } 6304 6305 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6306 tmp |= TACH_PWM_RESP_RATE(0x28); 6307 WREG32(CG_FDO_CTRL2, tmp); 6308 } 6309 6310 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6311 { 6312 int ret; 6313 6314 si_thermal_initialize(rdev); 6315 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6316 if (ret) 6317 return ret; 6318 ret = si_thermal_enable_alert(rdev, true); 6319 if (ret) 6320 return ret; 6321 if (rdev->pm.dpm.fan.ucode_fan_control) { 6322 ret = si_halt_smc(rdev); 6323 if (ret) 6324 return ret; 6325 ret = si_thermal_setup_fan_table(rdev); 6326 if (ret) 6327 return ret; 6328 ret = si_resume_smc(rdev); 6329 if (ret) 6330 return ret; 6331 si_thermal_start_smc_fan_control(rdev); 6332 } 6333 6334 return 0; 6335 } 6336 6337 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6338 { 6339 if (!rdev->pm.no_fan) { 6340 si_fan_ctrl_set_default_mode(rdev); 6341 si_fan_ctrl_stop_smc_fan_control(rdev); 6342 } 6343 } 6344 6345 int si_dpm_enable(struct radeon_device *rdev) 6346 { 6347 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6348 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6349 struct si_power_info *si_pi = si_get_pi(rdev); 6350 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6351 int ret; 6352 6353 if (si_is_smc_running(rdev)) 6354 return -EINVAL; 6355 if (pi->voltage_control || si_pi->voltage_control_svi2) 6356 si_enable_voltage_control(rdev, true); 6357 if (pi->mvdd_control) 6358 si_get_mvdd_configuration(rdev); 6359 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6360 ret = si_construct_voltage_tables(rdev); 6361 if (ret) { 6362 DRM_ERROR("si_construct_voltage_tables failed\n"); 6363 return ret; 6364 } 6365 } 6366 if (eg_pi->dynamic_ac_timing) { 6367 ret = si_initialize_mc_reg_table(rdev); 6368 if (ret) 6369 eg_pi->dynamic_ac_timing = false; 6370 } 6371 if (pi->dynamic_ss) 6372 si_enable_spread_spectrum(rdev, true); 6373 if (pi->thermal_protection) 6374 si_enable_thermal_protection(rdev, true); 6375 si_setup_bsp(rdev); 6376 si_program_git(rdev); 6377 si_program_tp(rdev); 6378 si_program_tpp(rdev); 6379 si_program_sstp(rdev); 6380 si_enable_display_gap(rdev); 6381 si_program_vc(rdev); 6382 ret = si_upload_firmware(rdev); 6383 if (ret) { 6384 DRM_ERROR("si_upload_firmware failed\n"); 6385 return ret; 6386 } 6387 ret = si_process_firmware_header(rdev); 6388 if (ret) { 6389 DRM_ERROR("si_process_firmware_header failed\n"); 6390 return ret; 6391 } 6392 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6393 if (ret) { 6394 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6395 return ret; 6396 } 6397 ret = si_init_smc_table(rdev); 6398 if (ret) { 6399 DRM_ERROR("si_init_smc_table failed\n"); 6400 return ret; 6401 } 6402 ret = si_init_smc_spll_table(rdev); 6403 if (ret) { 6404 DRM_ERROR("si_init_smc_spll_table failed\n"); 6405 return ret; 6406 } 6407 ret = si_init_arb_table_index(rdev); 6408 if (ret) { 6409 DRM_ERROR("si_init_arb_table_index failed\n"); 6410 return ret; 6411 } 6412 if (eg_pi->dynamic_ac_timing) { 6413 ret = si_populate_mc_reg_table(rdev, boot_ps); 6414 if (ret) { 6415 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6416 return ret; 6417 } 6418 } 6419 ret = si_initialize_smc_cac_tables(rdev); 6420 if (ret) { 6421 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6422 return ret; 6423 } 6424 ret = si_initialize_hardware_cac_manager(rdev); 6425 if (ret) { 6426 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6427 return ret; 6428 } 6429 ret = si_initialize_smc_dte_tables(rdev); 6430 if (ret) { 6431 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6432 return ret; 6433 } 6434 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6435 if (ret) { 6436 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6437 return ret; 6438 } 6439 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6440 if (ret) { 6441 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6442 return ret; 6443 } 6444 si_program_response_times(rdev); 6445 si_program_ds_registers(rdev); 6446 si_dpm_start_smc(rdev); 6447 ret = si_notify_smc_display_change(rdev, false); 6448 if (ret) { 6449 DRM_ERROR("si_notify_smc_display_change failed\n"); 6450 return ret; 6451 } 6452 si_enable_sclk_control(rdev, true); 6453 si_start_dpm(rdev); 6454 6455 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6456 6457 si_thermal_start_thermal_controller(rdev); 6458 6459 ni_update_current_ps(rdev, boot_ps); 6460 6461 return 0; 6462 } 6463 6464 static int si_set_temperature_range(struct radeon_device *rdev) 6465 { 6466 int ret; 6467 6468 ret = si_thermal_enable_alert(rdev, false); 6469 if (ret) 6470 return ret; 6471 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6472 if (ret) 6473 return ret; 6474 ret = si_thermal_enable_alert(rdev, true); 6475 if (ret) 6476 return ret; 6477 6478 return ret; 6479 } 6480 6481 int si_dpm_late_enable(struct radeon_device *rdev) 6482 { 6483 int ret; 6484 6485 ret = si_set_temperature_range(rdev); 6486 if (ret) 6487 return ret; 6488 6489 return ret; 6490 } 6491 6492 void si_dpm_disable(struct radeon_device *rdev) 6493 { 6494 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6495 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6496 6497 if (!si_is_smc_running(rdev)) 6498 return; 6499 si_thermal_stop_thermal_controller(rdev); 6500 si_disable_ulv(rdev); 6501 si_clear_vc(rdev); 6502 if (pi->thermal_protection) 6503 si_enable_thermal_protection(rdev, false); 6504 si_enable_power_containment(rdev, boot_ps, false); 6505 si_enable_smc_cac(rdev, boot_ps, false); 6506 si_enable_spread_spectrum(rdev, false); 6507 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6508 si_stop_dpm(rdev); 6509 si_reset_to_default(rdev); 6510 si_dpm_stop_smc(rdev); 6511 si_force_switch_to_arb_f0(rdev); 6512 6513 ni_update_current_ps(rdev, boot_ps); 6514 } 6515 6516 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6517 { 6518 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6519 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6520 struct radeon_ps *new_ps = &requested_ps; 6521 6522 ni_update_requested_ps(rdev, new_ps); 6523 6524 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6525 6526 return 0; 6527 } 6528 6529 static int si_power_control_set_level(struct radeon_device *rdev) 6530 { 6531 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6532 int ret; 6533 6534 ret = si_restrict_performance_levels_before_switch(rdev); 6535 if (ret) 6536 return ret; 6537 ret = si_halt_smc(rdev); 6538 if (ret) 6539 return ret; 6540 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6541 if (ret) 6542 return ret; 6543 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6544 if (ret) 6545 return ret; 6546 ret = si_resume_smc(rdev); 6547 if (ret) 6548 return ret; 6549 ret = si_set_sw_state(rdev); 6550 if (ret) 6551 return ret; 6552 return 0; 6553 } 6554 6555 int si_dpm_set_power_state(struct radeon_device *rdev) 6556 { 6557 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6558 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6559 struct radeon_ps *old_ps = &eg_pi->current_rps; 6560 int ret; 6561 6562 ret = si_disable_ulv(rdev); 6563 if (ret) { 6564 DRM_ERROR("si_disable_ulv failed\n"); 6565 return ret; 6566 } 6567 ret = si_restrict_performance_levels_before_switch(rdev); 6568 if (ret) { 6569 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6570 return ret; 6571 } 6572 if (eg_pi->pcie_performance_request) 6573 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6574 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6575 ret = si_enable_power_containment(rdev, new_ps, false); 6576 if (ret) { 6577 DRM_ERROR("si_enable_power_containment failed\n"); 6578 return ret; 6579 } 6580 ret = si_enable_smc_cac(rdev, new_ps, false); 6581 if (ret) { 6582 DRM_ERROR("si_enable_smc_cac failed\n"); 6583 return ret; 6584 } 6585 ret = si_halt_smc(rdev); 6586 if (ret) { 6587 DRM_ERROR("si_halt_smc failed\n"); 6588 return ret; 6589 } 6590 ret = si_upload_sw_state(rdev, new_ps); 6591 if (ret) { 6592 DRM_ERROR("si_upload_sw_state failed\n"); 6593 return ret; 6594 } 6595 ret = si_upload_smc_data(rdev); 6596 if (ret) { 6597 DRM_ERROR("si_upload_smc_data failed\n"); 6598 return ret; 6599 } 6600 ret = si_upload_ulv_state(rdev); 6601 if (ret) { 6602 DRM_ERROR("si_upload_ulv_state failed\n"); 6603 return ret; 6604 } 6605 if (eg_pi->dynamic_ac_timing) { 6606 ret = si_upload_mc_reg_table(rdev, new_ps); 6607 if (ret) { 6608 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6609 return ret; 6610 } 6611 } 6612 ret = si_program_memory_timing_parameters(rdev, new_ps); 6613 if (ret) { 6614 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6615 return ret; 6616 } 6617 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6618 6619 ret = si_resume_smc(rdev); 6620 if (ret) { 6621 DRM_ERROR("si_resume_smc failed\n"); 6622 return ret; 6623 } 6624 ret = si_set_sw_state(rdev); 6625 if (ret) { 6626 DRM_ERROR("si_set_sw_state failed\n"); 6627 return ret; 6628 } 6629 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6630 si_set_vce_clock(rdev, new_ps, old_ps); 6631 if (eg_pi->pcie_performance_request) 6632 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6633 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6634 if (ret) { 6635 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6636 return ret; 6637 } 6638 ret = si_enable_smc_cac(rdev, new_ps, true); 6639 if (ret) { 6640 DRM_ERROR("si_enable_smc_cac failed\n"); 6641 return ret; 6642 } 6643 ret = si_enable_power_containment(rdev, new_ps, true); 6644 if (ret) { 6645 DRM_ERROR("si_enable_power_containment failed\n"); 6646 return ret; 6647 } 6648 6649 ret = si_power_control_set_level(rdev); 6650 if (ret) { 6651 DRM_ERROR("si_power_control_set_level failed\n"); 6652 return ret; 6653 } 6654 6655 return 0; 6656 } 6657 6658 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6659 { 6660 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6661 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6662 6663 ni_update_current_ps(rdev, new_ps); 6664 } 6665 6666 #if 0 6667 void si_dpm_reset_asic(struct radeon_device *rdev) 6668 { 6669 si_restrict_performance_levels_before_switch(rdev); 6670 si_disable_ulv(rdev); 6671 si_set_boot_state(rdev); 6672 } 6673 #endif 6674 6675 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6676 { 6677 si_program_display_gap(rdev); 6678 } 6679 6680 union power_info { 6681 struct _ATOM_POWERPLAY_INFO info; 6682 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6683 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6684 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6685 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6686 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6687 }; 6688 6689 union pplib_clock_info { 6690 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6691 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6692 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6693 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6694 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6695 }; 6696 6697 union pplib_power_state { 6698 struct _ATOM_PPLIB_STATE v1; 6699 struct _ATOM_PPLIB_STATE_V2 v2; 6700 }; 6701 6702 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6703 struct radeon_ps *rps, 6704 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6705 u8 table_rev) 6706 { 6707 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6708 rps->class = le16_to_cpu(non_clock_info->usClassification); 6709 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6710 6711 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6712 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6713 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6714 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6715 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6716 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6717 } else { 6718 rps->vclk = 0; 6719 rps->dclk = 0; 6720 } 6721 6722 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6723 rdev->pm.dpm.boot_ps = rps; 6724 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6725 rdev->pm.dpm.uvd_ps = rps; 6726 } 6727 6728 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6729 struct radeon_ps *rps, int index, 6730 union pplib_clock_info *clock_info) 6731 { 6732 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6733 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6734 struct si_power_info *si_pi = si_get_pi(rdev); 6735 struct ni_ps *ps = ni_get_ps(rps); 6736 u16 leakage_voltage; 6737 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6738 int ret; 6739 6740 ps->performance_level_count = index + 1; 6741 6742 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6743 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6744 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6745 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6746 6747 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6748 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6749 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6750 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6751 si_pi->sys_pcie_mask, 6752 si_pi->boot_pcie_gen, 6753 clock_info->si.ucPCIEGen); 6754 6755 /* patch up vddc if necessary */ 6756 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6757 &leakage_voltage); 6758 if (ret == 0) 6759 pl->vddc = leakage_voltage; 6760 6761 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6762 pi->acpi_vddc = pl->vddc; 6763 eg_pi->acpi_vddci = pl->vddci; 6764 si_pi->acpi_pcie_gen = pl->pcie_gen; 6765 } 6766 6767 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6768 index == 0) { 6769 /* XXX disable for A0 tahiti */ 6770 si_pi->ulv.supported = false; 6771 si_pi->ulv.pl = *pl; 6772 si_pi->ulv.one_pcie_lane_in_ulv = false; 6773 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6774 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6775 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6776 } 6777 6778 if (pi->min_vddc_in_table > pl->vddc) 6779 pi->min_vddc_in_table = pl->vddc; 6780 6781 if (pi->max_vddc_in_table < pl->vddc) 6782 pi->max_vddc_in_table = pl->vddc; 6783 6784 /* patch up boot state */ 6785 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6786 u16 vddc, vddci, mvdd; 6787 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6788 pl->mclk = rdev->clock.default_mclk; 6789 pl->sclk = rdev->clock.default_sclk; 6790 pl->vddc = vddc; 6791 pl->vddci = vddci; 6792 si_pi->mvdd_bootup_value = mvdd; 6793 } 6794 6795 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6796 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6797 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6798 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6799 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6800 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6801 } 6802 } 6803 6804 static int si_parse_power_table(struct radeon_device *rdev) 6805 { 6806 struct radeon_mode_info *mode_info = &rdev->mode_info; 6807 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6808 union pplib_power_state *power_state; 6809 int i, j, k, non_clock_array_index, clock_array_index; 6810 union pplib_clock_info *clock_info; 6811 struct _StateArray *state_array; 6812 struct _ClockInfoArray *clock_info_array; 6813 struct _NonClockInfoArray *non_clock_info_array; 6814 union power_info *power_info; 6815 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6816 u16 data_offset; 6817 u8 frev, crev; 6818 u8 *power_state_offset; 6819 struct ni_ps *ps; 6820 6821 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6822 &frev, &crev, &data_offset)) 6823 return -EINVAL; 6824 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6825 6826 state_array = (struct _StateArray *) 6827 (mode_info->atom_context->bios + data_offset + 6828 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6829 clock_info_array = (struct _ClockInfoArray *) 6830 (mode_info->atom_context->bios + data_offset + 6831 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6832 non_clock_info_array = (struct _NonClockInfoArray *) 6833 (mode_info->atom_context->bios + data_offset + 6834 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6835 6836 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6837 state_array->ucNumEntries, GFP_KERNEL); 6838 if (!rdev->pm.dpm.ps) 6839 return -ENOMEM; 6840 power_state_offset = (u8 *)state_array->states; 6841 for (i = 0; i < state_array->ucNumEntries; i++) { 6842 u8 *idx; 6843 power_state = (union pplib_power_state *)power_state_offset; 6844 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6845 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6846 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6847 if (!rdev->pm.power_state[i].clock_info) 6848 return -EINVAL; 6849 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6850 if (ps == NULL) { 6851 kfree(rdev->pm.dpm.ps); 6852 return -ENOMEM; 6853 } 6854 rdev->pm.dpm.ps[i].ps_priv = ps; 6855 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6856 non_clock_info, 6857 non_clock_info_array->ucEntrySize); 6858 k = 0; 6859 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6860 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6861 clock_array_index = idx[j]; 6862 if (clock_array_index >= clock_info_array->ucNumEntries) 6863 continue; 6864 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6865 break; 6866 clock_info = (union pplib_clock_info *) 6867 ((u8 *)&clock_info_array->clockInfo[0] + 6868 (clock_array_index * clock_info_array->ucEntrySize)); 6869 si_parse_pplib_clock_info(rdev, 6870 &rdev->pm.dpm.ps[i], k, 6871 clock_info); 6872 k++; 6873 } 6874 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6875 } 6876 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6877 6878 /* fill in the vce power states */ 6879 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6880 u32 sclk, mclk; 6881 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6882 clock_info = (union pplib_clock_info *) 6883 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6884 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6885 sclk |= clock_info->si.ucEngineClockHigh << 16; 6886 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6887 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6888 rdev->pm.dpm.vce_states[i].sclk = sclk; 6889 rdev->pm.dpm.vce_states[i].mclk = mclk; 6890 } 6891 6892 return 0; 6893 } 6894 6895 int si_dpm_init(struct radeon_device *rdev) 6896 { 6897 struct rv7xx_power_info *pi; 6898 struct evergreen_power_info *eg_pi; 6899 struct ni_power_info *ni_pi; 6900 struct si_power_info *si_pi; 6901 struct atom_clock_dividers dividers; 6902 int ret; 6903 u32 mask; 6904 6905 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6906 if (si_pi == NULL) 6907 return -ENOMEM; 6908 rdev->pm.dpm.priv = si_pi; 6909 ni_pi = &si_pi->ni; 6910 eg_pi = &ni_pi->eg; 6911 pi = &eg_pi->rv7xx; 6912 6913 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6914 if (ret) 6915 si_pi->sys_pcie_mask = 0; 6916 else 6917 si_pi->sys_pcie_mask = mask; 6918 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6919 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6920 6921 si_set_max_cu_value(rdev); 6922 6923 rv770_get_max_vddc(rdev); 6924 si_get_leakage_vddc(rdev); 6925 si_patch_dependency_tables_based_on_leakage(rdev); 6926 6927 pi->acpi_vddc = 0; 6928 eg_pi->acpi_vddci = 0; 6929 pi->min_vddc_in_table = 0; 6930 pi->max_vddc_in_table = 0; 6931 6932 ret = r600_get_platform_caps(rdev); 6933 if (ret) 6934 return ret; 6935 6936 ret = r600_parse_extended_power_table(rdev); 6937 if (ret) 6938 return ret; 6939 6940 ret = si_parse_power_table(rdev); 6941 if (ret) 6942 return ret; 6943 6944 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6945 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6946 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6947 r600_free_extended_power_table(rdev); 6948 return -ENOMEM; 6949 } 6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6953 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6954 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6955 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6956 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6957 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6958 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6959 6960 if (rdev->pm.dpm.voltage_response_time == 0) 6961 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6962 if (rdev->pm.dpm.backbias_response_time == 0) 6963 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6964 6965 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6966 0, false, ÷rs); 6967 if (ret) 6968 pi->ref_div = dividers.ref_div + 1; 6969 else 6970 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6971 6972 eg_pi->smu_uvd_hs = false; 6973 6974 pi->mclk_strobe_mode_threshold = 40000; 6975 if (si_is_special_1gb_platform(rdev)) 6976 pi->mclk_stutter_mode_threshold = 0; 6977 else 6978 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6979 pi->mclk_edc_enable_threshold = 40000; 6980 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6981 6982 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6983 6984 pi->voltage_control = 6985 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6986 VOLTAGE_OBJ_GPIO_LUT); 6987 if (!pi->voltage_control) { 6988 si_pi->voltage_control_svi2 = 6989 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6990 VOLTAGE_OBJ_SVID2); 6991 if (si_pi->voltage_control_svi2) 6992 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6993 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6994 } 6995 6996 pi->mvdd_control = 6997 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6998 VOLTAGE_OBJ_GPIO_LUT); 6999 7000 eg_pi->vddci_control = 7001 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7002 VOLTAGE_OBJ_GPIO_LUT); 7003 if (!eg_pi->vddci_control) 7004 si_pi->vddci_control_svi2 = 7005 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7006 VOLTAGE_OBJ_SVID2); 7007 7008 si_pi->vddc_phase_shed_control = 7009 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7010 VOLTAGE_OBJ_PHASE_LUT); 7011 7012 rv770_get_engine_memory_ss(rdev); 7013 7014 pi->asi = RV770_ASI_DFLT; 7015 pi->pasi = CYPRESS_HASI_DFLT; 7016 pi->vrc = SISLANDS_VRC_DFLT; 7017 7018 pi->gfx_clock_gating = true; 7019 7020 eg_pi->sclk_deep_sleep = true; 7021 si_pi->sclk_deep_sleep_above_low = false; 7022 7023 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7024 pi->thermal_protection = true; 7025 else 7026 pi->thermal_protection = false; 7027 7028 eg_pi->dynamic_ac_timing = true; 7029 7030 eg_pi->light_sleep = true; 7031 #if defined(CONFIG_ACPI) 7032 eg_pi->pcie_performance_request = 7033 radeon_acpi_is_pcie_performance_request_supported(rdev); 7034 #else 7035 eg_pi->pcie_performance_request = false; 7036 #endif 7037 7038 si_pi->sram_end = SMC_RAM_END; 7039 7040 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7041 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7042 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7043 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7044 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7045 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7046 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7047 7048 si_initialize_powertune_defaults(rdev); 7049 7050 /* make sure dc limits are valid */ 7051 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7052 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7053 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7054 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7055 7056 si_pi->fan_ctrl_is_in_default_mode = true; 7057 7058 return 0; 7059 } 7060 7061 void si_dpm_fini(struct radeon_device *rdev) 7062 { 7063 int i; 7064 7065 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7066 kfree(rdev->pm.dpm.ps[i].ps_priv); 7067 } 7068 kfree(rdev->pm.dpm.ps); 7069 kfree(rdev->pm.dpm.priv); 7070 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7071 r600_free_extended_power_table(rdev); 7072 } 7073 7074 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7075 struct seq_file *m) 7076 { 7077 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7078 struct radeon_ps *rps = &eg_pi->current_rps; 7079 struct ni_ps *ps = ni_get_ps(rps); 7080 struct rv7xx_pl *pl; 7081 u32 current_index = 7082 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7083 CURRENT_STATE_INDEX_SHIFT; 7084 7085 if (current_index >= ps->performance_level_count) { 7086 seq_printf(m, "invalid dpm profile %d\n", current_index); 7087 } else { 7088 pl = &ps->performance_levels[current_index]; 7089 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7090 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7091 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7092 } 7093 } 7094 7095 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7096 { 7097 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7098 struct radeon_ps *rps = &eg_pi->current_rps; 7099 struct ni_ps *ps = ni_get_ps(rps); 7100 struct rv7xx_pl *pl; 7101 u32 current_index = 7102 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7103 CURRENT_STATE_INDEX_SHIFT; 7104 7105 if (current_index >= ps->performance_level_count) { 7106 return 0; 7107 } else { 7108 pl = &ps->performance_levels[current_index]; 7109 return pl->sclk; 7110 } 7111 } 7112 7113 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7114 { 7115 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7116 struct radeon_ps *rps = &eg_pi->current_rps; 7117 struct ni_ps *ps = ni_get_ps(rps); 7118 struct rv7xx_pl *pl; 7119 u32 current_index = 7120 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7121 CURRENT_STATE_INDEX_SHIFT; 7122 7123 if (current_index >= ps->performance_level_count) { 7124 return 0; 7125 } else { 7126 pl = &ps->performance_levels[current_index]; 7127 return pl->mclk; 7128 } 7129 } 7130