1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 #if 0 /* unused */ 255 static const struct si_dte_data dte_data_tahiti_le = 256 { 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271 }; 272 #endif 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1745 1746 static int si_populate_voltage_value(struct radeon_device *rdev, 1747 const struct atom_voltage_table *table, 1748 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1749 static int si_get_std_voltage_value(struct radeon_device *rdev, 1750 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1751 u16 *std_voltage); 1752 static int si_write_smc_soft_register(struct radeon_device *rdev, 1753 u16 reg_offset, u32 value); 1754 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1755 struct rv7xx_pl *pl, 1756 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1757 static int si_calculate_sclk_params(struct radeon_device *rdev, 1758 u32 engine_clock, 1759 SISLANDS_SMC_SCLK_VALUE *sclk); 1760 1761 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1762 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1763 1764 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1765 { 1766 struct si_power_info *pi = rdev->pm.dpm.priv; 1767 1768 return pi; 1769 } 1770 1771 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1772 u16 v, s32 t, u32 ileakage, u32 *leakage) 1773 { 1774 s64 kt, kv, leakage_w, i_leakage, vddc; 1775 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1776 s64 tmp; 1777 1778 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1779 vddc = div64_s64(drm_int2fixp(v), 1000); 1780 temperature = div64_s64(drm_int2fixp(t), 1000); 1781 1782 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1783 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1784 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1785 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1786 t_ref = drm_int2fixp(coeff->t_ref); 1787 1788 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1789 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1790 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1791 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1792 1793 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1794 1795 *leakage = drm_fixp2int(leakage_w * 1000); 1796 } 1797 1798 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1799 const struct ni_leakage_coeffients *coeff, 1800 u16 v, 1801 s32 t, 1802 u32 i_leakage, 1803 u32 *leakage) 1804 { 1805 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1806 } 1807 1808 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1809 const u32 fixed_kt, u16 v, 1810 u32 ileakage, u32 *leakage) 1811 { 1812 s64 kt, kv, leakage_w, i_leakage, vddc; 1813 1814 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1815 vddc = div64_s64(drm_int2fixp(v), 1000); 1816 1817 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1818 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1819 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1820 1821 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1822 1823 *leakage = drm_fixp2int(leakage_w * 1000); 1824 } 1825 1826 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1827 const struct ni_leakage_coeffients *coeff, 1828 const u32 fixed_kt, 1829 u16 v, 1830 u32 i_leakage, 1831 u32 *leakage) 1832 { 1833 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1834 } 1835 1836 1837 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1838 struct si_dte_data *dte_data) 1839 { 1840 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1841 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1842 u32 k = dte_data->k; 1843 u32 t_max = dte_data->max_t; 1844 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1845 u32 t_0 = dte_data->t0; 1846 u32 i; 1847 1848 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1849 dte_data->tdep_count = 3; 1850 1851 for (i = 0; i < k; i++) { 1852 dte_data->r[i] = 1853 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1854 (p_limit2 * (u32)100); 1855 } 1856 1857 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1858 1859 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1860 dte_data->tdep_r[i] = dte_data->r[4]; 1861 } 1862 } else { 1863 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1864 } 1865 } 1866 1867 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1868 { 1869 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1870 struct si_power_info *si_pi = si_get_pi(rdev); 1871 bool update_dte_from_pl2 = false; 1872 1873 if (rdev->family == CHIP_TAHITI) { 1874 si_pi->cac_weights = cac_weights_tahiti; 1875 si_pi->lcac_config = lcac_tahiti; 1876 si_pi->cac_override = cac_override_tahiti; 1877 si_pi->powertune_data = &powertune_data_tahiti; 1878 si_pi->dte_data = dte_data_tahiti; 1879 1880 switch (rdev->pdev->device) { 1881 case 0x6798: 1882 si_pi->dte_data.enable_dte_by_default = true; 1883 break; 1884 case 0x6799: 1885 si_pi->dte_data = dte_data_new_zealand; 1886 break; 1887 case 0x6790: 1888 case 0x6791: 1889 case 0x6792: 1890 case 0x679E: 1891 si_pi->dte_data = dte_data_aruba_pro; 1892 update_dte_from_pl2 = true; 1893 break; 1894 case 0x679B: 1895 si_pi->dte_data = dte_data_malta; 1896 update_dte_from_pl2 = true; 1897 break; 1898 case 0x679A: 1899 si_pi->dte_data = dte_data_tahiti_pro; 1900 update_dte_from_pl2 = true; 1901 break; 1902 default: 1903 if (si_pi->dte_data.enable_dte_by_default == true) 1904 DRM_ERROR("DTE is not enabled!\n"); 1905 break; 1906 } 1907 } else if (rdev->family == CHIP_PITCAIRN) { 1908 switch (rdev->pdev->device) { 1909 case 0x6810: 1910 case 0x6818: 1911 si_pi->cac_weights = cac_weights_pitcairn; 1912 si_pi->lcac_config = lcac_pitcairn; 1913 si_pi->cac_override = cac_override_pitcairn; 1914 si_pi->powertune_data = &powertune_data_pitcairn; 1915 si_pi->dte_data = dte_data_curacao_xt; 1916 update_dte_from_pl2 = true; 1917 break; 1918 case 0x6819: 1919 case 0x6811: 1920 si_pi->cac_weights = cac_weights_pitcairn; 1921 si_pi->lcac_config = lcac_pitcairn; 1922 si_pi->cac_override = cac_override_pitcairn; 1923 si_pi->powertune_data = &powertune_data_pitcairn; 1924 si_pi->dte_data = dte_data_curacao_pro; 1925 update_dte_from_pl2 = true; 1926 break; 1927 case 0x6800: 1928 case 0x6806: 1929 si_pi->cac_weights = cac_weights_pitcairn; 1930 si_pi->lcac_config = lcac_pitcairn; 1931 si_pi->cac_override = cac_override_pitcairn; 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1933 si_pi->dte_data = dte_data_neptune_xt; 1934 update_dte_from_pl2 = true; 1935 break; 1936 default: 1937 si_pi->cac_weights = cac_weights_pitcairn; 1938 si_pi->lcac_config = lcac_pitcairn; 1939 si_pi->cac_override = cac_override_pitcairn; 1940 si_pi->powertune_data = &powertune_data_pitcairn; 1941 si_pi->dte_data = dte_data_pitcairn; 1942 break; 1943 } 1944 } else if (rdev->family == CHIP_VERDE) { 1945 si_pi->lcac_config = lcac_cape_verde; 1946 si_pi->cac_override = cac_override_cape_verde; 1947 si_pi->powertune_data = &powertune_data_cape_verde; 1948 1949 switch (rdev->pdev->device) { 1950 case 0x683B: 1951 case 0x683F: 1952 case 0x6829: 1953 case 0x6835: 1954 si_pi->cac_weights = cac_weights_cape_verde_pro; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x682C: 1958 si_pi->cac_weights = cac_weights_cape_verde_pro; 1959 si_pi->dte_data = dte_data_sun_xt; 1960 break; 1961 case 0x6825: 1962 case 0x6827: 1963 si_pi->cac_weights = cac_weights_heathrow; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x6824: 1967 case 0x682D: 1968 si_pi->cac_weights = cac_weights_chelsea_xt; 1969 si_pi->dte_data = dte_data_cape_verde; 1970 break; 1971 case 0x682F: 1972 si_pi->cac_weights = cac_weights_chelsea_pro; 1973 si_pi->dte_data = dte_data_cape_verde; 1974 break; 1975 case 0x6820: 1976 si_pi->cac_weights = cac_weights_heathrow; 1977 si_pi->dte_data = dte_data_venus_xtx; 1978 break; 1979 case 0x6821: 1980 si_pi->cac_weights = cac_weights_heathrow; 1981 si_pi->dte_data = dte_data_venus_xt; 1982 break; 1983 case 0x6823: 1984 case 0x682B: 1985 case 0x6822: 1986 case 0x682A: 1987 si_pi->cac_weights = cac_weights_chelsea_pro; 1988 si_pi->dte_data = dte_data_venus_pro; 1989 break; 1990 default: 1991 si_pi->cac_weights = cac_weights_cape_verde; 1992 si_pi->dte_data = dte_data_cape_verde; 1993 break; 1994 } 1995 } else if (rdev->family == CHIP_OLAND) { 1996 switch (rdev->pdev->device) { 1997 case 0x6601: 1998 case 0x6621: 1999 case 0x6603: 2000 case 0x6605: 2001 si_pi->cac_weights = cac_weights_mars_pro; 2002 si_pi->lcac_config = lcac_mars_pro; 2003 si_pi->cac_override = cac_override_oland; 2004 si_pi->powertune_data = &powertune_data_mars_pro; 2005 si_pi->dte_data = dte_data_mars_pro; 2006 update_dte_from_pl2 = true; 2007 break; 2008 case 0x6600: 2009 case 0x6606: 2010 case 0x6620: 2011 case 0x6604: 2012 si_pi->cac_weights = cac_weights_mars_xt; 2013 si_pi->lcac_config = lcac_mars_pro; 2014 si_pi->cac_override = cac_override_oland; 2015 si_pi->powertune_data = &powertune_data_mars_pro; 2016 si_pi->dte_data = dte_data_mars_pro; 2017 update_dte_from_pl2 = true; 2018 break; 2019 case 0x6611: 2020 case 0x6613: 2021 case 0x6608: 2022 si_pi->cac_weights = cac_weights_oland_pro; 2023 si_pi->lcac_config = lcac_mars_pro; 2024 si_pi->cac_override = cac_override_oland; 2025 si_pi->powertune_data = &powertune_data_mars_pro; 2026 si_pi->dte_data = dte_data_mars_pro; 2027 update_dte_from_pl2 = true; 2028 break; 2029 case 0x6610: 2030 si_pi->cac_weights = cac_weights_oland_xt; 2031 si_pi->lcac_config = lcac_mars_pro; 2032 si_pi->cac_override = cac_override_oland; 2033 si_pi->powertune_data = &powertune_data_mars_pro; 2034 si_pi->dte_data = dte_data_mars_pro; 2035 update_dte_from_pl2 = true; 2036 break; 2037 default: 2038 si_pi->cac_weights = cac_weights_oland; 2039 si_pi->lcac_config = lcac_oland; 2040 si_pi->cac_override = cac_override_oland; 2041 si_pi->powertune_data = &powertune_data_oland; 2042 si_pi->dte_data = dte_data_oland; 2043 break; 2044 } 2045 } else if (rdev->family == CHIP_HAINAN) { 2046 si_pi->cac_weights = cac_weights_hainan; 2047 si_pi->lcac_config = lcac_oland; 2048 si_pi->cac_override = cac_override_oland; 2049 si_pi->powertune_data = &powertune_data_hainan; 2050 si_pi->dte_data = dte_data_sun_xt; 2051 update_dte_from_pl2 = true; 2052 } else { 2053 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2054 return; 2055 } 2056 2057 ni_pi->enable_power_containment = false; 2058 ni_pi->enable_cac = false; 2059 ni_pi->enable_sq_ramping = false; 2060 si_pi->enable_dte = false; 2061 2062 if (si_pi->powertune_data->enable_powertune_by_default) { 2063 ni_pi->enable_power_containment= true; 2064 ni_pi->enable_cac = true; 2065 if (si_pi->dte_data.enable_dte_by_default) { 2066 si_pi->enable_dte = true; 2067 if (update_dte_from_pl2) 2068 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2069 2070 } 2071 ni_pi->enable_sq_ramping = true; 2072 } 2073 2074 ni_pi->driver_calculate_cac_leakage = true; 2075 ni_pi->cac_configuration_required = true; 2076 2077 if (ni_pi->cac_configuration_required) { 2078 ni_pi->support_cac_long_term_average = true; 2079 si_pi->dyn_powertune_data.l2_lta_window_size = 2080 si_pi->powertune_data->l2_lta_window_size_default; 2081 si_pi->dyn_powertune_data.lts_truncate = 2082 si_pi->powertune_data->lts_truncate_default; 2083 } else { 2084 ni_pi->support_cac_long_term_average = false; 2085 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2086 si_pi->dyn_powertune_data.lts_truncate = 0; 2087 } 2088 2089 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2090 } 2091 2092 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2093 { 2094 return 1; 2095 } 2096 2097 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2098 { 2099 u32 xclk; 2100 u32 wintime; 2101 u32 cac_window; 2102 u32 cac_window_size; 2103 2104 xclk = radeon_get_xclk(rdev); 2105 2106 if (xclk == 0) 2107 return 0; 2108 2109 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2110 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2111 2112 wintime = (cac_window_size * 100) / xclk; 2113 2114 return wintime; 2115 } 2116 2117 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2118 { 2119 return power_in_watts; 2120 } 2121 2122 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2123 bool adjust_polarity, 2124 u32 tdp_adjustment, 2125 u32 *tdp_limit, 2126 u32 *near_tdp_limit) 2127 { 2128 u32 adjustment_delta, max_tdp_limit; 2129 2130 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2131 return -EINVAL; 2132 2133 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2134 2135 if (adjust_polarity) { 2136 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2138 } else { 2139 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2140 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2141 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2142 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2143 else 2144 *near_tdp_limit = 0; 2145 } 2146 2147 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2148 return -EINVAL; 2149 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2150 return -EINVAL; 2151 2152 return 0; 2153 } 2154 2155 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2156 struct radeon_ps *radeon_state) 2157 { 2158 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2159 struct si_power_info *si_pi = si_get_pi(rdev); 2160 2161 if (ni_pi->enable_power_containment) { 2162 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2163 PP_SIslands_PAPMParameters *papm_parm; 2164 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2165 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2166 u32 tdp_limit; 2167 u32 near_tdp_limit; 2168 int ret; 2169 2170 if (scaling_factor == 0) 2171 return -EINVAL; 2172 2173 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2174 2175 ret = si_calculate_adjusted_tdp_limits(rdev, 2176 false, /* ??? */ 2177 rdev->pm.dpm.tdp_adjustment, 2178 &tdp_limit, 2179 &near_tdp_limit); 2180 if (ret) 2181 return ret; 2182 2183 smc_table->dpm2Params.TDPLimit = 2184 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2185 smc_table->dpm2Params.NearTDPLimit = 2186 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2187 smc_table->dpm2Params.SafePowerLimit = 2188 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2189 2190 ret = si_copy_bytes_to_smc(rdev, 2191 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2192 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2193 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2194 sizeof(u32) * 3, 2195 si_pi->sram_end); 2196 if (ret) 2197 return ret; 2198 2199 if (si_pi->enable_ppm) { 2200 papm_parm = &si_pi->papm_parm; 2201 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2202 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2203 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2204 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2205 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2206 papm_parm->PlatformPowerLimit = 0xffffffff; 2207 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2208 2209 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2210 (u8 *)papm_parm, 2211 sizeof(PP_SIslands_PAPMParameters), 2212 si_pi->sram_end); 2213 if (ret) 2214 return ret; 2215 } 2216 } 2217 return 0; 2218 } 2219 2220 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2221 struct radeon_ps *radeon_state) 2222 { 2223 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2224 struct si_power_info *si_pi = si_get_pi(rdev); 2225 2226 if (ni_pi->enable_power_containment) { 2227 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2228 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2229 int ret; 2230 2231 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2232 2233 smc_table->dpm2Params.NearTDPLimit = 2234 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2235 smc_table->dpm2Params.SafePowerLimit = 2236 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2237 2238 ret = si_copy_bytes_to_smc(rdev, 2239 (si_pi->state_table_start + 2240 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2241 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2242 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2243 sizeof(u32) * 2, 2244 si_pi->sram_end); 2245 if (ret) 2246 return ret; 2247 } 2248 2249 return 0; 2250 } 2251 2252 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2253 const u16 prev_std_vddc, 2254 const u16 curr_std_vddc) 2255 { 2256 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2257 u64 prev_vddc = (u64)prev_std_vddc; 2258 u64 curr_vddc = (u64)curr_std_vddc; 2259 u64 pwr_efficiency_ratio, n, d; 2260 2261 if ((prev_vddc == 0) || (curr_vddc == 0)) 2262 return 0; 2263 2264 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2265 d = prev_vddc * prev_vddc; 2266 pwr_efficiency_ratio = div64_u64(n, d); 2267 2268 if (pwr_efficiency_ratio > (u64)0xFFFF) 2269 return 0; 2270 2271 return (u16)pwr_efficiency_ratio; 2272 } 2273 2274 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2275 struct radeon_ps *radeon_state) 2276 { 2277 struct si_power_info *si_pi = si_get_pi(rdev); 2278 2279 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2280 radeon_state->vclk && radeon_state->dclk) 2281 return true; 2282 2283 return false; 2284 } 2285 2286 static int si_populate_power_containment_values(struct radeon_device *rdev, 2287 struct radeon_ps *radeon_state, 2288 SISLANDS_SMC_SWSTATE *smc_state) 2289 { 2290 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2291 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2292 struct ni_ps *state = ni_get_ps(radeon_state); 2293 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2294 u32 prev_sclk; 2295 u32 max_sclk; 2296 u32 min_sclk; 2297 u16 prev_std_vddc; 2298 u16 curr_std_vddc; 2299 int i; 2300 u16 pwr_efficiency_ratio; 2301 u8 max_ps_percent; 2302 bool disable_uvd_power_tune; 2303 int ret; 2304 2305 if (ni_pi->enable_power_containment == false) 2306 return 0; 2307 2308 if (state->performance_level_count == 0) 2309 return -EINVAL; 2310 2311 if (smc_state->levelCount != state->performance_level_count) 2312 return -EINVAL; 2313 2314 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2315 2316 smc_state->levels[0].dpm2.MaxPS = 0; 2317 smc_state->levels[0].dpm2.NearTDPDec = 0; 2318 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2319 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2320 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2321 2322 for (i = 1; i < state->performance_level_count; i++) { 2323 prev_sclk = state->performance_levels[i-1].sclk; 2324 max_sclk = state->performance_levels[i].sclk; 2325 if (i == 1) 2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2327 else 2328 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2329 2330 if (prev_sclk > max_sclk) 2331 return -EINVAL; 2332 2333 if ((max_ps_percent == 0) || 2334 (prev_sclk == max_sclk) || 2335 disable_uvd_power_tune) { 2336 min_sclk = max_sclk; 2337 } else if (i == 1) { 2338 min_sclk = prev_sclk; 2339 } else { 2340 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2341 } 2342 2343 if (min_sclk < state->performance_levels[0].sclk) 2344 min_sclk = state->performance_levels[0].sclk; 2345 2346 if (min_sclk == 0) 2347 return -EINVAL; 2348 2349 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2350 state->performance_levels[i-1].vddc, &vddc); 2351 if (ret) 2352 return ret; 2353 2354 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2359 state->performance_levels[i].vddc, &vddc); 2360 if (ret) 2361 return ret; 2362 2363 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2364 if (ret) 2365 return ret; 2366 2367 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2368 prev_std_vddc, curr_std_vddc); 2369 2370 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2371 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2372 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2373 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2374 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2375 } 2376 2377 return 0; 2378 } 2379 2380 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2381 struct radeon_ps *radeon_state, 2382 SISLANDS_SMC_SWSTATE *smc_state) 2383 { 2384 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2385 struct ni_ps *state = ni_get_ps(radeon_state); 2386 u32 sq_power_throttle, sq_power_throttle2; 2387 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2388 int i; 2389 2390 if (state->performance_level_count == 0) 2391 return -EINVAL; 2392 2393 if (smc_state->levelCount != state->performance_level_count) 2394 return -EINVAL; 2395 2396 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2397 return -EINVAL; 2398 2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2403 enable_sq_ramping = false; 2404 2405 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2406 enable_sq_ramping = false; 2407 2408 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2409 enable_sq_ramping = false; 2410 2411 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2412 enable_sq_ramping = false; 2413 2414 for (i = 0; i < state->performance_level_count; i++) { 2415 sq_power_throttle = 0; 2416 sq_power_throttle2 = 0; 2417 2418 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2419 enable_sq_ramping) { 2420 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2421 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2422 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2423 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2424 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2425 } else { 2426 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2427 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2428 } 2429 2430 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2431 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2432 } 2433 2434 return 0; 2435 } 2436 2437 static int si_enable_power_containment(struct radeon_device *rdev, 2438 struct radeon_ps *radeon_new_state, 2439 bool enable) 2440 { 2441 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2442 PPSMC_Result smc_result; 2443 int ret = 0; 2444 2445 if (ni_pi->enable_power_containment) { 2446 if (enable) { 2447 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2448 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2449 if (smc_result != PPSMC_Result_OK) { 2450 ret = -EINVAL; 2451 ni_pi->pc_enabled = false; 2452 } else { 2453 ni_pi->pc_enabled = true; 2454 } 2455 } 2456 } else { 2457 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2458 if (smc_result != PPSMC_Result_OK) 2459 ret = -EINVAL; 2460 ni_pi->pc_enabled = false; 2461 } 2462 } 2463 2464 return ret; 2465 } 2466 2467 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2468 { 2469 struct si_power_info *si_pi = si_get_pi(rdev); 2470 int ret = 0; 2471 struct si_dte_data *dte_data = &si_pi->dte_data; 2472 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2473 u32 table_size; 2474 u8 tdep_count; 2475 u32 i; 2476 2477 if (dte_data == NULL) 2478 si_pi->enable_dte = false; 2479 2480 if (si_pi->enable_dte == false) 2481 return 0; 2482 2483 if (dte_data->k <= 0) 2484 return -EINVAL; 2485 2486 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2487 if (dte_tables == NULL) { 2488 si_pi->enable_dte = false; 2489 return -ENOMEM; 2490 } 2491 2492 table_size = dte_data->k; 2493 2494 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2495 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2496 2497 tdep_count = dte_data->tdep_count; 2498 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2499 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2500 2501 dte_tables->K = cpu_to_be32(table_size); 2502 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2503 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2504 dte_tables->WindowSize = dte_data->window_size; 2505 dte_tables->temp_select = dte_data->temp_select; 2506 dte_tables->DTE_mode = dte_data->dte_mode; 2507 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2508 2509 if (tdep_count > 0) 2510 table_size--; 2511 2512 for (i = 0; i < table_size; i++) { 2513 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2514 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2515 } 2516 2517 dte_tables->Tdep_count = tdep_count; 2518 2519 for (i = 0; i < (u32)tdep_count; i++) { 2520 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2521 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2522 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2523 } 2524 2525 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2526 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2527 kfree(dte_tables); 2528 2529 return ret; 2530 } 2531 2532 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2533 u16 *max, u16 *min) 2534 { 2535 struct si_power_info *si_pi = si_get_pi(rdev); 2536 struct radeon_cac_leakage_table *table = 2537 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2538 u32 i; 2539 u32 v0_loadline; 2540 2541 2542 if (table == NULL) 2543 return -EINVAL; 2544 2545 *max = 0; 2546 *min = 0xFFFF; 2547 2548 for (i = 0; i < table->count; i++) { 2549 if (table->entries[i].vddc > *max) 2550 *max = table->entries[i].vddc; 2551 if (table->entries[i].vddc < *min) 2552 *min = table->entries[i].vddc; 2553 } 2554 2555 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2556 return -EINVAL; 2557 2558 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2559 2560 if (v0_loadline > 0xFFFFUL) 2561 return -EINVAL; 2562 2563 *min = (u16)v0_loadline; 2564 2565 if ((*min > *max) || (*max == 0) || (*min == 0)) 2566 return -EINVAL; 2567 2568 return 0; 2569 } 2570 2571 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2572 { 2573 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2574 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2575 } 2576 2577 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2578 PP_SIslands_CacConfig *cac_tables, 2579 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2580 u16 t0, u16 t_step) 2581 { 2582 struct si_power_info *si_pi = si_get_pi(rdev); 2583 u32 leakage; 2584 unsigned int i, j; 2585 s32 t; 2586 u32 smc_leakage; 2587 u32 scaling_factor; 2588 u16 voltage; 2589 2590 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2591 2592 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2593 t = (1000 * (i * t_step + t0)); 2594 2595 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2596 voltage = vddc_max - (vddc_step * j); 2597 2598 si_calculate_leakage_for_v_and_t(rdev, 2599 &si_pi->powertune_data->leakage_coefficients, 2600 voltage, 2601 t, 2602 si_pi->dyn_powertune_data.cac_leakage, 2603 &leakage); 2604 2605 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2606 2607 if (smc_leakage > 0xFFFF) 2608 smc_leakage = 0xFFFF; 2609 2610 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2611 cpu_to_be16((u16)smc_leakage); 2612 } 2613 } 2614 return 0; 2615 } 2616 2617 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2618 PP_SIslands_CacConfig *cac_tables, 2619 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2620 { 2621 struct si_power_info *si_pi = si_get_pi(rdev); 2622 u32 leakage; 2623 unsigned int i, j; 2624 u32 smc_leakage; 2625 u32 scaling_factor; 2626 u16 voltage; 2627 2628 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2629 2630 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2631 voltage = vddc_max - (vddc_step * j); 2632 2633 si_calculate_leakage_for_v(rdev, 2634 &si_pi->powertune_data->leakage_coefficients, 2635 si_pi->powertune_data->fixed_kt, 2636 voltage, 2637 si_pi->dyn_powertune_data.cac_leakage, 2638 &leakage); 2639 2640 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2641 2642 if (smc_leakage > 0xFFFF) 2643 smc_leakage = 0xFFFF; 2644 2645 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2646 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2647 cpu_to_be16((u16)smc_leakage); 2648 } 2649 return 0; 2650 } 2651 2652 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2653 { 2654 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2655 struct si_power_info *si_pi = si_get_pi(rdev); 2656 PP_SIslands_CacConfig *cac_tables = NULL; 2657 u16 vddc_max, vddc_min, vddc_step; 2658 u16 t0, t_step; 2659 u32 load_line_slope, reg; 2660 int ret = 0; 2661 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2662 2663 if (ni_pi->enable_cac == false) 2664 return 0; 2665 2666 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2667 if (!cac_tables) 2668 return -ENOMEM; 2669 2670 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2671 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2672 WREG32(CG_CAC_CTRL, reg); 2673 2674 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2675 si_pi->dyn_powertune_data.dc_pwr_value = 2676 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2677 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2678 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2679 2680 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2681 2682 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2683 if (ret) 2684 goto done_free; 2685 2686 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2687 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2688 t_step = 4; 2689 t0 = 60; 2690 2691 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2692 ret = si_init_dte_leakage_table(rdev, cac_tables, 2693 vddc_max, vddc_min, vddc_step, 2694 t0, t_step); 2695 else 2696 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2697 vddc_max, vddc_min, vddc_step); 2698 if (ret) 2699 goto done_free; 2700 2701 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2702 2703 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2704 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2705 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2706 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2707 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2708 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2709 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2710 cac_tables->calculation_repeats = cpu_to_be32(2); 2711 cac_tables->dc_cac = cpu_to_be32(0); 2712 cac_tables->log2_PG_LKG_SCALE = 12; 2713 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2714 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2715 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2716 2717 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2718 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2719 2720 if (ret) 2721 goto done_free; 2722 2723 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2724 2725 done_free: 2726 if (ret) { 2727 ni_pi->enable_cac = false; 2728 ni_pi->enable_power_containment = false; 2729 } 2730 2731 kfree(cac_tables); 2732 2733 return 0; 2734 } 2735 2736 static int si_program_cac_config_registers(struct radeon_device *rdev, 2737 const struct si_cac_config_reg *cac_config_regs) 2738 { 2739 const struct si_cac_config_reg *config_regs = cac_config_regs; 2740 u32 data = 0, offset; 2741 2742 if (!config_regs) 2743 return -EINVAL; 2744 2745 while (config_regs->offset != 0xFFFFFFFF) { 2746 switch (config_regs->type) { 2747 case SISLANDS_CACCONFIG_CGIND: 2748 offset = SMC_CG_IND_START + config_regs->offset; 2749 if (offset < SMC_CG_IND_END) 2750 data = RREG32_SMC(offset); 2751 break; 2752 default: 2753 data = RREG32(config_regs->offset << 2); 2754 break; 2755 } 2756 2757 data &= ~config_regs->mask; 2758 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2759 2760 switch (config_regs->type) { 2761 case SISLANDS_CACCONFIG_CGIND: 2762 offset = SMC_CG_IND_START + config_regs->offset; 2763 if (offset < SMC_CG_IND_END) 2764 WREG32_SMC(offset, data); 2765 break; 2766 default: 2767 WREG32(config_regs->offset << 2, data); 2768 break; 2769 } 2770 config_regs++; 2771 } 2772 return 0; 2773 } 2774 2775 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2776 { 2777 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2778 struct si_power_info *si_pi = si_get_pi(rdev); 2779 int ret; 2780 2781 if ((ni_pi->enable_cac == false) || 2782 (ni_pi->cac_configuration_required == false)) 2783 return 0; 2784 2785 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2786 if (ret) 2787 return ret; 2788 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2789 if (ret) 2790 return ret; 2791 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2792 if (ret) 2793 return ret; 2794 2795 return 0; 2796 } 2797 2798 static int si_enable_smc_cac(struct radeon_device *rdev, 2799 struct radeon_ps *radeon_new_state, 2800 bool enable) 2801 { 2802 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2803 struct si_power_info *si_pi = si_get_pi(rdev); 2804 PPSMC_Result smc_result; 2805 int ret = 0; 2806 2807 if (ni_pi->enable_cac) { 2808 if (enable) { 2809 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2810 if (ni_pi->support_cac_long_term_average) { 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2812 if (smc_result != PPSMC_Result_OK) 2813 ni_pi->support_cac_long_term_average = false; 2814 } 2815 2816 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2817 if (smc_result != PPSMC_Result_OK) { 2818 ret = -EINVAL; 2819 ni_pi->cac_enabled = false; 2820 } else { 2821 ni_pi->cac_enabled = true; 2822 } 2823 2824 if (si_pi->enable_dte) { 2825 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2826 if (smc_result != PPSMC_Result_OK) 2827 ret = -EINVAL; 2828 } 2829 } 2830 } else if (ni_pi->cac_enabled) { 2831 if (si_pi->enable_dte) 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2833 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2835 2836 ni_pi->cac_enabled = false; 2837 2838 if (ni_pi->support_cac_long_term_average) 2839 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2840 } 2841 } 2842 return ret; 2843 } 2844 2845 static int si_init_smc_spll_table(struct radeon_device *rdev) 2846 { 2847 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2848 struct si_power_info *si_pi = si_get_pi(rdev); 2849 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2850 SISLANDS_SMC_SCLK_VALUE sclk_params; 2851 u32 fb_div, p_div; 2852 u32 clk_s, clk_v; 2853 u32 sclk = 0; 2854 int ret = 0; 2855 u32 tmp; 2856 int i; 2857 2858 if (si_pi->spll_table_start == 0) 2859 return -EINVAL; 2860 2861 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2862 if (spll_table == NULL) 2863 return -ENOMEM; 2864 2865 for (i = 0; i < 256; i++) { 2866 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2867 if (ret) 2868 break; 2869 2870 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2871 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2872 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2873 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2874 2875 fb_div &= ~0x00001FFF; 2876 fb_div >>= 1; 2877 clk_v >>= 6; 2878 2879 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2880 ret = -EINVAL; 2881 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2882 ret = -EINVAL; 2883 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2884 ret = -EINVAL; 2885 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2886 ret = -EINVAL; 2887 2888 if (ret) 2889 break; 2890 2891 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2892 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2893 spll_table->freq[i] = cpu_to_be32(tmp); 2894 2895 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2896 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2897 spll_table->ss[i] = cpu_to_be32(tmp); 2898 2899 sclk += 512; 2900 } 2901 2902 2903 if (!ret) 2904 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2905 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2906 si_pi->sram_end); 2907 2908 if (ret) 2909 ni_pi->enable_power_containment = false; 2910 2911 kfree(spll_table); 2912 2913 return ret; 2914 } 2915 2916 struct si_dpm_quirk { 2917 u32 chip_vendor; 2918 u32 chip_device; 2919 u32 subsys_vendor; 2920 u32 subsys_device; 2921 u32 max_sclk; 2922 u32 max_mclk; 2923 }; 2924 2925 /* cards with dpm stability problems */ 2926 static struct si_dpm_quirk si_dpm_quirk_list[] = { 2927 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 2928 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2929 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 2930 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 }, 2931 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, 2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 2934 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, 2935 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, 2936 { 0, 0, 0, 0 }, 2937 }; 2938 2939 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2940 u16 vce_voltage) 2941 { 2942 u16 highest_leakage = 0; 2943 struct si_power_info *si_pi = si_get_pi(rdev); 2944 int i; 2945 2946 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2947 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2948 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2949 } 2950 2951 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2952 return highest_leakage; 2953 2954 return vce_voltage; 2955 } 2956 2957 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2958 u32 evclk, u32 ecclk, u16 *voltage) 2959 { 2960 u32 i; 2961 int ret = -EINVAL; 2962 struct radeon_vce_clock_voltage_dependency_table *table = 2963 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2964 2965 if (((evclk == 0) && (ecclk == 0)) || 2966 (table && (table->count == 0))) { 2967 *voltage = 0; 2968 return 0; 2969 } 2970 2971 for (i = 0; i < table->count; i++) { 2972 if ((evclk <= table->entries[i].evclk) && 2973 (ecclk <= table->entries[i].ecclk)) { 2974 *voltage = table->entries[i].v; 2975 ret = 0; 2976 break; 2977 } 2978 } 2979 2980 /* if no match return the highest voltage */ 2981 if (ret) 2982 *voltage = table->entries[table->count - 1].v; 2983 2984 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2985 2986 return ret; 2987 } 2988 2989 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2990 struct radeon_ps *rps) 2991 { 2992 struct ni_ps *ps = ni_get_ps(rps); 2993 struct radeon_clock_and_voltage_limits *max_limits; 2994 bool disable_mclk_switching = false; 2995 bool disable_sclk_switching = false; 2996 u32 mclk, sclk; 2997 u16 vddc, vddci, min_vce_voltage = 0; 2998 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2999 u32 max_sclk = 0, max_mclk = 0; 3000 int i; 3001 struct si_dpm_quirk *p = si_dpm_quirk_list; 3002 3003 /* limit all SI kickers */ 3004 if (rdev->family == CHIP_PITCAIRN) { 3005 if ((rdev->pdev->revision == 0x81) || 3006 (rdev->pdev->device == 0x6810) || 3007 (rdev->pdev->device == 0x6811) || 3008 (rdev->pdev->device == 0x6816) || 3009 (rdev->pdev->device == 0x6817) || 3010 (rdev->pdev->device == 0x6806)) 3011 max_mclk = 120000; 3012 } else if (rdev->family == CHIP_OLAND) { 3013 if ((rdev->pdev->revision == 0xC7) || 3014 (rdev->pdev->revision == 0x80) || 3015 (rdev->pdev->revision == 0x81) || 3016 (rdev->pdev->revision == 0x83) || 3017 (rdev->pdev->revision == 0x87) || 3018 (rdev->pdev->device == 0x6604) || 3019 (rdev->pdev->device == 0x6605)) { 3020 max_sclk = 75000; 3021 max_mclk = 80000; 3022 } 3023 } else if (rdev->family == CHIP_HAINAN) { 3024 if ((rdev->pdev->revision == 0x81) || 3025 (rdev->pdev->revision == 0x83) || 3026 (rdev->pdev->revision == 0xC3) || 3027 (rdev->pdev->device == 0x6664) || 3028 (rdev->pdev->device == 0x6665) || 3029 (rdev->pdev->device == 0x6667)) { 3030 max_sclk = 75000; 3031 max_mclk = 80000; 3032 } 3033 } else if (rdev->family == CHIP_OLAND) { 3034 if ((rdev->pdev->revision == 0xC7) || 3035 (rdev->pdev->revision == 0x80) || 3036 (rdev->pdev->revision == 0x81) || 3037 (rdev->pdev->revision == 0x83) || 3038 (rdev->pdev->revision == 0x87) || 3039 (rdev->pdev->device == 0x6604) || 3040 (rdev->pdev->device == 0x6605)) { 3041 max_sclk = 75000; 3042 } 3043 } 3044 /* Apply dpm quirks */ 3045 while (p && p->chip_device != 0) { 3046 if (rdev->pdev->vendor == p->chip_vendor && 3047 rdev->pdev->device == p->chip_device && 3048 rdev->pdev->subsystem_vendor == p->subsys_vendor && 3049 rdev->pdev->subsystem_device == p->subsys_device) { 3050 max_sclk = p->max_sclk; 3051 max_mclk = p->max_mclk; 3052 break; 3053 } 3054 ++p; 3055 } 3056 /* limit mclk on all R7 370 parts for stability */ 3057 if (rdev->pdev->device == 0x6811 && 3058 rdev->pdev->revision == 0x81) 3059 max_mclk = 120000; 3060 /* limit sclk/mclk on Jet parts for stability */ 3061 if (rdev->pdev->device == 0x6665 && 3062 rdev->pdev->revision == 0xc3) { 3063 max_sclk = 75000; 3064 max_mclk = 80000; 3065 } 3066 3067 if (rps->vce_active) { 3068 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3069 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3070 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3071 &min_vce_voltage); 3072 } else { 3073 rps->evclk = 0; 3074 rps->ecclk = 0; 3075 } 3076 3077 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3078 ni_dpm_vblank_too_short(rdev)) 3079 disable_mclk_switching = true; 3080 3081 if (rps->vclk || rps->dclk) { 3082 disable_mclk_switching = true; 3083 disable_sclk_switching = true; 3084 } 3085 3086 if (rdev->pm.dpm.ac_power) 3087 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3088 else 3089 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3090 3091 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3092 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3093 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3094 } 3095 if (rdev->pm.dpm.ac_power == false) { 3096 for (i = 0; i < ps->performance_level_count; i++) { 3097 if (ps->performance_levels[i].mclk > max_limits->mclk) 3098 ps->performance_levels[i].mclk = max_limits->mclk; 3099 if (ps->performance_levels[i].sclk > max_limits->sclk) 3100 ps->performance_levels[i].sclk = max_limits->sclk; 3101 if (ps->performance_levels[i].vddc > max_limits->vddc) 3102 ps->performance_levels[i].vddc = max_limits->vddc; 3103 if (ps->performance_levels[i].vddci > max_limits->vddci) 3104 ps->performance_levels[i].vddci = max_limits->vddci; 3105 } 3106 } 3107 3108 /* limit clocks to max supported clocks based on voltage dependency tables */ 3109 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3110 &max_sclk_vddc); 3111 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3112 &max_mclk_vddci); 3113 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3114 &max_mclk_vddc); 3115 3116 for (i = 0; i < ps->performance_level_count; i++) { 3117 if (max_sclk_vddc) { 3118 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3119 ps->performance_levels[i].sclk = max_sclk_vddc; 3120 } 3121 if (max_mclk_vddci) { 3122 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3123 ps->performance_levels[i].mclk = max_mclk_vddci; 3124 } 3125 if (max_mclk_vddc) { 3126 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3127 ps->performance_levels[i].mclk = max_mclk_vddc; 3128 } 3129 if (max_mclk) { 3130 if (ps->performance_levels[i].mclk > max_mclk) 3131 ps->performance_levels[i].mclk = max_mclk; 3132 } 3133 if (max_sclk) { 3134 if (ps->performance_levels[i].sclk > max_sclk) 3135 ps->performance_levels[i].sclk = max_sclk; 3136 } 3137 } 3138 3139 /* XXX validate the min clocks required for display */ 3140 3141 if (disable_mclk_switching) { 3142 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3143 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3144 } else { 3145 mclk = ps->performance_levels[0].mclk; 3146 vddci = ps->performance_levels[0].vddci; 3147 } 3148 3149 if (disable_sclk_switching) { 3150 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3151 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3152 } else { 3153 sclk = ps->performance_levels[0].sclk; 3154 vddc = ps->performance_levels[0].vddc; 3155 } 3156 3157 if (rps->vce_active) { 3158 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3159 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3160 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3161 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3162 } 3163 3164 /* adjusted low state */ 3165 ps->performance_levels[0].sclk = sclk; 3166 ps->performance_levels[0].mclk = mclk; 3167 ps->performance_levels[0].vddc = vddc; 3168 ps->performance_levels[0].vddci = vddci; 3169 3170 if (disable_sclk_switching) { 3171 sclk = ps->performance_levels[0].sclk; 3172 for (i = 1; i < ps->performance_level_count; i++) { 3173 if (sclk < ps->performance_levels[i].sclk) 3174 sclk = ps->performance_levels[i].sclk; 3175 } 3176 for (i = 0; i < ps->performance_level_count; i++) { 3177 ps->performance_levels[i].sclk = sclk; 3178 ps->performance_levels[i].vddc = vddc; 3179 } 3180 } else { 3181 for (i = 1; i < ps->performance_level_count; i++) { 3182 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3183 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3184 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3185 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3186 } 3187 } 3188 3189 if (disable_mclk_switching) { 3190 mclk = ps->performance_levels[0].mclk; 3191 for (i = 1; i < ps->performance_level_count; i++) { 3192 if (mclk < ps->performance_levels[i].mclk) 3193 mclk = ps->performance_levels[i].mclk; 3194 } 3195 for (i = 0; i < ps->performance_level_count; i++) { 3196 ps->performance_levels[i].mclk = mclk; 3197 ps->performance_levels[i].vddci = vddci; 3198 } 3199 } else { 3200 for (i = 1; i < ps->performance_level_count; i++) { 3201 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3202 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3203 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3204 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3205 } 3206 } 3207 3208 for (i = 0; i < ps->performance_level_count; i++) 3209 btc_adjust_clock_combinations(rdev, max_limits, 3210 &ps->performance_levels[i]); 3211 3212 for (i = 0; i < ps->performance_level_count; i++) { 3213 if (ps->performance_levels[i].vddc < min_vce_voltage) 3214 ps->performance_levels[i].vddc = min_vce_voltage; 3215 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3216 ps->performance_levels[i].sclk, 3217 max_limits->vddc, &ps->performance_levels[i].vddc); 3218 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3219 ps->performance_levels[i].mclk, 3220 max_limits->vddci, &ps->performance_levels[i].vddci); 3221 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3222 ps->performance_levels[i].mclk, 3223 max_limits->vddc, &ps->performance_levels[i].vddc); 3224 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3225 rdev->clock.current_dispclk, 3226 max_limits->vddc, &ps->performance_levels[i].vddc); 3227 } 3228 3229 for (i = 0; i < ps->performance_level_count; i++) { 3230 btc_apply_voltage_delta_rules(rdev, 3231 max_limits->vddc, max_limits->vddci, 3232 &ps->performance_levels[i].vddc, 3233 &ps->performance_levels[i].vddci); 3234 } 3235 3236 ps->dc_compatible = true; 3237 for (i = 0; i < ps->performance_level_count; i++) { 3238 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3239 ps->dc_compatible = false; 3240 } 3241 } 3242 3243 #if 0 3244 static int si_read_smc_soft_register(struct radeon_device *rdev, 3245 u16 reg_offset, u32 *value) 3246 { 3247 struct si_power_info *si_pi = si_get_pi(rdev); 3248 3249 return si_read_smc_sram_dword(rdev, 3250 si_pi->soft_regs_start + reg_offset, value, 3251 si_pi->sram_end); 3252 } 3253 #endif 3254 3255 static int si_write_smc_soft_register(struct radeon_device *rdev, 3256 u16 reg_offset, u32 value) 3257 { 3258 struct si_power_info *si_pi = si_get_pi(rdev); 3259 3260 return si_write_smc_sram_dword(rdev, 3261 si_pi->soft_regs_start + reg_offset, 3262 value, si_pi->sram_end); 3263 } 3264 3265 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3266 { 3267 bool ret = false; 3268 u32 tmp, width, row, column, bank, density; 3269 bool is_memory_gddr5, is_special; 3270 3271 tmp = RREG32(MC_SEQ_MISC0); 3272 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3273 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3274 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3275 3276 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3277 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3278 3279 tmp = RREG32(MC_ARB_RAMCFG); 3280 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3281 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3282 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3283 3284 density = (1 << (row + column - 20 + bank)) * width; 3285 3286 if ((rdev->pdev->device == 0x6819) && 3287 is_memory_gddr5 && is_special && (density == 0x400)) 3288 ret = true; 3289 3290 return ret; 3291 } 3292 3293 static void si_get_leakage_vddc(struct radeon_device *rdev) 3294 { 3295 struct si_power_info *si_pi = si_get_pi(rdev); 3296 u16 vddc, count = 0; 3297 int i, ret; 3298 3299 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3300 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3301 3302 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3303 si_pi->leakage_voltage.entries[count].voltage = vddc; 3304 si_pi->leakage_voltage.entries[count].leakage_index = 3305 SISLANDS_LEAKAGE_INDEX0 + i; 3306 count++; 3307 } 3308 } 3309 si_pi->leakage_voltage.count = count; 3310 } 3311 3312 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3313 u32 index, u16 *leakage_voltage) 3314 { 3315 struct si_power_info *si_pi = si_get_pi(rdev); 3316 int i; 3317 3318 if (leakage_voltage == NULL) 3319 return -EINVAL; 3320 3321 if ((index & 0xff00) != 0xff00) 3322 return -EINVAL; 3323 3324 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3325 return -EINVAL; 3326 3327 if (index < SISLANDS_LEAKAGE_INDEX0) 3328 return -EINVAL; 3329 3330 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3331 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3332 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3333 return 0; 3334 } 3335 } 3336 return -EAGAIN; 3337 } 3338 3339 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3340 { 3341 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3342 bool want_thermal_protection; 3343 enum radeon_dpm_event_src dpm_event_src; 3344 3345 switch (sources) { 3346 case 0: 3347 default: 3348 want_thermal_protection = false; 3349 break; 3350 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3351 want_thermal_protection = true; 3352 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3353 break; 3354 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3355 want_thermal_protection = true; 3356 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3357 break; 3358 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3359 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3360 want_thermal_protection = true; 3361 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3362 break; 3363 } 3364 3365 if (want_thermal_protection) { 3366 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3367 if (pi->thermal_protection) 3368 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3369 } else { 3370 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3371 } 3372 } 3373 3374 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3375 enum radeon_dpm_auto_throttle_src source, 3376 bool enable) 3377 { 3378 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3379 3380 if (enable) { 3381 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3382 pi->active_auto_throttle_sources |= 1 << source; 3383 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3384 } 3385 } else { 3386 if (pi->active_auto_throttle_sources & (1 << source)) { 3387 pi->active_auto_throttle_sources &= ~(1 << source); 3388 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3389 } 3390 } 3391 } 3392 3393 static void si_start_dpm(struct radeon_device *rdev) 3394 { 3395 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3396 } 3397 3398 static void si_stop_dpm(struct radeon_device *rdev) 3399 { 3400 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3401 } 3402 3403 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3404 { 3405 if (enable) 3406 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3407 else 3408 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3409 3410 } 3411 3412 #if 0 3413 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3414 u32 thermal_level) 3415 { 3416 PPSMC_Result ret; 3417 3418 if (thermal_level == 0) { 3419 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3420 if (ret == PPSMC_Result_OK) 3421 return 0; 3422 else 3423 return -EINVAL; 3424 } 3425 return 0; 3426 } 3427 3428 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3429 { 3430 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3431 } 3432 #endif 3433 3434 #if 0 3435 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3436 { 3437 if (ac_power) 3438 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3439 0 : -EINVAL; 3440 3441 return 0; 3442 } 3443 #endif 3444 3445 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3446 PPSMC_Msg msg, u32 parameter) 3447 { 3448 WREG32(SMC_SCRATCH0, parameter); 3449 return si_send_msg_to_smc(rdev, msg); 3450 } 3451 3452 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3453 { 3454 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3455 return -EINVAL; 3456 3457 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3458 0 : -EINVAL; 3459 } 3460 3461 int si_dpm_force_performance_level(struct radeon_device *rdev, 3462 enum radeon_dpm_forced_level level) 3463 { 3464 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3465 struct ni_ps *ps = ni_get_ps(rps); 3466 u32 levels = ps->performance_level_count; 3467 3468 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3469 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3470 return -EINVAL; 3471 3472 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3473 return -EINVAL; 3474 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3475 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3476 return -EINVAL; 3477 3478 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3479 return -EINVAL; 3480 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3481 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3482 return -EINVAL; 3483 3484 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3485 return -EINVAL; 3486 } 3487 3488 rdev->pm.dpm.forced_level = level; 3489 3490 return 0; 3491 } 3492 3493 #if 0 3494 static int si_set_boot_state(struct radeon_device *rdev) 3495 { 3496 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3497 0 : -EINVAL; 3498 } 3499 #endif 3500 3501 static int si_set_sw_state(struct radeon_device *rdev) 3502 { 3503 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3504 0 : -EINVAL; 3505 } 3506 3507 static int si_halt_smc(struct radeon_device *rdev) 3508 { 3509 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3510 return -EINVAL; 3511 3512 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3513 0 : -EINVAL; 3514 } 3515 3516 static int si_resume_smc(struct radeon_device *rdev) 3517 { 3518 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3519 return -EINVAL; 3520 3521 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3522 0 : -EINVAL; 3523 } 3524 3525 static void si_dpm_start_smc(struct radeon_device *rdev) 3526 { 3527 si_program_jump_on_start(rdev); 3528 si_start_smc(rdev); 3529 si_start_smc_clock(rdev); 3530 } 3531 3532 static void si_dpm_stop_smc(struct radeon_device *rdev) 3533 { 3534 si_reset_smc(rdev); 3535 si_stop_smc_clock(rdev); 3536 } 3537 3538 static int si_process_firmware_header(struct radeon_device *rdev) 3539 { 3540 struct si_power_info *si_pi = si_get_pi(rdev); 3541 u32 tmp; 3542 int ret; 3543 3544 ret = si_read_smc_sram_dword(rdev, 3545 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3546 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3547 &tmp, si_pi->sram_end); 3548 if (ret) 3549 return ret; 3550 3551 si_pi->state_table_start = tmp; 3552 3553 ret = si_read_smc_sram_dword(rdev, 3554 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3555 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3556 &tmp, si_pi->sram_end); 3557 if (ret) 3558 return ret; 3559 3560 si_pi->soft_regs_start = tmp; 3561 3562 ret = si_read_smc_sram_dword(rdev, 3563 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3564 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3565 &tmp, si_pi->sram_end); 3566 if (ret) 3567 return ret; 3568 3569 si_pi->mc_reg_table_start = tmp; 3570 3571 ret = si_read_smc_sram_dword(rdev, 3572 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3573 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3574 &tmp, si_pi->sram_end); 3575 if (ret) 3576 return ret; 3577 3578 si_pi->fan_table_start = tmp; 3579 3580 ret = si_read_smc_sram_dword(rdev, 3581 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3582 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3583 &tmp, si_pi->sram_end); 3584 if (ret) 3585 return ret; 3586 3587 si_pi->arb_table_start = tmp; 3588 3589 ret = si_read_smc_sram_dword(rdev, 3590 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3591 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3592 &tmp, si_pi->sram_end); 3593 if (ret) 3594 return ret; 3595 3596 si_pi->cac_table_start = tmp; 3597 3598 ret = si_read_smc_sram_dword(rdev, 3599 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3600 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3601 &tmp, si_pi->sram_end); 3602 if (ret) 3603 return ret; 3604 3605 si_pi->dte_table_start = tmp; 3606 3607 ret = si_read_smc_sram_dword(rdev, 3608 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3609 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3610 &tmp, si_pi->sram_end); 3611 if (ret) 3612 return ret; 3613 3614 si_pi->spll_table_start = tmp; 3615 3616 ret = si_read_smc_sram_dword(rdev, 3617 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3618 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3619 &tmp, si_pi->sram_end); 3620 if (ret) 3621 return ret; 3622 3623 si_pi->papm_cfg_table_start = tmp; 3624 3625 return ret; 3626 } 3627 3628 static void si_read_clock_registers(struct radeon_device *rdev) 3629 { 3630 struct si_power_info *si_pi = si_get_pi(rdev); 3631 3632 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3633 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3634 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3635 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3636 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3637 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3638 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3639 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3640 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3641 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3642 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3643 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3644 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3645 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3646 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3647 } 3648 3649 static void si_enable_thermal_protection(struct radeon_device *rdev, 3650 bool enable) 3651 { 3652 if (enable) 3653 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3654 else 3655 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3656 } 3657 3658 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3659 { 3660 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3661 } 3662 3663 #if 0 3664 static int si_enter_ulp_state(struct radeon_device *rdev) 3665 { 3666 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3667 3668 udelay(25000); 3669 3670 return 0; 3671 } 3672 3673 static int si_exit_ulp_state(struct radeon_device *rdev) 3674 { 3675 int i; 3676 3677 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3678 3679 udelay(7000); 3680 3681 for (i = 0; i < rdev->usec_timeout; i++) { 3682 if (RREG32(SMC_RESP_0) == 1) 3683 break; 3684 udelay(1000); 3685 } 3686 3687 return 0; 3688 } 3689 #endif 3690 3691 static int si_notify_smc_display_change(struct radeon_device *rdev, 3692 bool has_display) 3693 { 3694 PPSMC_Msg msg = has_display ? 3695 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3696 3697 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3698 0 : -EINVAL; 3699 } 3700 3701 static void si_program_response_times(struct radeon_device *rdev) 3702 { 3703 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3704 u32 vddc_dly, acpi_dly, vbi_dly; 3705 u32 reference_clock; 3706 3707 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3708 3709 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3710 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3711 3712 if (voltage_response_time == 0) 3713 voltage_response_time = 1000; 3714 3715 acpi_delay_time = 15000; 3716 vbi_time_out = 100000; 3717 3718 reference_clock = radeon_get_xclk(rdev); 3719 3720 vddc_dly = (voltage_response_time * reference_clock) / 100; 3721 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3722 vbi_dly = (vbi_time_out * reference_clock) / 100; 3723 3724 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3725 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3726 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3727 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3728 } 3729 3730 static void si_program_ds_registers(struct radeon_device *rdev) 3731 { 3732 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3733 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3734 3735 if (eg_pi->sclk_deep_sleep) { 3736 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3737 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3738 ~AUTOSCALE_ON_SS_CLEAR); 3739 } 3740 } 3741 3742 static void si_program_display_gap(struct radeon_device *rdev) 3743 { 3744 u32 tmp, pipe; 3745 int i; 3746 3747 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3748 if (rdev->pm.dpm.new_active_crtc_count > 0) 3749 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3750 else 3751 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3752 3753 if (rdev->pm.dpm.new_active_crtc_count > 1) 3754 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3755 else 3756 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3757 3758 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3759 3760 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3761 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3762 3763 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3764 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3765 /* find the first active crtc */ 3766 for (i = 0; i < rdev->num_crtc; i++) { 3767 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3768 break; 3769 } 3770 if (i == rdev->num_crtc) 3771 pipe = 0; 3772 else 3773 pipe = i; 3774 3775 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3776 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3777 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3778 } 3779 3780 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3781 * This can be a problem on PowerXpress systems or if you want to use the card 3782 * for offscreen rendering or compute if there are no crtcs enabled. 3783 */ 3784 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3785 } 3786 3787 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3788 { 3789 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3790 3791 if (enable) { 3792 if (pi->sclk_ss) 3793 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3794 } else { 3795 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3796 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3797 } 3798 } 3799 3800 static void si_setup_bsp(struct radeon_device *rdev) 3801 { 3802 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3803 u32 xclk = radeon_get_xclk(rdev); 3804 3805 r600_calculate_u_and_p(pi->asi, 3806 xclk, 3807 16, 3808 &pi->bsp, 3809 &pi->bsu); 3810 3811 r600_calculate_u_and_p(pi->pasi, 3812 xclk, 3813 16, 3814 &pi->pbsp, 3815 &pi->pbsu); 3816 3817 3818 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3819 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3820 3821 WREG32(CG_BSP, pi->dsp); 3822 } 3823 3824 static void si_program_git(struct radeon_device *rdev) 3825 { 3826 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3827 } 3828 3829 static void si_program_tp(struct radeon_device *rdev) 3830 { 3831 int i; 3832 enum r600_td td = R600_TD_DFLT; 3833 3834 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3835 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3836 3837 if (td == R600_TD_AUTO) 3838 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3839 else 3840 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3841 3842 if (td == R600_TD_UP) 3843 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3844 3845 if (td == R600_TD_DOWN) 3846 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3847 } 3848 3849 static void si_program_tpp(struct radeon_device *rdev) 3850 { 3851 WREG32(CG_TPC, R600_TPC_DFLT); 3852 } 3853 3854 static void si_program_sstp(struct radeon_device *rdev) 3855 { 3856 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3857 } 3858 3859 static void si_enable_display_gap(struct radeon_device *rdev) 3860 { 3861 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3862 3863 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3864 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3865 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3866 3867 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3868 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3869 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3870 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3871 } 3872 3873 static void si_program_vc(struct radeon_device *rdev) 3874 { 3875 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3876 3877 WREG32(CG_FTV, pi->vrc); 3878 } 3879 3880 static void si_clear_vc(struct radeon_device *rdev) 3881 { 3882 WREG32(CG_FTV, 0); 3883 } 3884 3885 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3886 { 3887 u8 mc_para_index; 3888 3889 if (memory_clock < 10000) 3890 mc_para_index = 0; 3891 else if (memory_clock >= 80000) 3892 mc_para_index = 0x0f; 3893 else 3894 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3895 return mc_para_index; 3896 } 3897 3898 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3899 { 3900 u8 mc_para_index; 3901 3902 if (strobe_mode) { 3903 if (memory_clock < 12500) 3904 mc_para_index = 0x00; 3905 else if (memory_clock > 47500) 3906 mc_para_index = 0x0f; 3907 else 3908 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3909 } else { 3910 if (memory_clock < 65000) 3911 mc_para_index = 0x00; 3912 else if (memory_clock > 135000) 3913 mc_para_index = 0x0f; 3914 else 3915 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3916 } 3917 return mc_para_index; 3918 } 3919 3920 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3921 { 3922 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3923 bool strobe_mode = false; 3924 u8 result = 0; 3925 3926 if (mclk <= pi->mclk_strobe_mode_threshold) 3927 strobe_mode = true; 3928 3929 if (pi->mem_gddr5) 3930 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3931 else 3932 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3933 3934 if (strobe_mode) 3935 result |= SISLANDS_SMC_STROBE_ENABLE; 3936 3937 return result; 3938 } 3939 3940 static int si_upload_firmware(struct radeon_device *rdev) 3941 { 3942 struct si_power_info *si_pi = si_get_pi(rdev); 3943 int ret; 3944 3945 si_reset_smc(rdev); 3946 si_stop_smc_clock(rdev); 3947 3948 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3949 3950 return ret; 3951 } 3952 3953 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3954 const struct atom_voltage_table *table, 3955 const struct radeon_phase_shedding_limits_table *limits) 3956 { 3957 u32 data, num_bits, num_levels; 3958 3959 if ((table == NULL) || (limits == NULL)) 3960 return false; 3961 3962 data = table->mask_low; 3963 3964 num_bits = hweight32(data); 3965 3966 if (num_bits == 0) 3967 return false; 3968 3969 num_levels = (1 << num_bits); 3970 3971 if (table->count != num_levels) 3972 return false; 3973 3974 if (limits->count != (num_levels - 1)) 3975 return false; 3976 3977 return true; 3978 } 3979 3980 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3981 u32 max_voltage_steps, 3982 struct atom_voltage_table *voltage_table) 3983 { 3984 unsigned int i, diff; 3985 3986 if (voltage_table->count <= max_voltage_steps) 3987 return; 3988 3989 diff = voltage_table->count - max_voltage_steps; 3990 3991 for (i= 0; i < max_voltage_steps; i++) 3992 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3993 3994 voltage_table->count = max_voltage_steps; 3995 } 3996 3997 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3998 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3999 struct atom_voltage_table *voltage_table) 4000 { 4001 u32 i; 4002 4003 if (voltage_dependency_table == NULL) 4004 return -EINVAL; 4005 4006 voltage_table->mask_low = 0; 4007 voltage_table->phase_delay = 0; 4008 4009 voltage_table->count = voltage_dependency_table->count; 4010 for (i = 0; i < voltage_table->count; i++) { 4011 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4012 voltage_table->entries[i].smio_low = 0; 4013 } 4014 4015 return 0; 4016 } 4017 4018 static int si_construct_voltage_tables(struct radeon_device *rdev) 4019 { 4020 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4021 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4022 struct si_power_info *si_pi = si_get_pi(rdev); 4023 int ret; 4024 4025 if (pi->voltage_control) { 4026 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4027 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4028 if (ret) 4029 return ret; 4030 4031 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4032 si_trim_voltage_table_to_fit_state_table(rdev, 4033 SISLANDS_MAX_NO_VREG_STEPS, 4034 &eg_pi->vddc_voltage_table); 4035 } else if (si_pi->voltage_control_svi2) { 4036 ret = si_get_svi2_voltage_table(rdev, 4037 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4038 &eg_pi->vddc_voltage_table); 4039 if (ret) 4040 return ret; 4041 } else { 4042 return -EINVAL; 4043 } 4044 4045 if (eg_pi->vddci_control) { 4046 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 4047 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4048 if (ret) 4049 return ret; 4050 4051 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4052 si_trim_voltage_table_to_fit_state_table(rdev, 4053 SISLANDS_MAX_NO_VREG_STEPS, 4054 &eg_pi->vddci_voltage_table); 4055 } 4056 if (si_pi->vddci_control_svi2) { 4057 ret = si_get_svi2_voltage_table(rdev, 4058 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4059 &eg_pi->vddci_voltage_table); 4060 if (ret) 4061 return ret; 4062 } 4063 4064 if (pi->mvdd_control) { 4065 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4066 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4067 4068 if (ret) { 4069 pi->mvdd_control = false; 4070 return ret; 4071 } 4072 4073 if (si_pi->mvdd_voltage_table.count == 0) { 4074 pi->mvdd_control = false; 4075 return -EINVAL; 4076 } 4077 4078 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4079 si_trim_voltage_table_to_fit_state_table(rdev, 4080 SISLANDS_MAX_NO_VREG_STEPS, 4081 &si_pi->mvdd_voltage_table); 4082 } 4083 4084 if (si_pi->vddc_phase_shed_control) { 4085 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4086 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4087 if (ret) 4088 si_pi->vddc_phase_shed_control = false; 4089 4090 if ((si_pi->vddc_phase_shed_table.count == 0) || 4091 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4092 si_pi->vddc_phase_shed_control = false; 4093 } 4094 4095 return 0; 4096 } 4097 4098 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4099 const struct atom_voltage_table *voltage_table, 4100 SISLANDS_SMC_STATETABLE *table) 4101 { 4102 unsigned int i; 4103 4104 for (i = 0; i < voltage_table->count; i++) 4105 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4106 } 4107 4108 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4109 SISLANDS_SMC_STATETABLE *table) 4110 { 4111 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4112 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4113 struct si_power_info *si_pi = si_get_pi(rdev); 4114 u8 i; 4115 4116 if (si_pi->voltage_control_svi2) { 4117 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4118 si_pi->svc_gpio_id); 4119 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4120 si_pi->svd_gpio_id); 4121 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4122 2); 4123 } else { 4124 if (eg_pi->vddc_voltage_table.count) { 4125 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4126 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4127 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4128 4129 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4130 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4131 table->maxVDDCIndexInPPTable = i; 4132 break; 4133 } 4134 } 4135 } 4136 4137 if (eg_pi->vddci_voltage_table.count) { 4138 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4139 4140 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4141 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4142 } 4143 4144 4145 if (si_pi->mvdd_voltage_table.count) { 4146 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4147 4148 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4149 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4150 } 4151 4152 if (si_pi->vddc_phase_shed_control) { 4153 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4154 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4155 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4156 4157 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4158 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4159 4160 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4161 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4162 } else { 4163 si_pi->vddc_phase_shed_control = false; 4164 } 4165 } 4166 } 4167 4168 return 0; 4169 } 4170 4171 static int si_populate_voltage_value(struct radeon_device *rdev, 4172 const struct atom_voltage_table *table, 4173 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4174 { 4175 unsigned int i; 4176 4177 for (i = 0; i < table->count; i++) { 4178 if (value <= table->entries[i].value) { 4179 voltage->index = (u8)i; 4180 voltage->value = cpu_to_be16(table->entries[i].value); 4181 break; 4182 } 4183 } 4184 4185 if (i >= table->count) 4186 return -EINVAL; 4187 4188 return 0; 4189 } 4190 4191 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4192 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4193 { 4194 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4195 struct si_power_info *si_pi = si_get_pi(rdev); 4196 4197 if (pi->mvdd_control) { 4198 if (mclk <= pi->mvdd_split_frequency) 4199 voltage->index = 0; 4200 else 4201 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4202 4203 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4204 } 4205 return 0; 4206 } 4207 4208 static int si_get_std_voltage_value(struct radeon_device *rdev, 4209 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4210 u16 *std_voltage) 4211 { 4212 u16 v_index; 4213 bool voltage_found = false; 4214 *std_voltage = be16_to_cpu(voltage->value); 4215 4216 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4217 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4218 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4219 return -EINVAL; 4220 4221 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4222 if (be16_to_cpu(voltage->value) == 4223 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4224 voltage_found = true; 4225 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4226 *std_voltage = 4227 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4228 else 4229 *std_voltage = 4230 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4231 break; 4232 } 4233 } 4234 4235 if (!voltage_found) { 4236 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4237 if (be16_to_cpu(voltage->value) <= 4238 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4239 voltage_found = true; 4240 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4241 *std_voltage = 4242 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4243 else 4244 *std_voltage = 4245 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4246 break; 4247 } 4248 } 4249 } 4250 } else { 4251 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4252 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4253 } 4254 } 4255 4256 return 0; 4257 } 4258 4259 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4260 u16 value, u8 index, 4261 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4262 { 4263 voltage->index = index; 4264 voltage->value = cpu_to_be16(value); 4265 4266 return 0; 4267 } 4268 4269 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4270 const struct radeon_phase_shedding_limits_table *limits, 4271 u16 voltage, u32 sclk, u32 mclk, 4272 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4273 { 4274 unsigned int i; 4275 4276 for (i = 0; i < limits->count; i++) { 4277 if ((voltage <= limits->entries[i].voltage) && 4278 (sclk <= limits->entries[i].sclk) && 4279 (mclk <= limits->entries[i].mclk)) 4280 break; 4281 } 4282 4283 smc_voltage->phase_settings = (u8)i; 4284 4285 return 0; 4286 } 4287 4288 static int si_init_arb_table_index(struct radeon_device *rdev) 4289 { 4290 struct si_power_info *si_pi = si_get_pi(rdev); 4291 u32 tmp; 4292 int ret; 4293 4294 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4295 if (ret) 4296 return ret; 4297 4298 tmp &= 0x00FFFFFF; 4299 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4300 4301 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4302 } 4303 4304 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4305 { 4306 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4307 } 4308 4309 static int si_reset_to_default(struct radeon_device *rdev) 4310 { 4311 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4312 0 : -EINVAL; 4313 } 4314 4315 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4316 { 4317 struct si_power_info *si_pi = si_get_pi(rdev); 4318 u32 tmp; 4319 int ret; 4320 4321 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4322 &tmp, si_pi->sram_end); 4323 if (ret) 4324 return ret; 4325 4326 tmp = (tmp >> 24) & 0xff; 4327 4328 if (tmp == MC_CG_ARB_FREQ_F0) 4329 return 0; 4330 4331 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4332 } 4333 4334 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4335 u32 engine_clock) 4336 { 4337 u32 dram_rows; 4338 u32 dram_refresh_rate; 4339 u32 mc_arb_rfsh_rate; 4340 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4341 4342 if (tmp >= 4) 4343 dram_rows = 16384; 4344 else 4345 dram_rows = 1 << (tmp + 10); 4346 4347 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4348 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4349 4350 return mc_arb_rfsh_rate; 4351 } 4352 4353 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4354 struct rv7xx_pl *pl, 4355 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4356 { 4357 u32 dram_timing; 4358 u32 dram_timing2; 4359 u32 burst_time; 4360 4361 arb_regs->mc_arb_rfsh_rate = 4362 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4363 4364 radeon_atom_set_engine_dram_timings(rdev, 4365 pl->sclk, 4366 pl->mclk); 4367 4368 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4369 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4370 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4371 4372 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4373 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4374 arb_regs->mc_arb_burst_time = (u8)burst_time; 4375 4376 return 0; 4377 } 4378 4379 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4380 struct radeon_ps *radeon_state, 4381 unsigned int first_arb_set) 4382 { 4383 struct si_power_info *si_pi = si_get_pi(rdev); 4384 struct ni_ps *state = ni_get_ps(radeon_state); 4385 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4386 int i, ret = 0; 4387 4388 for (i = 0; i < state->performance_level_count; i++) { 4389 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4390 if (ret) 4391 break; 4392 ret = si_copy_bytes_to_smc(rdev, 4393 si_pi->arb_table_start + 4394 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4395 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4396 (u8 *)&arb_regs, 4397 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4398 si_pi->sram_end); 4399 if (ret) 4400 break; 4401 } 4402 4403 return ret; 4404 } 4405 4406 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4407 struct radeon_ps *radeon_new_state) 4408 { 4409 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4410 SISLANDS_DRIVER_STATE_ARB_INDEX); 4411 } 4412 4413 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4414 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4415 { 4416 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4417 struct si_power_info *si_pi = si_get_pi(rdev); 4418 4419 if (pi->mvdd_control) 4420 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4421 si_pi->mvdd_bootup_value, voltage); 4422 4423 return 0; 4424 } 4425 4426 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4427 struct radeon_ps *radeon_initial_state, 4428 SISLANDS_SMC_STATETABLE *table) 4429 { 4430 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4431 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4432 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4433 struct si_power_info *si_pi = si_get_pi(rdev); 4434 u32 reg; 4435 int ret; 4436 4437 table->initialState.levels[0].mclk.vDLL_CNTL = 4438 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4439 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4440 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4441 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4442 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4443 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4444 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4445 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4446 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4447 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4448 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4449 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4450 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4451 table->initialState.levels[0].mclk.vMPLL_SS = 4452 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4453 table->initialState.levels[0].mclk.vMPLL_SS2 = 4454 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4455 4456 table->initialState.levels[0].mclk.mclk_value = 4457 cpu_to_be32(initial_state->performance_levels[0].mclk); 4458 4459 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4460 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4461 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4462 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4463 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4464 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4465 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4466 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4467 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4468 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4469 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4470 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4471 4472 table->initialState.levels[0].sclk.sclk_value = 4473 cpu_to_be32(initial_state->performance_levels[0].sclk); 4474 4475 table->initialState.levels[0].arbRefreshState = 4476 SISLANDS_INITIAL_STATE_ARB_INDEX; 4477 4478 table->initialState.levels[0].ACIndex = 0; 4479 4480 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4481 initial_state->performance_levels[0].vddc, 4482 &table->initialState.levels[0].vddc); 4483 4484 if (!ret) { 4485 u16 std_vddc; 4486 4487 ret = si_get_std_voltage_value(rdev, 4488 &table->initialState.levels[0].vddc, 4489 &std_vddc); 4490 if (!ret) 4491 si_populate_std_voltage_value(rdev, std_vddc, 4492 table->initialState.levels[0].vddc.index, 4493 &table->initialState.levels[0].std_vddc); 4494 } 4495 4496 if (eg_pi->vddci_control) 4497 si_populate_voltage_value(rdev, 4498 &eg_pi->vddci_voltage_table, 4499 initial_state->performance_levels[0].vddci, 4500 &table->initialState.levels[0].vddci); 4501 4502 if (si_pi->vddc_phase_shed_control) 4503 si_populate_phase_shedding_value(rdev, 4504 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4505 initial_state->performance_levels[0].vddc, 4506 initial_state->performance_levels[0].sclk, 4507 initial_state->performance_levels[0].mclk, 4508 &table->initialState.levels[0].vddc); 4509 4510 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4511 4512 reg = CG_R(0xffff) | CG_L(0); 4513 table->initialState.levels[0].aT = cpu_to_be32(reg); 4514 4515 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4516 4517 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4518 4519 if (pi->mem_gddr5) { 4520 table->initialState.levels[0].strobeMode = 4521 si_get_strobe_mode_settings(rdev, 4522 initial_state->performance_levels[0].mclk); 4523 4524 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4525 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4526 else 4527 table->initialState.levels[0].mcFlags = 0; 4528 } 4529 4530 table->initialState.levelCount = 1; 4531 4532 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4533 4534 table->initialState.levels[0].dpm2.MaxPS = 0; 4535 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4536 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4537 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4538 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4539 4540 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4541 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4542 4543 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4544 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4545 4546 return 0; 4547 } 4548 4549 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4550 SISLANDS_SMC_STATETABLE *table) 4551 { 4552 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4553 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4554 struct si_power_info *si_pi = si_get_pi(rdev); 4555 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4556 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4557 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4558 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4559 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4560 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4561 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4562 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4563 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4564 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4565 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4566 u32 reg; 4567 int ret; 4568 4569 table->ACPIState = table->initialState; 4570 4571 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4572 4573 if (pi->acpi_vddc) { 4574 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4575 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4576 if (!ret) { 4577 u16 std_vddc; 4578 4579 ret = si_get_std_voltage_value(rdev, 4580 &table->ACPIState.levels[0].vddc, &std_vddc); 4581 if (!ret) 4582 si_populate_std_voltage_value(rdev, std_vddc, 4583 table->ACPIState.levels[0].vddc.index, 4584 &table->ACPIState.levels[0].std_vddc); 4585 } 4586 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4587 4588 if (si_pi->vddc_phase_shed_control) { 4589 si_populate_phase_shedding_value(rdev, 4590 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4591 pi->acpi_vddc, 4592 0, 4593 0, 4594 &table->ACPIState.levels[0].vddc); 4595 } 4596 } else { 4597 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4598 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4599 if (!ret) { 4600 u16 std_vddc; 4601 4602 ret = si_get_std_voltage_value(rdev, 4603 &table->ACPIState.levels[0].vddc, &std_vddc); 4604 4605 if (!ret) 4606 si_populate_std_voltage_value(rdev, std_vddc, 4607 table->ACPIState.levels[0].vddc.index, 4608 &table->ACPIState.levels[0].std_vddc); 4609 } 4610 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4611 si_pi->sys_pcie_mask, 4612 si_pi->boot_pcie_gen, 4613 RADEON_PCIE_GEN1); 4614 4615 if (si_pi->vddc_phase_shed_control) 4616 si_populate_phase_shedding_value(rdev, 4617 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4618 pi->min_vddc_in_table, 4619 0, 4620 0, 4621 &table->ACPIState.levels[0].vddc); 4622 } 4623 4624 if (pi->acpi_vddc) { 4625 if (eg_pi->acpi_vddci) 4626 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4627 eg_pi->acpi_vddci, 4628 &table->ACPIState.levels[0].vddci); 4629 } 4630 4631 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4632 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4633 4634 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4635 4636 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4637 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4638 4639 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4640 cpu_to_be32(dll_cntl); 4641 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4642 cpu_to_be32(mclk_pwrmgt_cntl); 4643 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4644 cpu_to_be32(mpll_ad_func_cntl); 4645 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4646 cpu_to_be32(mpll_dq_func_cntl); 4647 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4648 cpu_to_be32(mpll_func_cntl); 4649 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4650 cpu_to_be32(mpll_func_cntl_1); 4651 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4652 cpu_to_be32(mpll_func_cntl_2); 4653 table->ACPIState.levels[0].mclk.vMPLL_SS = 4654 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4655 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4656 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4657 4658 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4659 cpu_to_be32(spll_func_cntl); 4660 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4661 cpu_to_be32(spll_func_cntl_2); 4662 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4663 cpu_to_be32(spll_func_cntl_3); 4664 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4665 cpu_to_be32(spll_func_cntl_4); 4666 4667 table->ACPIState.levels[0].mclk.mclk_value = 0; 4668 table->ACPIState.levels[0].sclk.sclk_value = 0; 4669 4670 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4671 4672 if (eg_pi->dynamic_ac_timing) 4673 table->ACPIState.levels[0].ACIndex = 0; 4674 4675 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4676 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4677 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4678 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4679 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4680 4681 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4682 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4683 4684 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4685 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4686 4687 return 0; 4688 } 4689 4690 static int si_populate_ulv_state(struct radeon_device *rdev, 4691 SISLANDS_SMC_SWSTATE *state) 4692 { 4693 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4694 struct si_power_info *si_pi = si_get_pi(rdev); 4695 struct si_ulv_param *ulv = &si_pi->ulv; 4696 u32 sclk_in_sr = 1350; /* ??? */ 4697 int ret; 4698 4699 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4700 &state->levels[0]); 4701 if (!ret) { 4702 if (eg_pi->sclk_deep_sleep) { 4703 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4704 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4705 else 4706 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4707 } 4708 if (ulv->one_pcie_lane_in_ulv) 4709 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4710 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4711 state->levels[0].ACIndex = 1; 4712 state->levels[0].std_vddc = state->levels[0].vddc; 4713 state->levelCount = 1; 4714 4715 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4716 } 4717 4718 return ret; 4719 } 4720 4721 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4722 { 4723 struct si_power_info *si_pi = si_get_pi(rdev); 4724 struct si_ulv_param *ulv = &si_pi->ulv; 4725 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4726 int ret; 4727 4728 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4729 &arb_regs); 4730 if (ret) 4731 return ret; 4732 4733 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4734 ulv->volt_change_delay); 4735 4736 ret = si_copy_bytes_to_smc(rdev, 4737 si_pi->arb_table_start + 4738 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4739 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4740 (u8 *)&arb_regs, 4741 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4742 si_pi->sram_end); 4743 4744 return ret; 4745 } 4746 4747 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4748 { 4749 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4750 4751 pi->mvdd_split_frequency = 30000; 4752 } 4753 4754 static int si_init_smc_table(struct radeon_device *rdev) 4755 { 4756 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4757 struct si_power_info *si_pi = si_get_pi(rdev); 4758 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4759 const struct si_ulv_param *ulv = &si_pi->ulv; 4760 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4761 int ret; 4762 u32 lane_width; 4763 u32 vr_hot_gpio; 4764 4765 si_populate_smc_voltage_tables(rdev, table); 4766 4767 switch (rdev->pm.int_thermal_type) { 4768 case THERMAL_TYPE_SI: 4769 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4770 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4771 break; 4772 case THERMAL_TYPE_NONE: 4773 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4774 break; 4775 default: 4776 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4777 break; 4778 } 4779 4780 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4781 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4782 4783 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4784 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4785 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4786 } 4787 4788 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4789 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4790 4791 if (pi->mem_gddr5) 4792 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4793 4794 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4795 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4796 4797 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4798 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4799 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4800 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4801 vr_hot_gpio); 4802 } 4803 4804 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4805 if (ret) 4806 return ret; 4807 4808 ret = si_populate_smc_acpi_state(rdev, table); 4809 if (ret) 4810 return ret; 4811 4812 table->driverState = table->initialState; 4813 4814 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4815 SISLANDS_INITIAL_STATE_ARB_INDEX); 4816 if (ret) 4817 return ret; 4818 4819 if (ulv->supported && ulv->pl.vddc) { 4820 ret = si_populate_ulv_state(rdev, &table->ULVState); 4821 if (ret) 4822 return ret; 4823 4824 ret = si_program_ulv_memory_timing_parameters(rdev); 4825 if (ret) 4826 return ret; 4827 4828 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4829 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4830 4831 lane_width = radeon_get_pcie_lanes(rdev); 4832 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4833 } else { 4834 table->ULVState = table->initialState; 4835 } 4836 4837 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4838 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4839 si_pi->sram_end); 4840 } 4841 4842 static int si_calculate_sclk_params(struct radeon_device *rdev, 4843 u32 engine_clock, 4844 SISLANDS_SMC_SCLK_VALUE *sclk) 4845 { 4846 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4847 struct si_power_info *si_pi = si_get_pi(rdev); 4848 struct atom_clock_dividers dividers; 4849 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4850 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4851 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4852 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4853 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4854 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4855 u64 tmp; 4856 u32 reference_clock = rdev->clock.spll.reference_freq; 4857 u32 reference_divider; 4858 u32 fbdiv; 4859 int ret; 4860 4861 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4862 engine_clock, false, ÷rs); 4863 if (ret) 4864 return ret; 4865 4866 reference_divider = 1 + dividers.ref_div; 4867 4868 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4869 do_div(tmp, reference_clock); 4870 fbdiv = (u32) tmp; 4871 4872 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4873 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4874 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4875 4876 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4877 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4878 4879 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4880 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4881 spll_func_cntl_3 |= SPLL_DITHEN; 4882 4883 if (pi->sclk_ss) { 4884 struct radeon_atom_ss ss; 4885 u32 vco_freq = engine_clock * dividers.post_div; 4886 4887 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4888 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4889 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4890 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4891 4892 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4893 cg_spll_spread_spectrum |= CLK_S(clk_s); 4894 cg_spll_spread_spectrum |= SSEN; 4895 4896 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4897 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4898 } 4899 } 4900 4901 sclk->sclk_value = engine_clock; 4902 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4903 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4904 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4905 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4906 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4907 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4908 4909 return 0; 4910 } 4911 4912 static int si_populate_sclk_value(struct radeon_device *rdev, 4913 u32 engine_clock, 4914 SISLANDS_SMC_SCLK_VALUE *sclk) 4915 { 4916 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4917 int ret; 4918 4919 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4920 if (!ret) { 4921 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4922 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4923 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4924 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4925 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4926 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4927 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4928 } 4929 4930 return ret; 4931 } 4932 4933 static int si_populate_mclk_value(struct radeon_device *rdev, 4934 u32 engine_clock, 4935 u32 memory_clock, 4936 SISLANDS_SMC_MCLK_VALUE *mclk, 4937 bool strobe_mode, 4938 bool dll_state_on) 4939 { 4940 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4941 struct si_power_info *si_pi = si_get_pi(rdev); 4942 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4943 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4944 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4945 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4946 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4947 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4948 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4949 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4950 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4951 struct atom_mpll_param mpll_param; 4952 int ret; 4953 4954 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4955 if (ret) 4956 return ret; 4957 4958 mpll_func_cntl &= ~BWCTRL_MASK; 4959 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4960 4961 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4962 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4963 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4964 4965 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4966 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4967 4968 if (pi->mem_gddr5) { 4969 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4970 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4971 YCLK_POST_DIV(mpll_param.post_div); 4972 } 4973 4974 if (pi->mclk_ss) { 4975 struct radeon_atom_ss ss; 4976 u32 freq_nom; 4977 u32 tmp; 4978 u32 reference_clock = rdev->clock.mpll.reference_freq; 4979 4980 if (pi->mem_gddr5) 4981 freq_nom = memory_clock * 4; 4982 else 4983 freq_nom = memory_clock * 2; 4984 4985 tmp = freq_nom / reference_clock; 4986 tmp = tmp * tmp; 4987 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4988 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4989 u32 clks = reference_clock * 5 / ss.rate; 4990 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4991 4992 mpll_ss1 &= ~CLKV_MASK; 4993 mpll_ss1 |= CLKV(clkv); 4994 4995 mpll_ss2 &= ~CLKS_MASK; 4996 mpll_ss2 |= CLKS(clks); 4997 } 4998 } 4999 5000 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 5001 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 5002 5003 if (dll_state_on) 5004 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 5005 else 5006 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5007 5008 mclk->mclk_value = cpu_to_be32(memory_clock); 5009 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5010 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5011 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5012 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5013 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5014 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5015 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5016 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5017 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5018 5019 return 0; 5020 } 5021 5022 static void si_populate_smc_sp(struct radeon_device *rdev, 5023 struct radeon_ps *radeon_state, 5024 SISLANDS_SMC_SWSTATE *smc_state) 5025 { 5026 struct ni_ps *ps = ni_get_ps(radeon_state); 5027 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5028 int i; 5029 5030 for (i = 0; i < ps->performance_level_count - 1; i++) 5031 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5032 5033 smc_state->levels[ps->performance_level_count - 1].bSP = 5034 cpu_to_be32(pi->psp); 5035 } 5036 5037 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 5038 struct rv7xx_pl *pl, 5039 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5040 { 5041 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5042 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5043 struct si_power_info *si_pi = si_get_pi(rdev); 5044 int ret; 5045 bool dll_state_on; 5046 u16 std_vddc; 5047 bool gmc_pg = false; 5048 5049 if (eg_pi->pcie_performance_request && 5050 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 5051 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5052 else 5053 level->gen2PCIE = (u8)pl->pcie_gen; 5054 5055 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 5056 if (ret) 5057 return ret; 5058 5059 level->mcFlags = 0; 5060 5061 if (pi->mclk_stutter_mode_threshold && 5062 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5063 !eg_pi->uvd_enabled && 5064 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5065 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5066 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5067 5068 if (gmc_pg) 5069 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5070 } 5071 5072 if (pi->mem_gddr5) { 5073 if (pl->mclk > pi->mclk_edc_enable_threshold) 5074 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5075 5076 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5077 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5078 5079 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5080 5081 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5082 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5083 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5084 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5085 else 5086 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5087 } else { 5088 dll_state_on = false; 5089 } 5090 } else { 5091 level->strobeMode = si_get_strobe_mode_settings(rdev, 5092 pl->mclk); 5093 5094 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5095 } 5096 5097 ret = si_populate_mclk_value(rdev, 5098 pl->sclk, 5099 pl->mclk, 5100 &level->mclk, 5101 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5102 if (ret) 5103 return ret; 5104 5105 ret = si_populate_voltage_value(rdev, 5106 &eg_pi->vddc_voltage_table, 5107 pl->vddc, &level->vddc); 5108 if (ret) 5109 return ret; 5110 5111 5112 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5113 if (ret) 5114 return ret; 5115 5116 ret = si_populate_std_voltage_value(rdev, std_vddc, 5117 level->vddc.index, &level->std_vddc); 5118 if (ret) 5119 return ret; 5120 5121 if (eg_pi->vddci_control) { 5122 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5123 pl->vddci, &level->vddci); 5124 if (ret) 5125 return ret; 5126 } 5127 5128 if (si_pi->vddc_phase_shed_control) { 5129 ret = si_populate_phase_shedding_value(rdev, 5130 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5131 pl->vddc, 5132 pl->sclk, 5133 pl->mclk, 5134 &level->vddc); 5135 if (ret) 5136 return ret; 5137 } 5138 5139 level->MaxPoweredUpCU = si_pi->max_cu; 5140 5141 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5142 5143 return ret; 5144 } 5145 5146 static int si_populate_smc_t(struct radeon_device *rdev, 5147 struct radeon_ps *radeon_state, 5148 SISLANDS_SMC_SWSTATE *smc_state) 5149 { 5150 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5151 struct ni_ps *state = ni_get_ps(radeon_state); 5152 u32 a_t; 5153 u32 t_l, t_h; 5154 u32 high_bsp; 5155 int i, ret; 5156 5157 if (state->performance_level_count >= 9) 5158 return -EINVAL; 5159 5160 if (state->performance_level_count < 2) { 5161 a_t = CG_R(0xffff) | CG_L(0); 5162 smc_state->levels[0].aT = cpu_to_be32(a_t); 5163 return 0; 5164 } 5165 5166 smc_state->levels[0].aT = cpu_to_be32(0); 5167 5168 for (i = 0; i <= state->performance_level_count - 2; i++) { 5169 ret = r600_calculate_at( 5170 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5171 100 * R600_AH_DFLT, 5172 state->performance_levels[i + 1].sclk, 5173 state->performance_levels[i].sclk, 5174 &t_l, 5175 &t_h); 5176 5177 if (ret) { 5178 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5179 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5180 } 5181 5182 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5183 a_t |= CG_R(t_l * pi->bsp / 20000); 5184 smc_state->levels[i].aT = cpu_to_be32(a_t); 5185 5186 high_bsp = (i == state->performance_level_count - 2) ? 5187 pi->pbsp : pi->bsp; 5188 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5189 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5190 } 5191 5192 return 0; 5193 } 5194 5195 static int si_disable_ulv(struct radeon_device *rdev) 5196 { 5197 struct si_power_info *si_pi = si_get_pi(rdev); 5198 struct si_ulv_param *ulv = &si_pi->ulv; 5199 5200 if (ulv->supported) 5201 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5202 0 : -EINVAL; 5203 5204 return 0; 5205 } 5206 5207 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5208 struct radeon_ps *radeon_state) 5209 { 5210 const struct si_power_info *si_pi = si_get_pi(rdev); 5211 const struct si_ulv_param *ulv = &si_pi->ulv; 5212 const struct ni_ps *state = ni_get_ps(radeon_state); 5213 int i; 5214 5215 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5216 return false; 5217 5218 /* XXX validate against display requirements! */ 5219 5220 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5221 if (rdev->clock.current_dispclk <= 5222 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5223 if (ulv->pl.vddc < 5224 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5225 return false; 5226 } 5227 } 5228 5229 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5230 return false; 5231 5232 return true; 5233 } 5234 5235 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5236 struct radeon_ps *radeon_new_state) 5237 { 5238 const struct si_power_info *si_pi = si_get_pi(rdev); 5239 const struct si_ulv_param *ulv = &si_pi->ulv; 5240 5241 if (ulv->supported) { 5242 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5243 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5244 0 : -EINVAL; 5245 } 5246 return 0; 5247 } 5248 5249 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5250 struct radeon_ps *radeon_state, 5251 SISLANDS_SMC_SWSTATE *smc_state) 5252 { 5253 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5254 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5255 struct si_power_info *si_pi = si_get_pi(rdev); 5256 struct ni_ps *state = ni_get_ps(radeon_state); 5257 int i, ret; 5258 u32 threshold; 5259 u32 sclk_in_sr = 1350; /* ??? */ 5260 5261 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5262 return -EINVAL; 5263 5264 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5265 5266 if (radeon_state->vclk && radeon_state->dclk) { 5267 eg_pi->uvd_enabled = true; 5268 if (eg_pi->smu_uvd_hs) 5269 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5270 } else { 5271 eg_pi->uvd_enabled = false; 5272 } 5273 5274 if (state->dc_compatible) 5275 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5276 5277 smc_state->levelCount = 0; 5278 for (i = 0; i < state->performance_level_count; i++) { 5279 if (eg_pi->sclk_deep_sleep) { 5280 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5281 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5282 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5283 else 5284 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5285 } 5286 } 5287 5288 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5289 &smc_state->levels[i]); 5290 smc_state->levels[i].arbRefreshState = 5291 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5292 5293 if (ret) 5294 return ret; 5295 5296 if (ni_pi->enable_power_containment) 5297 smc_state->levels[i].displayWatermark = 5298 (state->performance_levels[i].sclk < threshold) ? 5299 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5300 else 5301 smc_state->levels[i].displayWatermark = (i < 2) ? 5302 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5303 5304 if (eg_pi->dynamic_ac_timing) 5305 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5306 else 5307 smc_state->levels[i].ACIndex = 0; 5308 5309 smc_state->levelCount++; 5310 } 5311 5312 si_write_smc_soft_register(rdev, 5313 SI_SMC_SOFT_REGISTER_watermark_threshold, 5314 threshold / 512); 5315 5316 si_populate_smc_sp(rdev, radeon_state, smc_state); 5317 5318 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5319 if (ret) 5320 ni_pi->enable_power_containment = false; 5321 5322 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5323 if (ret) 5324 ni_pi->enable_sq_ramping = false; 5325 5326 return si_populate_smc_t(rdev, radeon_state, smc_state); 5327 } 5328 5329 static int si_upload_sw_state(struct radeon_device *rdev, 5330 struct radeon_ps *radeon_new_state) 5331 { 5332 struct si_power_info *si_pi = si_get_pi(rdev); 5333 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5334 int ret; 5335 u32 address = si_pi->state_table_start + 5336 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5337 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5338 ((new_state->performance_level_count - 1) * 5339 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5340 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5341 5342 memset(smc_state, 0, state_size); 5343 5344 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5345 if (ret) 5346 return ret; 5347 5348 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5349 state_size, si_pi->sram_end); 5350 5351 return ret; 5352 } 5353 5354 static int si_upload_ulv_state(struct radeon_device *rdev) 5355 { 5356 struct si_power_info *si_pi = si_get_pi(rdev); 5357 struct si_ulv_param *ulv = &si_pi->ulv; 5358 int ret = 0; 5359 5360 if (ulv->supported && ulv->pl.vddc) { 5361 u32 address = si_pi->state_table_start + 5362 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5363 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5364 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5365 5366 memset(smc_state, 0, state_size); 5367 5368 ret = si_populate_ulv_state(rdev, smc_state); 5369 if (!ret) 5370 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5371 state_size, si_pi->sram_end); 5372 } 5373 5374 return ret; 5375 } 5376 5377 static int si_upload_smc_data(struct radeon_device *rdev) 5378 { 5379 struct radeon_crtc *radeon_crtc = NULL; 5380 int i; 5381 5382 if (rdev->pm.dpm.new_active_crtc_count == 0) 5383 return 0; 5384 5385 for (i = 0; i < rdev->num_crtc; i++) { 5386 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5387 radeon_crtc = rdev->mode_info.crtcs[i]; 5388 break; 5389 } 5390 } 5391 5392 if (radeon_crtc == NULL) 5393 return 0; 5394 5395 if (radeon_crtc->line_time <= 0) 5396 return 0; 5397 5398 if (si_write_smc_soft_register(rdev, 5399 SI_SMC_SOFT_REGISTER_crtc_index, 5400 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5401 return 0; 5402 5403 if (si_write_smc_soft_register(rdev, 5404 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5405 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5406 return 0; 5407 5408 if (si_write_smc_soft_register(rdev, 5409 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5410 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5411 return 0; 5412 5413 return 0; 5414 } 5415 5416 static int si_set_mc_special_registers(struct radeon_device *rdev, 5417 struct si_mc_reg_table *table) 5418 { 5419 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5420 u8 i, j, k; 5421 u32 temp_reg; 5422 5423 for (i = 0, j = table->last; i < table->last; i++) { 5424 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5425 return -EINVAL; 5426 switch (table->mc_reg_address[i].s1 << 2) { 5427 case MC_SEQ_MISC1: 5428 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5429 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5430 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5431 for (k = 0; k < table->num_entries; k++) 5432 table->mc_reg_table_entry[k].mc_data[j] = 5433 ((temp_reg & 0xffff0000)) | 5434 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5435 j++; 5436 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5437 return -EINVAL; 5438 5439 temp_reg = RREG32(MC_PMG_CMD_MRS); 5440 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5441 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5442 for (k = 0; k < table->num_entries; k++) { 5443 table->mc_reg_table_entry[k].mc_data[j] = 5444 (temp_reg & 0xffff0000) | 5445 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5446 if (!pi->mem_gddr5) 5447 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5448 } 5449 j++; 5450 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5451 return -EINVAL; 5452 5453 if (!pi->mem_gddr5) { 5454 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5455 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5456 for (k = 0; k < table->num_entries; k++) 5457 table->mc_reg_table_entry[k].mc_data[j] = 5458 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5459 j++; 5460 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5461 return -EINVAL; 5462 } 5463 break; 5464 case MC_SEQ_RESERVE_M: 5465 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5466 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5467 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5468 for(k = 0; k < table->num_entries; k++) 5469 table->mc_reg_table_entry[k].mc_data[j] = 5470 (temp_reg & 0xffff0000) | 5471 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5472 j++; 5473 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5474 return -EINVAL; 5475 break; 5476 default: 5477 break; 5478 } 5479 } 5480 5481 table->last = j; 5482 5483 return 0; 5484 } 5485 5486 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5487 { 5488 bool result = true; 5489 5490 switch (in_reg) { 5491 case MC_SEQ_RAS_TIMING >> 2: 5492 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5493 break; 5494 case MC_SEQ_CAS_TIMING >> 2: 5495 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5496 break; 5497 case MC_SEQ_MISC_TIMING >> 2: 5498 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5499 break; 5500 case MC_SEQ_MISC_TIMING2 >> 2: 5501 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5502 break; 5503 case MC_SEQ_RD_CTL_D0 >> 2: 5504 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5505 break; 5506 case MC_SEQ_RD_CTL_D1 >> 2: 5507 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5508 break; 5509 case MC_SEQ_WR_CTL_D0 >> 2: 5510 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5511 break; 5512 case MC_SEQ_WR_CTL_D1 >> 2: 5513 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5514 break; 5515 case MC_PMG_CMD_EMRS >> 2: 5516 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5517 break; 5518 case MC_PMG_CMD_MRS >> 2: 5519 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5520 break; 5521 case MC_PMG_CMD_MRS1 >> 2: 5522 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5523 break; 5524 case MC_SEQ_PMG_TIMING >> 2: 5525 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5526 break; 5527 case MC_PMG_CMD_MRS2 >> 2: 5528 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5529 break; 5530 case MC_SEQ_WR_CTL_2 >> 2: 5531 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5532 break; 5533 default: 5534 result = false; 5535 break; 5536 } 5537 5538 return result; 5539 } 5540 5541 static void si_set_valid_flag(struct si_mc_reg_table *table) 5542 { 5543 u8 i, j; 5544 5545 for (i = 0; i < table->last; i++) { 5546 for (j = 1; j < table->num_entries; j++) { 5547 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5548 table->valid_flag |= 1 << i; 5549 break; 5550 } 5551 } 5552 } 5553 } 5554 5555 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5556 { 5557 u32 i; 5558 u16 address; 5559 5560 for (i = 0; i < table->last; i++) 5561 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5562 address : table->mc_reg_address[i].s1; 5563 5564 } 5565 5566 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5567 struct si_mc_reg_table *si_table) 5568 { 5569 u8 i, j; 5570 5571 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5572 return -EINVAL; 5573 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5574 return -EINVAL; 5575 5576 for (i = 0; i < table->last; i++) 5577 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5578 si_table->last = table->last; 5579 5580 for (i = 0; i < table->num_entries; i++) { 5581 si_table->mc_reg_table_entry[i].mclk_max = 5582 table->mc_reg_table_entry[i].mclk_max; 5583 for (j = 0; j < table->last; j++) { 5584 si_table->mc_reg_table_entry[i].mc_data[j] = 5585 table->mc_reg_table_entry[i].mc_data[j]; 5586 } 5587 } 5588 si_table->num_entries = table->num_entries; 5589 5590 return 0; 5591 } 5592 5593 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5594 { 5595 struct si_power_info *si_pi = si_get_pi(rdev); 5596 struct atom_mc_reg_table *table; 5597 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5598 u8 module_index = rv770_get_memory_module_index(rdev); 5599 int ret; 5600 5601 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5602 if (!table) 5603 return -ENOMEM; 5604 5605 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5606 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5607 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5608 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5609 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5610 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5611 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5612 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5613 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5614 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5615 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5616 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5617 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5618 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5619 5620 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5621 if (ret) 5622 goto init_mc_done; 5623 5624 ret = si_copy_vbios_mc_reg_table(table, si_table); 5625 if (ret) 5626 goto init_mc_done; 5627 5628 si_set_s0_mc_reg_index(si_table); 5629 5630 ret = si_set_mc_special_registers(rdev, si_table); 5631 if (ret) 5632 goto init_mc_done; 5633 5634 si_set_valid_flag(si_table); 5635 5636 init_mc_done: 5637 kfree(table); 5638 5639 return ret; 5640 5641 } 5642 5643 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5644 SMC_SIslands_MCRegisters *mc_reg_table) 5645 { 5646 struct si_power_info *si_pi = si_get_pi(rdev); 5647 u32 i, j; 5648 5649 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5650 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5651 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5652 break; 5653 mc_reg_table->address[i].s0 = 5654 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5655 mc_reg_table->address[i].s1 = 5656 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5657 i++; 5658 } 5659 } 5660 mc_reg_table->last = (u8)i; 5661 } 5662 5663 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5664 SMC_SIslands_MCRegisterSet *data, 5665 u32 num_entries, u32 valid_flag) 5666 { 5667 u32 i, j; 5668 5669 for(i = 0, j = 0; j < num_entries; j++) { 5670 if (valid_flag & (1 << j)) { 5671 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5672 i++; 5673 } 5674 } 5675 } 5676 5677 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5678 struct rv7xx_pl *pl, 5679 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5680 { 5681 struct si_power_info *si_pi = si_get_pi(rdev); 5682 u32 i = 0; 5683 5684 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5685 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5686 break; 5687 } 5688 5689 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5690 --i; 5691 5692 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5693 mc_reg_table_data, si_pi->mc_reg_table.last, 5694 si_pi->mc_reg_table.valid_flag); 5695 } 5696 5697 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5698 struct radeon_ps *radeon_state, 5699 SMC_SIslands_MCRegisters *mc_reg_table) 5700 { 5701 struct ni_ps *state = ni_get_ps(radeon_state); 5702 int i; 5703 5704 for (i = 0; i < state->performance_level_count; i++) { 5705 si_convert_mc_reg_table_entry_to_smc(rdev, 5706 &state->performance_levels[i], 5707 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5708 } 5709 } 5710 5711 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5712 struct radeon_ps *radeon_boot_state) 5713 { 5714 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5715 struct si_power_info *si_pi = si_get_pi(rdev); 5716 struct si_ulv_param *ulv = &si_pi->ulv; 5717 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5718 5719 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5720 5721 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5722 5723 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5724 5725 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5726 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5727 5728 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5729 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5730 si_pi->mc_reg_table.last, 5731 si_pi->mc_reg_table.valid_flag); 5732 5733 if (ulv->supported && ulv->pl.vddc != 0) 5734 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5735 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5736 else 5737 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5738 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5739 si_pi->mc_reg_table.last, 5740 si_pi->mc_reg_table.valid_flag); 5741 5742 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5743 5744 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5745 (u8 *)smc_mc_reg_table, 5746 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5747 } 5748 5749 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5750 struct radeon_ps *radeon_new_state) 5751 { 5752 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5753 struct si_power_info *si_pi = si_get_pi(rdev); 5754 u32 address = si_pi->mc_reg_table_start + 5755 offsetof(SMC_SIslands_MCRegisters, 5756 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5757 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5758 5759 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5760 5761 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5762 5763 5764 return si_copy_bytes_to_smc(rdev, address, 5765 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5766 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5767 si_pi->sram_end); 5768 5769 } 5770 5771 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5772 { 5773 if (enable) 5774 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5775 else 5776 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5777 } 5778 5779 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5780 struct radeon_ps *radeon_state) 5781 { 5782 struct ni_ps *state = ni_get_ps(radeon_state); 5783 int i; 5784 u16 pcie_speed, max_speed = 0; 5785 5786 for (i = 0; i < state->performance_level_count; i++) { 5787 pcie_speed = state->performance_levels[i].pcie_gen; 5788 if (max_speed < pcie_speed) 5789 max_speed = pcie_speed; 5790 } 5791 return max_speed; 5792 } 5793 5794 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5795 { 5796 u32 speed_cntl; 5797 5798 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5799 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5800 5801 return (u16)speed_cntl; 5802 } 5803 5804 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5805 struct radeon_ps *radeon_new_state, 5806 struct radeon_ps *radeon_current_state) 5807 { 5808 struct si_power_info *si_pi = si_get_pi(rdev); 5809 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5810 enum radeon_pcie_gen current_link_speed; 5811 5812 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5813 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5814 else 5815 current_link_speed = si_pi->force_pcie_gen; 5816 5817 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5818 si_pi->pspp_notify_required = false; 5819 if (target_link_speed > current_link_speed) { 5820 switch (target_link_speed) { 5821 #if defined(CONFIG_ACPI) 5822 case RADEON_PCIE_GEN3: 5823 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5824 break; 5825 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5826 if (current_link_speed == RADEON_PCIE_GEN2) 5827 break; 5828 case RADEON_PCIE_GEN2: 5829 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5830 break; 5831 #endif 5832 default: 5833 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5834 break; 5835 } 5836 } else { 5837 if (target_link_speed < current_link_speed) 5838 si_pi->pspp_notify_required = true; 5839 } 5840 } 5841 5842 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5843 struct radeon_ps *radeon_new_state, 5844 struct radeon_ps *radeon_current_state) 5845 { 5846 struct si_power_info *si_pi = si_get_pi(rdev); 5847 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5848 u8 request; 5849 5850 if (si_pi->pspp_notify_required) { 5851 if (target_link_speed == RADEON_PCIE_GEN3) 5852 request = PCIE_PERF_REQ_PECI_GEN3; 5853 else if (target_link_speed == RADEON_PCIE_GEN2) 5854 request = PCIE_PERF_REQ_PECI_GEN2; 5855 else 5856 request = PCIE_PERF_REQ_PECI_GEN1; 5857 5858 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5859 (si_get_current_pcie_speed(rdev) > 0)) 5860 return; 5861 5862 #if defined(CONFIG_ACPI) 5863 radeon_acpi_pcie_performance_request(rdev, request, false); 5864 #endif 5865 } 5866 } 5867 5868 #if 0 5869 static int si_ds_request(struct radeon_device *rdev, 5870 bool ds_status_on, u32 count_write) 5871 { 5872 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5873 5874 if (eg_pi->sclk_deep_sleep) { 5875 if (ds_status_on) 5876 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5877 PPSMC_Result_OK) ? 5878 0 : -EINVAL; 5879 else 5880 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5881 PPSMC_Result_OK) ? 0 : -EINVAL; 5882 } 5883 return 0; 5884 } 5885 #endif 5886 5887 static void si_set_max_cu_value(struct radeon_device *rdev) 5888 { 5889 struct si_power_info *si_pi = si_get_pi(rdev); 5890 5891 if (rdev->family == CHIP_VERDE) { 5892 switch (rdev->pdev->device) { 5893 case 0x6820: 5894 case 0x6825: 5895 case 0x6821: 5896 case 0x6823: 5897 case 0x6827: 5898 si_pi->max_cu = 10; 5899 break; 5900 case 0x682D: 5901 case 0x6824: 5902 case 0x682F: 5903 case 0x6826: 5904 si_pi->max_cu = 8; 5905 break; 5906 case 0x6828: 5907 case 0x6830: 5908 case 0x6831: 5909 case 0x6838: 5910 case 0x6839: 5911 case 0x683D: 5912 si_pi->max_cu = 10; 5913 break; 5914 case 0x683B: 5915 case 0x683F: 5916 case 0x6829: 5917 si_pi->max_cu = 8; 5918 break; 5919 default: 5920 si_pi->max_cu = 0; 5921 break; 5922 } 5923 } else { 5924 si_pi->max_cu = 0; 5925 } 5926 } 5927 5928 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5929 struct radeon_clock_voltage_dependency_table *table) 5930 { 5931 u32 i; 5932 int j; 5933 u16 leakage_voltage; 5934 5935 if (table) { 5936 for (i = 0; i < table->count; i++) { 5937 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5938 table->entries[i].v, 5939 &leakage_voltage)) { 5940 case 0: 5941 table->entries[i].v = leakage_voltage; 5942 break; 5943 case -EAGAIN: 5944 return -EINVAL; 5945 case -EINVAL: 5946 default: 5947 break; 5948 } 5949 } 5950 5951 for (j = (table->count - 2); j >= 0; j--) { 5952 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5953 table->entries[j].v : table->entries[j + 1].v; 5954 } 5955 } 5956 return 0; 5957 } 5958 5959 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5960 { 5961 int ret = 0; 5962 5963 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5964 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5965 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5966 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5967 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5968 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5969 return ret; 5970 } 5971 5972 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5973 struct radeon_ps *radeon_new_state, 5974 struct radeon_ps *radeon_current_state) 5975 { 5976 u32 lane_width; 5977 u32 new_lane_width = 5978 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5979 u32 current_lane_width = 5980 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5981 5982 if (new_lane_width != current_lane_width) { 5983 radeon_set_pcie_lanes(rdev, new_lane_width); 5984 lane_width = radeon_get_pcie_lanes(rdev); 5985 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5986 } 5987 } 5988 5989 static void si_set_vce_clock(struct radeon_device *rdev, 5990 struct radeon_ps *new_rps, 5991 struct radeon_ps *old_rps) 5992 { 5993 if ((old_rps->evclk != new_rps->evclk) || 5994 (old_rps->ecclk != new_rps->ecclk)) { 5995 /* turn the clocks on when encoding, off otherwise */ 5996 if (new_rps->evclk || new_rps->ecclk) 5997 vce_v1_0_enable_mgcg(rdev, false); 5998 else 5999 vce_v1_0_enable_mgcg(rdev, true); 6000 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 6001 } 6002 } 6003 6004 void si_dpm_setup_asic(struct radeon_device *rdev) 6005 { 6006 int r; 6007 6008 r = si_mc_load_microcode(rdev); 6009 if (r) 6010 DRM_ERROR("Failed to load MC firmware!\n"); 6011 rv770_get_memory_type(rdev); 6012 si_read_clock_registers(rdev); 6013 si_enable_acpi_power_management(rdev); 6014 } 6015 6016 static int si_thermal_enable_alert(struct radeon_device *rdev, 6017 bool enable) 6018 { 6019 u32 thermal_int = RREG32(CG_THERMAL_INT); 6020 6021 if (enable) { 6022 PPSMC_Result result; 6023 6024 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 6025 WREG32(CG_THERMAL_INT, thermal_int); 6026 rdev->irq.dpm_thermal = false; 6027 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 6028 if (result != PPSMC_Result_OK) { 6029 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6030 return -EINVAL; 6031 } 6032 } else { 6033 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 6034 WREG32(CG_THERMAL_INT, thermal_int); 6035 rdev->irq.dpm_thermal = true; 6036 } 6037 6038 return 0; 6039 } 6040 6041 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 6042 int min_temp, int max_temp) 6043 { 6044 int low_temp = 0 * 1000; 6045 int high_temp = 255 * 1000; 6046 6047 if (low_temp < min_temp) 6048 low_temp = min_temp; 6049 if (high_temp > max_temp) 6050 high_temp = max_temp; 6051 if (high_temp < low_temp) { 6052 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6053 return -EINVAL; 6054 } 6055 6056 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6057 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6058 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6059 6060 rdev->pm.dpm.thermal.min_temp = low_temp; 6061 rdev->pm.dpm.thermal.max_temp = high_temp; 6062 6063 return 0; 6064 } 6065 6066 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6067 { 6068 struct si_power_info *si_pi = si_get_pi(rdev); 6069 u32 tmp; 6070 6071 if (si_pi->fan_ctrl_is_in_default_mode) { 6072 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6073 si_pi->fan_ctrl_default_mode = tmp; 6074 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6075 si_pi->t_min = tmp; 6076 si_pi->fan_ctrl_is_in_default_mode = false; 6077 } 6078 6079 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6080 tmp |= TMIN(0); 6081 WREG32(CG_FDO_CTRL2, tmp); 6082 6083 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6084 tmp |= FDO_PWM_MODE(mode); 6085 WREG32(CG_FDO_CTRL2, tmp); 6086 } 6087 6088 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6089 { 6090 struct si_power_info *si_pi = si_get_pi(rdev); 6091 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6092 u32 duty100; 6093 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6094 u16 fdo_min, slope1, slope2; 6095 u32 reference_clock, tmp; 6096 int ret; 6097 u64 tmp64; 6098 6099 if (!si_pi->fan_table_start) { 6100 rdev->pm.dpm.fan.ucode_fan_control = false; 6101 return 0; 6102 } 6103 6104 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6105 6106 if (duty100 == 0) { 6107 rdev->pm.dpm.fan.ucode_fan_control = false; 6108 return 0; 6109 } 6110 6111 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6112 do_div(tmp64, 10000); 6113 fdo_min = (u16)tmp64; 6114 6115 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6116 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6117 6118 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6119 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6120 6121 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6122 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6123 6124 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6125 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6126 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6127 6128 fan_table.slope1 = cpu_to_be16(slope1); 6129 fan_table.slope2 = cpu_to_be16(slope2); 6130 6131 fan_table.fdo_min = cpu_to_be16(fdo_min); 6132 6133 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6134 6135 fan_table.hys_up = cpu_to_be16(1); 6136 6137 fan_table.hys_slope = cpu_to_be16(1); 6138 6139 fan_table.temp_resp_lim = cpu_to_be16(5); 6140 6141 reference_clock = radeon_get_xclk(rdev); 6142 6143 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6144 reference_clock) / 1600); 6145 6146 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6147 6148 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6149 fan_table.temp_src = (uint8_t)tmp; 6150 6151 ret = si_copy_bytes_to_smc(rdev, 6152 si_pi->fan_table_start, 6153 (u8 *)(&fan_table), 6154 sizeof(fan_table), 6155 si_pi->sram_end); 6156 6157 if (ret) { 6158 DRM_ERROR("Failed to load fan table to the SMC."); 6159 rdev->pm.dpm.fan.ucode_fan_control = false; 6160 } 6161 6162 return 0; 6163 } 6164 6165 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6166 { 6167 struct si_power_info *si_pi = si_get_pi(rdev); 6168 PPSMC_Result ret; 6169 6170 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6171 if (ret == PPSMC_Result_OK) { 6172 si_pi->fan_is_controlled_by_smc = true; 6173 return 0; 6174 } else { 6175 return -EINVAL; 6176 } 6177 } 6178 6179 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6180 { 6181 struct si_power_info *si_pi = si_get_pi(rdev); 6182 PPSMC_Result ret; 6183 6184 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6185 6186 if (ret == PPSMC_Result_OK) { 6187 si_pi->fan_is_controlled_by_smc = false; 6188 return 0; 6189 } else { 6190 return -EINVAL; 6191 } 6192 } 6193 6194 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6195 u32 *speed) 6196 { 6197 u32 duty, duty100; 6198 u64 tmp64; 6199 6200 if (rdev->pm.no_fan) 6201 return -ENOENT; 6202 6203 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6204 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6205 6206 if (duty100 == 0) 6207 return -EINVAL; 6208 6209 tmp64 = (u64)duty * 100; 6210 do_div(tmp64, duty100); 6211 *speed = (u32)tmp64; 6212 6213 if (*speed > 100) 6214 *speed = 100; 6215 6216 return 0; 6217 } 6218 6219 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6220 u32 speed) 6221 { 6222 struct si_power_info *si_pi = si_get_pi(rdev); 6223 u32 tmp; 6224 u32 duty, duty100; 6225 u64 tmp64; 6226 6227 if (rdev->pm.no_fan) 6228 return -ENOENT; 6229 6230 if (si_pi->fan_is_controlled_by_smc) 6231 return -EINVAL; 6232 6233 if (speed > 100) 6234 return -EINVAL; 6235 6236 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6237 6238 if (duty100 == 0) 6239 return -EINVAL; 6240 6241 tmp64 = (u64)speed * duty100; 6242 do_div(tmp64, 100); 6243 duty = (u32)tmp64; 6244 6245 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6246 tmp |= FDO_STATIC_DUTY(duty); 6247 WREG32(CG_FDO_CTRL0, tmp); 6248 6249 return 0; 6250 } 6251 6252 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6253 { 6254 if (mode) { 6255 /* stop auto-manage */ 6256 if (rdev->pm.dpm.fan.ucode_fan_control) 6257 si_fan_ctrl_stop_smc_fan_control(rdev); 6258 si_fan_ctrl_set_static_mode(rdev, mode); 6259 } else { 6260 /* restart auto-manage */ 6261 if (rdev->pm.dpm.fan.ucode_fan_control) 6262 si_thermal_start_smc_fan_control(rdev); 6263 else 6264 si_fan_ctrl_set_default_mode(rdev); 6265 } 6266 } 6267 6268 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6269 { 6270 struct si_power_info *si_pi = si_get_pi(rdev); 6271 u32 tmp; 6272 6273 if (si_pi->fan_is_controlled_by_smc) 6274 return 0; 6275 6276 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6277 return (tmp >> FDO_PWM_MODE_SHIFT); 6278 } 6279 6280 #if 0 6281 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6282 u32 *speed) 6283 { 6284 u32 tach_period; 6285 u32 xclk = radeon_get_xclk(rdev); 6286 6287 if (rdev->pm.no_fan) 6288 return -ENOENT; 6289 6290 if (rdev->pm.fan_pulses_per_revolution == 0) 6291 return -ENOENT; 6292 6293 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6294 if (tach_period == 0) 6295 return -ENOENT; 6296 6297 *speed = 60 * xclk * 10000 / tach_period; 6298 6299 return 0; 6300 } 6301 6302 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6303 u32 speed) 6304 { 6305 u32 tach_period, tmp; 6306 u32 xclk = radeon_get_xclk(rdev); 6307 6308 if (rdev->pm.no_fan) 6309 return -ENOENT; 6310 6311 if (rdev->pm.fan_pulses_per_revolution == 0) 6312 return -ENOENT; 6313 6314 if ((speed < rdev->pm.fan_min_rpm) || 6315 (speed > rdev->pm.fan_max_rpm)) 6316 return -EINVAL; 6317 6318 if (rdev->pm.dpm.fan.ucode_fan_control) 6319 si_fan_ctrl_stop_smc_fan_control(rdev); 6320 6321 tach_period = 60 * xclk * 10000 / (8 * speed); 6322 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6323 tmp |= TARGET_PERIOD(tach_period); 6324 WREG32(CG_TACH_CTRL, tmp); 6325 6326 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6327 6328 return 0; 6329 } 6330 #endif 6331 6332 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6333 { 6334 struct si_power_info *si_pi = si_get_pi(rdev); 6335 u32 tmp; 6336 6337 if (!si_pi->fan_ctrl_is_in_default_mode) { 6338 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6339 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6340 WREG32(CG_FDO_CTRL2, tmp); 6341 6342 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6343 tmp |= TMIN(si_pi->t_min); 6344 WREG32(CG_FDO_CTRL2, tmp); 6345 si_pi->fan_ctrl_is_in_default_mode = true; 6346 } 6347 } 6348 6349 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6350 { 6351 if (rdev->pm.dpm.fan.ucode_fan_control) { 6352 si_fan_ctrl_start_smc_fan_control(rdev); 6353 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6354 } 6355 } 6356 6357 static void si_thermal_initialize(struct radeon_device *rdev) 6358 { 6359 u32 tmp; 6360 6361 if (rdev->pm.fan_pulses_per_revolution) { 6362 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6363 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6364 WREG32(CG_TACH_CTRL, tmp); 6365 } 6366 6367 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6368 tmp |= TACH_PWM_RESP_RATE(0x28); 6369 WREG32(CG_FDO_CTRL2, tmp); 6370 } 6371 6372 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6373 { 6374 int ret; 6375 6376 si_thermal_initialize(rdev); 6377 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6378 if (ret) 6379 return ret; 6380 ret = si_thermal_enable_alert(rdev, true); 6381 if (ret) 6382 return ret; 6383 if (rdev->pm.dpm.fan.ucode_fan_control) { 6384 ret = si_halt_smc(rdev); 6385 if (ret) 6386 return ret; 6387 ret = si_thermal_setup_fan_table(rdev); 6388 if (ret) 6389 return ret; 6390 ret = si_resume_smc(rdev); 6391 if (ret) 6392 return ret; 6393 si_thermal_start_smc_fan_control(rdev); 6394 } 6395 6396 return 0; 6397 } 6398 6399 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6400 { 6401 if (!rdev->pm.no_fan) { 6402 si_fan_ctrl_set_default_mode(rdev); 6403 si_fan_ctrl_stop_smc_fan_control(rdev); 6404 } 6405 } 6406 6407 int si_dpm_enable(struct radeon_device *rdev) 6408 { 6409 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6410 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6411 struct si_power_info *si_pi = si_get_pi(rdev); 6412 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6413 int ret; 6414 6415 if (si_is_smc_running(rdev)) 6416 return -EINVAL; 6417 if (pi->voltage_control || si_pi->voltage_control_svi2) 6418 si_enable_voltage_control(rdev, true); 6419 if (pi->mvdd_control) 6420 si_get_mvdd_configuration(rdev); 6421 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6422 ret = si_construct_voltage_tables(rdev); 6423 if (ret) { 6424 DRM_ERROR("si_construct_voltage_tables failed\n"); 6425 return ret; 6426 } 6427 } 6428 if (eg_pi->dynamic_ac_timing) { 6429 ret = si_initialize_mc_reg_table(rdev); 6430 if (ret) 6431 eg_pi->dynamic_ac_timing = false; 6432 } 6433 if (pi->dynamic_ss) 6434 si_enable_spread_spectrum(rdev, true); 6435 if (pi->thermal_protection) 6436 si_enable_thermal_protection(rdev, true); 6437 si_setup_bsp(rdev); 6438 si_program_git(rdev); 6439 si_program_tp(rdev); 6440 si_program_tpp(rdev); 6441 si_program_sstp(rdev); 6442 si_enable_display_gap(rdev); 6443 si_program_vc(rdev); 6444 ret = si_upload_firmware(rdev); 6445 if (ret) { 6446 DRM_ERROR("si_upload_firmware failed\n"); 6447 return ret; 6448 } 6449 ret = si_process_firmware_header(rdev); 6450 if (ret) { 6451 DRM_ERROR("si_process_firmware_header failed\n"); 6452 return ret; 6453 } 6454 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6455 if (ret) { 6456 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6457 return ret; 6458 } 6459 ret = si_init_smc_table(rdev); 6460 if (ret) { 6461 DRM_ERROR("si_init_smc_table failed\n"); 6462 return ret; 6463 } 6464 ret = si_init_smc_spll_table(rdev); 6465 if (ret) { 6466 DRM_ERROR("si_init_smc_spll_table failed\n"); 6467 return ret; 6468 } 6469 ret = si_init_arb_table_index(rdev); 6470 if (ret) { 6471 DRM_ERROR("si_init_arb_table_index failed\n"); 6472 return ret; 6473 } 6474 if (eg_pi->dynamic_ac_timing) { 6475 ret = si_populate_mc_reg_table(rdev, boot_ps); 6476 if (ret) { 6477 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6478 return ret; 6479 } 6480 } 6481 ret = si_initialize_smc_cac_tables(rdev); 6482 if (ret) { 6483 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6484 return ret; 6485 } 6486 ret = si_initialize_hardware_cac_manager(rdev); 6487 if (ret) { 6488 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6489 return ret; 6490 } 6491 ret = si_initialize_smc_dte_tables(rdev); 6492 if (ret) { 6493 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6494 return ret; 6495 } 6496 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6497 if (ret) { 6498 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6499 return ret; 6500 } 6501 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6502 if (ret) { 6503 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6504 return ret; 6505 } 6506 si_program_response_times(rdev); 6507 si_program_ds_registers(rdev); 6508 si_dpm_start_smc(rdev); 6509 ret = si_notify_smc_display_change(rdev, false); 6510 if (ret) { 6511 DRM_ERROR("si_notify_smc_display_change failed\n"); 6512 return ret; 6513 } 6514 si_enable_sclk_control(rdev, true); 6515 si_start_dpm(rdev); 6516 6517 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6518 6519 si_thermal_start_thermal_controller(rdev); 6520 6521 ni_update_current_ps(rdev, boot_ps); 6522 6523 return 0; 6524 } 6525 6526 static int si_set_temperature_range(struct radeon_device *rdev) 6527 { 6528 int ret; 6529 6530 ret = si_thermal_enable_alert(rdev, false); 6531 if (ret) 6532 return ret; 6533 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6534 if (ret) 6535 return ret; 6536 ret = si_thermal_enable_alert(rdev, true); 6537 if (ret) 6538 return ret; 6539 6540 return ret; 6541 } 6542 6543 int si_dpm_late_enable(struct radeon_device *rdev) 6544 { 6545 int ret; 6546 6547 ret = si_set_temperature_range(rdev); 6548 if (ret) 6549 return ret; 6550 6551 return ret; 6552 } 6553 6554 void si_dpm_disable(struct radeon_device *rdev) 6555 { 6556 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6557 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6558 6559 if (!si_is_smc_running(rdev)) 6560 return; 6561 si_thermal_stop_thermal_controller(rdev); 6562 si_disable_ulv(rdev); 6563 si_clear_vc(rdev); 6564 if (pi->thermal_protection) 6565 si_enable_thermal_protection(rdev, false); 6566 si_enable_power_containment(rdev, boot_ps, false); 6567 si_enable_smc_cac(rdev, boot_ps, false); 6568 si_enable_spread_spectrum(rdev, false); 6569 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6570 si_stop_dpm(rdev); 6571 si_reset_to_default(rdev); 6572 si_dpm_stop_smc(rdev); 6573 si_force_switch_to_arb_f0(rdev); 6574 6575 ni_update_current_ps(rdev, boot_ps); 6576 } 6577 6578 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6579 { 6580 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6581 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6582 struct radeon_ps *new_ps = &requested_ps; 6583 6584 ni_update_requested_ps(rdev, new_ps); 6585 6586 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6587 6588 return 0; 6589 } 6590 6591 static int si_power_control_set_level(struct radeon_device *rdev) 6592 { 6593 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6594 int ret; 6595 6596 ret = si_restrict_performance_levels_before_switch(rdev); 6597 if (ret) 6598 return ret; 6599 ret = si_halt_smc(rdev); 6600 if (ret) 6601 return ret; 6602 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6603 if (ret) 6604 return ret; 6605 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6606 if (ret) 6607 return ret; 6608 ret = si_resume_smc(rdev); 6609 if (ret) 6610 return ret; 6611 ret = si_set_sw_state(rdev); 6612 if (ret) 6613 return ret; 6614 return 0; 6615 } 6616 6617 int si_dpm_set_power_state(struct radeon_device *rdev) 6618 { 6619 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6620 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6621 struct radeon_ps *old_ps = &eg_pi->current_rps; 6622 int ret; 6623 6624 ret = si_disable_ulv(rdev); 6625 if (ret) { 6626 DRM_ERROR("si_disable_ulv failed\n"); 6627 return ret; 6628 } 6629 ret = si_restrict_performance_levels_before_switch(rdev); 6630 if (ret) { 6631 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6632 return ret; 6633 } 6634 if (eg_pi->pcie_performance_request) 6635 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6636 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6637 ret = si_enable_power_containment(rdev, new_ps, false); 6638 if (ret) { 6639 DRM_ERROR("si_enable_power_containment failed\n"); 6640 return ret; 6641 } 6642 ret = si_enable_smc_cac(rdev, new_ps, false); 6643 if (ret) { 6644 DRM_ERROR("si_enable_smc_cac failed\n"); 6645 return ret; 6646 } 6647 ret = si_halt_smc(rdev); 6648 if (ret) { 6649 DRM_ERROR("si_halt_smc failed\n"); 6650 return ret; 6651 } 6652 ret = si_upload_sw_state(rdev, new_ps); 6653 if (ret) { 6654 DRM_ERROR("si_upload_sw_state failed\n"); 6655 return ret; 6656 } 6657 ret = si_upload_smc_data(rdev); 6658 if (ret) { 6659 DRM_ERROR("si_upload_smc_data failed\n"); 6660 return ret; 6661 } 6662 ret = si_upload_ulv_state(rdev); 6663 if (ret) { 6664 DRM_ERROR("si_upload_ulv_state failed\n"); 6665 return ret; 6666 } 6667 if (eg_pi->dynamic_ac_timing) { 6668 ret = si_upload_mc_reg_table(rdev, new_ps); 6669 if (ret) { 6670 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6671 return ret; 6672 } 6673 } 6674 ret = si_program_memory_timing_parameters(rdev, new_ps); 6675 if (ret) { 6676 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6677 return ret; 6678 } 6679 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6680 6681 ret = si_resume_smc(rdev); 6682 if (ret) { 6683 DRM_ERROR("si_resume_smc failed\n"); 6684 return ret; 6685 } 6686 ret = si_set_sw_state(rdev); 6687 if (ret) { 6688 DRM_ERROR("si_set_sw_state failed\n"); 6689 return ret; 6690 } 6691 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6692 si_set_vce_clock(rdev, new_ps, old_ps); 6693 if (eg_pi->pcie_performance_request) 6694 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6695 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6696 if (ret) { 6697 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6698 return ret; 6699 } 6700 ret = si_enable_smc_cac(rdev, new_ps, true); 6701 if (ret) { 6702 DRM_ERROR("si_enable_smc_cac failed\n"); 6703 return ret; 6704 } 6705 ret = si_enable_power_containment(rdev, new_ps, true); 6706 if (ret) { 6707 DRM_ERROR("si_enable_power_containment failed\n"); 6708 return ret; 6709 } 6710 6711 ret = si_power_control_set_level(rdev); 6712 if (ret) { 6713 DRM_ERROR("si_power_control_set_level failed\n"); 6714 return ret; 6715 } 6716 6717 return 0; 6718 } 6719 6720 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6721 { 6722 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6723 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6724 6725 ni_update_current_ps(rdev, new_ps); 6726 } 6727 6728 #if 0 6729 void si_dpm_reset_asic(struct radeon_device *rdev) 6730 { 6731 si_restrict_performance_levels_before_switch(rdev); 6732 si_disable_ulv(rdev); 6733 si_set_boot_state(rdev); 6734 } 6735 #endif 6736 6737 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6738 { 6739 si_program_display_gap(rdev); 6740 } 6741 6742 union power_info { 6743 struct _ATOM_POWERPLAY_INFO info; 6744 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6745 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6746 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6747 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6748 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6749 }; 6750 6751 union pplib_clock_info { 6752 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6753 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6754 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6755 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6756 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6757 }; 6758 6759 union pplib_power_state { 6760 struct _ATOM_PPLIB_STATE v1; 6761 struct _ATOM_PPLIB_STATE_V2 v2; 6762 }; 6763 6764 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6765 struct radeon_ps *rps, 6766 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6767 u8 table_rev) 6768 { 6769 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6770 rps->class = le16_to_cpu(non_clock_info->usClassification); 6771 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6772 6773 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6774 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6775 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6776 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6777 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6778 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6779 } else { 6780 rps->vclk = 0; 6781 rps->dclk = 0; 6782 } 6783 6784 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6785 rdev->pm.dpm.boot_ps = rps; 6786 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6787 rdev->pm.dpm.uvd_ps = rps; 6788 } 6789 6790 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6791 struct radeon_ps *rps, int index, 6792 union pplib_clock_info *clock_info) 6793 { 6794 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6795 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6796 struct si_power_info *si_pi = si_get_pi(rdev); 6797 struct ni_ps *ps = ni_get_ps(rps); 6798 u16 leakage_voltage; 6799 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6800 int ret; 6801 6802 ps->performance_level_count = index + 1; 6803 6804 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6805 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6806 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6807 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6808 6809 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6810 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6811 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6812 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6813 si_pi->sys_pcie_mask, 6814 si_pi->boot_pcie_gen, 6815 clock_info->si.ucPCIEGen); 6816 6817 /* patch up vddc if necessary */ 6818 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6819 &leakage_voltage); 6820 if (ret == 0) 6821 pl->vddc = leakage_voltage; 6822 6823 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6824 pi->acpi_vddc = pl->vddc; 6825 eg_pi->acpi_vddci = pl->vddci; 6826 si_pi->acpi_pcie_gen = pl->pcie_gen; 6827 } 6828 6829 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6830 index == 0) { 6831 /* XXX disable for A0 tahiti */ 6832 si_pi->ulv.supported = false; 6833 si_pi->ulv.pl = *pl; 6834 si_pi->ulv.one_pcie_lane_in_ulv = false; 6835 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6836 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6837 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6838 } 6839 6840 if (pi->min_vddc_in_table > pl->vddc) 6841 pi->min_vddc_in_table = pl->vddc; 6842 6843 if (pi->max_vddc_in_table < pl->vddc) 6844 pi->max_vddc_in_table = pl->vddc; 6845 6846 /* patch up boot state */ 6847 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6848 u16 vddc, vddci, mvdd; 6849 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6850 pl->mclk = rdev->clock.default_mclk; 6851 pl->sclk = rdev->clock.default_sclk; 6852 pl->vddc = vddc; 6853 pl->vddci = vddci; 6854 si_pi->mvdd_bootup_value = mvdd; 6855 } 6856 6857 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6858 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6859 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6860 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6861 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6862 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6863 } 6864 } 6865 6866 static int si_parse_power_table(struct radeon_device *rdev) 6867 { 6868 struct radeon_mode_info *mode_info = &rdev->mode_info; 6869 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6870 union pplib_power_state *power_state; 6871 int i, j, k, non_clock_array_index, clock_array_index; 6872 union pplib_clock_info *clock_info; 6873 struct _StateArray *state_array; 6874 struct _ClockInfoArray *clock_info_array; 6875 struct _NonClockInfoArray *non_clock_info_array; 6876 union power_info *power_info; 6877 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6878 u16 data_offset; 6879 u8 frev, crev; 6880 u8 *power_state_offset; 6881 struct ni_ps *ps; 6882 6883 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6884 &frev, &crev, &data_offset)) 6885 return -EINVAL; 6886 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6887 6888 state_array = (struct _StateArray *) 6889 (mode_info->atom_context->bios + data_offset + 6890 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6891 clock_info_array = (struct _ClockInfoArray *) 6892 (mode_info->atom_context->bios + data_offset + 6893 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6894 non_clock_info_array = (struct _NonClockInfoArray *) 6895 (mode_info->atom_context->bios + data_offset + 6896 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6897 6898 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6899 state_array->ucNumEntries, GFP_KERNEL); 6900 if (!rdev->pm.dpm.ps) 6901 return -ENOMEM; 6902 power_state_offset = (u8 *)state_array->states; 6903 for (i = 0; i < state_array->ucNumEntries; i++) { 6904 u8 *idx; 6905 power_state = (union pplib_power_state *)power_state_offset; 6906 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6907 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6908 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6909 if (!rdev->pm.power_state[i].clock_info) 6910 return -EINVAL; 6911 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6912 if (ps == NULL) { 6913 kfree(rdev->pm.dpm.ps); 6914 return -ENOMEM; 6915 } 6916 rdev->pm.dpm.ps[i].ps_priv = ps; 6917 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6918 non_clock_info, 6919 non_clock_info_array->ucEntrySize); 6920 k = 0; 6921 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6922 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6923 clock_array_index = idx[j]; 6924 if (clock_array_index >= clock_info_array->ucNumEntries) 6925 continue; 6926 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6927 break; 6928 clock_info = (union pplib_clock_info *) 6929 ((u8 *)&clock_info_array->clockInfo[0] + 6930 (clock_array_index * clock_info_array->ucEntrySize)); 6931 si_parse_pplib_clock_info(rdev, 6932 &rdev->pm.dpm.ps[i], k, 6933 clock_info); 6934 k++; 6935 } 6936 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6937 } 6938 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6939 6940 /* fill in the vce power states */ 6941 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6942 u32 sclk, mclk; 6943 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6944 clock_info = (union pplib_clock_info *) 6945 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6946 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6947 sclk |= clock_info->si.ucEngineClockHigh << 16; 6948 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6949 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6950 rdev->pm.dpm.vce_states[i].sclk = sclk; 6951 rdev->pm.dpm.vce_states[i].mclk = mclk; 6952 } 6953 6954 return 0; 6955 } 6956 6957 int si_dpm_init(struct radeon_device *rdev) 6958 { 6959 struct rv7xx_power_info *pi; 6960 struct evergreen_power_info *eg_pi; 6961 struct ni_power_info *ni_pi; 6962 struct si_power_info *si_pi; 6963 struct atom_clock_dividers dividers; 6964 int ret; 6965 u32 mask; 6966 6967 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6968 if (si_pi == NULL) 6969 return -ENOMEM; 6970 rdev->pm.dpm.priv = si_pi; 6971 ni_pi = &si_pi->ni; 6972 eg_pi = &ni_pi->eg; 6973 pi = &eg_pi->rv7xx; 6974 6975 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6976 if (ret) 6977 si_pi->sys_pcie_mask = 0; 6978 else 6979 si_pi->sys_pcie_mask = mask; 6980 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6981 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6982 6983 si_set_max_cu_value(rdev); 6984 6985 rv770_get_max_vddc(rdev); 6986 si_get_leakage_vddc(rdev); 6987 si_patch_dependency_tables_based_on_leakage(rdev); 6988 6989 pi->acpi_vddc = 0; 6990 eg_pi->acpi_vddci = 0; 6991 pi->min_vddc_in_table = 0; 6992 pi->max_vddc_in_table = 0; 6993 6994 ret = r600_get_platform_caps(rdev); 6995 if (ret) 6996 return ret; 6997 6998 ret = r600_parse_extended_power_table(rdev); 6999 if (ret) 7000 return ret; 7001 7002 ret = si_parse_power_table(rdev); 7003 if (ret) 7004 return ret; 7005 7006 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7007 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 7008 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 7009 r600_free_extended_power_table(rdev); 7010 return -ENOMEM; 7011 } 7012 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7013 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7014 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7015 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7016 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7017 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7018 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7019 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7020 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7021 7022 if (rdev->pm.dpm.voltage_response_time == 0) 7023 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7024 if (rdev->pm.dpm.backbias_response_time == 0) 7025 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7026 7027 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 7028 0, false, ÷rs); 7029 if (ret) 7030 pi->ref_div = dividers.ref_div + 1; 7031 else 7032 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7033 7034 eg_pi->smu_uvd_hs = false; 7035 7036 pi->mclk_strobe_mode_threshold = 40000; 7037 if (si_is_special_1gb_platform(rdev)) 7038 pi->mclk_stutter_mode_threshold = 0; 7039 else 7040 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7041 pi->mclk_edc_enable_threshold = 40000; 7042 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7043 7044 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7045 7046 pi->voltage_control = 7047 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7048 VOLTAGE_OBJ_GPIO_LUT); 7049 if (!pi->voltage_control) { 7050 si_pi->voltage_control_svi2 = 7051 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7052 VOLTAGE_OBJ_SVID2); 7053 if (si_pi->voltage_control_svi2) 7054 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7055 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7056 } 7057 7058 pi->mvdd_control = 7059 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7060 VOLTAGE_OBJ_GPIO_LUT); 7061 7062 eg_pi->vddci_control = 7063 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7064 VOLTAGE_OBJ_GPIO_LUT); 7065 if (!eg_pi->vddci_control) 7066 si_pi->vddci_control_svi2 = 7067 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7068 VOLTAGE_OBJ_SVID2); 7069 7070 si_pi->vddc_phase_shed_control = 7071 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7072 VOLTAGE_OBJ_PHASE_LUT); 7073 7074 rv770_get_engine_memory_ss(rdev); 7075 7076 pi->asi = RV770_ASI_DFLT; 7077 pi->pasi = CYPRESS_HASI_DFLT; 7078 pi->vrc = SISLANDS_VRC_DFLT; 7079 7080 pi->gfx_clock_gating = true; 7081 7082 eg_pi->sclk_deep_sleep = true; 7083 si_pi->sclk_deep_sleep_above_low = false; 7084 7085 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7086 pi->thermal_protection = true; 7087 else 7088 pi->thermal_protection = false; 7089 7090 eg_pi->dynamic_ac_timing = true; 7091 7092 eg_pi->light_sleep = true; 7093 #if defined(CONFIG_ACPI) 7094 eg_pi->pcie_performance_request = 7095 radeon_acpi_is_pcie_performance_request_supported(rdev); 7096 #else 7097 eg_pi->pcie_performance_request = false; 7098 #endif 7099 7100 si_pi->sram_end = SMC_RAM_END; 7101 7102 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7103 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7104 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7105 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7106 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7107 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7108 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7109 7110 si_initialize_powertune_defaults(rdev); 7111 7112 /* make sure dc limits are valid */ 7113 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7114 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7115 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7116 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7117 7118 si_pi->fan_ctrl_is_in_default_mode = true; 7119 7120 return 0; 7121 } 7122 7123 void si_dpm_fini(struct radeon_device *rdev) 7124 { 7125 int i; 7126 7127 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7128 kfree(rdev->pm.dpm.ps[i].ps_priv); 7129 } 7130 kfree(rdev->pm.dpm.ps); 7131 kfree(rdev->pm.dpm.priv); 7132 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7133 r600_free_extended_power_table(rdev); 7134 } 7135 7136 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7137 struct seq_file *m) 7138 { 7139 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7140 struct radeon_ps *rps = &eg_pi->current_rps; 7141 struct ni_ps *ps = ni_get_ps(rps); 7142 struct rv7xx_pl *pl; 7143 u32 current_index = 7144 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7145 CURRENT_STATE_INDEX_SHIFT; 7146 7147 if (current_index >= ps->performance_level_count) { 7148 seq_printf(m, "invalid dpm profile %d\n", current_index); 7149 } else { 7150 pl = &ps->performance_levels[current_index]; 7151 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7152 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7153 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7154 } 7155 } 7156 7157 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7158 { 7159 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7160 struct radeon_ps *rps = &eg_pi->current_rps; 7161 struct ni_ps *ps = ni_get_ps(rps); 7162 struct rv7xx_pl *pl; 7163 u32 current_index = 7164 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7165 CURRENT_STATE_INDEX_SHIFT; 7166 7167 if (current_index >= ps->performance_level_count) { 7168 return 0; 7169 } else { 7170 pl = &ps->performance_levels[current_index]; 7171 return pl->sclk; 7172 } 7173 } 7174 7175 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7176 { 7177 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7178 struct radeon_ps *rps = &eg_pi->current_rps; 7179 struct ni_ps *ps = ni_get_ps(rps); 7180 struct rv7xx_pl *pl; 7181 u32 current_index = 7182 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7183 CURRENT_STATE_INDEX_SHIFT; 7184 7185 if (current_index >= ps->performance_level_count) { 7186 return 0; 7187 } else { 7188 pl = &ps->performance_levels[current_index]; 7189 return pl->mclk; 7190 } 7191 } 7192